Semiconductor device

Abstract

A semiconductor device includes a substrate having a first conductivity type, an epitaxial layer disposed on the substrate, wherein the epitaxial layer has a second conductivity type different from the first conductivity type, and a first high voltage well disposed in the epitaxial layer, wherein the first high voltage well has the first conductivity type. The semiconductor device further includes source and drain regions disposed in the epitaxial layer, wherein the source and drain regions have the first conductivity type, and a buried layer structure disposed within the substrate and having the second conductivity type. The buried layer structure includes a first buried layer under the source region and a second buried layer under the drain region. The first buried layer laterally abuts the second buried layer, and a bottom surface of the second buried layer is lower than a bottom surface of the first buried layer.

Description

Technical Field

[0001] This invention relates to semiconductor devices, and more particularly to buried layer structures. Background Technology

[0002] High-voltage semiconductor technology is suitable for microwave / RF power amplifiers. Traditional high-voltage semiconductor devices, such as vertically diffused metal-oxide-semiconductor (VDMOS) transistors and laterally diffused metal-oxide-semiconductor (LDMOS) transistors, are primarily used in applications above 12V. The advantages of high-voltage semiconductor devices lie in their cost-effectiveness and compatibility with other processes, and they are widely used in display driver integrated circuits, power supplies, power management, communications, automotive electronics, and industrial control.

[0003] While existing high-voltage semiconductor devices have largely fulfilled their original applications, they are not entirely satisfactory in every aspect. For example, breakdown voltage, vertical punch-through voltage, and on-state resistance require further improvement. Therefore, there are still some issues to be overcome regarding high-voltage semiconductor devices and manufacturing technologies. Summary of the Invention

[0004] A semiconductor device includes: a substrate having a first conductivity type; an epitaxial layer disposed on the substrate, wherein the epitaxial layer has a second conductivity type different from the first conductivity type; and a first high-voltage well disposed in the epitaxial layer, wherein the first high-voltage well has the first conductivity type. The semiconductor device further includes: a source region and a drain region disposed in the epitaxial layer, wherein the source region and drain region have the first conductivity type; and a buried layer structure disposed within the substrate and having a second conductivity type. The buried layer structure includes: a first buried layer located below the source region; and a second buried layer located below the drain region. The first buried layer is laterally adjacent to the second buried layer, and the bottom surface of the second buried layer is lower than the bottom surface of the first buried layer. Attached Figure Description

[0005] The various aspects of embodiments of the present invention will be described in detail below with reference to the accompanying drawings. It should be noted that, in accordance with industry standard practice, the various features are not drawn to scale. In fact, the dimensions of various components can be arbitrarily enlarged or reduced to clearly demonstrate the features of the embodiments of the present invention.

[0006] Figure 1 This is a schematic cross-sectional view of a semiconductor device according to some embodiments of the present invention.

[0007] Figure 2 According to some embodiments of the present invention, a drain current-voltage curve of a semiconductor device is illustrated.

[0008] Figure 3 According to some embodiments of the present invention, a drain current-voltage curve of a semiconductor device is illustrated.

[0009] Icon labels:

[0010] 10: Semiconductor devices

[0011] 20: Drain current-voltage curve

[0012] 30: Drain current-voltage curve

[0013] 100: Base

[0014] 102: Epitaxial layer

[0015] 104: Buried structure

[0016] 106: First buried layer

[0017] 108: Second Embedded Layer

[0018] 110: First High-Pressure Trap

[0019] 112: Second High-Pressure Trap

[0020] 114: Third High-Pressure Trap

[0021] 116: Trap

[0022] 118: Drift Zone

[0023] 122: Doped region

[0024] 124: Heavily Doped Region

[0025] 126: Source Region

[0026] 128: Drain region

[0027] 132a: First isolation structure

[0028] 132b: Second isolation structure

[0029] 132c: Third isolation structure

[0030] 132d: Fourth isolation structure

[0031] 136: Gate Structure

[0032] 140: Interlayer dielectric layer

[0033] 142: First guide hole

[0034] 144: Second guide hole

[0035] 146: Third guide hole

[0036] 152: Substrate Electrode

[0037] 154: Source Electrode

[0038] 156: Drain electrode Detailed Implementation

[0039] The following provides numerous different embodiments or examples for implementing various components of embodiments of the present invention. Specific examples of components and configurations are described below to simplify embodiments of the present invention. Of course, these are merely examples and are not intended to limit embodiments of the present invention. For example, the description mentioning that a first component is formed on top of a second component may include embodiments in which the first and second components are in direct contact, or embodiments in which an additional component is formed between the first and second components such that the first and second components are not in direct contact. Furthermore, element symbols and / or letters may be repeated in various examples. Such repetition is for simplification and clarity and does not in itself govern the relationship between the various embodiments and / or configurations discussed.

[0040] Furthermore, in some embodiments of the present invention, terms such as “connection” and “interconnection”, unless otherwise defined, may refer to two structures being in direct contact, or to two structures not being in direct contact, wherein there is another structure disposed between the two structures.

[0041] Furthermore, spatially related terms such as “below,” “under,” “lower,” “above,” “above,” and similar terms may be used here to describe the relationship between one element or component and other elements or components as shown in the figure. These spatial terms are intended to encompass different orientations of the device in use or operation, as well as the orientations shown in the figure. When the device is rotated to other orientations (rotated 90° or other orientations), the spatial relative descriptions used here can also be interpreted according to the orientation after rotation.

[0042] The terms "about," "approximately," and "roughly" as used herein generally mean within ±20%, preferably ±10%, and even more preferably within ±5%, ±3%, ±2%, ±1%, or 0.5% of a given value. The values ​​given herein are approximate; that is, unless specifically stated otherwise, the given values ​​may imply the meaning of "about," "approximately," or "roughly."

[0043] The following describes some embodiments of the invention in which additional steps may be provided before, during, and / or after the multiple stages described in these embodiments. Additional components may be added to the semiconductor device structure. Some of the components may be replaced or omitted in different embodiments. Although some of the embodiments discussed perform the steps in a particular order, these steps may still be performed in another logical order.

[0044] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. It is understood that these terms, such as those defined in a general dictionary, should be interpreted as having a meaning consistent with the background or context of the relevant art and this invention, and should not be interpreted in an idealized or overly formal manner, unless specifically defined in the embodiments of this invention.

[0045] The semiconductor device of this invention illustrates embodiments of high-voltage integrated circuits, particularly embodiments of laterally diffused metal oxide semiconductor (LDMOS) transistors. In the prior art, the doping concentration and structural profile of each semiconductor region of a LDMOS transistor are typically adjusted during the fabrication process to generate sufficiently high breakdown voltage and vertical punch-through voltage, and sufficiently low on-state resistance, thereby further optimizing overall performance. However, in practical fabrication processes, such as integrated bipolar complementary metal oxide semiconductor-double diffused metal oxide semiconductor (BCD) processes, adjusting the doping concentration or structural profile of the semiconductor regions may require the use of additional masks, thus increasing the overall fabrication cost.

[0046] To improve the breakdown voltage, vertical breakdown voltage, and on-resistance of laterally diffused metal-oxide-semiconductor (MOSFET) transistors, embodiments of the present invention incorporate a double-diffused buried layer structure with a stepped profile into the MOSFET. This buried layer structure, in addition to traversing the source and drain regions of the transistor, also includes components extending downwards to different junction depths. In other words, the buried layer structure can simultaneously add a vertically assisted depletion layer (VADL) and a laterally assisted depletion layer (LADL), thereby improving the overall device's breakdown voltage, vertical breakdown voltage, and on-resistance. laterally diffused MOSFETs with high breakdown voltage and vertical breakdown voltage, and low on-resistance can also be widely used in lighting, flat panel displays, audio equipment, switch-mode power supplies, power control, and other fields.

[0047] Figure 1 This is a schematic cross-sectional view of a semiconductor device 10 according to some embodiments of the present invention. In some embodiments, the semiconductor device may include any number of active and passive components. Active components include metal-oxide-semiconductor (MOS) transistors, complementary metal-oxide-semiconductor (CMOS) transistors, lateral-diffused metal-oxide-semiconductor (LDMOS) transistors, bipolar complementary metal-oxide-semiconductor-double diffused metal-oxide-semiconductor (BCD) transistors, planar transistors, fin field-effect transistors (FinFETs), gate-all-around field-effect transistors (GAAFETs), other similar devices, or combinations thereof. Passive components include metal traces, capacitors, inductors, resistors, diodes, bonding pads, or other similar structures. For simplicity, Figure 1 Only illustrative examples of laterally diffused metal-oxide semiconductors are shown.

[0048] Reference Figure 1The semiconductor device 10 may include a substrate 100, an epitaxial layer 102, a buried layer structure 104, a first isolation structure 132a, a second isolation structure 132b, a third isolation structure 132c, a fourth isolation structure 132d, a gate structure 136, an interlayer dielectric layer 140, a first via 142, a second via 144, a third via 146, a base electrode 152, a source electrode 154, and a drain electrode 156. In some embodiments, the epitaxial layer 102 may include a first high-voltage well 110, a second high-voltage well 112, and a third high-voltage well 114. The first high-voltage well 110 may include a well 116 and a drift region 118. The third high-voltage well 114 may include a doped region 122. The well 116 may include a heavily doped region 124 and a source region 126. The drift region 118 may include a drain region 128. Furthermore, the buried layer structure 104 may include a first buried layer 106 and a second buried layer 108.

[0049] Reference Figure 1 The substrate 100 may be, for example, a wafer or a chip, but the embodiments of the present invention are not limited thereto. In some embodiments, the substrate 100 may be a semiconductor substrate, such as a silicon substrate. Furthermore, in some embodiments, the semiconductor substrate may also be: an elemental semiconductor, including germanium; a compound semiconductor, including gallium nitride (GaN), silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), and / or indium antimonide (InSb); or an alloy semiconductor, including silicon germanium (SiGe) alloy, gallium arsenide phosphide (GaAsP) alloy, aluminum indium arsenide (AlInAs) alloy, aluminum gallium arsenide (AlGaAs) alloy, and gallium indium arsenide (GaInAs). Gallium arsenide (GaInAs) alloys, gallium indium phosphide (GaInP) alloys, and / or gallium indium arsenide phosphide (GaInAsP) alloys, or combinations thereof.

[0050] In other embodiments, substrate 100 may also be a semiconductor on-insulator (SOI) substrate. The SOI substrate may include a substrate, a buried oxide (BOX) layer disposed on the substrate, and a semiconductor layer disposed on the buried oxide layer. Furthermore, substrate 100 may be of a first conductivity type or a second conductivity type different from the first conductivity type. In the following embodiments, the first conductivity type and the second conductivity type may represent P-type and N-type, respectively. The first conductivity type (P-type) and the second conductivity type (N-type) may each be doped with a suitable dopant (or impurity). P-type dopant may include boron (B), indium (In), aluminum (Al), and gallium (Ga), while N-type dopant may include phosphorus (P) and arsenic (As). In a particular embodiment of the invention, substrate 100 may be of the first conductivity type (P-type) with a doping concentration of approximately 1 × 10⁻⁶. 19 cm -3 and 3×10 19 cm -3 between.

[0051] In other embodiments, substrate 100 may include an isolation structure (not shown) to define active regions and electrically isolate active region components within or above substrate 100, but this embodiment of the invention is not limited thereto. The isolation structure may include a deep trench isolation (DTI) structure, a shallow trench isolation (STI) structure, or a local oxidation of silicon (LOCOS) structure. In some embodiments, forming the isolation structure may include, for example, forming an insulating layer on substrate 100, selectively etching the insulating layer and substrate 100 to form a trench extending from the top surface of substrate 100 to a location within substrate 100, wherein the trench is located between adjacent active regions. Next, forming the isolation structure may include growing a nitrogen-rich liner (such as silicon oxynitride (SiON) or other similar materials) along the trench, and then filling the trench with an insulating material (such as silicon dioxide (SiO2), silicon nitride (SiN), silicon oxynitride, or other similar materials) using a deposition process. Subsequently, the insulating material in the trench is annealed, and the substrate 100 is planarized to remove excess insulating material, so that the insulating material in the trench is flush with the top surface of the substrate 100.

[0052] Continue to refer to Figure 1 An epitaxial layer 102 is formed on a substrate 100. According to some embodiments of the present invention, the epitaxial layer 102 has a second conductivity type (N-type) with a doping concentration of approximately 1.13 × 10⁻⁶. 15 cm -3 and 2.30×10 15 cm -3 In a specific embodiment of the invention, the substrate 100 and the epitaxial layer 102 may have different conductivity types, and the doping concentration of the substrate 100 is greater than that of the epitaxial layer 102. The material of the epitaxial layer 102 may include silicon, silicon germanium, silicon carbide, other similar materials, or combinations thereof. The thickness of the epitaxial layer 102 may be approximately between 3 μm and 7 μm. The epitaxial layer 102 may be formed by epitaxial processes, including metal-organic chemical vapor deposition (MOCVD), hydride vapor phase epitaxy (HVPE), molecular beam epitaxy (MBE), other suitable methods, or combinations thereof.

[0053] Reference Figure 1 The semiconductor device 10 includes a buried layer structure 104 disposed within a substrate 100 and an epitaxial layer 102, comprising a first buried layer 106 and a second buried layer 108. Since the second buried layer 108 and the subsequently formed drift region 118 can be formed from the same mask, the overall number of masks required for the semiconductor device 10 does not increase even if the buried layer structure 104 has two different components, thus not significantly increasing manufacturing costs or cycle time. In some embodiments, the first buried layer 106 and the second buried layer 108 have a second conductivity type (N-type). According to some embodiments of the invention, the first buried layer 106 is laterally adjacent to the second buried layer 108, and the bottom surface of the second buried layer 108 is lower than the bottom surface of the first buried layer 106. In some alternative embodiments, the first buried layer 106 and the second buried layer 108 may be laterally separated, depending on application and design requirements.

[0054] The method for forming the first buried layer 106 and the second buried layer 108 may include ion-implanting an N-type dopant (e.g., phosphorus or arsenic) into a substrate 100 before forming the epitaxial layer 102, performing heat treatment to drive the implanted ions into the substrate 100, and then forming the epitaxial layer 102 on the substrate 100. In some embodiments, since the epitaxial layer 102 is formed under high-temperature conditions, the implanted ions diffuse into the epitaxial layer 102. Figure 1As shown, the first buried layer 106 and the second buried layer 108 are located near the interface between the substrate 100 and the epitaxial layer 102, with a portion within the substrate 100 and another portion within the epitaxial layer 102. Since the first buried layer 106 and the second buried layer 108 are diffused in the same epitaxial process, the overall top of the buried layer structure 104 can have a planarized surface.

[0055] The function of the first buried layer 106 is to provide more complete isolation below the source region, which helps prevent leakage current and further improves the breakdown voltage of the overall device. The location of the first buried layer 106 can be regarded as the high-side region of the semiconductor device 10. In some embodiments, the doping concentration of the first buried layer 106 may be approximately between 1 × 10⁻⁶. 15 cm -3 and 5×10 15 cm -3 In some embodiments of the invention, the doping concentration of the first buried layer 106 is higher than that of the second buried layer 108. The first buried layer 106 is designed to have a relatively high doping concentration and a denser distribution of dopants. Therefore, the vertical dimension of the first buried layer 106 is smaller than that of the second buried layer 108. The vertical dimension of the first buried layer 106 is approximately between 4 μm and 5 μm. The lateral dimension of the first buried layer 106 can extend from the first high-voltage well 110 subsequently formed in the epitaxial layer 102 to the second high-voltage well 112. The extent of lateral extension depends on the isolation requirements of the depletion region. According to some embodiments, a complete depletion region can reduce leakage current and improve the overall device breakdown voltage, vertical breakdown voltage, and on-resistance.

[0056] The function of the second buried layer 108 is to provide a larger junction depth below the drift region, allowing the depletion region to extend vertically and thus increasing the vertical breakdown voltage. The location of the second buried layer 108 can be considered as the low-side region of the semiconductor device 10. Furthermore, the junction depth can be the connection region between the epitaxial layer 102 and the substrate 100, as defined by the buried layer structure 104. In some embodiments, the doping concentration of the second buried layer 108 can be approximately between 1.5 × 10⁻⁶. 15 cm -3 and 4.5×10 15 cm -3As mentioned earlier, the doping concentration of the first buried layer 106 is higher than that of the second buried layer 108. By design, the second buried layer 108, in addition to having a relatively low doping concentration, has a more dispersed distribution of dopants. Therefore, the vertical dimension of the second buried layer 108 is approximately twice that of the first buried layer 106, meaning it has a wider interface, which can more effectively prevent leakage current between the drift region and the underlying substrate. It is worth noting that because the first high-voltage well 110 subsequently formed on the second buried layer 108 has a very high doping concentration, the dopants in the second buried layer 108 do not diffuse upwards, but rather diffuse downwards into the substrate 100, which has a lower doping concentration. In other words, the top surfaces of the first buried layer 106 and the second buried layer 108 can remain substantially coplanar.

[0057] According to some embodiments of the present invention, the first buried layer 106 and the second buried layer 108 of the buried layer structure 104 form a stepped profile at the bottom due to different dopant distributions. The buried layer structure 104 can simultaneously maintain the characteristics of a continuous structure and dual diffusion. The junction depth of the second buried layer 108 is greater than that of the first buried layer 106, allowing the portion of the depletion region below the drift region 118 to extend further downward. In some embodiments, the drift region 118 can be considered as the region between the gate and drain terminals, and thus has a critical impact on the overall device performance. As the depletion region below the drift region 118 extends downward, the region between the drift region 118 and the depletion region below it becomes larger, thus creating a larger electric field. The reduced surface field (RESURF) effect on the epitaxial layer 102 is also enhanced. The buried layer structure 104 of the present invention achieves a continuous structure, a gradual change in doping concentration, and an extension of the depletion region. When the doping concentration and electric field can be controlled in a more balanced manner, the depletion region can be "depleted" more completely, which helps to optimize the characteristics of the overall device.

[0058] Continue to refer to Figure 1 A first high-voltage well 110, a second high-voltage well 112, and a third high-voltage well 114 can be formed within the epitaxial layer 102. The first high-voltage well 110, the second high-voltage well 112, and the third high-voltage well 114 extend vertically from the top surface of the epitaxial layer 102 to the interface between the epitaxial layer 102 and the substrate 100 or the interface between the epitaxial layer 102 and the buried layer structure 104. According to some embodiments of the present invention, the first high-voltage well 110 and the third high-voltage well 114 may be of a first conductivity type (P-type), while the second high-voltage well 112 may be of a second conductivity type (N-type). Since the high-voltage wells of the first conductivity type and the high-voltage wells of the second conductivity type are staggered in the horizontal direction, a bipolar (PNP) junction is formed, which can further improve the charge balance state, making the expected depletion region more completely "depleted".

[0059] The first high-voltage well 110, the second high-voltage well 112, and the third high-voltage well 114 can be formed by, for example, ion implantation and / or diffusion processes. In an alternative embodiment, instead of using ion implantation and / or diffusion processes, the first high-voltage well 110, the second high-voltage well 112, and the third high-voltage well 114 can be in-situ doped during the growth of the epitaxial layer 102. In other embodiments, in-situ and implantation doping can be used together.

[0060] The first high-voltage well 110 may be located above a portion of the first buried layer 106 and all of the second buried layer 108. In some embodiments, the doping concentration of the first high-voltage well 110 may be between approximately 7 × 10⁻⁶. 15 cm -3 and 9×10 15 cm -3 The first high-voltage well 110 may include a subsequently formed well 116 and a drift region 118, which further include a source region 126 and a drain region 128, respectively. Furthermore, a subsequently formed gate structure 136 is also disposed on the surface of the first high-voltage well 110 of the epitaxial layer 102 and is laterally located between the source region 126 and the drain region 128.

[0061] The second high-pressure sink 112 may be laterally adjacent to the first high-pressure sink 110. For example... Figure 1 As shown, the second high-pressure well 112 is horizontally disposed between the first high-pressure well 110 and the third high-pressure well 114. In some embodiments, the doping concentration of the second high-pressure well 112 may be between approximately 1 × 10⁻⁶. 16 cm -3 and 3×10 16 cm -3 Between. The first buried layer 106 may extend partially beneath the second high-voltage trap 112. As previously mentioned, the extension of the first buried layer 106 provides more complete isolation, which helps prevent leakage current.

[0062] The third high-voltage well 114 may be laterally adjacent to the second high-voltage well 112. In some embodiments, the doping concentration of the third high-voltage well 114 may be between approximately -5 × 10⁻⁶. 17 cm -3 and -1×10 17 cm -3 Between. The third high-voltage well 114 may include a subsequently formed doped region 122. Since the substrate 100, the third high-voltage well 114 in the epitaxial layer 102, and the doped region 122 are all of the first conductivity type (P-type), the subsequently formed base electrode 152 may allow the semiconductor device 10 to be grounded from the top or from the bottom.

[0063] Reference Figure 1 A well 116 and a drift region 118 may be formed within the first high-voltage well 110, extending from the top surface of the first high-voltage well 110. According to some embodiments of the invention, the well 116 may be of a second conductivity type (N-type), while the drift region 118 may be of a first conductivity type (P-type). The well 116 and the drift region 118 are laterally separated. The method of forming the well 116 and the drift region 118 may be similar to the method of forming the first high-voltage well 110, the second high-voltage well 112, and the third high-voltage well 114, and the details will not be repeated here.

[0064] The well 116 may be located above the first buried layer 106. In some embodiments, the doping concentration of the well 116 may be between approximately 1 × 10⁻⁶. 16 cm -3 and 2×10 16 cm -3 The well 116 may include a subsequently formed heavily doped region 124 and a source region 126. The thickness of the well 116 may be approximately between 2.0 μm and 2.5 μm.

[0065] The drift region 118 may be located above the second buried layer 108. As previously mentioned, the drift region 118 and the second buried layer 108 may have the same lateral dimensions, thus allowing the use of the same mask during fabrication to further reduce fabrication costs. The drift region 118 enables the semiconductor device 10 to generate a long depletion region under high-voltage operation, thereby reducing excessive electric field concentration and improving breakdown voltage. Furthermore, the doping concentration of the drift region 118 also determines the on-resistance of the semiconductor device 10. In some embodiments, the doping concentration of the drift region 118 may be between approximately -8 × 10⁻⁶. 15 cm -3 and -7×10 15 cm -3 The drift region 118 may include a subsequently formed drain region 128. The thickness of the drift region 118 may be approximately between 2 μm and 4 μm.

[0066] Continue to refer to Figure 1 A heavily doped region 124 and a source region 126 can be formed within the well 116, extending from the top surface of the well 116. According to some embodiments of the invention, the heavily doped region 124 may be of a second conductivity type (N-type), while the source region 126 may be of a first conductivity type (P-type). The heavily doped region 124 and the source region 126 are laterally adjacent to each other. The method of forming the heavily doped region 124 and the source region 126 can be similar to the method of forming the first high-voltage well 110, the second high-voltage well 112, and the third high-voltage well 114, and the details will not be repeated here.

[0067] In some embodiments, the doping concentration of the heavily doped region 124 may be between approximately 1.0 × 10⁻⁶. 19 cm-3 and 1.5×10 19 cm -3 The heavily doped region 124 can be coupled simultaneously with the source region 126 to the subsequently formed source electrode 154. The thickness of the heavily doped region 124 can be approximately between 0.2 μm and 0.5 μm. The heavily doped region 124 having a second conductivity type can achieve charge balance with the source region 126 having a first conductivity type, and provides an ohmic contact of the second conductivity type for the source electrode 154.

[0068] In some embodiments, the doping concentration of the source region 126 may be between approximately -2 × 10⁻⁶. 19 cm -3 and -2×10 18 cm -3 The thickness of the source region 126 can be approximately between 0.2 μm and 0.5 μm.

[0069] Reference Figure 1 A drain region 128 may be formed within the drift region 118, extending from the top surface of the drift region 118. According to some embodiments of the invention, the drain region 128 may be of a first conductivity type (P-type). In some embodiments, the doping concentration of the drain region 128 may be between approximately -2 × 10⁻⁶. 19 cm -3 and -2×10 18 cm -3 The thickness of the drain region 128 can be approximately between 0.3 μm and 0.6 μm. The drain region 128 can be coupled to the subsequently formed drain electrode 156. The method of forming the drain region 128 can be similar to the method of forming the first high-voltage well 110, the second high-voltage well 112, and the third high-voltage well 114, and the details will not be repeated here.

[0070] Continue to refer to Figure 1 A first isolation structure 132a, a second isolation structure 132b, a third isolation structure 132c, and a fourth isolation structure 132d can be formed on the epitaxial layer 102. Specifically, since their fabrication process involves high-temperature processing, the first isolation structure 132a, the second isolation structure 132b, the third isolation structure 132c, and the fourth isolation structure 132d are partially embedded within the epitaxial layer 102. According to some embodiments of the present invention, the first isolation structure 132a, the second isolation structure 132b, the third isolation structure 132c, and the fourth isolation structure 132d can isolate various conductive components to prevent electrical short circuits from occurring in the semiconductor device 10 during operation.

[0071] like Figure 1As shown, the doped region 122 in the third high-voltage well 114 can be laterally located between the first isolation structure 132a and the second isolation structure 132b. The second isolation structure 132b can laterally isolate the doped region 122 from the well 116 of the first high-voltage well 110. The heavily doped region 124 and the source region 126 of the well 116, as well as the subsequently formed gate structure 136, can be laterally located between the second isolation structure 132b and the third isolation structure 132c. It should be noted that the gate structure 136 can extend onto a portion of the surface of the third isolation structure 132c. The drain region 128 of the drift region 118 can be laterally located between the third isolation structure 132c and the fourth isolation structure 132d.

[0072] In some embodiments, silicon oxide (SiO) can be used to form a first isolation structure 132a, a second isolation structure 132b, a third isolation structure 132c, and a fourth isolation structure 132d, which may be silicon partial oxide isolation structures formed by thermal oxidation. In other embodiments, the first isolation structure 132a, the second isolation structure 132b, the third isolation structure 132c, and the fourth isolation structure 132d may be shallow trench isolation structures formed by etching, oxidation, and deposition processes.

[0073] Reference Figure 1 After forming the first isolation structure 132a, the second isolation structure 132b, the third isolation structure 132c, and the fourth isolation structure 132d, a gate structure 136 can be formed on the epitaxial layer 102. The gate structure 136 can extend horizontally from the well 116, through the first high-voltage well 110, and reach the drift region 118. The portion of the epitaxial layer 102 contacted by the gate structure 136 can be considered as a channel region of the semiconductor device 10, and the gate structure 136 can serve as the gate terminal of an active component. According to some embodiments of the present invention, the source region 126, the drain region 128, and the gate structure 136 form a transistor of a first conductivity type (P-type), such as a laterally diffused metal-oxide semiconductor. The transistor has a channel region of a second conductivity type (N-type). The thickness of the gate structure 136 can be approximately between 0.25 μm and 0.30 μm. In some embodiments, the gate structure 136 may include a gate dielectric layer (not shown) and a gate electrode (not shown) disposed on the gate dielectric layer. In other embodiments, the semiconductor device 10 may have a transistor of a second conductivity type (N-type) and a channel region of a first conductivity type (P-type), and be equipped with a buried layer structure of the first conductivity type (P-type), but such a configuration is relatively uncommon in the industry.

[0074] The gate dielectric layer material may include high-k dielectric materials (e.g., materials with a K value greater than 7), which may include hafnium oxide (HfO2), hafnium silicate, hafnium siliconoxynitride (HfSiON), hafnium aluminum oxide (HfAlO), hafnium lanthanum oxide (HfLaO), hafnium zirconium oxide (HfZrO), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), lanthanum oxide (LaO), aluminum oxide, aluminum silicon oxide (AlSiO), zirconium oxide, titanium oxide (TiO), tantalum oxide (Ta2O5), and yttrium oxide. The gate dielectric layer of the gate structure 136 can be formed by chemical vapor deposition (CVD), atomic layer deposition (ALD), other similar methods, or combinations thereof.

[0075] The materials for the gate electrode may include amorphous silicon, polysilicon, poly-SiGe, metal nitrides (such as titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), titanium aluminum nitride (TiAlN), or other similar materials), metal silicides (such as nickel silicide (NiSi), cobalt silicide (CoSi), tantalum silicon nitride (TaSiN), or other similar materials), metal carbides (such as tantalum carbide (TaC), tantalum carbonitride (TaCN), or other similar materials), metal oxides, and metals. The metals may include cobalt (Co), ruthenium (Ru), aluminum (Al), palladium (Pd), platinum (Pt), tungsten (W), copper (Cu), titanium (Ti), tantalum (Ta), silver (Ag), gold (Au), nickel (Ni), other similar materials, combinations thereof, or multiple layers thereof. The gate electrode of the gate structure 136 may be formed by physical vapor deposition (PVD), atomic layer deposition, plating, other suitable processes, or combinations thereof.

[0076] Continue to refer to Figure 1 An interlayer dielectric layer 140 can be formed on the epitaxial layer 102. In some embodiments, the interlayer dielectric layer 140 may cover the first isolation structure 132a, the second isolation structure 132b, the third isolation structure 132c, the fourth isolation structure 132d, and the gate structure 136. In addition to providing mechanical protection and insulation to the underlying components, the interlayer dielectric layer 140 can also isolate conductive materials at different levels. The material of the interlayer dielectric layer 140 may include silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, and silicon oxynitrocarbide (SiO2). x N y C 1-x-y(where x and y are in the range of 0 to 1), tetraethylorthosilicate (TEOS), undoped silicate glass, doped silicon oxide (such as boron-doped phospho-silicate glass (BPSG), fused silica glass (FSG), phospho-silicate glass (PSG), boron-doped silicate glass (BSG), or other similar materials), low-k dielectric materials, or other suitable dielectric materials.

[0077] The thickness of the interlayer dielectric layer 140 can be approximately between and Between. The interlayer dielectric layer 140 can be formed by chemical vapor deposition, high-density plasma chemical vapor deposition (HDP-CVD), plasma-enhanced chemical vapor deposition (PECVD), low-pressure chemical vapor deposition (LPCVD), flowable chemical vapor deposition (FCVD), sub-atmospheric chemical vapor deposition (SACVD), other similar methods, or combinations thereof.

[0078] Reference Figure 1A first via 142, a second via 144, and a third via 146 can be formed through the interlayer dielectric layer 140. The first via 142, the second via 144, and the third via 146 can physically contact the doped region 122, the heavily doped region 124, the source region 126, and the drain region 128, respectively. Furthermore, a base electrode 152, a source electrode 154, and a drain electrode 156 can be formed on the interlayer dielectric layer 140. In some embodiments, the base electrode 152 is electrically coupled to the doped region 122 through the first via 142, the source electrode 154 is electrically coupled to the heavily doped region 124 and the source region 126 through the second via 144, and the drain electrode 156 is electrically coupled to the drain region 128 through the third via 146. As previously mentioned, the base electrode 152 can serve as an electrical ground for the semiconductor device 10. The source electrode 154 and the drain electrode 156 can be used as the source and drain terminals of the active component, respectively.

[0079] The first via 142, the second via 144, the third via 146, the base electrode 152, the source electrode 154, and the drain electrode 156 can be integrally formed and therefore comprise the same material, which can be similar to the material of the gate electrode of the gate structure 136; details will not be repeated here. First, a plurality of openings can be formed in the interlayer dielectric layer 140, corresponding to the doped region 122, the heavily doped region 124, the source region 126, and the drain region 128, respectively. Next, the aforementioned material can be deposited blanket-deposited on the interlayer dielectric layer 140 using a suitable deposition process. This material, in addition to being formed on the surface of the interlayer dielectric layer 140, also fills all the openings to form the first via 142, the second via 144, and the third via 146. The deposited film can be patterned using a photolithography process followed by an etching process to form the base electrode 152, the source electrode 154, and the drain electrode 156. Photolithography processes may include photoresist coating, soft baking, exposure, post-exposure baking, development, other similar techniques, or combinations thereof. Etching processes may include dry etching, wet etching, other similar methods, or combinations thereof. Based on a monolithic process, the substrate electrode 152, source electrode 154, and drain electrode 156 may have substantially the same thickness, which may be approximately between [missing information - likely a value] and [missing information - likely a value]. and between.

[0080] Figure 2According to some embodiments of the present invention, a drain current-voltage curve 20 of a semiconductor device is illustrated. According to some embodiments of the present invention, the drain current-voltage curve 20 compares two configurations of semiconductor devices. A conventional design (represented by dashed lines) may be a buried layer structure with a single buried layer, for example, a first buried layer 106 extending from a second high-voltage well 112 below a drift region 118. A new design (represented by solid lines) may be the semiconductor device 10 disclosed in this invention, which has a buried layer structure 104 with a stepped profile of double diffusion. Because the buried layer structure 104 achieves a continuous structure, a gradual change in doping concentration, and an extension of the depletion region, the new design (e.g., semiconductor device 10) can significantly improve the breakdown voltage to above 160V.

[0081] Figure 3 According to some embodiments of the present invention, a drain current-voltage curve 30 of a semiconductor device is illustrated. According to some embodiments of the present invention, the drain current-voltage curve 30 includes the drain current-voltage distributions of three different conventional designs and a novel design of the present invention (e.g., semiconductor device 10) in the on-state. Compared to the three conventional designs, the novel design can have a higher drain saturation current and / or greater high-voltage withstand characteristics due to the continuous structure, gradual doping concentration, and expansion of the depletion region achieved by the buried layer structure 104.

[0082] In one specific embodiment, three conventional and novel designs are compared. Design features are listed and electrical parameters are measured. Relevant data are summarized in Table 1.

[0083] Table 1

[0084]

[0085] In three conventional designs, the first and second conventional designs have the same dopant but different doping concentrations. The first and third conventional designs have the same doping concentration but different dopants. The novel design of the present invention (e.g., semiconductor device 10) can exhibit a relatively high breakdown voltage. Although the breakdown voltage of the second conventional design may be slightly higher than that of the novel design, the second conventional design also has excessively high on-resistance, which may directly impact the performance of the device. In addition to a sufficient breakdown voltage, the novel design also maintains a sufficiently low on-resistance, and the vertical breakdown voltage is within an acceptable range.

[0086] The buried layer structure of this invention comprises a first buried layer and a second buried layer with different dopant distributions. Due to the different dopant distributions, a stepped profile is formed at the bottom of the buried layer structure. The buried layer structure can simultaneously maintain a continuous structure and the characteristics of dual diffusion. The interface depth of the second buried layer is greater than that of the first buried layer, allowing the portion of the depletion region below the drift region to extend further downward. As the depletion region below the drift region extends downward, the area between the drift region and the depletion region below it becomes larger, thus creating a larger electric field. The reduction of surface electric field effects on the epitaxial layer is also enhanced. The buried layer structure of this invention achieves a continuous structure, a gradual change in doping concentration, and an expansion of the depletion region. When the doping concentration and electric field can be more balanced and controlled, the depletion region can be "depleted" more completely, which helps to optimize the characteristics of the overall device.

[0087] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand the viewpoints of the embodiments of the present invention. Those skilled in the art should understand that other processes and structures can be easily designed or modified based on the embodiments of the present invention to achieve the same objectives and / or advantages as the embodiments described herein. Those skilled in the art should also understand that such equivalent structures do not depart from the spirit and scope of the present invention, and that various changes, substitutions, and replacements can be made without departing from the spirit and scope of the present invention.

Claims

1. A semiconductor device, characterized in that, include: A substrate having a first type of conductivity; An epitaxial layer is disposed on the substrate, wherein the epitaxial layer has a second conductivity type different from the first conductivity type; A first high-voltage well is disposed in the epitaxial layer, wherein the first high-voltage well has the first conductivity type; A source region and a drain region are disposed in the epitaxial layer, wherein the source region and the drain region have the first conductivity type; as well as A buried layer structure, disposed within the substrate and having the second conductivity type, wherein the buried layer structure includes: A first buried layer is located below the source region; as well as A second buried layer is located below the drain region, wherein the first buried layer is laterally adjacent to the second buried layer, the bottom surface of the second buried layer is lower than the bottom surface of the first buried layer, and the vertical dimension of the first buried layer is smaller than the vertical dimension of the second buried layer. The bottom of the buried structure is stepped. The top of the buried structure has a flattened surface.

2. The semiconductor device according to claim 1, characterized in that, The doping concentration of the first buried layer is higher than that of the second buried layer.

3. The semiconductor device according to claim 1, characterized in that, Also includes: A second high-voltage well is disposed in the epitaxial layer and has the second conductivity type, wherein the second high-voltage well is adjacent to the first high-voltage well; as well as A third high-voltage well is disposed in the epitaxial layer and has the first conductivity type, wherein the third high-voltage well is adjacent to the second high-voltage well.

4. The semiconductor device according to claim 3, characterized in that, The first buried layer extends laterally from below the first high-pressure sink to below the second high-pressure sink.

5. The semiconductor device according to claim 1, characterized in that, It also includes a doped region that is laterally adjacent to the source region.

6. The semiconductor device according to claim 5, characterized in that, The heavily doped region and the source region are located in a well, wherein the well has the second conductivity type.

7. The semiconductor device according to claim 6, characterized in that, It also includes a gate structure located laterally between the source region and the drain region.

8. The semiconductor device according to claim 7, characterized in that, It also includes a drift region disposed below the gate structure and having the first conductivity type, wherein the drain region is located within the drift region.

9. The semiconductor device according to claim 8, characterized in that, The gate structure extends laterally from the well to the drift region, wherein an inter-dielectric layer covers the gate structure.

10. The semiconductor device according to claim 8, characterized in that, The trap and the drift region are located within the first high-pressure trap.

11. The semiconductor device according to claim 8, characterized in that, The lateral dimension of the second buried layer is equal to the lateral dimension of the drift zone.

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