Power transmission device capable of improving arc phenomenon

Abstract

A power delivery apparatus that improves arc phenomenon includes a power delivery charger and a power delivery sink. The power delivery charger detects the coupling state between the power delivery charger and the power delivery sink and determines whether the present power delivery is for high voltage applications. When the power delivery charger determines that the power delivery is for high voltage applications, the power delivery charger provides an output capacitor resonance fast discharge path to quickly pull down the output voltage of the power delivery charger upon detecting that the power delivery charger and the power delivery sink are unplugged from each other, thereby improving arc phenomenon.

Description

Technical Field

[0001] This invention relates to a power delivery device, and more particularly to a USB Type-C power delivery device that can improve the arcing phenomenon. Background Technology

[0002] The new generation Universal Serial Bus (USB) Type-C connector can simultaneously support data, audio, and video transmission, reversible insertion, and high-efficiency charging. With its high compatibility and high transmission rate, it is widely used in information and communication devices.

[0003] Figure 1 and Figure 2 This is a schematic diagram of the existing USB Type-C standard transmission interface, in which... Figure 1 The pin diagram of the USB Type-C socket is shown, while Figure 2 The pinout of the USB Type-C connector is shown. To support reversible insertion, both the USB Type-C socket and the connector have two sets of symmetrical pins, designated A1-A12 and B1-B12 respectively. The configuration channel pins CC1 / CC2 are used to detect reversibility, connection status, determine the downstream facing port (DFP) and upstream facing port (UFP), configure the power supply pins Vbus and Vconn, configure other modes (alternate or accessory mode), and perform other related power delivery (PD) communication operations. Power is supplied through the Vbus pin only when a connected device is detected by the configuration channel pins CC1 / CC2.

[0004] In simple terms, the PD protocol is a fast charging standard. An existing PD system includes a PD charger and a PD charging device, which can establish a PD connection through a USB Type-C connector.

[0005] Figure 3This diagram illustrates the voltage and connection relationship of the power supply pin Vbus in an existing PD system. The vertical axis represents voltage value, and the horizontal axis represents time. V1 represents the voltage value of the power supply pin Vbus of the PD charger, while V2 represents the voltage value of the power supply pin Vbus of the PD receiving device. Before time T1, the PD charger normally supplies power to the PD receiving device, at which point V1 = V2. Assuming that at time T1, the user unplugs the PD charger from the PD receiving device, the energy storage element of the PD charger can maintain the potential of V1 for a period of time. In contrast, the PD receiving device has no input capacitor, so its input voltage V2 drops rapidly when the PD charger is unplugged. According to the USB Type-C PD specifications, when the voltage difference (V1-V2) between the power supply pin Vbus of the PD charger and the power supply pin Vbus of the PD receiving device is greater than 12V, there is a high probability of causing an electrical arc, raising safety concerns. Therefore, a power transmission device that can mitigate the arcing phenomenon is needed. Summary of the Invention

[0006] This invention provides a power delivery charger that improves arcing, comprising a first power supply pin, a first configuration channel pin, a boost-type active power factor correction circuit, an active clamp flyback converter circuit, and an output voltage communication circuit. The first power supply pin supplies power to a second power supply pin of a power delivery receiving device, and the first configuration channel pin receives a pull-down voltage when coupled to a second configuration channel pin of the power delivery receiving device. The boost-type active power factor correction circuit converts an AC voltage supplied by mains power into a first pulsating DC voltage, and includes a first output capacitor and a first power switch for storing the energy of the first pulsating DC voltage. A first terminal of the first power switch is coupled to a first terminal of the output capacitor, a second terminal is coupled to a second terminal of the output capacitor, and a control terminal receives a first control signal. The active clamp flyback converter circuit converts the first pulsating DC voltage into a second pulsating DC voltage, and includes a transformer, a clamping voltage capacitor, a second power switch, and an active clamping switch. The transformer, used to induce the energy of the first pulsating DC voltage from a primary side to a secondary side to supply the second pulsating DC voltage, includes a primary winding on the primary side, comprising a first dotted terminal and a first non-dotted terminal; a secondary winding on the secondary side, comprising a second dotted terminal and a second non-dotted terminal; and a discharge winding for providing a discharge inductance. A first terminal of the clamping voltage capacitor is coupled to the boost-type active power factor correction circuit to receive the first pulsating DC voltage, and a second terminal is coupled to a first terminal of the discharge inductor. A first terminal of the second power switch is coupled to the first non-dotted terminal, and a second terminal is coupled to a ground potential, while a control terminal is used to receive a second control signal. A first terminal of the active clamping switch is coupled to the first non-dotted terminal, and a second terminal is coupled to the first terminal of the discharge inductor, while a control terminal is used to receive a third control signal. The first terminal of the second output capacitor is coupled to the first power supply pin, and the second terminal is coupled to a ground pin to store the energy of the second pulsating DC voltage. The output voltage communication circuit is used to selectively couple the second terminal of the discharge inductor to the first configuration channel pin based on the potential of the first power supply pin and the potential of the first configuration channel pin. Attached Figure Description

[0007] Figure 1 and Figure 2 This is a schematic diagram of the existing USB Type-C standard transmission interface.

[0008] Figure 3 This diagram illustrates the voltage and connection relationship of the Vbus pin used for power supply in an existing power transmission device.

[0009] Figure 4This is a functional block diagram of a power transmission device according to an embodiment of the present invention.

[0010] Figure 5 This is a schematic diagram illustrating the implementation of the power transmission charger in an embodiment of the present invention.

[0011] Figure 6 This is a schematic diagram of the fast discharge path of the output capacitor provided by the power transmission device in an embodiment of the present invention.

[0012] Figure 7 This is a schematic diagram of the potential and connection relationship of the power supply pin Vbus in the power transmission device of this invention.

[0013] The reference numerals in the attached figures are explained as follows:

[0014] 10: Boost-type active power factor correction circuit

[0015] 12: Rectifier

[0016] 20: Active clamp flyback circuit

[0017] 30: Output voltage communication circuit

[0018] 50: USB Type-C interface

[0019] 100: PD System

[0020] 110: PD charger

[0021] 120: PD charging device

[0022] TR: Transformer

[0023] JACK1, PLUG1, JACK2: Connector

[0024] PDIC1, PDIC2: Power Delivery Integrated Circuits

[0025] V IN DC voltage

[0026] V OUT Output voltage

[0027] V AC AC voltage

[0028] VA: Discharge control signal

[0029] VF: Reference voltage

[0030] VO1, VO2: Pulsating DC voltage

[0031] Vp: Comparison signal

[0032] Vc: Connection signal

[0033] Vd: Pull-down voltage

[0034] RD: Pull-down resistor

[0035] CO1-CO3: Output capacitors

[0036] CC: Clamping voltage capacitor

[0037] DO1, DO2: Output diodes

[0038] D1-D4: Rectifier diodes

[0039] LM1, LM2: Boost inductors

[0040] LX: Discharge Inductor

[0041] LR: Leakage inductance

[0042] Q1, Q2: Power switches

[0043] Q3: Active clamp switch

[0044] QX: Discharge switch

[0045] QB: Blocking switch

[0046] GD1-GD3, GDX, GDB: Control signals

[0047] NP: Primary winding and number of turns

[0048] NS: Secondary winding and number of turns

[0049] NX: Discharge winding

[0050] PWMIC: Pulse Width Modulation Integrated Circuit

[0051] CP: Comparator

[0052] AND: Logic circuit

[0053] Vbus: Power supply pin

[0054] CC1 / CC2: Configuration channel pins

[0055] GND: Ground pin

[0056] P1~P12: Pins Detailed Implementation

[0057] Figure 4This is a functional block diagram of a PD system 100 according to an embodiment of the present invention. The PD system 100 includes a PD charger 110 and a PD charging device 120. The PD charger 110 includes a connector JACK1, a connector PLUG1, a boost-type active power factor correction (PFC) circuit 10, an active clampflyback conversion circuit 20, and an output voltage communication circuit 30. The PD charging device 120 includes a connector JACK2 and a power delivery integrated circuit PDIC2, wherein the power delivery integrated circuit PDIC2 includes a pull-up resistor RD.

[0058] The PD charger 110 can be connected to AC power via connector JACK1 at its input terminal and to connector JACK2 at its output terminal via connector PLUG1 at its output terminal. Connector PLUG1 of the PD charger 110 can be connected to connector JACK2 at the PD charging device 120 via a USB Type-C interface 50, wherein the pin configurations of connector PLUG1 and connector JACK2 are as follows: Figure 1 and Figure 2 As shown. To simplify the explanation, Figure 4 Only the power supply pin Vbus, configuration channel pins CC1 / CC2, and ground pin GND related to the operation of this invention are shown.

[0059] PD charger 110 can convert AC voltage V supplied by mains power. AC Converted into an output voltage V OUT This supplies the power required for the PD charging device 120 to operate. The PD charging device 120 can receive the power or instructions from the PD charging device 120 via the connector JACK2 located at its input terminal. The power delivery integrated circuit PDIC2 monitors the output voltage V. OUT In this state, it communicates with the PD charger 110 through the USB Type-C interface 50 to ensure that the power supply is operating normally.

[0060] Figure 5 This is a schematic diagram illustrating the implementation of the PD charger 110 in the PD system 100 according to an embodiment of the present invention. The boost-type active power factor correction circuit 10 of the PD system 100 includes a rectifier 12, a power switch Q1, an output diode DO1, an output capacitor CO1, and a boost inductor LM1, which can adjust the output power according to the AC voltage V supplied by the mains power. AC To provide a pulsating DC voltage VO1. In this embodiment of the invention, rectifier 12 may be a bridge rectifier, which includes rectifier diodes D1-D4, used to convert the AC voltage V supplied by the mains power into a pulsating DC voltage VO1. ACConverted to DC voltage V IN However, the implementation of rectifier 12 does not limit the scope of the present invention.

[0061] The first terminal of the boost inductor LM1 is coupled to the rectifier 12 to receive the DC voltage V. IN The first terminal is coupled to the anode of the output diode DO1, and can store the DC voltage V. IN The energy of the output capacitor CO1 is stored by connecting its first terminal to the cathode of the output diode DO1 and its second terminal to ground. IN The energy is used to provide a pulsating DC voltage VO1. The first terminal of the power switch Q1 is coupled to the anode of the output diode DO1, and the second terminal is coupled to the ground potential. The control terminal receives a control signal GD1, which can be used to perform high-frequency switching to allow the boost inductor LM1 to store and release energy, so that the input current follows the input voltage, thereby improving the power factor and reducing current harmonics.

[0062] The active clamp flyback converter circuit 20 of the PD system 100 includes a transformer TR, a power switch Q2, an active clamp switch Q3, a leakage inductor LR, a magnetizing inductor LM2, a clamping voltage capacitor CC, an output capacitor CO2, and an output diode DO2. The active clamp flyback converter circuit 20 can receive a pulsating DC voltage VO1 at its input and provide a pulsating DC voltage VO2 at its output.

[0063] The transformer TR includes a primary winding (represented by the number of turns NP), a secondary winding (represented by the number of turns NS), and a discharge winding (represented by the number of turns NX). The first terminal of the leakage inductance LR is coupled to the boost-type active power factor correction circuit 10, while the second terminal is coupled to the dotted terminal of the primary winding NP in the transformer TR. The first terminal of the magnetizing inductance LM2 is coupled to the dotted terminal of the primary winding NP in the transformer TR, while the second terminal is coupled to the non-dotted terminal of the primary winding NP in the transformer TR. The discharge winding NX of the transformer TR provides a discharge inductance LX. The first terminal of the clamping voltage capacitor CC is coupled to the pulsating DC voltage VO1, while the second terminal is coupled to the first terminal of the discharge inductance LX. The first terminal of the power switch Q2 is coupled to the non-dotted terminal of the primary winding NP in the transformer TR, the second terminal is coupled to ground potential, and the control terminal receives a control signal GD2. The first terminal of the active clamp switch Q3 is coupled to the non-spotted terminal of the primary winding NP of the transformer TR, and the second terminal is coupled to the first terminal of the discharge inductor LX. The control terminal receives a control signal GD3. The anode of the output diode DO2 is coupled to the non-spotted terminal of the secondary winding NS of the transformer TR, and the cathode is coupled to the output terminal of the active clamp flyback switching circuit 20. The first terminal of the output capacitor CO2 is coupled to the cathode of the output diode DO2, and the second terminal is coupled to the spotted terminal of the secondary winding NS of the transformer TR.

[0064] The pulsating DC voltage VO1 output by the boost-type active power factor correction circuit 10 is the input voltage of the active clamp flyback converter circuit 20, and can be transmitted to the dotted terminal of the primary winding NP in the transformer TR through the leakage inductor LR. The transformer TR can induce the energy of the corresponding pulsating DC voltage VO1 stored in the primary winding NP to the secondary winding NS, and the output capacitor CO2 can store the energy of the secondary winding NS to provide the pulsating DC voltage VO2. During the operation of the transformer TR, the relationship of the relevant voltages is V NP / V NS =NP / NS, where V NP V represents the transvoltage of the primary winding NP. NS This represents the voltage across the secondary winding NS, while in boost applications, the number of turns NS in the secondary winding is greater than the number of turns NP in the primary winding.

[0065] In the operation of the active clamp flyback switching circuit 20, the power switch Q2 and the active clamp switch Q3 operate in a complementary manner, meaning that the control signals GD2 and GD3 are out of phase at the same time, so that one set of switches is turned on while the other set of switches is turned off. The output diode DO2 and the active clamp switch Q3 operate synchronously, turning on or off simultaneously. When the power switch Q2 is on, the active clamp switch Q3 and the output diode DO2 are off. At this time, the leakage inductor LR and the magnetizing inductor LM2 will store the energy corresponding to the pulsating DC voltage VO1. When the power switch Q2 is off, the active clamp switch Q3 and the output diode DO2 are on. At this time, the energy stored in the leakage inductor LR will be absorbed by the clamping voltage capacitor CC to avoid high-frequency resonance loss caused by the parasitic capacitance of the leakage inductor LR and the power switch Q2. The energy stored in the magnetizing inductor LM2 is induced from the primary winding NP of the transformer TR to the secondary winding NS, and then supplied to the output capacitor CO2 via the output diode DO2 to store the relevant energy.

[0066] The output voltage communication circuit 30 of the PD system 100 includes a pulse width modulation integrated circuit (PWMIC), a comparator CP, a blocking switch QB, a logic circuit AND, a discharge switch QX, an output capacitor CO3, and a power transfer integrated circuit (PDIC1). The PWMIC includes pins P1 to P7, where pin P1 outputs a control signal GD1 to the control terminal of power switch Q1, pin P2 outputs a control signal GD2 to the control terminal of power switch Q2, pin P3 outputs a control signal GD3 to the control terminal of active clamp switch Q3, pin P4 outputs a control signal GDB to the control terminal of blocking switch QB, pin P5 outputs a control signal GDX to the control terminal of discharge switch QX, pin P6 receives a discharge control signal VA, and pin P7 outputs a reference voltage VF.

[0067] The first terminal of the blocking switch QB is coupled to the active clamp flyback switching circuit 20 to receive the pulsating DC voltage VO2, and the second terminal is coupled to the power supply pin Vbus of the connector PLUG1. The control terminal is coupled to pin P4 of the pulse width modulation integrated circuit (PWMIC) to receive the control signal GDB. The first terminal of the discharge switch QX is coupled to the second terminal of the discharge inductor LX, and the second terminal is coupled to the power supply pin Vbus of the connector PLUG1. The control terminal is coupled to pin P5 of the pulse width modulation integrated circuit (PWMIC) to receive the control signal GDX. The output capacitor CO3 is coupled between the power supply pin Vbus of the connector PLUG1 and the ground pin GND.

[0068] The positive input of comparator CP is coupled to the power supply pin Vbus of connector PLUG1, and the negative input is coupled to pin P7 of the pulse width modulation integrated circuit (PWMIC) to receive the reference voltage VF. The output is used to output a comparison signal Vp to the AND logic circuit. Comparator CP provides the comparison signal Vp based on the voltages at its positive and negative inputs: when the voltage at the power supply pin Vbus of connector PLUG1 is greater than the reference voltage VF, comparator CP outputs a comparison signal Vp with a first potential (e.g., high); when the voltage at the power supply pin Vbus of connector PLUG1 is not greater than the reference voltage VF, comparator CP outputs a comparison signal Vp with a second potential (e.g., low).

[0069] The logic circuit AND includes pins P8 to P10. The first input pin P8 is coupled to the output of comparator CP to receive a comparison signal Vp. The second input pin P9 is coupled to the power transfer integrated circuit PDIC to receive a connection signal Vc. The output pin P10 is coupled to pin P6 of the pulse width modulation integrated circuit PWMIC to provide a discharge control signal VA. In this embodiment, the logic circuit AND can be an AND gate. When both the comparison signal Vp received by the first input pin P8 and the connection signal Vc received by the second input pin P9 are high, the logic circuit AND outputs a high-level discharge control signal VA. When neither the comparison signal Vp received by the first input pin P8 nor the connection signal Vc received by the second input pin P9 are high, the logic circuit AND outputs a low-level discharge control signal VA.

[0070] The power delivery integrated circuit PDIC2 includes pins P11 to P12, where the input pin P11 is coupled to the configuration channel pins CC1 / CC2 of the connector PLUG1, and the output pin P12 is coupled to pin P9 of the logic circuit AND. For example... Figure 4 As shown, after the PD charger 110 and the PD charging device 120 are connected, the configuration channel pins CC1 / CC2 of connector PLUG1 and connector JACK2 are connected to each other. The constant power supply provided by the PD charger 110 will be applied to the pull-down resistor R of the PD charging device 120. DA pull-down voltage Vd is established. When the input pin P11 of the power delivery integrated circuit PDIC2 detects the pull-down voltage Vd, it outputs a connection signal Vc with a second potential (e.g., a low-potential negative saturation voltage) to the pin P9 of the logic circuit AND. When it is determined that the pull-down voltage Vd falls within the correct voltage range, the power delivery integrated circuit PDIC2 instructs the pulse width modulation integrated circuit PWMIC to provide a drive signal GDB with an enable potential on its pin P4 to turn on the blocking switch QB, so that the pulsating DC voltage VO2 can be transferred to the output capacitor CO3 to store energy, so as to power the Vbus pin of the connector PLUG1 to the Vbus pin of the connector JACK2. Then, the configuration channel pins CC1 / CC2 of the connector PLUG1 and the configuration channel pins CC1 / CC2 of the connector JACK2 communicate continuously, so that the PD charger 110 raises the voltage of the Vbus pin of the connector PLUG1 to the voltage required for the operation of the PD charging device 120.

[0071] When the user disconnects the PD charger 110 from the PD charging device 120, the configuration channel pins CC1 / CC2 of connector PLUG1 and connector JACK2 are separated from each other. At this time, the PD charger 110 has no output (the voltage of the Vbus pin of connector PLUG1 is 0). When the pin of the power delivery integrated circuit PDIC2 does not detect the pull-down voltage Vd, it outputs a connection signal Vc with a first potential (e.g., a high-potential positive saturation voltage) to the pin P9 of the logic circuit AND, and instructs the pulse width modulation integrated circuit PWMIC to provide a control signal GDB with a de-energizing potential on its pin P4 to turn off the blocking switch QB.

[0072] As mentioned earlier, after the user unplugs the PD charger 110 from the PD charging device 120, the input capacitor CO3 of the PD charger 110 can maintain the potential of the Vbus pin of the connector PLUG1 for a period of time, while the potential of the Vbus pin of the connector JACK2 in the PD charging device 120 will drop rapidly. According to the USB Type-C related PD specifications, when the voltage difference between the power supply pin Vbus of the PD charger 110 and the power supply pin Vbus of the PD charging device 120 is greater than 12V, there is a high probability of arcing. Therefore, in this embodiment of the invention, the reference voltage VF can be set to 12V (but this does not limit the scope of the invention).

[0073] In this invention, the comparison voltage Vp provided by the comparator CP indicates whether the power supply of the PD charger 110 is a high-voltage application, while the connection signal Vc provided by the power transfer integrated circuit PDIC2 indicates whether the PD charger 110 and the PD charging device 120 are connected to each other. Under normal PD operation with the PD charger 110 and the PD charging device 120 connected, the power supply pins Vbus of the PD charger 110 and the PD charging device 120 will have the same voltage (voltage difference is 0), and there is no risk of arcing. After the user unplugs the PD charger 110 from the PD charging device 120, if the power supply of the PD charger 110 is not a high-voltage application, the probability of arcing caused by the voltage difference between the power supply pins Vbus of the PD charger 110 and the PD charging device 120 is very small. More specifically, when the AND logic circuit of the present invention determines, based on the comparison voltage Vp and the connection signal Vc, that "the power supply of the PD charger 110 is a high voltage application" and "the PD charger 110 and the PD charging device 120 are separated from each other" are not simultaneously true, its output discharge control signal VA will instruct the pulse width modulation integrated circuit PWMIC to output a control signal GDX with a de-energizing potential to turn off the discharge switch QX.

[0074] When the AND logic circuit of the present invention determines, based on the comparison voltage Vp and the connection signal Vc, that "the power supply of the PD charger 110 is a high voltage application" and "the PD charger 110 and the PD charging device 120 are separated from each other" are both true, the output discharge control signal VA will instruct the pulse width modulation integrated circuit PWMIC to output a control signal GDX with an enable potential to turn on the discharge switch QX, thereby coupling the second end of the discharge inductor LX to the power supply pin Vbus of the connector PLUG1.

[0075] Figure 6 This is a schematic diagram of the fast discharge path of the output capacitor resonant circuit provided by the PD system 100 in this embodiment of the invention. As mentioned earlier, the condition for the discharge switch QX to be turned on by the control signal GDX is that the power transfer integrated circuit PDIC2 detects the pull-down voltage Vd (representing that the PD charger 110 is connected to the PD charging device 120), and the comparator CP determines that the voltage of the power supply pin Vbus of the connector PLUG1 is greater than the reference voltage VF (representing that the power supply of the PD charger 110 is a high voltage application, which may cause an arc at the moment of disconnection). When the discharge switch QX is turned on by the control signal GDX, the output capacitor CO3, the discharge inductor LX, the clamping voltage capacitor CC, and the output capacitor CO1 will form Figure 5 The diagram shows the rapid discharge path of the output capacitor resonantly. The energy stored in the output capacitor CO3 can be rapidly discharged to ground potential (e.g., through the discharge inductor LX, clamping voltage capacitor CC, and output capacitor CO1) sequentially. Figure 5(As indicated by the arrow in the image), to reduce the voltage difference between the power supply pin Vbus voltage in the connector PLUG1 of the PD charger 110 and the power supply pin Vbus voltage in the connector PLUG2 of the PD charging device 120 at the moment of disconnection, thereby improving the arcing phenomenon.

[0076] Figure 7 This is a schematic diagram showing the potential and connection relationship of the power supply pin Vbus in the PD system 100 of this embodiment of the invention. The vertical axis represents the voltage value, the horizontal axis represents time, V1' represents the power supply pin Vbus voltage of the PD charger 110, and V2 represents the power supply pin Vbus voltage of the PD charging device 120. Before time point T1, the PD charger 110 normally supplies power to the PD charging device, at which time V1' = V2. Assuming that at time point T1, the user unplugs the PD charger 110 from the PD charging device 120, the output capacitor resonant fast discharge path composed of the output capacitor CO3, discharge inductor LX, clamping voltage capacitor CC, and output capacitor CO1 can quickly discharge the energy stored in the output capacitor CO3, thereby improving the arcing phenomenon.

[0077] In this embodiment of the invention, the power switches Q1-Q2, the active clamp switch Q3, the discharge switch QX, and the blocking switch QB can be metal-oxide-semiconductor field-effect transistors (MOSFETs), bipolar junction transistors (BJTs), or other components with similar functions. For N-type transistors, the enable potential is high, and the disable potential is low; for P-type transistors, the enable potential is low, and the disable potential is high. However, the types of switches described above do not limit the scope of this invention.

[0078] In summary, the PD system of this invention detects the coupling state between the PD charger and the PD charging device, and determines whether the power supply of the PD charger is for a high-voltage application. When it is determined that the power supply of the PD charger is for a high-voltage application, once the PD charger and the PD charging device are detected to be disconnected from each other, this invention provides a rapid discharge path for the output capacitor resonance to quickly lower the output voltage of the PD charger, thereby improving the arcing phenomenon.

[0079] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made within the scope of the claims of the present invention should be included in the scope of the present invention.

Claims

1. A power transmission device capable of mitigating electric arc phenomena, comprising: A first power supply pin is used to supply power to a second power supply pin of a power transmission charging device; A first configuration channel pin is used to receive a pull-down voltage when coupled to a second configuration channel pin of the power delivery charging device; A boost-type active power factor correction circuit is used to convert an AC voltage supplied by mains power into a first pulsating DC voltage, comprising: A first output capacitor is used to store the energy of the first pulsating DC voltage; A first power switch, comprising: One of the first terminals is coupled to one of the first terminals of the output capacitor; A second terminal is coupled to a second terminal of the output capacitor; and A control terminal is used to receive a first control signal; An active clamp flyback converter circuit is used to convert the first pulsating DC voltage into a second pulsating DC voltage, comprising: A transformer, used to induce energy from a primary side to a secondary side of a first pulsating DC voltage to supply the second pulsating DC voltage, comprises: A primary winding is provided on the primary side, which includes a first dotted end and a first non-dotted end; A primary winding, disposed on the secondary side, includes a second dotted terminal and a second non-dotted terminal; and A discharge winding is used to provide a discharge inductance; A clamping voltage capacitor, comprising: A first terminal is coupled to the boost-type active power factor correction circuit to receive the first pulsating DC voltage; and A second terminal is coupled to a first terminal of the discharge inductor; A second power switch, comprising: One of the first ends is coupled to the first non-dot end; A second terminal is coupled to a ground potential; and One control terminal is used to receive a second control signal; An active clamping switch, comprising: One of the first ends is coupled to the first non-dot end; A second terminal is coupled to the first terminal of the discharge inductor; and One control terminal is used to receive a third control signal; A second output capacitor, with its first end coupled to the first power supply pin and its second end coupled to a ground pin, is used to store the energy of the second pulsating DC voltage; and An output voltage communication circuit is used to selectively couple a second end of the discharge inductor to the first power supply pin based on the potential of the first power supply pin and the potential of the first configuration channel pin.

2. The power transmission device of claim 1, wherein when the potential of the first power supply pin is higher than a reference voltage and the value of the pull-down voltage is not within a predetermined range, the output voltage communication circuit couples the second terminal of the discharge inductor to the first configuration channel pin, so that the energy of the second output capacitor is discharged sequentially through the discharge inductor, the clamping voltage capacitor and the first output capacitor to the ground potential.

3. The power transmission device as claimed in claim 1, wherein the active clamp flyback conversion circuit further comprises: A leakage inductance, which includes: A first terminal, coupled to the first terminal of the clamping voltage capacitor; and A second end, coupled to the first dotted end; and A magnetizing inductor, which includes: A first end, coupled to the first dot end; and The second end is coupled to the first non-dot end.

4. The power transmission device as claimed in claim 1, wherein the active clamp flyback conversion circuit further comprises: An output diode, the anode of which is coupled to the second non-pointed terminal of the secondary winding in the transformer; and A second output capacitor, the first end of which is coupled to a cathode of the output diode, and the second end of which is coupled to a second dot terminal of the secondary winding in the transformer.

5. The power transmission device as claimed in claim 2, wherein the output voltage communication circuit comprises: A pulse width modulation integrated circuit, comprising: A first pin is used to output the first control signal; A second pin is used to output the second control signal; A third pin is used to output the third control signal; A fourth pin is used to output a fourth control signal; The fifth pin is used to output a fifth control signal; A sixth pin is used to receive a discharge control signal; and A seventh pin is used to output a reference voltage; A comparator, which includes: A positive input terminal is coupled to the first power supply pin; A negative input terminal is coupled to the seventh pin of the pulse width modulation integrated circuit to receive the reference voltage; and One output terminal is used to output a comparison signal; A power delivery integrated circuit, comprising: An input terminal is coupled to the first configuration channel pin; and One output terminal is used to output a connection signal; A logic circuit, comprising: A first input terminal is coupled to the output terminal of the comparator to receive the comparison signal; A second input terminal is coupled to the output terminal of the power delivery integrated circuit to receive the connection signal; and An output terminal is provided to output the discharge control signal to the sixth pin of the pulse width modulation integrated circuit; and A discharge switch, comprising: One of the first terminals is coupled to a second terminal of the discharge inductor; A second terminal is coupled to the first configuration channel pin; and A control terminal is coupled to the fifth pin of the pulse width modulation integrated circuit to receive the fifth control signal.

6. The power transmission device as claimed in claim 5, wherein: When the voltage of the first power supply pin is higher than the reference voltage, the comparator outputs a comparison signal with a first potential; When the voltage of the first power supply pin is not higher than the reference voltage, the comparator outputs a comparison signal with a second potential; When the value of the pull-down voltage received by the input terminal of the power supply integrated circuit from the first power supply pin is not within the predetermined range, the power supply integrated circuit outputs the connection signal with a third potential. When the value of the pull-down voltage received by the input terminal of the power supply integrated circuit from the first power supply pin is within a predetermined range, the power supply integrated circuit outputs the connection signal with a fourth potential. When the first input terminal of the logic circuit receives the comparison signal with the first potential, and when the second input terminal of the logic circuit receives the connection signal with the third potential, the logic circuit outputs the discharge control signal with a fifth potential. When the sixth pin of the pulse width modulation integrated circuit receives the discharge control signal with the fifth potential, the pulse width modulation integrated circuit outputs the fifth control signal with the same potential to turn on the discharge switch. The first potential is different from the second potential; and The third potential is different from the fourth potential.

7. The power transmission device as claimed in claim 6, wherein: This logic circuit is an AND gate; The first potential and the third potential are each a high potential; and The second potential and the fourth potential are each a low potential.

8. The power transmission device as claimed in claim 5, wherein the output voltage communication circuit further comprises: A blocking switch, comprising: One terminal is coupled to the active clamp flyback converter circuit to receive the second pulsating DC voltage; A second terminal is coupled to the first configuration channel pin; and A control terminal, the fourth pin of the pulse width modulation integrated circuit is used to receive the fourth control signal.

9. The power transmission device as claimed in claim 1, wherein the boost-type active power factor correction circuit further comprises: A rectifier is used to convert the AC voltage into a DC voltage. A boost inductor, the first terminal of which is coupled to the rectifier to receive the DC voltage, and the second terminal of which is coupled to the first terminal of the first power switch to store the energy of the DC voltage; and An output diode, the anode of which is coupled to the second terminal of the boost inductor, and the cathode of which is coupled to the first output capacitor.

10. The power transmission device as claimed in claim 1, wherein the communication interface is a USB Type-C interface.

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