Low-ripple four-tube boost-buck switching power supply control circuit with enhanced transient response

Abstract

The application provides a low-ripple four-tube step-up and step-down switching power supply control circuit capable of enhancing transient response, comprising a sample and hold circuit, an error amplifier EA, a timing circuit, a volt-second balance circuit, a high-level sampling circuit, a logic control circuit and a driving circuit; the application adopts inductance front-end sampling, has a voltage double-loop sampling mode and has a better linear regulation rate compared with a traditional four-tube step-up and step-down circuit. The application adopts DCM conduction, CCM conduction under heavy load, and realizes the restart of the timer by adding a reset signal, thereby avoiding the disorder of the timing signal caused by the change of two timing signals due to the change of loop load and the like.

Description

Technical Field

[0001] This invention relates to switching power supply circuits, and more particularly to a low-ripple four-transistor buck-boost switching power supply control circuit that can enhance transient response. Background Technology

[0002] In power management systems, switching power supplies are widely used due to their advantages such as wide voltage ramp-up / buck range and high efficiency. With increasing emphasis on low power consumption, switching power supplies need to operate at lower output voltages and higher output currents. Four-transistor buck-boost circuits (FSBBs) are primarily used in various consumer electronics products and new energy vehicles due to their excellent characteristics of wide voltage range and high power output. Isolated FSBBs offer good reliability and electrical isolation, and are divided into primary-side sampling and secondary-side sampling. Secondary-side sampling has low ripple and good transient response, while primary-side sampling has linear compensation and constant current characteristics. To achieve lower ripple, secondary-side sampling is generally used, which requires higher loop compensation.

[0003] The FSBB has three operating states: First stage: Q1 and Q4 are turned on, energy storage stage, charging the primary inductor. Second stage: Q2 and Q3 are turned on, energy transfer stage, power transfer to the secondary side through the transformer coil. Third stage: Q2 and Q4 are turned on, current clamping stage, resetting the inductor current and turning on Q1 via ZVS through the inductor reverse current. This completes the DCM conduction process.

[0004] To ensure high conversion efficiency, all four switching transistors need to operate under ZVS soft-switching, which requires inserting a certain dead time between switching intervals to achieve ZVS conduction. Simultaneously, the switching power supply circuit has multiple control modes, including single-mode, dual-mode, and multi-mode control, to accommodate different loads and operating frequencies. To cover a wider range of load variations, sampling multi-mode control is needed to achieve higher efficiency. The transformer primary inductance may generate a large reverse current during power transmission, which can cause current backflow in the next conduction cycle, reducing the efficiency of the switching power supply. This invention samples the inductor current and turns off transistor Q3 in time before current backflow occurs in the primary inductance.

[0005] To achieve faster transient response and improve the linear regulation of the switching power supply, this paper improves the linear regulation through advance sampling, and adopts an adaptive multi-mode operating environment and makes all four transistors operate in ZVS conduction mode to achieve soft switching and improve efficiency. Summary of the Invention

[0006] Objective of the Invention: To further improve the performance of FSBBs, this invention aims to increase the linear regulation and reduce ripple to improve efficiency. It proposes a method using inductor front-end sampling to improve the linear regulation of switching power supplies. Simultaneously, it adopts DCM mode for the on-state control and can adaptively change the operating frequency and duty cycle to improve efficiency when the load changes.

[0007] Technical solution:

[0008] To achieve the above objectives, the present invention employs the following technical solution in a four-transistor buck-boost switching power supply circuit:

[0009] A low-ripple four-transistor buck-boost switching power supply control circuit that enhances transient response includes a sample-and-hold circuit, an error amplifier EA, a timing circuit, a volt-second balancing circuit, a high-level sampling circuit, a logic control circuit, and a driver circuit.

[0010] The positive terminal of the input voltage VIN is connected to the drain of power transistor Q1, and its negative terminal is connected to the source terminals of power transistors Q2 and Q4, as well as one end of capacitor C1 and resistor R2. The source terminal of power transistor Q1 is connected to the drain terminal of power transistor Q2 and one side of the primary winding of the transformer. The source terminal of power transistor Q3 and the drain terminal of power transistor Q4 are connected to the other end of the primary winding of the transformer. The drain terminal of power transistor Q3 is connected to one end of resistor R1 and capacitor C1. Resistor R2 is connected to resistor R1. One side of the secondary winding of the transformer is grounded and simultaneously connected to one end of capacitor C2, impedance ROUT, and resistor R3. The other side is connected to the positive terminal of the diode. The negative terminal of the diode is connected to capacitor C2, impedance ROUT, resistor R3, and the output terminal VOUT.

[0011] The input of the sample-and-hold circuit is connected to resistor R2 when sampling on the primary side and resistor R3 when sampling on the secondary side. The output of the sample-and-hold circuit is connected to the non-inverting input of error amplifier EA. The inverting input of error amplifier EA is connected to the reference voltage source VREF. The output Verr of the error amplifier is connected to the input of the timing circuit. The positive terminal VL+ and the negative terminal VL- of the transformer primary inductor are connected to one 1 / K sampler. The outputs of the two 1 / K samples are connected to the input of the volt-second balancing circuit. One of the 1 / K samples is also connected to the input of the high-level sampling circuit. The volt-second balancing output Q3B is connected to the input of the logic control circuit. The output of the high-level sampling circuit is connected to the input of the timing circuit. The output of the timing circuit is connected to the logic control circuit. The output of the logic control circuit is connected to the driver circuit. The driver circuit outputs control signals Q1, Q2, Q3, and Q4.

[0012] Preferably, the high-level sampling circuit includes a first delay unit, a first AND gate, and a third switch:

[0013] The control signal Q1 is used to provide the control signal for the third switch through the first delay unit and the first AND gate.

[0014] Preferably, the timing circuit includes a first timer and a second timer. The first timer includes a first voltage-controlled current source, a capacitor C3, a first switch, a first SR flip-flop, a fourth delay unit, a fifth delay unit, a sixth delay unit, a first comparator, and a first pulse generator.

[0015] The input terminal of the first voltage-controlled current source is connected to the output Verr of the error amplifier EA. The output of the first voltage-controlled current source is connected to capacitor C3 and the positive terminal of the first comparator. The output of the first comparator is connected to the fourth delay unit and generates a control signal Q1ST through the first pulse generator. Then, it generates Q1ON through the control signal Q4 and the conduction judgment signal. At the same time, the output of the first pulse generator is connected to the fifth delay unit and the S terminal of the first SR flip-flop. The R terminal of the first SR flip-flop is connected to the output of the second timer after passing through the sixth delay unit and the third pulse generator. The output terminal Q of the first SR flip-flop is connected to the control terminal of the first switch. The first switch is connected across capacitor C3.

[0016] The second timer includes a second voltage-controlled current source, capacitor C4, a second switch, a second SR flip-flop, a second comparator, a second delay unit, and a third delay unit.

[0017] The input terminal of the second voltage-controlled current source is connected to the third switch. The other end of the third switch is connected to the sampling signal VL+1 / K of the positive terminal of the primary inductor of the transformer. This signal is then weighted with the bias voltage Vbias and connected to the negative terminal of the first comparator of the first timer. The output terminal of the second timer is connected to capacitor C4 and the positive terminal of the second comparator. The negative terminal of the second comparator is connected to the output Verr of the error amplifier EA. The output of the second comparator is connected to an inverter and a second pulse generator through the second delay unit. The second pulse generator generates a control signal Q2ST, which is connected to the S terminal of the second SR flip-flop through the third delay unit. The R terminal of the second SR flip-flop is connected to the signal Q1ON generated by the first timer. The output terminal Q of the second SR flip-flop is connected to the control signal of the second switch. The second switch is connected across capacitor C4.

[0018] Preferably, the logic control circuit includes a third comparator, a third SR flip-flop, a second AND gate, a fourth AND gate, a third AND gate, a fifth AND gate, a fourth pulse generator, a fourth SR flip-flop, a fifth SR flip-flop, a sixth SR flip-flop, a seventh delay unit, an eighth delay unit, a ninth delay unit, a tenth delay unit, and a fifth pulse generator.

[0019] An external fixed bias Vbias is connected to the positive terminal of the third comparator. The negative terminal of the third comparator is connected to the negative terminal of the primary inductor to sample the signal VL-1 / K. The output of the third comparator is connected to one end of the second and third AND gates. The other end of the third AND gate is connected to the NOT output of the third SR flip-flop. The signal after passing through the seventh delay unit is connected to the output of the third AND gate, which is connected to the S terminal of the fourth pulse generator and the fourth SR flip-flop. The R terminal of the fourth SR flip-flop is connected to the control signal Q2ST, and the output Q of the fourth SR flip-flop is connected to the control signal Q4. The output Q of the fifth SR flip-flop is connected to the other end of the second AND gate, and the output of the second AND gate is connected to the S terminal of the sixth SR flip-flop. The R terminal of the sixth SR flip-flop is also connected to Q2ST, and the output Q of the sixth SR flip-flop is connected to the eighth delay unit to generate Q1, and the NOT output terminal of the sixth SR flip-flop is connected to the sixth SR flip-flop. The signal is transmitted through the fifth pulse generator and the ninth delay unit to the S terminal of the third SR flip-flop, while the NOT output terminal of the sixth SR flip-flop is connected to the Ninth SR flip-flop. Connect one end of the fourth AND gate, and the other end of the fourth AND gate is Q1, which is connected to the inverter and the output of the tenth delay unit. The fourth AND gate outputs signal Q2. Signal Q3B passes through the sixth pulse generator and is connected to the R terminal of the third SR flip-flop. The output Q of the third SR flip-flop is connected to one end of the fifth AND gate, and the other end of the fifth AND gate is connected to signal Q2. The fifth AND gate outputs signal Q3.

[0020] Preferably, the sample-and-hold circuit includes an input signal VSEN connected to one end of a fourth switch via a follower, the fourth switch connected to signal Q3, the other end of the fourth switch connected to capacitor C5 and the input of the follower, the output of the follower connected to resistor R4, the other end of R4 connected to the non-inverting input terminal of error amplifier EA, and one end of resistor R5 and capacitor C7, the other end of resistor R2 connected to capacitor C6, the other ends of capacitors C6 and C7 connected to the output Verr of error amplifier, and the inverting terminal of error amplifier connected to reference voltage source VREF.

[0021] Preferably, the volt-second balancing circuit controls the Q3 turn-off circuit. The sampling signal VL+1 / K at the positive terminal of the primary inductor is connected to the follower input. The follower output is connected to one end of resistor R5. The other end of resistor R5 is connected to resistors R6 and R7 and the non-inverting terminal of the operational amplifier. The other end of resistor R6 is grounded. The other end of resistor R7 is connected to the external bias signal Vtr1. The sampling signal VL-1 / K at the negative terminal of the primary inductor is connected to the follower input. The follower output is connected to one end of resistor R8. The other end of resistor R8 is connected to the inverting terminal of the operational amplifier and one end of resistor R9. The other end of resistor R9 is connected to the operational amplifier output, one end of the fifth switch, and the positive terminal of the fourth comparator. Signal Q1 is connected to the R terminal of the seventh SR flip-flop. Q1ON is connected to the S terminal of the seventh SR flip-flop. The Q output of the seventh SR flip-flop is connected to the switch control signal. The external bias voltage Vtr2 is connected to one end of resistor R10. The other end of resistor R10 is connected to the other end of the fifth switch, capacitor C8, and the negative terminal of the fourth comparator. The output of the fourth comparator generates the Q3B signal.

[0022] Beneficial effects:

[0023] 1. This invention uses inductor front-end sampling and has a voltage dual-loop sampling mode, which has a better linear regulation rate compared with the traditional four-transistor buck-boost circuit.

[0024] 2. This invention employs DCM conduction and CCM conduction under heavy load. The timer is restarted by adding a reset signal, which avoids the timing signals from becoming disordered due to changes in loop load or other reasons. Attached Figure Description

[0025] Figure 1 This is a system block diagram of the FSBB dual-voltage sampling multi-mode control architecture of the present invention;

[0026] Figure 2 This is a schematic diagram illustrating the specific implementation of the dual-voltage loop sampling control of the present invention;

[0027] Figure 3 This is a schematic diagram of the sample-and-hold and error amplification circuit and the volt-second balance circuit of the present invention;

[0028] Figure 4 (a) is the Cadence simulation result of the transient linear regulation rate of the overall loop using secondary side sampling in the single voltage loop and the dual voltage loop of the present invention;

[0029] Figure 4 (b) is the Cadence simulation result of the transient linear regulation rate of the overall loop using primary-side sampling, comparing the single voltage loop and the dual voltage loop of the present invention;

[0030] Figure 5 This is a Cadence simulation diagram of the output voltage ripple after the circuit loop of this invention has stabilized. Detailed Implementation

[0031] To facilitate understanding of the present invention, a more complete description will be given below with reference to the accompanying drawings. Preferred embodiments of the invention are shown in the drawings. However, the invention can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

[0032] Figure 1This is a system block diagram of the FSBB dual-voltage sampling multi-mode control architecture of the present invention. Four power transistors are driven by control signals Q1, Q2, Q3, and Q4, respectively. The positive terminal of the input voltage VIN is connected to the drain of transistor Q1, and the negative terminal of VIN is connected to the source terminals of transistors Q2 and Q4, as well as one end of capacitors C1 and resistor R2. The source terminal of Q1 is connected to the drain terminal of Q2 and one side of the primary winding of the transformer. The source terminal of Q3 is connected to the drain terminal of Q4 and the other end of the primary winding of the transformer. The drain terminal of Q3 is connected to one end of resistors R1 and C1, and R2 is connected to R1. One side of the secondary winding of the transformer is grounded and connected to one end of capacitors C2, ROUT, and R3. The other side is connected to the positive terminal of a diode. The negative terminal of the diode is connected to C2, ROUT, R3, and the output terminal VOUT. The input terminal of the sample-and-hold circuit is connected to resistor R2 during primary-side sampling and to resistor R3 during secondary-side sampling. The output of the sample-and-hold circuit is connected to the non-inverting input terminal of an error amplifier (EA). The inverting input terminal of the error amplifier is connected to a reference voltage source (VREF), and the output (Verr) of the error amplifier is connected to the timer input terminal. The positive and negative terminals (VL+, VL-) of the transformer primary inductance are connected to 1 / K sampling, with the sampling value being 1 / K times the original value. The 1 / K sampling output is connected to the input of the volt-second balancing circuit and the high-level sampling input. The volt-second balancing output (Q3B) is connected to the input of the logic control circuit. The high-level sampling output is connected to the input of the timing circuit. The output of the timing circuit is connected to the logic control circuit. The output of the logic control circuit is connected to the driver circuit, which outputs control signals Q1, Q2, Q3, and Q4.

[0033] Its working principle is as follows: The output voltage is determined by the secondary sampling resistor R3. The sampled value is then processed by the timing circuit, and the error amplifier generates the output Verr. This output Verr, along with the high-level sampling result, controls the timing circuit. The speed of the timer affects the generation of Q1 and Q2 signals in the subsequent logic control circuit. Specifically, a rise in Verr accelerates the conduction of Q1 and slows down the conduction of Q2. A rise in the input voltage causes a synchronous rise in the potential sampling at the inductor's front end, leading to a rise in the high-level sampling result, which in turn slows down the conduction of Q1 and accelerates the conduction of Q2. This results in a faster response to input fluctuations and improved linear regulation. Simultaneously, the inductor current is sampled. The left side VL+ and the right side VL- are used by the volt-second balance circuit to determine the operating state of the inductor and the loop, and to provide a timely turn-off signal for Q3. Finally, the logic control circuit modulates the dead time between different control signals and provides control signals to the switching transistors through the driver circuit.

[0034] Figure 2This is a schematic diagram of the dual-sampling control implementation of the present invention, including the implementation diagram of the high-level sampling circuit, timing circuit, and logic control circuit. In the high-level sampling circuit, the Q1 signal, after passing through a delay unit and an AND gate, provides a switch control signal. The sampling signal (VL+ / K) at the positive terminal of the primary inductor is connected to one end of the switch via a follower, and the other end is connected to the input terminal of the voltage-controlled current source of Timer 2. The other end is simultaneously weighted with the bias voltage Vbias and connected to the negative terminal of the comparator of Timer 1. The output terminal of Timer 2 is connected to capacitor C2 and the positive terminal of the comparator. The negative terminal of the comparator is connected to the output of the error amplifier (Verr). The comparator output, after passing through a delay unit, is connected to an inverter and a pulse generator. The pulse generator generates the Q2 control signal (Q2ST), which is simultaneously connected to the S terminal of the SR flip-flop through the delay unit. The R terminal is connected to the Q1ON signal generated by Timer 1. The Q terminal of the SR flip-flop output is connected to the control signal of the switch, and the switch is connected across capacitor C2. The input of the voltage-controlled current source of Timer 1 is connected to the output of the error amplifier (Verr). The output of the voltage-controlled current source is connected to capacitor C1 and the positive terminal of the comparator. The output of the comparator is connected to the delay unit and generates the Q1 control signal (Q1ST) through the pulse generator. Then, the Q1ON signal is generated through the Q4 conduction judgment signal. At the same time, the output of the pulse generator is connected to the S terminal of the SR flip-flop through the delay unit, and the R terminal is connected to the output of the inverter of Timer 2 after passing through the delay unit and the pulse generator. The Q terminal of the SR flip-flop is connected to the switch control terminal, and the switch is connected across capacitor C1. In the logic control circuit, the external fixed bias (Vbias) is connected to the positive terminal of the comparator, and the negative terminal is connected to the sampling signal (VL- / K) at the negative terminal of the primary inductor. The comparator output is connected to one end of two AND gates. The other end of one of the AND gates is connected to the signal from the delay unit after passing through the Q-not output of the SR flip-flop. The output of the AND gate is connected to the pulse generator and then to the S terminal of the SR flip-flop. The R terminal is connected to Q2ST, and the Q terminal of the SR flip-flop outputs the Q4 control signal. The S-terminal of the SR flip-flop controlled by Q1ST is connected to the other end of an AND gate. The output of the AND gate is connected to the S-terminal of the SR flip-flop, and its R-terminal is connected to Q2ST. The Q-terminal of the SR flip-flop is connected to a delay unit to generate Q1. The NOT terminal of Q is connected to the S-terminal of the SR flip-flop via a pulse generator and a delay unit. Simultaneously, the NOT terminal of Q is connected to one end of the AND gate, and the other end is connected to Q1, which is then connected to the output of an inverter connected to a delay unit. The AND gate outputs Q2 to generate a signal. Q1 is connected to the inverter output and fed back to the R-terminal of the SR flip-flop in Q1ST. Q3B is connected to the R-terminal of the SR flip-flop via a pulse generator. The Q-terminal of the SR flip-flop is connected to one end of an AND gate, and the other end is connected to Q2. The AND gate outputs Q3 to generate a signal.

[0035] The principle is as follows: High-level sampling obtains the voltage value VL+ / K at the left end of the transformer's primary inductance through a follower. This value is one-K times the input voltage when Q1 is on, and zero at other times. Therefore, Q1 is used to achieve high-level sampling of this voltage. Timer 2 controls the controlled current source to charge the load C2 through a high-level sampling, and compares this charge with the error amplifier output Verr via a comparator to generate the Q2 turn-on signal Q2ST. Timer 2 is restarted when Q1 generates the turn-on signal. Timer 1 controls the controlled current source to charge the load C1 through Verr, and compares the result with the weighted average of the external bias Vbias and the high-level sample value via a comparator to generate the Q1 turn-on signal Q1ST. Timer 1 is restarted by the Q2 turn-on signal. By defining restart signals between timers, the timing discrepancies caused by changes in the loop conditions when timers are timed separately are avoided. The logic control circuit compares the sampled voltage at the inductor's back end with a fixed bias using a comparator to determine if the ZVS condition for Q4 to turn on is met, and controls Q4 to conduct. Q3B is the output value of the volt-second balance terminal of the front module. After the volt-second balance judgment indicates that the inductor has completed one cycle of charging and discharging, the output Q3B controls the turn-off of Q3. The output Q1ST of Timer 1 controls the conduction of Q1 and the turn-off of Q2, while the output Q2ST of Timer 2 controls the conduction of Q2 and Q3 and the turn-off of Q1 and Q4. Simultaneously, the logic control circuit inserts dead time between the energy storage stage, energy transfer stage, and current clamping stage by inserting delay units.

[0036] Figure 3 The sample-and-hold, error amplification, and volt-second balancing circuit used in this invention has the following characteristics: The sample-and-hold circuit input VSEN is connected to one end of a switch via a follower. The switch control signal is connected to Q3. The other end of the switch is connected to capacitor C3 and the follower input. The follower output is connected to resistor R1. The other end of R1 is connected to the non-inverting input of the error amplifier (EA), and one end of resistors R2 and C1. The other end of R2 is connected to C2. The other ends of C1 and C2 are connected to the error amplifier output (Verr). The inverting terminal of the error amplifier is connected to a reference voltage source (VREF). The volt-second balancing control Q3 turns off the circuit. The sampling signal (VL+ / K) at the positive terminal of the primary inductor is connected to the follower input. The follower output is connected to one end of R3. The other end of R3 is connected to R4, R5, and the non-inverting terminal of the operational amplifier. The other end of R4 is grounded. The other end of R5 is connected to an external bias signal (Vtr1). The sampling signal (VL- / K) at the negative terminal of the primary inductor is connected to the input of the follower. The follower output is connected to one end of resistor R6. The other end of R6 is connected to the inverting input of the op-amp and one end of resistor R7. The other end of R7 is connected to the op-amp output, one end of the switch, and the positive terminal of the comparator. Q1 is connected to the R terminal of the SR flip-flop, and Q1ON is connected to the S terminal of the SR flip-flop. The Q terminal of the SR flip-flop is connected to the switch control signal. An external bias voltage (Vtr2) is connected to one end of resistor R8. The other end of R8 is connected to the other end of the switch, capacitor C4, and the negative terminal of the comparator. The comparator output generates the Q3B signal.

[0037] The principle is as follows: the output terminal is sampled through a follower, Q3 signal, and sampling capacitor C3. Then, the sampled signal and the reference signal are compared by an error amplifier to output Verr, which further controls the timer. R1, R2, C1, and C2 are used to implement type II compensation for the loop, and the poles and zeros introduced are shown in (1):

[0038]

[0039] Among them, Verr and V + These are the output and non-inverting input of the error amplifier, respectively. The type II compensation is a loop with two poles at frequencies of 0 and (C1+C2) / R2C1C2, and a zero at frequency of 1 / R2C2.

[0040] The volt-second balancing circuit samples the voltage difference across the inductor using two followers, then obtains the inductor current waveform through a subtractor. Adjusting Vtr1 increases the subtractor's output value, shifting Vtr1 upwards from its original value. Adjusting Vtr2 determines the charging speed of the RC charging network composed of R8 and C4, charging capacitor C4 during the sampling interval, with the charging speed increasing as Vtr2 increases. Finally, a comparator determines the generation of the Q3 turn-off signal Q3B before volt-second balancing.

[0041] Figure 4 This document presents Cadence simulation results of the transient linear regulation of the entire loop, using a 0.5µm SOI process with an input environment switching from 150V to 100V, an output voltage of 22.8V, a load of 22A, and a switching frequency of 250kHz. The results show that the linear regulation of the dual-voltage loop with primary-side sampling is 9.09% with primary-side sampling, compared to 40.5% with single-voltage loop sampling. Conversely, the linear regulation of the dual-voltage loop with secondary-side sampling is 7.02%, compared to 50.2% with single-voltage loop sampling. These results demonstrate that regardless of whether primary-side or secondary-side sampling is used, the dual-voltage loop exhibits better linear modulation than the single-voltage loop, while the secondary-side sampling results in a lower linear regulation.

[0042] Figure 5 The Cadence simulation diagram shows the output voltage ripple after loop stabilization of the circuit of this invention under the conditions of input voltage 150V, output voltage 22.8V, load 22A, and switching frequency 250kHz. The results show that the maximum ripple voltage fluctuation is 223mV, and the output fluctuation is 0.978%. The ripple calculation formula for the switching power supply is shown in Equation 2:

[0043]

[0044] Among them, V IN V OUT f represents the input voltage and the output voltage.s For the switching operating frequency, C ESR C is the equivalent resistance of the output capacitor. L This is the load capacitor. Because the input and output voltage difference in this invention is large and the switching frequency is low, the ripple size is within a reasonable range.

[0045] The above description, in conjunction with the accompanying drawings, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the invention is limited to these descriptions; the above descriptions are merely preferred embodiments of the invention. For those skilled in the art, various improvements and modifications can be made without departing from the principles of the invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A low-ripple four-transistor buck-boost switching power supply control circuit that enhances transient response, characterized in that, This includes a sample-and-hold circuit, an error amplifier EA, a timing circuit, a volt-second balancing circuit, a high-level sampling circuit, a logic control circuit, and a driver circuit. The positive terminal of the input voltage VIN is connected to the drain of power transistor Q1, and its negative terminal is connected to the source terminals of power transistors Q2 and Q4, as well as one end of capacitor C1 and resistor R2. The source terminal of power transistor Q1 is connected to the drain terminal of power transistor Q2 and one side of the primary winding of the transformer. The source terminal of power transistor Q3 and the drain terminal of power transistor Q4 are connected to the other end of the primary winding of the transformer. The drain terminal of power transistor Q3 is connected to one end of resistor R1 and capacitor C1. Resistor R2 is connected to resistor R1. One side of the secondary winding of the transformer is grounded and simultaneously connected to one end of capacitor C2, impedance ROUT, and resistor R3. The other side is connected to the positive terminal of the diode. The negative terminal of the diode is connected to capacitor C2, impedance ROUT, resistor R3, and the output terminal VOUT. The input of the sample-and-hold circuit is connected to resistor R2 when sampling on the primary side and resistor R3 when sampling on the secondary side. The output of the sample-and-hold circuit is connected to the non-inverting input of error amplifier EA. The inverting input of error amplifier EA is connected to the reference voltage source VREF. The output Verr of the error amplifier is connected to the input of the timing circuit. The positive terminal VL+ and the negative terminal VL- of the transformer primary inductor are connected to one 1 / K sampler. The outputs of the two 1 / K samples are connected to the input of the volt-second balancing circuit. One of the 1 / K samples is also connected to the input of the high-level sampling circuit. The volt-second balancing output Q3B is connected to the input of the logic control circuit. The output of the high-level sampling circuit is connected to the input of the timing circuit. The output of the timing circuit is connected to the logic control circuit. The output of the logic control circuit is connected to the driver circuit. The driver circuit outputs control signals Q1, Q2, Q3, and Q4.

2. The low-ripple four-transistor buck-boost switching power supply control circuit with enhanced transient response as described in claim 1, characterized in that, The high-level sampling circuit includes a first delay unit, a first AND gate, and a third switch: The control signal Q1 is used to provide the control signal for the third switch through the first delay unit and the first AND gate.

3. The low-ripple four-transistor buck-boost switching power supply control circuit with enhanced transient response as described in claim 2, characterized in that, The timing circuit includes a first timer and a second timer. The first timer includes a first voltage-controlled current source, a capacitor C3, a first switch, a first SR flip-flop, a fourth delay unit, a fifth delay unit, a sixth delay unit, a first comparator, and a first pulse generator. The input terminal of the first voltage-controlled current source is connected to the output Verr of the error amplifier EA. The output of the first voltage-controlled current source is connected to the positive terminal of capacitor C3 and the positive terminal of the first comparator. The output of the first comparator is connected to the fourth delay unit and generates a control signal Q1ST through the first pulse generator. The control signal Q1ST generates Q1ON through the control signal Q4 conduction judgment signal. At the same time, the output of the first pulse generator is connected to the fifth delay unit and the S terminal of the first SR flip-flop. The R terminal of the first SR flip-flop is connected to the output of the second timer after passing through the sixth delay unit and the third pulse generator. The output terminal Q of the first SR flip-flop is connected to the control terminal of the first switch. The first switch is connected across the capacitor C3. The second timer includes a second voltage-controlled current source, capacitor C4, a second switch, a second SR flip-flop, a second comparator, a second delay unit, and a third delay unit. The input terminal of the second voltage-controlled current source is connected to one end of the third switch. The other end of the third switch is connected to the sampling signal VL+1 / K of the positive terminal of the primary inductor of the transformer. This signal is then weighted with the bias voltage Vbias and connected to the negative terminal of the first comparator of the first timer. The output terminal of the second timer is connected to the positive terminal of capacitor C4 and the positive terminal of the second comparator. The negative terminal of the second comparator is connected to the output Verr of the error amplifier EA. The output of the second comparator is connected to the inverter and the second pulse generator through the second delay unit. The second pulse generator generates a control signal Q2ST. The control signal Q2ST is connected to the S terminal of the second SR flip-flop through the third delay unit. The R terminal of the second SR flip-flop is connected to the signal Q1ON generated by the first timer. The output terminal Q of the second SR flip-flop is connected to the control signal of the second switch. The second switch is connected across the two ends of capacitor C4.

4. The low-ripple four-transistor buck-boost switching power supply control circuit with enhanced transient response as described in claim 1, characterized in that, The logic control circuit includes a third comparator, a third SR flip-flop, a second AND gate, a fourth AND gate, a third AND gate, a fifth AND gate, a fourth pulse generator, a fourth SR flip-flop, a fifth SR flip-flop, a sixth SR flip-flop, a seventh delay unit, an eighth delay unit, a ninth delay unit, a tenth delay unit, and a fifth pulse generator. An external fixed bias Vbias is connected to the positive terminal of the third comparator. The negative terminal of the third comparator is connected to the negative terminal of the primary inductor to sample the signal VL-1 / K. The output of the third comparator is connected to one end of the second and third AND gates. The other end of the third AND gate is connected to the NOT output of the third SR flip-flop. The signal after passing through the seventh delay unit is connected to the S terminal of the third AND gate via the fourth pulse generator. The R terminal of the fourth SR flip-flop is connected to the control signal Q2ST. The output Q of the fourth SR flip-flop is connected to the control signal Q4. The output Q of the fifth SR flip-flop is connected to the other end of the second AND gate. The output of the second AND gate is connected to the S terminal of the sixth SR flip-flop. The R terminal of the sixth SR flip-flop is also connected to Q2ST. The output Q of the sixth SR flip-flop is connected to the Q1 generated by the eighth delay unit. The NOT output terminal of the sixth SR flip-flop is also connected to the signal after passing through the seventh delay unit. The signal is transmitted through the fifth pulse generator and the ninth delay unit to the S terminal of the third SR flip-flop, while the NOT output terminal of the sixth SR flip-flop is connected to the Ninth SR flip-flop. Connect one end of the fourth AND gate, and the other end of the fourth AND gate is Q1, which is connected to the output of the inverter through the tenth delay unit. The fourth AND gate outputs signal Q2. Signal Q3B is connected to the R terminal of the third SR flip-flop through the sixth pulse generator. The output Q of the third SR flip-flop is connected to one end of the fifth AND gate, and the other end of the fifth AND gate is connected to signal Q2. The fifth AND gate outputs signal Q3.

5. The low-ripple four-transistor buck-boost switching power supply control circuit with enhanced transient response as described in claim 1, characterized in that, The sample-and-hold circuit includes an input signal VSEN connected to one end of a fourth switch via a follower, the fourth switch connected to signal Q3, the other end of the fourth switch connected to capacitor C5 and the input of the follower, the output of the follower connected to resistor R4, the other end of R4 connected to the non-inverting input terminal EA of error amplifier, one end of resistor R5 and capacitor C7, the other end of resistor R5 connected to capacitor C6, the other ends of capacitors C6 and C7 connected to the output Verr of error amplifier, and the inverting terminal of error amplifier connected to the reference voltage source VREF.

6. The low-ripple four-transistor buck-boost switching power supply control circuit with enhanced transient response as described in claim 1, characterized in that, The volt-second balancing circuit controls the Q3 turn-off circuit. The sampling signal VL+1 / K at the positive terminal of the primary inductor is connected to the input of the follower. The output of the follower is connected to one end of resistor R5. The other end of resistor R5 is connected to resistors R6 and R7 and the non-inverting terminal of the op-amp. The other end of resistor R6 is grounded. The other end of resistor R7 is connected to the external bias signal Vtr1. The sampling signal VL-1 / K at the negative terminal of the primary inductor is connected to the input of the follower. The output of the follower is connected to one end of resistor R8. The other end of resistor R8 is connected to the inverting terminal of the op-amp and one end of resistor R9. The other end of resistor R9 is connected to the output of the op-amp, one end of the fifth switch, and the positive terminal of the fourth comparator. Signal Q1 is connected to the R terminal of the seventh SR flip-flop. Q1ON is connected to the S terminal of the seventh SR flip-flop. The Q output of the seventh SR flip-flop is connected to the switch control signal. The external bias voltage Vtr2 is connected to one end of resistor R10. The other end of resistor R10 is connected to the other end of the fifth switch, capacitor C8, and the negative terminal of the fourth comparator. The output of the fourth comparator generates signal Q3B.

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