A conduction time generation circuit and a switching converter

Abstract

The application provides a conduction time generating circuit and a switching converter. The conduction time generating circuit comprises: a slope module, which generates a slope signal according to a driving signal of a main power tube and an input voltage; a compensation module, which generates a compensation signal according to the input voltage and a duty cycle; and a timing signal generating module, which generates a timing signal according to the slope signal, the compensation signal and an output feedback signal. The compensation signal offsets the delay time of the timing signal, so that the conduction time is a preset conduction time corresponding to the duty cycle, and the switching frequency remains constant under different duty cycles. The conduction time generating circuit can adaptively generate the compensation signal according to the duty cycle and the input voltage of the switching converter, reduce the delay influence of the circuit itself, control the conduction time of the main power tube to be the preset conduction time corresponding to the certain duty cycle when the duty cycle is a certain value, and realize that the switching frequency of the main power tube remains constant under different duty cycles.

Description

Technical Field

[0001] This invention belongs to the field of power electronics technology, specifically relating to a conduction time generation circuit and a switching converter. Background Technology

[0002] The COT (constant-on-time) architecture of the BUCK converter has become a research hotspot in the field of DC-DC switching power supplies due to its advantages such as fast transient response, simple structure, and high efficiency under light load. In COT control mode, the on-time (Ton) of the main power transistor is constant, and the duty cycle is changed by adjusting the off-time (Toff) to achieve stable control of the output voltage. However, since there is no fixed clock, COT control mode is actually a frequency conversion control mode. Furthermore, its variable operating frequency makes the design of external EMI filter circuits challenging. Therefore, the constant-frequency COT architecture has become a significant area of ​​research.

[0003] like Figure 1 As shown, the existing solution proposes ACOT (adaptive constant on time) control. In ACOT control mode, the on-time is inversely proportional to the input voltage and directly proportional to the output voltage. This can cancel out the influence of the input and output voltages on the switching frequency, thus making the switching frequency approximately constant. However, due to the comparator delay in this circuit structure, the generated on-time is too long, leading to a decrease in the switching frequency of the switching converter. Furthermore, as the duty cycle of the switching converter decreases, the delay in the on-time generation circuit amplifies the decrease in switching frequency.

[0004] Therefore, there is an urgent need in the existing technology for a conduction time generation circuit that can eliminate the delay effect caused by the circuit itself, thereby controlling the actual conduction time of the main power transistor to be equal to the preset conduction time, and can also adaptively overcome the delay effect caused by the circuit according to the change of the duty cycle of the switching converter, so that the switching frequency of the switching converter remains constant under different duty cycles. Summary of the Invention

[0005] To address the aforementioned technical problems, this invention proposes a conduction time generation circuit and a switching converter, wherein the conduction time generation circuit is used to control the conduction time of the main power transistor in the switching converter, and the conduction time generation circuit includes:

[0006] The ramp module generates a ramp signal based on the drive signal of the main power transistor and the input voltage of the switching converter;

[0007] The compensation module generates a compensation signal based on the input voltage of the switching converter and the duty cycle of the switching converter.

[0008] A timing signal generation module generates a timing signal based on the ramp signal, the compensation signal, and the output feedback signal. The timing signal represents the conduction time of the main power transistor, and the output feedback signal represents the output of the switching converter.

[0009] The compensation signal is used to offset the delay time generated by the timing signal, so that the switching frequency of the main power transistor remains constant under different duty cycles.

[0010] Furthermore, when the input voltage remains constant, the compensation signal is inversely proportional to the duty cycle of the switching converter.

[0011] Furthermore, the inverse coefficient of the inverse relationship is obtained based on the switching cycle of the main power transistor and the delay time.

[0012] Preferably, the ramp module generates a first ramp signal based on the driving signal in the active state and the input voltage, the slope of the first ramp signal being greater than zero, and the driving signal in the active state driving the main power transistor to turn on.

[0013] Preferably, the timing signal generation module includes:

[0014] The comparison unit compares the superimposed signal of the compensation signal and the ramp signal with the output feedback signal to generate a turn-off trigger signal that characterizes the control of the main power transistor to turn off.

[0015] The logic unit processes the shutdown trigger signal to generate the timing signal.

[0016] Furthermore, the superposition of the compensation signal and the first ramp signal increases the slope of the first ramp signal.

[0017] Preferably, the ramp module includes: a first current source, a first capacitor, and a first switching transistor. The positive terminal of the first capacitor is connected to the first current source, the negative terminal of the first capacitor is grounded, the first switching transistor is connected in parallel with the first capacitor, and the positive terminal of the first capacitor is connected to the timing signal generation module.

[0018] Preferably, the compensation module includes: a second current source, a second capacitor, and a second switch transistor. The positive terminal of the second capacitor is connected to the second current source, the negative terminal of the second capacitor is grounded, the first current terminal of the second switch transistor is connected to the second current source, and the second current terminal of the second switch transistor is connected to the positive terminal of the first capacitor.

[0019] Preferably, the comparison unit includes a comparator, the logic unit includes an RS flip-flop, the inverting input of the comparator receives the output feedback signal, the non-inverting input of the comparator receives the superimposed signal, and the output of the comparator is connected to the reset terminal of the RS flip-flop.

[0020] A switching converter, including a buck switching converter, the switching converter including the on-time generation circuit described above, the on-time generation circuit controlling the on-time of the main power transistor of the switching converter.

[0021] The conduction time generation circuit proposed in this invention generates compensation signals of different magnitudes according to the duty cycle of the switching converter to offset the delay effect generated by the circuit itself. Thus, when the duty cycle is a certain value, the conduction time of the main power transistor is controlled to be a preset conduction time corresponding to that duty cycle. It can also achieve a constant switching frequency when the duty cycle changes. Attached Figure Description

[0022] Figure 1 This refers to the on-time generation circuit in the existing technology;

[0023] Figure 2 This is a block diagram of the conduction time generation circuit proposed in this invention;

[0024] Figure 3 This is a further detailed structural block diagram of the conduction time generation circuit proposed in this invention;

[0025] Figure 4 The specific circuit structure of the conduction time generation circuit proposed in this invention is shown below;

[0026] Figure 5 A comparison diagram showing the comparator flip-off times in the prior art and the conduction time generation circuit proposed in this invention;

[0027] Figure 6 This is a timing diagram of each driving signal in the conduction time generation circuit proposed in this invention. Detailed Implementation

[0028] Figure 1This is an existing on-time generation circuit used to control the on-time of the main power transistor in a switching converter, ensuring that the on-time of the main power transistor is a preset on-time Ton. When the first drive signal in the active state controls the main power transistor to turn on, the switch M0 turns off, and a current source I0 proportional to the input voltage Vin charges capacitor C0. At this time, the voltage Vramp on capacitor C0 rises linearly. When Vramp is greater than the output voltage Vout of the switching converter, the output signal Ton_reset of comparator CMP0 flips, resetting the first drive signal in the active state and thus outputting the first drive signal in the inactive state. The first drive signal in the inactive state controls the main power transistor to turn off. Therefore, the existing technology controls the turn-off time of the main power transistor by comparing the output voltages Vout and Vramp through comparator CMP0, thereby controlling the on-time of the main power transistor to the preset on-time Ton.

[0029] According to the formula for charging capacitor C0 by current source I0, we can obtain:

[0030] Therefore, theoretically, the on-time of the main power transistor is the preset on-time Ton, and the preset on-time Ton satisfies: Where D is the duty cycle, therefore the theoretical switching period T satisfies: That is, the theoretical switching period T is a constant value that is independent of the input voltage Vin and the output voltage Vout, so the theoretical switching frequency also remains constant.

[0031] However, in practical applications, the comparator in the circuit has a delay, denoted as Td. That is, when Vramp increases to the output voltage Vout, the comparator output does not immediately flip; instead, it flips only after Vramp increases to the output voltage Vout and then after a time Td. Therefore, the actual on-time of the main power switch is relatively long, and the actual on-time Ton' satisfies: Ton' = Ton + Td.

[0032] Furthermore, due to the circuit delay, the actual on-time of the main power transistor is longer, which affects the switching frequency of the switching converter, preventing it from remaining constant. Specifically, the actual switching cycle... If remember Then △1 represents the proportion of the delay time Td to the preset conduction time Ton. And because... Therefore, if the input voltage and / or output voltage are changed in practical applications, causing the duty cycle D to decrease, the reduction in switching frequency will be greater. That is, if the duty cycle of the switching converter decreases, the delay time Td will cause the switching frequency f to decrease even more, making the subsequent filtering design more complex.

[0033] Therefore, in order to solve the various problems caused by the delay in existing conduction time generation circuits, this invention proposes a conduction time generation circuit for controlling the conduction time of the main power transistor in a switching converter to a preset conduction time. This conduction time generation circuit includes:

[0034] The ramp module generates a ramp signal based on the drive signal of the main power transistor and the input voltage of the switching converter.

[0035] The compensation module generates a compensation signal based on the input voltage and duty cycle of the switching converter.

[0036] The timing signal generation module generates timing signals based on ramp signals, compensation signals, and output feedback signals. The timing signals characterize the conduction time of the main power transistor, and the output feedback signals characterize the output magnitude of the switching converter.

[0037] The compensation signal is used to offset the delay time generated by the timing signal, so as to control the conduction time of the main power transistor to a preset conduction time corresponding to the duty cycle when the duty cycle is a certain value, and to control the switching frequency of the main power transistor to remain constant when the duty cycle changes.

[0038] Therefore, the conduction time generation circuit proposed in this invention generates compensation signals of different magnitudes according to the duty cycle of the switching converter to offset the delay effect generated by the circuit itself. Thus, when the duty cycle is a certain value, the conduction time of the main power transistor is controlled to be a preset conduction time corresponding to the duty cycle. It can also achieve constant switching frequency when the duty cycle changes.

[0039] The conduction time generation circuit proposed in this invention will be further described below with reference to specific embodiments.

[0040] like Figure 2 and Figure 3 As shown, the conduction time generation circuit proposed in this invention includes:

[0041] The ramp module generates a first ramp signal based on the active state drive signal and the input voltage. The slope of the first ramp signal is greater than zero, and the active state drive signal drives the main power transistor to turn on.

[0042] The compensation module generates a compensation signal based on the input voltage and the duty cycle of the switching converter. When the input voltage remains constant, the compensation signal is inversely proportional to the duty cycle, and the inverse coefficient of this relationship is...

[0043] The timing signal generation module includes a comparison unit and a logic unit. The comparison unit obtains the turn-off trigger signal by comparing the superimposed signal of the compensation signal and the ramp signal with the output voltage of the switch converter. The superposition of the compensation signal and the ramp signal increases the slope of the first ramp signal. The logic unit generates the timing signal after performing logical operations on the turn-off trigger signal.

[0044] Specifically, such as Figure 3 As shown, the ramp module includes: a first current source I1, a first capacitor C1, and a first switch M1. The positive terminal of the first capacitor C1 is connected to the output terminal of the first current source I1, and the negative terminal of the first capacitor C1 is grounded. The first switch M1 is connected in parallel with the first capacitor C1. The compensation module includes: a second current source I2, a second capacitor C2, and a second switch M2. The positive terminal of the second capacitor C2 is connected to the output terminal of the second current source I2, and the negative terminal of the second capacitor C2 is grounded. The drain of the second switch M2 is connected to the positive terminal of the second capacitor C2, and the source of the second switch M2 is connected to the positive terminal of the first capacitor C1. The output current of the first current source I1 is Vin / R, the output current of the second current source I2 is kVin / R, and the sum of the capacitance values ​​of the first capacitor C1 and the second capacitor C2 is equal to the capacitance value of capacitor C0.

[0045] Furthermore, such as Figure 3 As shown, the comparison unit includes a comparator CMP1, and the logic unit includes an RS flip-flop. The inverting input of the comparator CMP1 receives the output voltage, and the non-inverting input of the comparator CMP1 receives the superimposed signal of the ramp signal and the compensation signal. The output of the comparator CMP1 is connected to the reset terminal of the RS flip-flop.

[0046] In summary, the working principle of this conduction time generation circuit is as follows: When the first drive signal in the active state drives the main power transistor to conduct, the second drive signal in the inactive state controls the first switch M1 to turn off, and the first current source I1 begins to charge the first capacitor C1, causing the positive voltage Vramp of the first capacitor C1 to increase linearly. During the conduction period of the main power transistor, the drive signal TG controls the second switch M2 to conduct, and the second capacitor C2 and the first capacitor C1 share charge. Subsequently, the first current source I1 and the second current source I2 simultaneously charge the first capacitor C1 and the second capacitor C2. Therefore, the second capacitor C2, which stores charge, compensates for the charge of the first capacitor C1 during its charging process, making the growth slope of Vramp larger, thereby advancing the flip-off time of the comparator CMP1 output, thus offsetting the delay effect caused by the comparator CMP1. The RS flip-flop then determines the turn-off time of the main power transistor based on the flip-off time of the comparator CMP1 output, thereby outputting the complete active state first drive signal. Figure 5As shown, the implementation demonstrates the output flipping time of comparator CMP0. If the output flipping of comparator CMP0 had no delay, it would occur at time t1. However, due to the existence of the delay time Td, comparator CMP0 actually flips its output at time t2. In this invention, the ramp signal is compensated so that comparator CMP1 flips its output at time t1, thereby canceling the delay time Td.

[0047] It should be noted that, as Figure 6 As shown, considering that the second capacitor C2 needs to be discharged after charging to repeat the above process, the generation time of the driving signal TG will be slightly later than the generation time of the second driving signal in the invalid state. Therefore, the time difference between the generation times of the two driving signals can be used to discharge the second capacitor C2.

[0048] In summary, by controlling the output switching time of comparator CMP1 to advance in order to offset the inherent delay of comparator CMP1, this invention achieves the goal of controlling the on-time of the main power transistor to a preset on-time Ton within the switching cycle T.

[0049] The following theoretical analysis further illustrates the principle of this invention. The charging time of the first current source I1 is a preset conduction time Ton, and the charging time of the second current source I2 is T. According to the capacitor voltage equation, we know that:

[0050]

[0051] Since C1 + C2 = C0, then so It can be equivalent to the equivalent compensation current generated by the second current source I2 within the preset conduction time Ton. This equivalent compensation current can characterize the compensation signal, and it can be seen that when the input voltage is constant, the equivalent current is inversely proportional to the duty cycle.

[0052] According to the equation It = VC, when VC remains constant, if but △2 represents a small quantity.

[0053] Because the equivalent compensation current compensates for Vramp, causing the comparator CMP toggling time to be advanced, thus canceling the delay time Td, the preset on-time Ton satisfies:

[0054] Ton = Ton(1-△2) + Td, then Ton△2 = Td. Then we can obtain It can then be deduced that when the input voltage is constant, the equivalent current is inversely proportional to the duty cycle, and this inverse proportionality coefficient is: R is a fixed value related to the overall structural parameters of the switching converter. Those skilled in the art can obtain the specific value of R based on the specific circuit structure.

[0055] In this embodiment, the first drive signal in the valid state is a high-level signal, the first drive signal in the invalid state is a low-level signal, and the second drive signal in the invalid state is a low-level signal. This is not limited in other embodiments. Furthermore, in this embodiment, the second drive signal and the first drive signal are synchronously generated by the two outputs of the RS flip-flop, thus enabling the first switch M1 to be synchronously turned off when the main power transistor is turned on. However, in other embodiments, the first drive signal can also be synchronously inverted to obtain the second drive signal.

[0056] In summary, the conduction time generation circuit proposed in this invention generates compensation signals of different magnitudes according to the duty cycle of the switching converter to offset the delay effect generated by the circuit itself. Thus, when the duty cycle is a certain value, the conduction time of the main power transistor is controlled to be a preset conduction time corresponding to that duty cycle. It can also achieve constant switching frequency when the duty cycle changes.

[0057] The present invention also proposes a switch converter, which includes the conduction time generation circuit mentioned above, the conduction time generation circuit controlling the conduction time of the main power transistor of the switch converter, and the switch converter is a BUCK converter.

Claims

1. A conduction time generation circuit, applied to a switching converter, the switching converter including a main power transistor, characterized in that, include: The ramp module generates a ramp signal based on the drive signal of the main power transistor and the input voltage of the switching converter; The compensation module generates a compensation signal based on the input voltage of the switching converter and the duty cycle of the switching converter. A timing signal generation module generates a timing signal based on the ramp signal, the compensation signal, and the output feedback signal. The timing signal represents the conduction time of the main power transistor, and the output feedback signal represents the output of the switching converter. The compensation signal is used to offset the delay time generated by the timing signal, so that the switching frequency of the main power transistor remains constant under different duty cycles.

2. The conduction time generation circuit as described in claim 1, characterized in that, When the input voltage remains constant, the compensation signal is inversely proportional to the duty cycle of the switching converter.

3. The conduction time generation circuit as described in claim 2, characterized in that, The inverse coefficient of the inverse relationship is obtained based on the switching cycle of the main power transistor and the delay time.

4. The conduction time generation circuit as described in claim 1, characterized in that, The ramp module generates a first ramp signal based on the driving signal in the active state and the input voltage. The slope of the first ramp signal is greater than zero, and the driving signal in the active state drives the main power transistor to turn on.

5. The conduction time generation circuit as described in claim 4, characterized in that, The timing signal generation module includes: The comparison unit compares the superimposed signal of the compensation signal and the ramp signal with the output feedback signal to generate a turn-off trigger signal that characterizes the control of the main power transistor to turn off. The logic unit processes the shutdown trigger signal to generate the timing signal.

6. The conduction time generation circuit as described in claim 5, characterized in that, The superposition of the compensation signal and the first ramp signal increases the slope of the first ramp signal.

7. The conduction time generation circuit as described in claim 1 or 4, characterized in that, The ramp module includes: a first current source, a first capacitor, and a first switching transistor. The positive terminal of the first capacitor is connected to the first current source, the negative terminal of the first capacitor is grounded, the first switching transistor is connected in parallel with the first capacitor, and the positive terminal of the first capacitor is connected to the timing signal generation module.

8. The conduction time generation circuit as described in claim 7, characterized in that, The compensation module includes: a second current source, a second capacitor, and a second switching transistor. The positive terminal of the second capacitor is connected to the second current source, and the negative terminal of the second capacitor is grounded. The first current terminal of the second switching transistor is connected to the second current source, and the second current terminal of the second switching transistor is connected to the positive terminal of the first capacitor.

9. The conduction time generation circuit as described in claim 5, characterized in that, The comparison unit includes a comparator, the logic unit includes an RS flip-flop, the inverting input of the comparator receives the output feedback signal, the non-inverting input of the comparator receives the superimposed signal, and the output of the comparator is connected to the reset terminal of the RS flip-flop.

10. A switching converter, the switching converter including a step-down switching converter, characterized in that, The switching converter includes the conduction time generation circuit according to any one of claims 1-9, wherein the conduction time generation circuit controls the conduction time of the main power transistor of the switching converter.

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