Delay-locked loop and chip

Abstract

The application provides a delay-locked loop and a chip. The delay-locked loop comprises a preset number of serially connected delay lines, a phase detector and a delay control module. The delay line is used for generating a delay for an input clock signal and outputting a clock signal with a preset phase difference from a reference clock signal. The last delay line outputs the delayed clock signal to the phase detector. The delay control module is used for increasing the number of turned-on delay units of each delay line from 0 by an increment of 1 until the output result of the phase detector is locked, and determining a first number of turned-on delay units of each delay line. The first number of turned-on delay units of each delay line is updated according to a delay line step table until the output result of the phase detector is locked, and a second number of turned-on delay units of each delay line is determined. The second number is not less than the first number. The delay-locked loop has the advantages of saving circuit area, low cost and power consumption and high locking accuracy.

Description

Technical Field

[0001] This application relates to the field of delay phase-locked loop (PLL) technology, and in particular to a delay phase-locked loop and its chip. 。 Background Technology

[0002] Currently, interface circuit chips typically use delay phase-locked loops to generate clocks of different phases for delay adjustment or sampling.

[0003] Since a single delay-locked loop (PLL) can only generate one configurable clock signal, multiple PLLs are required when multiple clocks with different phases are needed, leading to an increase in chip area and power consumption. Summary of the Invention

[0004] In view of this, this application provides a delay phase-locked loop and chip, which generates multiple clock signals with different phases by setting multiple series delay lines in a delay phase-locked loop. Compared with the existing multiple delay phase-locked loops that generate multiple clock signals with different phases, the chip circuit area and power consumption are reduced.

[0005] In a first aspect, embodiments of this application provide a delay phase-locked loop for generating a preset number of clock signals having a preset phase relationship with a reference clock signal, comprising: a preset number of series-connected delay lines, a phase detector, and a delay control module; the reference clock signal is respectively input to the first delay line and the phase detector;

[0006] The delay line is used to delay the input clock signal and output a clock signal with a preset phase difference from the reference clock signal. The delay is the product of the number of delay units that are turned on and the delay time of the delay unit, as determined by the delay control module. The last delay line outputs the delayed clock signal to the phase detector.

[0007] The phase detector is used to determine whether the time-delayed phase-locked loop is locked based on the reference clock signal and the delayed clock signal.

[0008] The delay control module is used to increment the number of conducting delay units of each delay line from 0 in increments of 1 until the phase detector output is locked, thereby determining a first number of conducting delay units for each delay line; and to update the first number of conducting delay units for each delay line according to a pre-set delay line step table until the phase detector output is locked, thereby determining a second number of conducting delay units for each delay line, wherein the second number is not less than the first number.

[0009] In one possible implementation, the preset phase difference is an integer multiple of the quotient of 360 degrees and a preset number, where the preset number is a power of 2.

[0010] In one possible implementation, the delay generated by each delay line to the reference clock signal is the product of the sum of the number of delay units that are turned on by the delay line and all the delay units before it, and the delay time of the delay unit.

[0011] In one possible implementation, the phase detector is specifically used for:

[0012] Determine whether the rising edges of the reference clock signal and the delayed clock signal are aligned. If they are, the delay phase-locked loop is determined to be in a locked state, and an output indicating that it is locked is output to the delay control module. Otherwise, the delay phase-locked loop is determined to be in an unlocked state, and an output indicating that it is unlocked is output to the delay control module.

[0013] In one possible implementation, the first number of delay units turned on for each delay line is the same.

[0014] In one possible implementation, the number of active delay units for each delay line is incremented from 0 by 1 until the phase detector output is locked, thus determining the first number of active delay units for each delay line; including:

[0015] Increment the number of active delay units for each delay line by 1, where the initial value of the number of active delay units for each delay line is 0;

[0016] The output of the phase detector is obtained, wherein the output is determined by the currently received delayed clock signal and the reference clock signal;

[0017] If the output result is locked, then set the first number of the current number of the conducting delay units of each delay line to the current number of conducting delay units minus 1, and end; otherwise, continue to increment the number of the current number of the conducting delay units of each delay line by 1.

[0018] In one possible implementation, the delay line step table includes a preset number of rows of data, wherein the row data includes an update status of the number of conduction delay units of the preset number of delay lines, the update status including a first update status and a second update status, wherein the first update status is that the number of conduction delay units remains unchanged, and the second update status is that the number of conduction delay units is increased by 1; the number of delay lines set to the second update status in each row is the same as the row number, wherein the column number of the delay lines set to the second update status is an integer value obtained by rounding down an integer multiple of the quotient of the preset number and the row number.

[0019] In one possible implementation, according to a pre-set delay line step table, the first number of delay units turned on for each delay line is updated until the phase detector output is locked, and a second number of delay units turned on for each delay line is determined; including:

[0020] Starting from the first row of the delay line step table, retrieve the update status of the number of conduction delay units for each delay line row by row;

[0021] The current number of active delay units of the corresponding delay line is updated by utilizing the update status of the number of active delay units of each delay line; wherein, the initial value of the number of active delay units of each delay line is a first number.

[0022] Obtain the output result of the phase detector, wherein the output result is determined by the currently received delayed clock signal and the reference clock signal;

[0023] If the output result is locked, then the number of currently active delay units for each delay line is determined as the second number, and the process ends; otherwise, continue to obtain the update status of the number of active delay units for each delay line in the next row of the delay line step table.

[0024] Secondly, embodiments of this application provide a chip, including: a delay phase-locked loop according to embodiments of this application.

[0025] In one possible implementation, it further includes: a timer module connected to a delay phase-locked loop, the timer module being configured to: generate a pulse width modulation waveform with a preset frequency and duty cycle using a preset number of clock signals output by the delay phase-locked loop that have a preset phase relationship with a reference clock signal.

[0026] The delay phase-locked loop of this application has the advantages of saving circuit area, low cost and power consumption, and high locking accuracy. Attached Figure Description

[0027] Figure 1 This is a schematic diagram of the structure of the delay phase-locked loop according to an embodiment of this application;

[0028] Figure 2 This is a schematic diagram of eight clock signals with phase differences from a reference clock signal, representing embodiments of this application.

[0029] Figure 3 This is a schematic diagram of a delay phase-locked loop comprising eight series-connected delay lines, according to an embodiment of this application. Detailed Implementation

[0030] Various embodiments and features of this application are described herein with reference to the accompanying drawings.

[0031] It should be understood that various modifications can be made to the embodiments described herein. Therefore, the above description should not be considered as limiting, but merely as an example of embodiments. Other modifications within the scope and spirit of this application will be apparent to those skilled in the art.

[0032] The accompanying drawings, which are included in and form part of this specification, illustrate embodiments of the present application and, together with the general description of the present application given above and the detailed description of the embodiments given below, serve to explain the principles of the present application.

[0033] These and other features of this application will become apparent from the following description of preferred forms of embodiments given as non-limiting examples, with reference to the accompanying drawings.

[0034] It should also be understood that although this application has been described with reference to some specific examples, those skilled in the art can certainly implement many other equivalent forms of this application.

[0035] The above and other aspects, features and advantages of this application will become more apparent when taken in conjunction with the accompanying drawings and in view of the following detailed description.

[0036] Specific embodiments of this application are described thereafter with reference to the accompanying drawings; however, it should be understood that the claimed embodiments are merely examples of this application, which can be implemented in various ways. Well-known and / or repeated functions and structures are not described in detail to avoid unnecessary or redundant details that could obscure the application. Therefore, the specific structural and functional details claimed herein are not intended to be limiting, but merely serve as the basis and representative basis for the claims to teach those skilled in the art to use this application in a variety of substantially any suitable detailed structures.

[0037] This specification may use the phrases “in one embodiment,” “in another embodiment,” “in yet another embodiment,” or “in other embodiments,” all of which may refer to one or more of the same or different embodiments according to this application.

[0038] First, a brief introduction to the design concept of the embodiments of this application will be given.

[0039] Currently, interface chip circuits typically use delay-locked loops (PLLs) to generate clocks of different phases for delay adjustment or sampling. For example, the frequency and duty cycle accuracy of the PWM waveform output by an eTimer module depend on the eTimer module's operating clock frequency. Furthermore, the accuracy of the eTimer module in capturing input signals also depends on its operating clock frequency.

[0040] Existing delay-locked loops (DLLs) typically include a delay line, a phase detector, and a controller. The delay line receives an externally input reference clock signal, delays it, and sends the delayed clock signal to the phase detector. The phase detector compares the delayed clock signal with the reference clock signal to determine the phase difference, which is then sent to the controller. The delay line usually consists of multiple delay units connected in series; the delay of the delay chain is equal to the product of the number of delay units and their respective delay times.

[0041] Since a single delay phase-locked loop (PLL) can only generate one clock signal with a configurable phase difference, multiple PLLs are required when multiple clock signals with different phase differences are needed, which increases the area and power consumption of the chip circuit.

[0042] To address the aforementioned technical problems, this application improves upon existing delay-locked loops by designing a single delay line as N cascaded delay lines. The function of each delay line is to delay the input clock signal and output a clock signal with a corresponding phase difference. Therefore, N delay lines output N clock signals with different phase differences. Furthermore, the delay-locked loop of this application also includes a phase detector and a delay control module. The phase detector determines whether the delay-locked loop is locked, and the delay control module determines the delay of each delay line by setting the number of conducting delay units on each delay line, so that each delay line simultaneously outputs a clock signal with a preset phase difference.

[0043] For existing methods that output N clock signals with a preset phase difference from the reference clock through N delay phase-locked loops, this application can output N clock signals with a preset phase difference from the reference clock through a single delay phase-locked loop. This saves the area of ​​the delay phase-locked loop, reduces power consumption, reduces circuit cost, and also provides higher clock locking accuracy, meaning the generated clock signal has higher precision.

[0044] After introducing the application scenarios and design concepts of the embodiments of this application, the technical solutions provided by the embodiments of this application will be described below.

[0045] like Figure 1 As shown, this application embodiment provides a delay phase-locked loop for generating N clock signals with a preset phase relationship to a reference clock signal, including: N series-connected delay lines, a phase detector, and a delay control module;

[0046] The delay line is used to delay the input clock signal and output a clock signal with a preset phase difference from the reference clock signal. The delay is the product of the number of delay units that are turned on, determined by the delay control module, and the delay time of the delay unit. The Nth delay line outputs the delayed clock signal to the phase detector.

[0047] The phase detector is used to determine whether the time-delayed phase-locked loop is locked based on the reference clock signal and the delayed clock signal.

[0048] The delay control module is used to increment the number of conducting delay units of each delay line from 0 in increments of 1 until the phase detector output is locked, thereby determining the first number of conducting delay units for each delay line; and to update the first number of conducting delay units for each delay line according to a pre-set delay line step table until the phase detector output is locked, thereby determining the second number of conducting delay units for each delay line, wherein the second number is not less than the first number.

[0049] The reference clock signal is input to the first delay line and the phase detector, respectively; the first delay line is input to generate a clock signal with a preset phase difference, and the phase detector is input to determine whether the delay phase-locked loop is set.

[0050] In this embodiment, the delay of the delay line is adjustable, and the delay is adjusted by adjusting the number of conducting delay units.

[0051] Preferably, the delay control module is implemented through circuitry according to its function.

[0052] In this embodiment of the application, the N clock signals having a preset phase relationship with the reference clock signal include: Clock signals with phase difference of degrees Clock signals with phase difference of degrees, ... The clock signals have a phase difference of 12 degrees and a phase difference of 360 degrees, where N is a power of 2, for example, N = 2, 4, 8, 16, etc. Each delay line outputs a clock signal with a preset phase difference from the reference clock; that is, the phase difference is relative to the reference clock signal.

[0053] For example, such as Figure 2 As shown, when the number of delay lines N equals 8, the eight clock signals with a preset phase relationship with the reference clock signal clk_ref include: a clock signal clk_ph45 with a 45-degree phase difference, a clock signal clk_ph90 with a 90-degree phase difference, a clock signal clk_ph135 ​​with a 135-degree phase difference, a clock signal clk_ph180 with a 180-degree phase difference, a clock signal clk_ph225 with a 225-degree phase difference, a clock signal clk_ph270 with a 270-degree phase difference, a clock signal clk_ph315 with a 315-degree phase difference, and a clock signal clk_ph360 with a 360-degree phase difference.

[0054] In this embodiment, the delay of the delay line is adjustable. The delay line includes multiple delay units. The delay is determined by adjusting the number of conducting delay units, where the delay is the product of the number of conducting delay units and the delay time of each delay unit. The delay is maximized when all delay units are conducting. The delay control module is used to control the number of conducting delay units in each delay line, thereby controlling the magnitude of the delay.

[0055] It should be noted that this application does not limit how the conduction of the delay unit is controlled; for example, a switch can be linked to each delay unit.

[0056] like Figure 1 As shown, for the first delay line, its input clock signal is the reference clock signal; for the second clock signal, its input clock signal is the delayed clock signal output from the first delay line; and for the nth delay line, its input clock signal is the delayed clock signal output from the (n-1)th delay line. Therefore, the delay of the nth delay line relative to the reference clock signal is the product of the number of delay units in the first n delay lines and the delay time of each delay unit; where 1 <n≤N。

[0057] In this embodiment of the application, the phase detector is specifically used for:

[0058] Determine whether the rising edges of the reference clock signal and the delayed clock signal are aligned. If they are, the delay phase-locked loop is determined to be in a locked state, and an output indicating that it is locked is output to the delay control module. Otherwise, the delay phase-locked loop is determined to be in an unlocked state, and an output indicating that it is unlocked is output to the delay control module.

[0059] For example, in a delay-locked loop (DLL) with eight cascaded delay lines, when the rising edges of the reference clock signal `clk_ref` and the delayed clock signal are not aligned, the DLL is in an unlocked state, and the phase detector `phase_dector` outputs 0. When the rising edges of the reference clock signal `clk_ref` and the delayed clock signal are aligned, i.e., the delayed clock signal has a 360-degree phase difference (`clk_out_ph360`), the DLL is in a locked state, and the phase detector `phase_dector` outputs 1.

[0060] Since the N delay lines in this embodiment are connected in series, and the delay of the nth delay line to the reference clock signal is the product of the number of delay units of the first n delay lines and the delay time of the delay units, in order to make each delay line output a clock signal with a preset phase difference, it is necessary to determine the delay of each delay line, that is, the number of delay units that are turned on in each delay line.

[0061] For existing delay lines with N parallel structures, since the N delay lines are independent and do not interfere with each other, the delay, i.e., the number of conducting delay units, can be obtained directly through the clock signals with configured phase differences output by each delay line. However, in the embodiments of this application, the delay lines are in series, not independent, and will affect each other. The function of the delay control module is to determine the number of conducting delay units for each delay line, which is achieved through two steps: coarse adjustment and fine adjustment.

[0062] The coarse adjustment step includes: incrementing the number of active delay units for each delay line from 0 in increments of 1 until the phase detector output is locked, thus determining the initial number of active delay units for each delay line. It can be seen that the initial number of active delay units for each delay line determined by the coarse adjustment step is the same.

[0063] In this embodiment of the application, the number of delayed units turned on for each delayed line is incremented from 0 by 1 until the output of the phase detector is locked, thereby determining the first number of delayed units turned on for each delayed line; including:

[0064] Step S1: Increment the number of active delay units for each delay line by 1. The initial value of the number of active delay units for each delay line is 0, i.e., the delay is 0.

[0065] The initial delay of each delay line is 0, meaning that all delay units are not conductive.

[0066] Step S2: Obtain the output result of the phase detector, wherein the output result is determined by the currently received delayed clock signal and the reference clock signal;

[0067] Step S3: Determine if the output result is locked. If yes, proceed to step S4; otherwise, proceed to step S1.

[0068] Step S4: Set the first number of the conducting delay units of each delay line to the current number of delay units minus 1, and then end.

[0069] For example, when a time-locked loop (TLL) includes eight cascaded delay lines, the delay control module first controls each delay line to conduct one delay unit. The delay of the clock signal output from the eighth delay line is then the product of the delay times of the eight delay units and the delay time of each delay unit. The phase detector determines whether the rising edge of the clock signal output from the eighth delay line is aligned with the rising edge of the reference clock signal. If they are not aligned, it outputs 0 (indicating not locked) to the delay control module. The delay control module then controls each delay line to conduct one more delay unit. The delay of the clock signal output from the eighth delay line is then the product of the delay times of the sixteen delay units and the delay time of each delay unit. The phase detector again determines whether the rising edge of the clock signal output from the eighth delay line is aligned with the rising edge of the reference clock signal. If they are not aligned... If the clock signal from the eighth delay line is aligned with the reference clock signal, the output will be 0 (indicating unlocked). The delay control module will then control each delay line to conduct one more delay unit. The delay of the clock signal output from the eighth delay line will be the product of the delay time of the 24 delay units and the delay time of the delay unit. The phase detector will determine whether the rising edge of the clock signal output from the eighth delay line is aligned with the rising edge of the reference clock signal. If aligned, the output will be 1 (indicating locked) to the delay control module. The delay control module will determine that the total number of delayed units that are activated in the eight series delay lines is between 16 and 24. The initial number of activated delayed units in each delay line is 2. This is the range of the total number of activated delayed units obtained from the coarse adjustment step and the minimum value of the number of activated delayed units in each delay line.

[0070] After obtaining the range of the total number of conducting delay units of the series delay lines, it is necessary to further determine the second number of conducting delay units of each delay line through a fine-tuning step, wherein the second number is not less than the first number.

[0071] The fine-tuning steps include: updating the first number of conducting delay units for each delay line according to a pre-set delay line step table, until the output of the phase detector is locked, and determining the second number of conducting delay units for each delay line.

[0072] In this embodiment of the application, in order to implement the fine-tuning step, it is necessary to pre-establish a delay line step table. For N delay lines, the delay line step table includes N rows and N columns of data. Each row includes the update status of the number of conduction delay units of the N delay lines. The update status includes a first update status and a second update status. In the first update status, the number of conduction delay units remains unchanged, and in the second update status, the number of conduction delay units is increased by 1. The m-th row is set to have m delay lines set to the second update status. The column numbers of the delay lines set to the second update status are: [N×1 / m], [N×2 / m], ... and N, where [·] represents rounding to the nearest integer.

[0073] Specifically, the principle for setting the delay line step table is as follows:

[0074] The first line adds one conducting delay unit to the entire series delay lines, where the added position is the Nth delay line;

[0075] The second line adds two conducting delay units to the entire series delay lines, with the addition positions being the N / 2th delay line and the Nth delay line, respectively;

[0076] The third row adds 3 conducting delay units to the entire series delay lines, with the addition positions being the [N / 3]th delay line, the [2N / 3]th delay line, and the Nth delay line, respectively;

[0077] This process continues until the Nth row, where the Nth row adds N conducting delay units to the entire series delay lines, with each delay line adding one conducting delay unit.

[0078] Specifically, based on a pre-set delay line step table, the first number of active delay units for each delay line is updated until the phase detector output is locked, thus determining the second number of active delay units for each delay line; including:

[0079] Step T1: Obtain the update status of the number of conduction delay units for each delay line in the m-th row of the delay line step table; where the initial value of m is 1;

[0080] Step T2: Update the current number of active delay units of the corresponding delay line using the update status of the number of active delay units of each delay line; where, when m=1, the current number of active delay units of the delay line is the first number;

[0081] Step T3: Obtain the output result of the phase detector, wherein the output result is determined by the currently received delayed clock signal and the reference clock signal;

[0082] Step T4: Determine if the output result is locked. If yes, proceed to step T5; otherwise, increment m by 1 and proceed to step T1.

[0083] Step T5: Determine the number of currently active delay units for each delay line as the second number, and end.

[0084] Once the number of currently active delay units for each delay line is determined through fine-tuning steps, the delay phase-locked loop is locked. At this point, each delay line outputs a clock signal with a preset phase difference.

[0085] The specific implementation of the present invention will be described below with reference to a specific scenario. See also Figure 3As shown, in this specific application scenario, the time-delay phase-locked loop includes eight series-connected delay lines, a phase detector, and a delay control module; the reference clock signal is input to the first delay line and the phase detector respectively; and the eight delay lines output as shown in the figure. Figure 2 The eight clock signals shown are: clk_ph45 (45-degree phase difference), clk_ph90 (90-degree phase difference), clk_ph135 ​​(135-degree phase difference), clk_ph180 (180-degree phase difference), clk_ph225 (225-degree phase difference), clk_ph270 (270-degree phase difference), clk_ph315 (315-degree phase difference), and clk_ph360 (360-degree phase difference).

[0086] The delay control module first determines the initial number of delay units to be turned on for each delay line through coarse adjustment. The specific implementation process is as follows:

[0087] The delay control module controls each delay line to activate one delay unit. The delay of the clock signal output from the eighth delay line is the product of the delay times of the eight delay units and the delay time of each delay unit. The phase detector checks if the rising edge of the clock signal output from the eighth delay line is aligned with the rising edge of the reference clock signal. If they are not aligned, it outputs 0 (indicating unlocked) to the delay control module. The delay control module then controls each delay line to activate one more delay unit. The delay of the clock signal output from the eighth delay line is the product of the delay times of the 16 delay units and the delay time of each delay unit. The phase detector again checks if the rising edge of the clock signal output from the eighth delay line is aligned with the rising edge of the reference clock signal. If they are not aligned, it outputs 0 (indicating unlocked). The clock signal output from the eighth delay line is then sent to the delay control module. The delay control module controls each delay line to conduct one more delay unit. The delay of the clock signal output from the eighth delay line is the product of the delay time of the 24 delay units and the delay time of the delay unit. The phase detector determines whether the rising edge of the clock signal output from the eighth delay line is aligned with the rising edge of the reference clock signal. If aligned, it outputs 1 (indicating lock) to the delay control module. The delay control module determines that the total number of delayed units conducted by the eight series delay lines is between 16 and 24. The first number of delayed units conducted by each delay line is 2. This is the range of the total number of delayed units conducted obtained from the coarse adjustment step and the minimum value of the number of delayed units conducted by each delay line.

[0088] Create a delay line step table containing eight rows of data, as shown in Table 1:

[0089] Table 1: Delay Line Step Table

[0090]

[0091] Based on the aforementioned delay line step table, the delay control module updates the number of conduction delay units for each delay line, ensuring that the initial number is 2. After each update, the phase detector checks whether the delay phase-locked loop (PLL) is locked. If not, the module updates the number of conduction delay units for each delay line based on the next row of data until the PLL is locked. The number of conduction delay units for each delay line at this point is the final number of conduction delay units, i.e., the second number. The delay determined in this way causes each delay line to output a clock signal with a preset phase difference.

[0092] The number of active delay units for each delay line is updated according to the data in the first row, and the phase detector is locked. The second number of active delay units for the eight delay lines is as follows: 2, 2, 2, 2, 2, 2, 2 and 3. The total number of active delay units for the eight series-connected delay lines is 17.

[0093] Otherwise, the number of active delay units for each delay line is updated according to the data in the second row, and the phase detector is locked. Then the second number of active delay units for the eight delay lines is: 2, 2, 2, 3, 2, 2, 2 and 3; the total number of active delay units for the eight series-connected delay lines is 18.

[0094] Otherwise, the number of active delay units for each delay line is updated according to the data in the third row, and the phase detector is locked. Then the second number of active delay units for the eight delay lines is: 2, 2, 3, 2, 3, 2, 2 and 3; the total number of active delay units for the eight series-connected delay lines is 19.

[0095] Otherwise, the number of active delay units for each delay line is updated according to the data in the fourth row, and the phase detector is locked. Then the second number of active delay units for the eight delay lines is: 2, 3, 2, 3, 2, 3, 2 and 3; the total number of active delay units for the eight series-connected delay lines is 20.

[0096] Otherwise, the number of active delay units for each delay line is updated according to the data in the fifth row, and the phase detector is locked. The second number of active delay units for the eight delay lines is then: 2, 3, 3, 2, 3, 3, 2 and 3; the total number of active delay units for the eight series-connected delay lines is 21.

[0097] Otherwise, the number of active delay units for each delay line is updated according to the data in the sixth row, and the phase detector is locked. Then the second number of active delay units for the eight delay lines is: 3, 2, 3, 3, 3, 2, 3 and 3; the total number of active delay units for the eight series-connected delay lines is 22.

[0098] Otherwise, the number of active delay units for each delay line is updated according to the data in the seventh row, and the phase detector is locked. Then the second number of active delay units for the eight delay lines is: 3, 3, 3, 2, 3, 3, 3 and 3; the total number of active delay units for the eight series-connected delay lines is 23.

[0099] Otherwise, update the number of active delay units for each delay line according to the data in the eighth row. Then the second number of active delay units for the eight delay lines is 3, 3, 3, 3, 3, 3, 3 and 3 respectively; the total number of active delay units for the eight series-connected delay lines is 24.

[0100] Based on the same inventive concept, this application also provides a chip, including: the delay phase-locked loop of the above embodiment. Because this chip has the delay phase-locked loop of this embodiment, it saves circuit area, has lower cost, lower power consumption, and higher clock accuracy.

[0101] Furthermore, the chip also includes a timer module (eTimer) connected to the delay phase-locked loop. The timer module is used to generate a pulse width modulation waveform (PWM) with a preset frequency and duty cycle by using N clock signals output by the delay phase-locked loop that have a preset phase relationship with the reference clock signal.

[0102] In the various embodiments of this application, the order of the above-mentioned processes does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0103] Those skilled in the art will recognize that the various illustrative logical blocks (ILBs) and steps described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this application.

[0104] In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.

[0105] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0106] In addition, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0107] In the above embodiments, implementation can be achieved entirely or partially through software, hardware, firmware, or any combination thereof. When implemented using software, it can be implemented entirely or partially in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of this application are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, digital subscriber line) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that integrates one or more available media. The available medium can be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., solid-state drive), etc.

[0108] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A delay-locked loop (PLL) for generating a preset number of clock signals having a preset phase relationship with a reference clock signal, characterized in that, include: A preset number of cascaded delay lines, phase detectors, and delay control modules; The reference clock signal is input to the first delay line and the phase detector, respectively; The delay line is used to delay the input clock signal and output a clock signal with a preset phase difference from the reference clock signal. The delay is the product of the number of delay units that are turned on and the delay time of the delay unit, as determined by the delay control module. The last delay line outputs the delayed clock signal to the phase detector. The phase detector is used to determine whether the time-delayed phase-locked loop is locked based on the reference clock signal and the delayed clock signal. The delay control module is used to increment the number of active delay units for each delay line from 0 in increments of 1 until the phase detector output is locked, thus determining a first number of active delay units for each delay line; and to update the first number of active delay units for each delay line according to a pre-set delay line step table until the phase detector output is locked, thus determining a second number of active delay units for each delay line, wherein the second number is not less than the first number; wherein... The delay line step table includes a preset number of rows of data. Each row of data includes an update status of the number of active delay units for the preset number of delay lines. The update status includes a first update status and a second update status. In the first update status, the number of active delay units remains unchanged. In the second update status, the number of active delay units is increased by 1. The number of delay lines set to the second update status in each row is the same as the row number. The column number of the delay lines set to the second update status is an integer value obtained by rounding down an integer multiple of the preset number and the row number.

2. The delay phase-locked loop according to claim 1, characterized in that, The preset phase difference is an integer multiple of the quotient of 360 degrees and a preset number, and the preset number is a power of 2.

3. The delay phase-locked loop according to claim 1, characterized in that, The delay generated by each delay line to the reference clock signal is the product of the sum of the number of delay units that are turned on by the delay line and all the delay units before it, and the delay time of the delay unit.

4. The delay phase-locked loop according to claim 1, characterized in that, The phase detector is specifically used for: Determine whether the rising edges of the reference clock signal and the delayed clock signal are aligned. If they are, the delay phase-locked loop is determined to be in a locked state, and an output indicating that it is locked is output to the delay control module. Otherwise, the delay phase-locked loop is determined to be in an unlocked state, and an output indicating that it is unlocked is output to the delay control module.

5. The delay phase-locked loop according to claim 1, characterized in that, The number of delay units that are turned on in each delay line is the same initially.

6. The delay phase-locked loop according to claim 5, characterized in that, The number of active delay units for each delay line is incremented from 0 by 1 until the phase detector output is locked, thus determining the initial number of active delay units for each delay line; including: Increment the number of active delay units for each delay line by 1, where the initial value of the number of active delay units for each delay line is 0; The output of the phase detector is obtained, wherein the output is determined by the currently received delayed clock signal and the reference clock signal; If the output result is locked, then set the first number of active delay units for each delay line to the current number of delay units minus 1, and end; otherwise, continue to increment the number of active delay units for each delay line by 1.

7. The delay phase-locked loop according to claim 1, characterized in that, According to the pre-set delay line step table, the first number of delay units that are turned on for each delay line is updated until the output of the phase detector is locked, and the second number of delay units that are turned on for each delay line is determined. include: Starting from the first row of the delay line step table, retrieve the update status of the number of conduction delay units for each delay line row by row; The current number of active delay units of the corresponding delay line is updated by utilizing the update status of the number of active delay units of each delay line; wherein, the initial value of the number of active delay units of each delay line is a first number. The output of the phase detector is obtained, wherein the output is determined by the currently received delayed clock signal and the reference clock signal; If the output result is locked, then the number of currently active delay units for each delay line is determined as the second number, and the process ends; otherwise, continue to obtain the update status of the number of active delay units for each delay line in the next row of the delay line step table.

8. A chip, characterized in that, include: The delay phase-locked loop according to any one of claims 1-7.

9. The chip according to claim 8, characterized in that, Also includes: A timer module connected to a delay phase-locked loop is configured to generate a pulse width modulation waveform with a preset frequency and duty cycle using a preset number of clock signals output by the delay phase-locked loop that have a preset phase relationship with a reference clock signal.

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