A phase frequency detector and delay-locked loop

Abstract

The application discloses a frequency discriminator and phase detector, comprising: a start control circuit, which is used for adjusting the state of an input reference signal and a to-be-locked signal based on the control of an external enable signal, and outputting signals CLK_ref and CLK_fb; a frequency discriminator and phase detector circuit, which comprises two TSPC-based D latches D1 and D2, two cross-coupled reset branches R1 and R2, and two Latch latch structures L1 and L2; wherein the latch D1, the reset branch R1 and the Latch latch structure L1 are used for performing phase detection on the input signal CLK_ref and outputting differential signals UP and UPb; and the latch D2, the reset branch R2 and the Latch latch structure L2 are used for performing phase detection on the input signal CLK_fb and outputting differential signals DN and DNb. The phase detection range of the frequency discriminator and phase detector can reach ±2π, and the design requirement of a DLL on the phase detection range can be met.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor integrated circuit technology, specifically relating to a frequency and phase detector and a delay phase-locked loop. Background Technology

[0002] With the rapid development of integrated circuits, delay-locked loops (DLLs) have become a commonly used on-chip clock generation technology. They utilize negative feedback mechanisms to achieve low jitter clocks with relatively low power consumption and area. The phase frequency detector (PFD) is a crucial component of the DLL. It is responsible for identifying the rising edges of two input signals and generating two output control signals, UP and DN, with a specific pulse width. The difference between the rising edges is proportional to the output pulse width. In the design of the PFD, the two key design parameters are detection range and detection accuracy. First, it is essential to ensure that there is no dead zone in the phase detection. While meeting this condition, the detection range should be maximized as much as possible. To meet the design requirements, a suitable circuit structure needs to be selected. To avoid false locking, a startup circuit is often added as an auxiliary step.

[0003] Traditional PFD structures with startup control circuits, such as Figure 1 As shown, the startup control circuit consists of two D flip-flops, two NAND gates, and two inverters, which suffers from large area and power consumption. The PD circuit includes two static D flip-flops, one NOR gate, and a delay unit for eliminating dead time. CLK_ref and CLK_fb are the reference clock signal and the voltage-controlled delay chain output signal, respectively. When either of them rises, the corresponding D flip-flop is set to 1. When both flip-flops are set to 1, the D flip-flop reset terminal Rst is active. When CLK_ref and CLK_fb are in phase and frequency, the UP and DN terminals of the PFD output output pulse signals of the same pulse width. This causes the CP charging and discharging switch to turn on simultaneously, resulting in the CP output current still being zero.

[0004] However, for a delay-locked loop (PLL), the phase detection range of the above circuit does not meet the requirements. If the rising edge of CLK_fb is very close to the next rising edge of CLK_ref, the reset pulse will cover the next rising edge region of the input clock, resulting in a missed phase detection of one rising edge of CLK_ref, causing an error in the PFD phase detection in the next cycle. Therefore, to ensure that the PFD functions properly, the reliable range of the PFD phase detection is reduced to 4π-2Δ, where Δ is the narrow pulse width generated by the reset, such as... Figure 2 As shown.

[0005] In summary, the phase detection range of existing frequency and phase detectors does not meet the design requirements of DLL, which is a technical problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0006] To address the technical problem that the phase detection range of existing frequency and phase detection circuits does not meet the design requirements of a delayed phase-locked loop (DLL), this invention provides a frequency and phase detector and a delayed phase-locked loop. The technical problem to be solved by this invention is achieved through the following technical solution:

[0007] In a first aspect, the present invention provides a frequency and phase detector, comprising:

[0008] The start control circuit is used to adjust the state of the input reference signal Q0 and the signal to be locked Qn based on the external enable signal, and output signals CLK_ref and CLK_fb.

[0009] The frequency and phase detector circuit includes two TSPC-based D latches D1 and D2, two cross-coupled reset branches R1 and R2, and two latch structures L1 and L2 to ensure the consistency of the output results at both ends.

[0010] In this configuration, both latch D1 and reset branch R1 are connected to the signal CLK_ref. The latch structure L1 is connected to the output of latch D1, and the input of reset branch R1 is also connected to the output of latch D2. Latch D1, reset branch R1, and latch structure L1 are used to perform phase detection on the input signal CLK_ref and output narrow pulse width differential signals UP and UPb with phase information.

[0011] Both latch D2 and reset branch R2 are connected to signal CLK_fb. Latch structure L2 is connected to the output of latch D2, and the input of reset branch R2 is also connected to the output of latch D1. Latch D2, reset branch R2 and latch structure L2 are used to perform phase detection on the input signal CLK_fb and output narrow pulse width differential signals DN and DNb with phase information.

[0012] Secondly, the present invention provides a delay phase-locked loop, including a frequency and phase detector, a charge pump, a loop filter, and a voltage-controlled delay line; the frequency and phase detector includes a start-up control circuit and a frequency and phase detector circuit.

[0013] The startup control circuit is used to suppress harmonic lock-up of the DLL, so that the DLL can quickly enter the correct lock-up state.

[0014] The differential signals UP, UPb and DN, DNb output by the frequency and phase detector circuit are used to control the two switching current sources to complete the charging and discharging of the filter capacitor.

[0015] The charge pump is used to convert the phase information output by the frequency and phase detector circuit into an analog control voltage;

[0016] The loop filter is used to establish the dynamic characteristics of the loop and filter out high-frequency noise in the output voltage of the frequency and phase detector, and works with the charge pump to generate an analog control voltage.

[0017] The voltage-controlled delay line is used to delay the input clock by one clock cycle before outputting it, so that the output clock of the last stage is phase-aligned with the input clock. The delay amount of the delay unit is adjusted by the control voltage generated by the charge pump.

[0018] The frequency and phase detector mentioned herein is the frequency and phase detector provided in the first aspect of this invention.

[0019] The beneficial effects of this invention are:

[0020] 1. The frequency and phase detector provided by this invention replaces the traditional static DFF with a dynamic DFF based on TSPC, and changes the original one reset branch to two cross-coupled reset branches, so that the phase detection range of the frequency and phase detector reaches ±2π. At the same time, the output is adjusted to differential signals UP, UPb and DN, DNb, so that the subsequent charge pump becomes differential operation mode, which effectively alleviates the charge sharing effect, reduces the static phase difference after DLL locking, and meets the design requirements of DLL for phase detection range.

[0021] 2. The present invention also simplifies the structure of the startup control circuit, using only a D flip-flop to control the corresponding timing, and introduces a dummy matching load in the first path, so that the phase of the signal output by the startup control circuit is equal to the delay time of the original signal, thereby reducing the phase detection error; and this structure reduces the noise sources introduced by the internal modules, thereby reducing power consumption and output clock jitter.

[0022] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0023] Figure 1 A schematic diagram of a traditional frequency and phase detector;

[0024] Figure 2 A schematic diagram of the phase detection range of a traditional frequency and phase detector;

[0025] Figure 3 This is a structural block diagram of a frequency and phase detector provided in an embodiment of the present invention;

[0026] Figure 4 A detailed circuit diagram of the start-up control circuit provided in an embodiment of the present invention;

[0027] Figure 5A detailed circuit diagram of the frequency and phase detector circuit provided in the embodiments of the present invention;

[0028] Figure 6 This is a schematic diagram of the phase detection range of the frequency and phase detector provided in an embodiment of the present invention;

[0029] Figure 7 This is a structural block diagram of a delay phase-locked loop provided in an embodiment of the present invention. Detailed Implementation

[0030] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.

[0031] Example 1

[0032] Please see Figure 3 , Figure 3 This is a structural block diagram of a frequency and phase detector provided in an embodiment of the present invention. The frequency and phase detector provided in this embodiment includes:

[0033] The start control circuit SC is used to adjust the state of the input reference signal Q0 and the signal to be locked Qn based on the external enable signal, and output signals CLK_ref and CLK_fb.

[0034] The frequency and phase detector circuit PFD includes two D latches D1 and D2 based on TSPC (True Single Phase Clock), two cross-coupled reset branches R1 and R2, and two latch structures L1 and L2 to ensure the consistency of the output results at both ends.

[0035] In this circuit, latch D1 and reset branch R1 are both connected to the signal CLK_ref. Latch structure L1 is connected to the output of latch D1, and the input of reset branch R1 is also connected to the output of latch D2. Latch D1, reset branch R1 and latch structure L1 are used to perform phase detection on the input signal CLK_ref and output narrow pulse width differential signals UP and UPb with phase information.

[0036] Both latch D2 and reset branch R2 are connected to the signal CLK_fb. Latch structure L2 is connected to the output of latch D2, and the input of reset branch R2 is also connected to the output of latch D1. Latch D2, reset branch R2 and latch structure L2 are used to perform phase detection on the input signal CLK_fb and output narrow pulse width differential signals DN and DNb with phase information.

[0037] Alternatively, as one implementation method, please refer to Figure 4 , Figure 4This is a detailed circuit diagram of the startup control circuit provided in an embodiment of the present invention. The startup control circuit provided in this embodiment includes a D flip-flop DFF1, a first buffer BUF1, a capacitor C, a first NAND gate NAND1, a second NAND gate NAND2, a first inverter INV1, and a second inverter INV2; wherein,

[0038] The input of D flip-flop DFF1 is connected to a high level VDD. The CLK terminal of D flip-flop DFF1 is connected to the output of the first NAND gate NAND1. The reset terminal of D flip-flop DFF1 is connected to an external enable signal START.

[0039] One input of the first NAND gate NAND1 is connected to the output of the D flip-flop DFF1, and the other input is connected to the reference signal Q0.

[0040] The input of the first inverter INV1 is connected to the output of the first NAND gate NAND1;

[0041] One end of capacitor C is connected to the input terminal of the first inverter INV1, and the other end is grounded;

[0042] The output of the first inverter INV1 serves as the first output of the start control circuit, outputting the signal CLK_ref.

[0043] The input of the first buffer BUF1 is connected to an external enable signal START;

[0044] One input of the second NAND gate NAND2 is connected to the output of the first buffer BUF1, and the other input is connected to the signal Qn to be locked.

[0045] The input of the second inverter INV2 is connected to the output of the second NAND gate NAND2;

[0046] The output of the second inverter INV2 serves as the second output of the start control circuit, outputting the signal CLK_fb.

[0047] The D flip-flop DFF1, the first NAND gate NAND1, the capacitor C, and the first inverter INV1 constitute the first path Path1, and the first buffer BUF1, the second NAND gate NAND2, and the second inverter INV2 constitute the second path Path2.

[0048] This embodiment adjusts the input reference signal and the signal to be locked into the initial state of the phase detector by adjusting the startup control circuit; this effectively prevents harmonic lock-up of the DLL, allowing the DLL to quickly enter the correct locking state. Compared with traditional frequency and phase detectors, this embodiment simplifies the structure of the startup control circuit, using only a D flip-flop to control the corresponding timing, and introduces a dummy matching load in the first path, making the phase of the signal output by the startup control circuit equal to the delay time of the original signal, thus reducing phase detection error; moreover, this structure reduces noise sources introduced by internal modules, lowering power consumption and output clock jitter.

[0049] Furthermore, the frequency and phase detector circuit provided by this invention replaces the static DFF with a dynamic DFF based on TSPC. Specifically, in this embodiment, both latch D1 and latch D2 include multi-stage cascaded inverters, and the inverters are CMOS inverters with pre-charge transistors; wherein,

[0050] The first input of the first-stage inverter of latch D1 is connected to the first output of the start control circuit to receive the signal CLK_ref; the second input of the first-stage inverter of latch D1 is connected to the output of the reset branch R1; the input of the intermediate-stage inverter of latch D1 is connected to the output of the previous stage inverter; the output of the last-stage inverter of latch D1 is connected to the input of the latch structure L1.

[0051] The first input of the first-stage inverter of latch D2 is connected to the second output of the start control circuit to receive the signal CLK_fb; the second input of the first-stage inverter of latch D2 is connected to the output of the reset branch R2; the input of the intermediate-stage inverter of latch D2 is connected to the output of the previous stage inverter; the output of the last-stage inverter of latch D2 is connected to the input of the latch structure L2.

[0052] Alternatively, as one implementation method, please refer to Figure 5 , Figure 5 A detailed circuit diagram of a frequency and phase detector circuit provided in an embodiment of the present invention is shown. The latch D1 includes two cascaded inverters: the first inverter includes a first PMOS transistor PM1, a third PMOS transistor PM3, and a second NMOS transistor NM2; the second inverter includes a second PMOS transistor PM2, a first NMOS transistor NM1, and a third NMOS transistor NM3.

[0053] The gate of the third PMOS transistor PM3 is connected to the first output of the startup control circuit as the first input of the first-stage inverter; the gate of the first PMOS transistor PM1 and the gate of the second NMOS transistor NM2 are connected to the output of the reset branch R1 as the second input of the first-stage inverter.

[0054] The source of the first PMOS transistor PM1 and the source of the second PMOS transistor PM2 are both connected to the power supply.

[0055] The drain of the first PMOS transistor PM1 is connected to the source of the third PMOS transistor PM3.

[0056] The drain of the third PMOS transistor PM3 is connected to the drain of the second NMOS transistor NM2, and is connected to the gate of the second PMOS transistor PM2 and the gate of the third NMOS transistor NM3 as the output terminal of the first stage inverter.

[0057] The source of the second NMOS transistor NM2 and the source of the third NMOS transistor NM3 are grounded;

[0058] The gate of the first NMOS transistor NM1 is connected to the first output terminal of the startup control circuit;

[0059] The source of the first NMOS transistor NM1 is connected to the drain of the third NMOS transistor NM3;

[0060] The drain of the second PMOS transistor PM2 is connected to the drain of the first NMOS transistor NM1, and serves as the output of the second-stage inverter and latch D1.

[0061] Among them, the third PMOS transistor PM3 and the first NMOS transistor NM1 are pre-charge transistors; and the substrates of all PMOS transistors are connected to the power supply VDD, while the substrates of all NMOS transistors are grounded.

[0062] Correspondingly, latch D2 includes two cascaded inverters, wherein the first inverter includes the fourth PMOS transistor PM4, the sixth PMOS transistor PM6, and the fifth NMOS transistor NM5; and the second inverter includes the fifth PMOS transistor PM5, the fourth NMOS transistor NM4, and the sixth NMOS transistor NM6.

[0063] The gate of the sixth PMOS transistor PM6 is connected to the second output of the startup control circuit as the first input of the first-stage inverter; the gates of the fourth PMOS transistor PM4 and the fifth NMOS transistor NM5 are connected to the output of the reset branch R2 as the second input of the first-stage inverter.

[0064] The source of the fourth PMOS transistor PM4 and the source of the fifth PMOS transistor PM5 are both connected to the power supply.

[0065] The drain of the fourth PMOS transistor PM4 is connected to the source of the sixth PMOS transistor PM6.

[0066] The drain of the sixth PMOS transistor PM6 is connected to the drain of the fifth NMOS transistor NM5, and serves as the output terminal of the first-stage inverter, connecting the gate of the fifth PMOS transistor PM5 and the gate of the sixth NMOS transistor NM6.

[0067] The source of the fifth NMOS transistor NM5 and the source of the sixth NMOS transistor NM6 are grounded;

[0068] The gate of the fourth NMOS transistor NM4 is connected to the first output terminal of the startup control circuit;

[0069] The source of the fourth NMOS transistor NM4 is connected to the drain of the sixth NMOS transistor NM6;

[0070] The drain of the fifth PMOS transistor PM5 is connected to the drain of the fourth NMOS transistor NM4, and serves as the output of the second-stage inverter and latch D2.

[0071] Among them, the sixth PMOS transistor PM6 and the fourth NMOS transistor NM4 are pre-charge transistors; and the substrates of all PMOS transistors are connected to the power supply VDD, while the substrates of all NMOS transistors are grounded.

[0072] Furthermore, this embodiment replaces one reset branch in the existing frequency and phase detector circuit with two cross-coupled reset branches R1 and R2. For details, please refer to [link to documentation]. Figure 5 The reset branch R1 includes a third inverter INV3, a first NOR gate NOR1, and a second buffer BUF2;

[0073] The input terminal of the third inverter INV3 is connected to the first output terminal of the start control circuit;

[0074] One input of the first NOR gate NOR1 is connected to the output of the third inverter INV3, and the other input is connected to the output of the latch D2.

[0075] The input of the second buffer BUF2 is connected to the output of the first NOR gate NOR1;

[0076] The output of the second buffer BUF2 serves as the output of the reset branch R1 and is connected to the second input of the first-stage inverter in latch D1.

[0077] Accordingly, the reset branch R2 includes a fourth inverter INV4, a second NOR gate NOR2, and a third buffer BUF3; wherein,

[0078] The input terminal of the fourth inverter INV4 is connected to the second output terminal of the start-up control circuit;

[0079] One input of the second NOR gate NOR2 is connected to the output of the fourth inverter INV4, and the other input is connected to the output of the latch D1.

[0080] The input of the third buffer BUF3 is connected to the output of the second NOR gate NOR2;

[0081] The output of the third buffer BUF3 serves as the output of the reset branch R2 and is connected to the second input of the first-stage inverter in latch D2.

[0082] In addition, in order to effectively alleviate the charge sharing effect and reduce the static phase difference after DLL locking, the subsequent charge pump input is selected to operate in a differential mode of UP, UPb and DN, DNb. In order to ensure the consistency of the above signals output by PFD, latch structures L1 and L2 are adopted to ensure the consistency of the dual-end output results.

[0083] For details, please continue to see Figure 5 The latch structure L1 includes a fourth buffer BUF4, a transmission gate TD1, a fifth inverter INV5, a sixth inverter INV6, a seventh inverter INV7, an eighth inverter INV8, and a ninth inverter INV9;

[0084] The input of the fourth buffer BUF4 is connected to the output of the latch D1 as the input of the latch structure L1.

[0085] The output of the fourth buffer BUF4 is divided into two branches. The first branch is connected in series with the fifth inverter INV5, the sixth inverter INV6, and the seventh inverter INV7. The second branch is connected in series with the transmission gate TD1, the eighth inverter INV8, and the ninth inverter INV9.

[0086] In transmission gate TD1, the NMOS gate is connected to the power supply, and the PMOS gate is grounded.

[0087] The output of the sixth inverter INV6 is also connected to the input of the eighth inverter INV8, and the input of the sixth inverter INV6 is also connected to the output of the eighth inverter INV8.

[0088] The outputs of the seventh inverter INV7 and the ninth inverter INV9 serve as the outputs of the Latch structure L1, outputting narrow pulse width differential signals UP and UPb, respectively.

[0089] Correspondingly, the latch structure L2 includes the fifth buffer BUF5, the second transmission gate TD2, the tenth inverter INV10, the eleventh inverter INV11, the twelfth inverter INV12, the thirteenth inverter INV13, and the fourteenth inverter INV14.

[0090] The input of the fifth buffer BUF5 is connected to the output of latch D2 as the input of latch structure L2.

[0091] The output of the fifth buffer BUF5 is divided into two branches. The first branch is connected in series with the tenth inverter INV10, the eleventh inverter INV11, and the twelfth inverter INV12. The second branch is connected in series with the second transmission gate TD2, the thirteenth inverter INV13, and the fourteenth inverter INV14.

[0092] In the second transmission gate TD2, the NMOS gate is connected to the power supply, and the PMOS gate is grounded.

[0093] The output of the eleventh inverter INV11 is also connected to the input of the thirteenth inverter INV13, and the input of the eleventh inverter INV11 is also connected to the output of the thirteenth inverter INV13.

[0094] The outputs of the twelfth inverter INV12 and the fourteenth inverter INV14 serve as the outputs of the Latch structure L2, outputting narrow pulse width differential signals DN and DNb, respectively.

[0095] Please refer to the above. Figure 5 and Figure 6 , Figure 6 This is a schematic diagram of the phase detection characteristic curve of a frequency-phase detector provided in an embodiment of the present invention. Wherein, Figure 5 In the circuit, node A is one input of the first NOR gate NOR1 in the reset branch R1, node B is the other input of the first NOR gate NOR1, node C is the output of the first NOR gate NOR1, and node D is the output of the first stage inverter in latch D1, which is also the connection between the drain of the third PMOS transistor PM3 and the drain of the second NMOS transistor NM2; node A' is one input of the second NOR gate NOR2 in the reset branch R2, node B' is the other input of the second NOR gate NOR2, node C' is the output of the second NOR gate NOR2, and node D' is the output of the first stage inverter in latch D2, which is also the connection between the drain of the sixth PMOS transistor PM6 and the drain of the fifth NMOS transistor NM5.

[0096] Under initial conditions, when CLK_ref, CLK_fb, UP, and DN are all low, nodes D / D' are pre-charged to high. When the rising edge of CLK_ref precedes the rising edge of CLK_fb (i.e., during the period when CLK_ref is high and CLK_fb is still low), node B' discharges to low, forming a high-level pulse for UP after passing through an inverter. Since node B is still high, node C remains low. If the rising edge of CLK_fb arrives before the falling edge of CLK_ref, then after the output rising edge arrives, D' is inverted and transmitted to node B, resulting in a low level, triggering DN to generate a high-level pulse. Subsequently, since A, B, A', and B' are all low, after passing through a NOR gate, nodes C and C' are high, initiating the reset path. The C / C' signal, after three stages of inverted transmission, forces UP and DN to be simultaneously pulled down and reset to low. The width of the narrow pulse for DN is determined by the sum of the propagation delays of the NOR gate and the three stages of INV gates. The phase detection analysis process and results described above for the (0, π) phase difference range also apply to the (-π, 0) phase difference range. Therefore, in the (-π, π) range, the PFD exhibits linear gain characteristics.

[0097] Within the range of (π, 2π), if the rising edge of the output clock lags behind the rising edge of the input clock by half a clock cycle (i.e., the rising edge of the output clock arrives after the falling edge of the input clock), then a phase detection mechanism similar to that in the range of (0, π) also holds true within the range of (-2π, -π). Therefore, within the ranges of (-2π, -π) and (π, 2π), UP remains at a fixed high level after the rising edge of the input reference clock arrives, while DN remains fixed as the reset pulse triggered by the rising edge of the output clock. That is, the effective pulse width of UP-DN is fixed within each phase detection cycle, and the voltage output by CP is constant.

[0098] Within the range of (-π, π), the UP and DN pulses are reset to low level; while within the ranges of (-2π, -π) and (π, 2π), only the pulses with phase lag are reset to low level, while the pulses with phase lead remain high. Thus, the PFD output voltage exhibits a linear variation characteristic within the range of (-π, π), meaning the PFD gain is constant; within the ranges of (-2π, -π) and (π, 2π), the output voltage saturates, corresponding to the maximum and minimum outputs, respectively, meaning the PFD gain is constant at 0. Therefore, within the entire ±2π phase difference range, the PFD phase detector exhibits nonlinear characteristics, with a linear region within the ±π sub-region and a nonlinear saturation region in the remaining region. At the critical point ±π, the output voltage exhibits a jump. The complete phase detection characteristic curve is shown below. Figure 6 As shown.

[0099] The frequency and phase detector provided by this invention replaces the traditional static DFF with a dynamic DFF based on TSPC, and changes the original single reset branch to two cross-coupled reset branches, so that the phase detection range of the frequency and phase detector reaches ±2π. At the same time, the output is adjusted to differential signals UP, UPb and DN, DNb, so that the subsequent charge pump operates in differential mode, effectively mitigating the charge sharing effect, reducing the static phase difference after DLL locking, and meeting the design requirements of DLL for phase detection range.

[0100] Example 2

[0101] Based on Embodiment 1 above, this embodiment provides a delayed phase-locked loop. Please refer to... Figure 7 , Figure 7 This is a structural block diagram of a delay phase-locked loop provided in an embodiment of the present invention.

[0102] This embodiment provides a delay phase-locked loop including a frequency and phase detector, a charge pump, a loop filter, and a voltage-controlled delay line. The frequency and phase detector includes a start-up control circuit and a frequency and phase detector circuit.

[0103] The start-up control circuit is used to suppress harmonic lock-up of the DLL, enabling the DLL to quickly enter the correct lock-up state.

[0104] The differential signals UP, UPb and DN, DNb output by the frequency and phase detector circuit are used to control the two switching current sources to complete the charging and discharging of the filter capacitor.

[0105] A charge pump is used to convert the phase information output by the frequency and phase detector circuit into an analog control voltage;

[0106] The loop filter is used to establish the dynamic characteristics of the loop and filter out high-frequency noise in the output voltage of the frequency and phase detector, and works with the charge pump to generate analog control voltage.

[0107] The voltage-controlled delay line is used to delay the input clock by one clock cycle before outputting, so that the output clock of the last stage is phase-aligned with the input clock. The delay amount of the delay unit is adjusted by the control voltage generated by the charge pump.

[0108] The circuit structure of the frequency and phase detector adopts the frequency and phase detector provided in the above embodiment one. The specific circuit structure can be referred to the above embodiment one. This embodiment will not be described in detail here.

[0109] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A frequency and phase detector, characterized in that, include: The start control circuit is used to adjust the state of the input reference signal Q0 and the signal to be locked Qn based on the external enable signal, and output signals CLK_ref and CLK_fb. The frequency and phase detector circuit includes two TSPC-based D latches D1 and D2, two cross-coupled reset branches R1 and R2, and two latch structures L1 and L2 to ensure the consistency of the output results at both ends. In this configuration, both latch D1 and reset branch R1 are connected to the signal CLK_ref. The latch structure L1 is connected to the output of latch D1, and the input of reset branch R1 is also connected to the output of latch D2. Latch D1, reset branch R1, and latch structure L1 are used to perform phase detection on the input signal CLK_ref and output narrow pulse width differential signals UP and UPb with phase information. Both latch D2 and reset branch R2 are connected to signal CLK_fb. Latch structure L2 is connected to the output of latch D2, and the input of reset branch R2 is also connected to the output of latch D1. Latch D2, reset branch R2 and latch structure L2 are used to perform phase detection on the input signal CLK_fb and output narrow pulse width differential signals DN and DNb with phase information.

2. The frequency and phase detector according to claim 1, characterized in that, The startup control circuit includes a D flip-flop DFF1, a first buffer BUF1, a capacitor C, a first NAND gate NAND1, a second NAND gate NAND2, a first inverter INV1, and a second inverter INV2; wherein... The input of the D flip-flop DFF1 is connected to a high level VDD, the CLK terminal of the D flip-flop DFF1 is connected to the output of the first NAND gate NAND1, and the reset terminal Reset of the D flip-flop DFF1 is connected to an external enable signal START. One input of the first NAND gate NAND1 is connected to the output of the D flip-flop DFF1, and the other input is connected to the reference signal Q0. The input terminal of the first inverter INV1 is connected to the output terminal of the first NAND gate NAND1; One end of the capacitor C is connected to the input terminal of the first inverter INV1, and the other end is grounded; The output of the first inverter INV1 serves as the first output of the start control circuit, outputting the signal CLK_ref. The input terminal of the first buffer BUF1 is connected to an external enable signal START; One input of the second NAND gate NAND2 is connected to the output of the first buffer BUF1, and the other input is connected to the lock signal Qn; The input of the second inverter INV2 is connected to the output of the second NAND gate NAND2; The output of the second inverter INV2 serves as the second output of the start control circuit, outputting the signal CLK_fb. The D flip-flop DFF1, the first NAND gate NAND1, the capacitor C, and the first inverter INV1 constitute the first path Path1, and the first buffer BUF1, the second NAND gate NAND2, and the second inverter INV2 constitute the second path Path2.

3. The frequency and phase detector according to claim 1, characterized in that, Both latches D1 and D2 include multi-stage cascaded inverters, and the inverters are CMOS inverters with pre-charge transistors; wherein, The first input terminal of the first-stage inverter of latch D1 is connected to the first output terminal of the start control circuit to receive the signal CLK_ref; the second input terminal of the first-stage inverter of latch D1 is connected to the output terminal of the reset branch R1; the input terminal of the intermediate-stage inverter of latch D1 is connected to the output terminal of the previous stage inverter; the output terminal of the last-stage inverter of latch D1 is connected to the input terminal of the latch structure L1. The first input terminal of the first-stage inverter of latch D2 is connected to the second output terminal of the start control circuit to receive the signal CLK_fb; the second input terminal of the first-stage inverter of latch D2 is connected to the output terminal of the reset branch R2; the input terminal of the intermediate-stage inverter of latch D2 is connected to the output terminal of the previous stage inverter; the output terminal of the last-stage inverter of latch D2 is connected to the input terminal of the latch structure L2.

4. The frequency and phase detector according to claim 3, characterized in that, The latch D1 includes two cascaded inverters, wherein the first inverter includes a first PMOS transistor PM1, a third PMOS transistor PM3, and a second NMOS transistor NM2; and the second inverter includes a second PMOS transistor PM2, a first NMOS transistor NM1, and a third NMOS transistor NM3. The gate of the third PMOS transistor PM3 is connected to the first output terminal of the startup control circuit as the first input terminal of the first-stage inverter; the gates of the first PMOS transistor PM1 and the second NMOS transistor NM2 are connected to the output terminal of the reset branch R1 as the second input terminal of the first-stage inverter. The source of the first PMOS transistor PM1 and the source of the second PMOS transistor PM2 are both connected to a power supply. The drain of the first PMOS transistor PM1 is connected to the source of the third PMOS transistor PM3; The drain of the third PMOS transistor PM3 is connected to the drain of the second NMOS transistor NM2, and serves as the output terminal of the first-stage inverter, connected to the gate of the second PMOS transistor PM2 and the gate of the third NMOS transistor NM3. The source of the second NMOS transistor NM2 and the source of the third NMOS transistor NM3 are grounded; The gate of the first NMOS transistor NM1 is connected to the first output terminal of the startup control circuit; The source of the first NMOS transistor NM1 is connected to the drain of the third NMOS transistor NM3; The drain of the second PMOS transistor PM2 is connected to the drain of the first NMOS transistor NM1, and serves as the output of the second-stage inverter and latch D1. The third PMOS transistor PM3 and the first NMOS transistor NM1 are pre-charge transistors; and the substrates of all PMOS transistors are connected to the power supply VDD, while the substrates of all NMOS transistors are grounded.

5. The frequency and phase detector according to claim 3, characterized in that, The latch D2 includes two cascaded inverters, wherein the first inverter includes a fourth PMOS transistor PM4, a sixth PMOS transistor PM6, and a fifth NMOS transistor NM5; and the second inverter includes a fifth PMOS transistor PM5, a fourth NMOS transistor NM4, and a sixth NMOS transistor NM6. The gate of the sixth PMOS transistor PM6 is connected to the second output of the startup control circuit as the first input of the first-stage inverter; the gates of the fourth PMOS transistor PM4 and the fifth NMOS transistor NM5 are connected to the output of the reset branch R2 as the second input of the first-stage inverter. The source of the fourth PMOS transistor PM4 and the source of the fifth PMOS transistor PM5 are both connected to a power supply. The drain of the fourth PMOS transistor PM4 is connected to the source of the sixth PMOS transistor PM6. The drain of the sixth PMOS transistor PM6 is connected to the drain of the fifth NMOS transistor NM5, and serves as the output terminal of the first-stage inverter, which is connected to the gate of the fifth PMOS transistor PM5 and the gate of the sixth NMOS transistor NM6. The source of the fifth NMOS transistor NM5 and the source of the sixth NMOS transistor NM6 are grounded; The gate of the fourth NMOS transistor NM4 is connected to the first output terminal of the startup control circuit; The source of the fourth NMOS transistor NM4 is connected to the drain of the sixth NMOS transistor NM6; The drain of the fifth PMOS transistor PM5 is connected to the drain of the fourth NMOS transistor NM4, and serves as the output of the second-stage inverter and latch D2. Among them, the sixth PMOS transistor PM6 and the fourth NMOS transistor NM4 are pre-charge transistors; and the substrates of all PMOS transistors are connected to the power supply VDD, while the substrates of all NMOS transistors are grounded.

6. The frequency and phase detector according to claim 1, characterized in that, The reset branch R1 includes a third inverter INV3, a first NOR gate NOR1, and a second buffer BUF2; wherein... The input terminal of the third inverter INV3 is connected to the first output terminal of the start-up control circuit; One input of the first NOR gate NOR1 is connected to the output of the third inverter INV3, and the other input is connected to the output of the latch D2. The input of the second buffer BUF2 is connected to the output of the first NOR gate NOR1; The output of the second buffer BUF2 serves as the output of the reset branch R1 and is connected to the second input of the first-stage inverter in the latch D1.

7. The frequency and phase detector according to claim 1, characterized in that, The reset branch R2 includes a fourth inverter INV4, a second NOR gate NOR2, and a third buffer BUF3; wherein... The input terminal of the fourth inverter INV4 is connected to the second output terminal of the start-up control circuit; One input of the second NOR gate NOR2 is connected to the output of the fourth inverter INV4, and the other input is connected to the output of the latch D1. The input of the third buffer BUF3 is connected to the output of the second NOR gate NOR2; The output of the third buffer BUF3 serves as the output of the reset branch R2 and is connected to the second input of the first-stage inverter in the latch D2.

8. The frequency and phase detector according to claim 1, characterized in that, The latch structure L1 includes a fourth buffer BUF4, a transmission gate TD1, a fifth inverter INV5, a sixth inverter INV6, a seventh inverter INV7, an eighth inverter INV8, and a ninth inverter INV9; wherein... The input of the fourth buffer BUF4 is connected to the output of the latch D1 as the input of the latch structure L1. The output of the fourth buffer BUF4 is divided into two branches. The first branch is connected in series with the fifth inverter INV5, the sixth inverter INV6, and the seventh inverter INV7. The second branch is connected in series with the transmission gate TD1, the eighth inverter INV8, and the ninth inverter INV9. The NMOS gate in the transmission gate TD1 is connected to the power supply, and the PMOS gate is grounded. The output terminal of the sixth inverter INV6 is also connected to the input terminal of the eighth inverter INV8, and the input terminal of the sixth inverter INV6 is also connected to the output terminal of the eighth inverter INV8. The output terminals of the seventh inverter INV7 and the ninth inverter INV9 serve as the output terminals of the latch structure L1, respectively outputting narrow pulse width differential signals UP and UPb.

9. The frequency and phase detector according to claim 3, characterized in that, The latch structure L2 includes a fifth buffer BUF5, a second transmission gate TD2, a tenth inverter INV10, an eleventh inverter INV11, a twelfth inverter INV12, a thirteenth inverter INV13, and a fourteenth inverter INV14. The input terminal of the fifth buffer BUF5 is connected to the output terminal of the latch structure L2 as the input terminal of the latch D2. The output of the fifth buffer BUF5 is divided into two branches. The first branch is connected in series with the tenth inverter INV10, the eleventh inverter INV11, and the twelfth inverter INV12. The second branch is connected in series with the second transmission gate TD2, the thirteenth inverter INV13, and the fourteenth inverter INV14. In the second transmission gate TD2, the NMOS gate is connected to the power supply, and the PMOS gate is grounded; The output terminal of the eleventh inverter INV11 is also connected to the input terminal of the thirteenth inverter INV13, and the input terminal of the eleventh inverter INV11 is also connected to the output terminal of the thirteenth inverter INV13. The output terminals of the twelfth inverter INV12 and the fourteenth inverter INV14 serve as the output terminals of the latch structure L2, outputting narrow pulse width differential signals DN and DNb respectively.

10. A delay phase-locked loop, characterized in that, It includes a frequency and phase detector, a charge pump, a loop filter, and a voltage-controlled delay line; the frequency and phase detector includes a startup control circuit and a frequency and phase detector circuit. The startup control circuit is used to suppress harmonic lock-up of the DLL, so that the DLL can quickly enter the correct lock-up state. The differential signals UP, UPb and DN, DNb output by the frequency and phase detector circuit are used to control the two switching current sources to complete the charging and discharging of the filter capacitor. The charge pump is used to convert the phase information output by the frequency and phase detector circuit into an analog control voltage; The loop filter is used to establish the dynamic characteristics of the loop and filter out high-frequency noise in the output voltage of the frequency and phase detector, and works with the charge pump to generate an analog control voltage. The voltage-controlled delay line is used to delay the input clock by one clock cycle before outputting it, so that the output clock of the last stage is phase-aligned with the input clock. The delay amount of the delay unit is adjusted by the control voltage generated by the charge pump. The frequency and phase detector is the frequency and phase detector according to any one of claims 1 to 9.

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