A differential charge pump circuit applied to a delay-locked loop
Patent Information
- Application Number
- CN202311287247.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2023-10-07
- Publication Date
- 2026-10-30
- Estimated Expiration
- 2043-10-07
AI Technical Summary
即使DLL电路处于锁定状态，LF上仍有可能有电荷转移，导致控制电压Vctrl产生波动，增大锁定后的静态相位误差以及输出时钟的抖动
[0012]本发明的应用于延迟锁相环的差分型电荷泵电路，克服了传统的单端电荷泵无法很好的抑制电流源失配导致DLL锁定后静态相差增大以及Cascode结构导致控制电压摆幅受限的问题，通过差分型的开关电路有效缓解电荷共享问题，抑制电流失配，减小DLL锁定后的静态相差；通过改进Cascode电路，降低其中晶体管的过驱动电压，从而使控制电压的摆幅得到有效拓展。
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Figure CN117254803B_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of integrated circuit technology, specifically relating to a differential charge pump circuit applied to a delay phase-locked loop. Background Technology
[0002] A typical delay phase-locked loop (DLL) circuit includes a phase frequency detector (PFD), a charge pump (CP), a loop filter (LF), and a voltage-controlled delay chain (VCDL), such as... Figure 1 As shown. A delay-locked loop (VCDL) is a negative feedback system that adjusts the delay time of the VCDL by detecting and identifying the phase difference between two input periodic signals. When the system is stable, the precise delay generated does not change with external conditions. Initially, because the edges of the input reference clock and the feedback output clock are misaligned, the DLL is in an unlocked state. The PFD module detects and identifies a clock signal with a certain phase difference, outputting two pulse control signals UP and DN to guide the subsequent CP to charge and discharge the LF, changing the value of the control voltage Vctrl, thereby adjusting the delay time of the VCDL. This achieves the function of adjusting the phase relationship between the input and output clocks. The output is fed back to the PFD for the next cycle of phase detection adjustment. The phase difference between the two signals is 2π, ultimately ensuring that the delay time between the input reference clock and the output clock is exactly one clock cycle of the input reference signal, while the output clock frequency is the same as the input reference clock frequency. After the DLL completes locking, it enters a dynamically balanced locked state.
[0003] Traditional single-ended charge pumps along with loop filters, such as Figure 2 As shown, a switch controlled by the UP signal has one end connected to a voltage source vdd and the other end connected to a current source I. UP The other end of the current source is connected to another current source I. DN I DN The other end is connected to a switch, which is controlled by a DN signal. The other end of the switch is grounded. A capacitor is connected between the two current sources as a low-pass filter, and the final output is Vctrl. The two current sources I... DN and I UP The currents are equal. When the UP signal is high and the DN signal is low, the upper switch is open and the lower switch is closed, the output node of the charge pump is charged and the voltage increases; conversely, the output node is discharged and the voltage decreases; if both UP and DN are high or low, the output node does not charge or discharge and the voltage remains unchanged.
[0004] Many factors can negatively impact charge pump performance, with the mismatch between the upper and lower current sources being a critical one. Even when the DLL circuit is locked, charge transfer can still occur on the LF, causing fluctuations in the control voltage Vctrl, increasing the static phase error after locking and the jitter of the output clock. Furthermore, since the delay generated by the subsequent VCDL is affected by Vctrl, a large swing of Vctrl is required to achieve a wide delay time range, especially important in low-voltage processes.
[0005] Therefore, how to reduce the charging and discharging current mismatch in the charge pump circuit of the phase-locked loop and increase the control voltage swing is a technical problem that urgently needs to be solved by those skilled in the art. Summary of the Invention
[0006] To address the aforementioned problems in the prior art, this invention provides a differential charge pump circuit applied to a delay phase-locked loop. The technical problem to be solved by this invention is achieved through the following technical solution:
[0007] This invention provides a differential charge pump circuit for a delay phase-locked loop, comprising: a Cascode current mirror circuit and a switching circuit, wherein,
[0008] The output of the Cascode current mirror circuit is connected to the input of the switching circuit, and the output of the switching circuit is connected to the input of the low-pass filter.
[0009] The Cascode current mirror circuit includes a basic current mirror and an improved Cascode circuit. The basic current mirror is used to replicate the current of the current source and input the replicated current to the improved Cascode circuit. The improved Cascode circuit is used to generate charging current and discharging current according to the current, and increases the swing of the control voltage output by the switching circuit by adding a series MOS transistor.
[0010] The switching circuit is a differential switching circuit, used to control the charging and discharging of the Cascode current mirror circuit according to the pulse control signal output by the frequency and phase detector, and to generate the control voltage through the low-pass filter.
[0011] Compared with the prior art, the beneficial effects of the present invention are as follows:
[0012] The differential charge pump circuit of this invention, applied to a delay phase-locked loop (DLL), overcomes the problems of traditional single-ended charge pumps failing to effectively suppress the increase in static phase difference after DLL lock-in due to current source mismatch and the limitation of control voltage swing caused by the Cascode structure. By using a differential switching circuit, it effectively alleviates the charge sharing problem, suppresses current mismatch, and reduces the static phase difference after DLL lock-in. By improving the Cascode circuit, it reduces the overdrive voltage of the transistors, thereby effectively expanding the control voltage swing.
[0013] The above description is merely an overview of the technical solution of the present invention. In order to better understand the technical means of the present invention and to implement it in accordance with the contents of the specification, and to make the above and other objects, features and advantages of the present invention more apparent and understandable, preferred embodiments are described in detail below with reference to the accompanying drawings. Attached Figure Description
[0014] Figure 1 This is a diagram of a traditional delay phase-locked loop structure provided by an embodiment of the present invention.
[0015] Figure 2 This is a schematic diagram of a conventional single-ended charge pump and low-pass filter structure provided by an embodiment of the present invention;
[0016] Figure 3 This is a structural block diagram of a differential charge pump circuit applied to a delay phase-locked loop provided by an embodiment of the present invention;
[0017] Figure 4 This is a circuit diagram of a differential charge pump circuit applied to a delay phase-locked loop provided by an embodiment of the present invention. Detailed Implementation
[0018] To further illustrate the technical means and effects adopted by the present invention to achieve the intended purpose, the following describes in detail a differential charge pump circuit applied to a delay phase-locked loop according to the present invention, in conjunction with the accompanying drawings and specific embodiments.
[0019] The foregoing and other technical contents, features, and effects of the present invention will be clearly presented in the following detailed description of specific embodiments in conjunction with the accompanying drawings. Through the description of the specific embodiments, a more in-depth and concrete understanding can be gained of the technical means and effects adopted by the present invention to achieve its intended purpose. However, the accompanying drawings are for reference and illustration only and are not intended to limit the technical solutions of the present invention.
[0020] This invention provides a differential charge pump circuit applied to a delay phase-locked loop (PLL). Please refer to [link to relevant documentation]. Figure 3 and Figure 4 , Figure 3This is a structural block diagram of a differential charge pump circuit applied to a delay phase-locked loop provided by an embodiment of the present invention; Figure 4 This is a circuit diagram of a differential charge pump circuit applied to a delay phase-locked loop provided by an embodiment of the present invention.
[0021] like Figure 3 As shown, the differential charge pump circuit applied to the delay phase-locked loop in this embodiment includes a Cascode current mirror circuit 10 and a switching circuit 20. The output terminal of the Cascode current mirror circuit 10 is connected to the input terminal of the switching circuit 20, and the output terminal of the switching circuit 20 is connected to the input terminal of the low-pass filter 30.
[0022] In an optional embodiment, the Cascode current mirror circuit 10 includes a basic current mirror 101 and an improved Cascode circuit. The basic current mirror 101 is used to replicate the current of the current source and input the replicated current to the improved Cascode circuit; the improved Cascode circuit is used to generate charging current and discharging current according to the current, and to increase the swing of the control voltage Vctrl output by the switching circuit by adding a series MOSFET.
[0023] In this embodiment, the current source is a current source provided by the bandgap.
[0024] In this embodiment, the improved Cascode circuit includes: a first Cascode branch 102 and a second Cascode branch 103, wherein the input terminal of the first Cascode branch 102 is connected to the first output terminal of the basic current mirror 101, and is used to generate a charging current based on the current replicated by the basic current mirror 101; the input terminal of the second Cascode branch 103 is connected to the second output terminal of the basic current mirror 101, and is used to generate a discharging current based on the current replicated by the basic current mirror 101; the mismatch rate between the charging current and the discharging current is less than 1%.
[0025] In an optional embodiment, the switching circuit 20 is a differential switching circuit used to control the charging and discharging of the Cascode current mirror circuit 10 according to the pulse control signal output by the frequency and phase detector, and to generate a control voltage Vctrl through the low-pass filter 30.
[0026] In this embodiment, the frequency and phase detector outputs two pulse control signals, including a first pulse control signal UP and a second pulse control signal DN.
[0027] like Figure 2As shown, in this embodiment, the basic current mirror 101 includes: MOSFET M19, MOSFET M20, MOSFET M21, MOSFET M22, MOSFET M23, MOSFET M24, MOSFET M25, MOSFET M26, MOSFET M27 and MOSFET M28.
[0028] In this configuration, the drain of MOSFET M19 is connected to its gate and current source, and its source is connected to the drain of MOSFET M21. The gates of MOSFET M21 and M22 are both connected to the power supply, and the sources of MOSFET M21 and M22 are both connected to the ground. The drain of MOSFET M22 is connected to the source of MOSFET M20, and the gate of MOSFET M20 is connected to the gate of MOSFET M19. The gate of MOSFET M26 is connected to the power supply, its source is connected to the ground, its drain is connected to the source of MOSFET M25, and the gate of MOSFET M25 is connected to the gate of MOSFET M19. The drain serves as the first output terminal of the basic current mirror 101.
[0029] In this configuration, the drain of MOSFET M24 is connected to its gate, the drain of MOSFET M20, and the gate of MOSFET M28, respectively; the drain of MOSFET M23 is connected to the source of MOSFET M24; the gates of MOSFET M23 and MOSFET M27 are both connected to ground, and the sources of MOSFET M23 and MOSFET M27 are both connected to the power supply; the source of MOSFET M28 is connected to the drain of MOSFET M27, and the drain serves as the second output terminal of the basic current mirror 101.
[0030] Optionally, MOSFETs M19, M20, M21, M22, M25, and M26 are all NMOS transistors; MOSFETs M23, M24, M27, and M28 are all PMOS transistors.
[0031] like Figure 2 As shown, in this embodiment, the first Cascode branch 102 is a charging branch, including: MOS transistors M1, M2, M3, M4, M9 and M10.
[0032] In this circuit, the gate of MOSFET M1 is connected to the gate of MOSFET M3; the sources of MOSFET M1 and MOSFET M3 are both connected to the power supply terminal; the drain of MOSFET M3 is connected to the source of MOSFET M4; the source of MOSFET M2 is connected to the drain of MOSFET M1, the gate of MOSFET M4 is connected to the gate of MOSFET M4, and the drain of MOSFET M2 is connected to the first input terminal of the switching circuit 20.
[0033] The source of MOSFET M9 is connected to the drain of MOSFET M4 and the gate of MOSFET M3, and the gate of MOSFET M10 is connected to the gate and drain of MOSFET M10, respectively. The source of MOSFET M10 is connected to the drain of MOSFET M9 and the gate of MOSFET M4, and the drain of MOSFET M10 is connected to the first output terminal of the basic current mirror 101.
[0034] Optionally, MOSFETs M1, M2, M3, M4, M9, and M10 are all PMOS transistors.
[0035] like Figure 2 As shown, in this embodiment, the second Cascode branch 103 is a discharge branch, including: MOS transistors M5, M6, M7, M8, M11, and M12.
[0036] In this circuit, the gate of MOSFET M6 is connected to the gate of MOSFET M8; the sources of MOSFET M6 and MOSFET M8 are both connected to the ground terminal; the drain of MOSFET M8 is connected to the source of MOSFET M7; the source of MOSFET M5 is connected to the drain of MOSFET M6; the gate of MOSFET M5 is connected to the gate of MOSFET M7; and the drain of MOSFET M5 is connected to the second input terminal of the switching circuit 20.
[0037] The source of MOSFET M12 is connected to the drain of MOSFET M7 and the gate of MOSFET M8, and the gate of MOSFET M11 is connected to the gate and drain of MOSFET M11. The source of MOSFET M11 is connected to the drain of MOSFET M12 and the gate of MOSFET M7, and the drain of MOSFET M11 is connected to the second output terminal of the basic current mirror 101.
[0038] Optionally, MOSFETs M5, M6, M7, M8, M11, and M12 are all NMOS transistors.
[0039] like Figure 2 As shown, in this embodiment, the switching circuit 20 includes: MOSFET M13, MOSFET M14, MOSFET M15, MOSFET M16, MOSFET M17, MOSFET M18 and amplifier OP.
[0040] Specifically, the gate of MOS transistor M13 inputs the first differential signal UP of the first pulse control signal output by the frequency and phase detector; the gate of MOS transistor M14 inputs the second differential signal UPb of the first pulse control signal output by the frequency and phase detector; the source of MOS transistor M13 and the source of MOS transistor M14 are both connected to the output terminal of the first Cascode branch 102; the drain of MOS transistor M14 is connected to the drain and source of MOS transistor M17 respectively, and the gate of MOS transistor M17 inputs the first differential signal UP of the first pulse control signal.
[0041] Specifically, the gate of MOS transistor M16 inputs the first differential signal DN of the second pulse control signal output by the frequency and phase detector; the gate of MOS transistor M15 inputs the second differential signal DNb of the second pulse control signal output by the frequency and phase detector; the source of MOS transistor M15 and the source of MOS transistor M16 are both connected to the output terminal of the second Cascode branch 103; the drain of MOS transistor M16 is connected to the drain and source of MOS transistor M18 respectively, and the gate of MOS transistor M18 inputs the second differential signal DNb of the second pulse control signal.
[0042] The positive input terminal of amplifier OP is connected to the drain of MOSFET M14 and the drain of MOSFET M16, respectively, and the negative input terminal is connected to its output terminal, the drain of MOSFET M13 and the drain of MOSFET M15, respectively. The positive input terminal of amplifier OP serves as the output terminal of switching circuit 20 and is connected to the input terminal of low-pass filter 30.
[0043] Optionally, MOSFETs M13, M14, and M17 are all PMOS transistors; MOSFETs M15, M16, and M18 are all NMOS transistors; and amplifier OP is a rail-to-rail unity-gain amplifier.
[0044] Optionally, the low-pass filter 30 is a capacitor C, with its upper plate connected to the positive input terminal of the amplifier OP and its lower plate connected to ground. In this embodiment, the capacitance of capacitor C is 1.3pF.
[0045] This invention relates to a differential charge pump circuit applied to a delay phase-locked loop (DLL). An improved Cascode circuit reduces the overdrive voltage on the charge / discharge branches, generating a low-mismatch charge pump charge / discharge current. This current is then filtered through a low-pass filter to obtain a wide-swing control voltage. This overcomes the problems of traditional single-ended charge pumps failing to effectively suppress current source mismatch leading to increased static phase difference after DLL lock-in, and the limited control voltage swing caused by the Cascode structure. The differential switching circuit effectively alleviates charge sharing issues, suppresses current mismatch, and reduces the static phase difference after DLL lock-in. Furthermore, by improving the Cascode circuit and reducing the overdrive voltage of its transistors, the control voltage swing is effectively extended.
[0046] Furthermore, the principle of increasing the control voltage swing using the improved Cascode circuit in this embodiment will be explained.
[0047] In a typical Cascode circuit structure, taking the discharge branch as an example, using a DIode connection for NMOS transistor M8 will pull up the gate of NMOS transistor M8 (the drain of NMOS transistor M6) by one NMOS transistor threshold voltage V. TNSimilarly, for the charging branch PMOS transistor M1, the threshold voltage V of the PMOS transistor will be reduced by one. TP In this way, the swing of the final output control voltage Vctrl will be reduced. TN +V TP .
[0048] In this embodiment, PMOS transistors (M9, M10) and NMOS transistors (M11, M12) are connected in series in the charging and discharging branches, respectively, transforming the Cascode circuit into a wide-swing, high-matching Cascode structure. Taking the discharging branch as an example, NMOS transistors M12 and M11 are connected in series. NMOS transistor M11 is connected in a diode configuration and operates in the saturation region, while NMOS transistor M12 operates in the linear resistance region. Based on the fact that the current flowing through NMOS transistors M11 and M12 is equal, and the overdrive voltage of the equivalent transistor of NMOS transistors M11 and M12 connected in series is twice the overdrive voltage of NMOS transistor M12 (ignoring the substrate bias effect), combined with the IV square law formula of NMOS transistors, it can be theoretically derived that the width-to-length ratio of NMOS transistor M12 is 1 / 3 of the width-to-length ratio of NMOS transistor M11. Simultaneously, the gate of NMOS transistor M8 is connected to the source of NMOS transistor M12 (and the drain of NMOS transistor M7), while the gate of NMOS transistor M7 is correspondingly connected to the drain of NMOS transistor M12. This way, the drain of NMOS transistor M8 (which is not connected in MOS diode form) will be released by a threshold voltage V. TN Its minimum voltage will also be reduced to an overdrive voltage Δ. Therefore, the swing of the output control voltage Vctrl is effectively expanded to Δ-(VDD-Δ), where VDD is the power supply voltage.
[0049] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations are intended to cover non-exclusive inclusion, such that an article or apparatus comprising a list of elements includes not only those elements but also other elements not expressly listed. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the article or apparatus that includes said element. Terms such as "connected" or "linked" are not limited to physical or mechanical connections but can include electrical connections, whether direct or indirect.
[0050] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.
Claims
1. A differential charge pump circuit applied to a delay phase-locked loop, characterized in that, include: Cascode current mirror circuit and switching circuit, wherein, The output of the Cascode current mirror circuit is connected to the input of the switching circuit, and the output of the switching circuit is connected to the input of the low-pass filter. The Cascode current mirror circuit includes a basic current mirror and an improved Cascode circuit. The basic current mirror is used to replicate the current of the current source and input the replicated current to the improved Cascode circuit. The improved Cascode circuit is used to generate charging current and discharging current according to the current, and increases the swing of the control voltage output by the switching circuit by adding a series MOS transistor. The improved Cascode circuit includes a first Cascode branch and a second Cascode branch, wherein the input terminal of the first Cascode branch is connected to the first output terminal of the basic current mirror, and is used to generate a charging current based on the current replicated by the basic current mirror; the input terminal of the second Cascode branch is connected to the second output terminal of the basic current mirror, and is used to generate a discharging current based on the current replicated by the basic current mirror; the mismatch rate between the charging current and the discharging current is less than 1%. The first Cascode branch includes: MOSFETs M1, M2, M3, M4, M9, and M10. The gate of MOSFET M1 is connected to the gate of MOSFET M3. The sources of MOSFETs M1 and M3 are both connected to a power supply terminal, and the drain of MOSFET M3 is connected to the source of MOSFET M4. The source of MOSFET M2 is connected to the drain of MOSFET M1, its gate is connected to the gate of MOSFET M4, and its drain is connected to the open circuit. The first input terminal of the switching circuit; the source of MOSFET M9 is connected to the drain of MOSFET M4 and the gate of MOSFET M3, and the gate of MOSFET M10 is connected to the gate and drain of MOSFET M10; the source of MOSFET M10 is connected to the drain of MOSFET M9 and the gate of MOSFET M4, and the drain of MOSFET M10 is connected to the first output terminal of the basic current mirror; MOSFETs M1, M2, M3, M4, M9, and M10 are all PMOS transistors; The second Cascode branch includes: MOSFETs M5, M6, M7, M8, M11, and M12. The gate of MOSFET M6 is connected to the gate of MOSFET M8. The sources of both MOSFET M6 and M8 are connected to ground. The drain of MOSFET M8 is connected to the source of MOSFET M7. The source of MOSFET M5 is connected to the drain of MOSFET M6, its gate is connected to the gate of MOSFET M7, and its drain is connected to the switch. The second input terminal of the circuit; the source of MOSFET M12 is connected to the drain of MOSFET M7 and the gate of MOSFET M8, respectively, and the gate is connected to the gate and drain of MOSFET M11, respectively; the source of MOSFET M11 is connected to the drain of MOSFET M12 and the gate of MOSFET M7, respectively, and the drain is connected to the second output terminal of the basic current mirror; MOSFETs M5, M6, M7, M8, M11, and M12 are all NMOS transistors; The switching circuit is a differential switching circuit, used to control the charging and discharging of the Cascode current mirror circuit according to the pulse control signal output by the frequency and phase detector, and to generate the control voltage through the low-pass filter.
2. The differential charge pump circuit applied to a delay phase-locked loop according to claim 1, characterized in that, The basic current mirror includes: MOSFETs M19, M20, M21, M22, M23, M24, M25, M26, M27, and M28, wherein... The drain of the MOS transistor M19 is connected to its gate and the current source, respectively, and the source is connected to the drain of the MOS transistor M21. The gates of the MOS transistors M21 and M22 are both connected to the power supply terminal, and the sources of the MOS transistors M21 and M22 are both connected to the ground terminal. The drain of the MOS transistor M22 is connected to the source of the MOS transistor M20, and the gate of the MOS transistor M20 is connected to the gate of the MOS transistor M19. The gate of the MOSFET M26 is connected to the power supply terminal, the source is connected to the ground terminal, the drain is connected to the source of the MOSFET M25, the gate of the MOSFET M25 is connected to the gate of the MOSFET M19, and the drain serves as the first output terminal of the basic current mirror. The drain of the MOS transistor M24 is connected to its gate, the drain of the MOS transistor M20, and the gate of the MOS transistor M28, respectively. The drain of the MOS transistor M23 is connected to the source of the MOS transistor M24; the gates of the MOS transistor M23 and the MOS transistor M27 are both connected to the ground terminal; and the sources of the MOS transistor M23 and the MOS transistor M27 are both connected to the power supply terminal. The source of the MOSFET M28 is connected to the drain of the MOSFET M27, and the drain serves as the second output terminal of the basic current mirror.
3. The differential charge pump circuit applied to a delay phase-locked loop according to claim 2, characterized in that, The MOS transistors M19, M20, M21, M22, M25, and M26 are all NMOS transistors; The MOS transistors M23, M24, M27 and M28 are all PMOS transistors.
4. The differential charge pump circuit applied to a delay phase-locked loop according to claim 1, characterized in that, The switching circuit includes: MOSFETs M13, M14, M15, M16, M17, and M18, and amplifier OP. The gate of the MOS transistor M13 receives the first differential signal of the first pulse control signal output by the frequency and phase detector; the gate of the MOS transistor M14 receives the second differential signal of the first pulse control signal output by the frequency and phase detector; the sources of the MOS transistors M13 and M14 are both connected to the output terminal of the first Cascode branch. The drain of the MOS transistor M14 is connected to the drain and source of the MOS transistor M17, respectively, and the gate of the MOS transistor M17 receives the first differential signal of the first pulse control signal. The gate of the MOS transistor M16 receives the first differential signal of the second pulse control signal output by the frequency and phase detector; the gate of the MOS transistor M15 receives the second differential signal of the second pulse control signal output by the frequency and phase detector; the source of the MOS transistor M15 and the source of the MOS transistor M16 are both connected to the output terminal of the second Cascode branch. The drain of the MOS transistor M16 is connected to the drain and source of the MOS transistor M18, respectively, and the gate of the MOS transistor M18 receives the second differential signal of the second pulse control signal. The positive input terminal of the amplifier OP is connected to the drain of the MOSFET M14 and the drain of the MOSFET M16, respectively, and the negative input terminal is connected to its output terminal, the drain of the MOSFET M13 and the drain of the MOSFET M15, respectively; the positive input terminal of the amplifier OP serves as the output terminal of the switching circuit and is connected to the input terminal of the low-pass filter.
5. The differential charge pump circuit applied to a delay phase-locked loop according to claim 4, characterized in that, MOS transistors M13, M14, and M17 are all PMOS transistors; MOS transistors M15, M16, and M18 are all NMOS transistors; and amplifier OP is a rail-to-rail unity-gain amplifier.