Method, device and equipment for recovering oversampled data and storage medium

Abstract

The application discloses a method and device for recovering oversampling data, equipment and a storage medium, and converts serial data into oversampling data, carries out delay processing on the oversampling data, obtains first delay oversampling data, splices the first delay oversampling data with the oversampling data, and obtains first oversampling splicing data; carries out sliding comparison on the first oversampling splicing data and first binary string sequence data, obtains jump edge information of the oversampling data, carries out mapping processing on the jump edge information, and obtains a jump edge position; inputs the jump edge position into an edge information shaping circuit to carry out shaping processing, and obtains an edge position; calculates a sampling position of the oversampling data according to the edge position, carries out sampling processing on the oversampling data based on the sampling position, and obtains effective sampling data; inputs the effective sampling data into a bit width conversion circuit, and outputs fixed bit width effective data; compared with the prior art, the technical scheme of the application can improve the accuracy of oversampling data recovery.

Description

Technical Field

[0001] This invention relates to the field of communication technology, and in particular to methods, apparatus, devices and storage media for recovering oversampled data. Background Technology

[0002] In some protocols, although the line rate is within the operating range of SERDES, the data is bursty and there are strict requirements for data recovery time, such as the GPON protocol (1.244Gbps, etc.). The CDR circuit lock-in inside SERDES takes a certain amount of time, which is usually difficult to meet the requirements. Therefore, oversampling circuits can be used in FPGAs to quickly recover data.

[0003] In burst data mode, if the SERDES sampling clock is stable and not from the same source as the serial data, the edge position and sampling position will increase or decrease when data is available. When data arrives from 0, the sampling position remains unchanged from the end of the last data, but the edge position has changed by several values. Therefore, the first few cycles of data may be sampled incorrectly. Similarly, when the sampling clock is unstable, the direction of edge position change is irregular. In this case, the requirements for the data recovery module are more stringent. Some protocols (GPON) need to lock the data within a limited preamble length, so in this case, there are strict requirements for the data recovery time of the oversampled data recovery logic.

[0004] In existing technologies, when SERDES is used in low-rate scenarios, the method of recovering the original data from the oversampled data is usually adopted. However, it generally shifts the output parallel oversampled data by 1 bit and uses a pairwise XOR method to find the data edge. When the signal is poor or the sampling clock is jittery, it is easy to cause edge misjudgment, resulting in low accuracy in subsequent data recovery. Summary of the Invention

[0005] The technical problem to be solved by the present invention is to provide a method, apparatus, device and storage medium for recovering oversampled data, thereby improving the accuracy of oversampled data recovery.

[0006] To address the aforementioned technical problems, this invention provides a method for recovering oversampled data, comprising: The received serial data is converted into oversampled data, the oversampled data is delayed to obtain first delayed oversampled data, and the first delayed oversampled data and the oversampled data are concatenated to obtain first oversampled concatenated data. The first oversampled spliced ​​data is compared with the preset first binary string sequence data to obtain the transition edge information of the oversampled data, and the transition edge information is mapped to obtain the transition edge position. The transition edge position is input to the edge information shaping circuit so that the edge information shaping circuit can shape the transition edge position to obtain the edge position; Based on the edge position, the sampling position of the oversampled data is calculated, and the oversampled data is sampled based on the sampling position to obtain valid sampled data; The valid sampled data is input into the bit-width conversion circuit so that the bit-width conversion circuit outputs valid data with a fixed bit width.

[0007] In one possible implementation, the first oversampled concatenated data is compared with a preset first binary string sequence data using a sliding comparison to obtain the transition edge information of the oversampled data, specifically including: Obtain the preset sequence length of the first binary string sequence data, and select multiple data segments from the first oversampled concatenated data in a preset order based on the sequence length; Each data segment is compared with the first binary string sequence data. If the data segment is the same as the first binary string sequence data, it is considered that the first data bit in the current data segment has the oversampled data transition edge, and the first data bit is assigned the value 1. Otherwise, it is considered that the first data bit in the current data segment does not have the oversampled data transition edge, and the first data bit is assigned the value 0. By integrating the first data bit assignment data corresponding to each data segment, the transition edge information of the oversampled data is obtained.

[0008] In one possible implementation, mapping the transition edge information to obtain the transition edge position specifically includes: The transition edge information is divided into multiple transition edge granularity segments. Each transition edge granularity segment is compared with multiple preset second binary string sequences of data. Based on the comparison results, the phase position of the transition edge in each transition edge granularity segment is determined. By integrating all phase positions, the transition edge position of the oversampled data is obtained.

[0009] In one possible implementation, before inputting the transition edge position to the edge information shaping circuit, the method further includes: Extract the transition edge position segment from the transition edge position, compare the transition edge position segment with multiple third binary string sequences, and if there is a third binary string sequence that is the same as the transition edge position segment, then delay the transition edge position to obtain a first delayed transition edge position, and update the first delayed transition edge position to the current transition edge position.

[0010] In one possible implementation, the transition edge position is input to an edge information shaping circuit, so that the edge information shaping circuit shapes the transition edge position to obtain the edge position, specifically including: The transition edge position is input into the edge information shaping circuit so that the edge information shaping circuit performs a delay processing on the transition edge position to obtain a second delayed transition edge position. The second delayed transition edge position is then further delayed to obtain a third delayed transition edge position. The second delayed transition edge position and the third delayed transition edge position are incremented by 1 respectively to obtain the second incremented delayed transition edge position and the third incremented delayed transition edge position; If the position of the second plus one delay transition edge is the same as the position of the third delay transition edge, or the position of the third plus one delay transition edge is the same as the position of the second delay transition edge, then the transition edge is considered to be in invalid oscillation, and the transition edge position is taken as the edge position.

[0011] In one possible implementation, calculating the sampling position of the oversampled data based on the edge position specifically includes: Set a preset phase offset value and obtain the current sampling position. Subtract the current sampling position from the edge position and add the phase offset value to obtain the sampling phase offset value. Determine whether the sampling phase offset value is 0. If it is, then directly use the current sampling position as the sampling position. Otherwise, adjust the current sampling position according to the sampling phase offset value to obtain the sampling position of the oversampled data.

[0012] In one possible implementation, adjusting the current sampling position based on the sampling phase offset value specifically includes: Set the first sampling phase offset threshold, the second sampling phase offset threshold, and the third sampling phase offset threshold; When it is determined that the sampling phase offset value is not less than the first sampling phase offset threshold, the current sampling position is decremented by 1 to obtain the first adjustment position, and the first adjustment position is updated to the current sampling position; When it is determined that the sampling phase offset value is not less than the second sampling phase offset threshold and is less than the first sampling phase offset threshold, the current sampling position is reduced by 2 to obtain the second adjustment position, and the second adjustment position is updated to the current sampling position; When it is determined that the sampling phase offset value is greater than the third sampling phase offset threshold and less than the second sampling phase offset threshold, the current sampling position is incremented by 2 to obtain the third adjustment position, and the third adjustment position is updated to the current sampling position; When it is determined that the sampling phase offset value is not greater than the third sampling phase offset threshold, the current sampling position is incremented by 1 to obtain the fourth adjustment position, and the fourth adjustment position is updated to the current sampling position.

[0013] In one possible implementation, the oversampled data is sampled based on the sampling location to obtain valid sampled data, specifically including: The oversampled data is then subjected to delay processing to obtain second delayed oversampled data, third delayed oversampled data, and fourth delayed oversampled data; First sample data is extracted from the second delayed oversampled data, and second sample data is extracted from the fourth delayed oversampled data. The first sample data, the second sample data, and the third delayed oversampled data are then concatenated to obtain second oversampled concatenated data. The sampling position is delayed to obtain the current sampling position and the sampling position of the previous clock cycle; When it is determined that the current sampling position is within a preset first range, multiple sets of first valid datasets are extracted from the second oversampled spliced ​​data according to the current sampling position. All valid data in each set of first valid datasets are added together to obtain multiple sets of first valid data sums. If the sum of first valid data is greater than a preset valid data sum threshold, the first valid data sampled from the first valid data sum and the corresponding valid dataset is determined to be 1. Otherwise, the first valid data sampled from the first valid data sum and the corresponding first valid dataset is determined to be 0. The first valid data corresponding to all first valid datasets are integrated to obtain the first valid sampled data. When it is determined that the sampling position of the previous clock cycle is at a preset first target position and the current sampling position is 0, then according to the sampling position of the previous clock cycle, multiple sets of second effective datasets are extracted from the second oversampled spliced ​​data. All effective data in each set of second effective datasets are added together to obtain multiple sets of second effective data sums. If the second effective data sum is greater than a preset effective data sum threshold, then the second effective data sampled from the second effective data sum and the corresponding effective dataset is determined to be 1. Otherwise, the second effective data sampled from the second effective data sum and the corresponding second effective dataset is determined to be 0. The second sampled data and the second effective data corresponding to all second effective datasets are integrated to obtain the second effective sampled data. When it is determined that the sampling position of the previous clock cycle is at the preset second target position and the current sampling position is 1, then according to the sampling position of the previous clock cycle, multiple sets of third effective datasets are extracted from the second oversampled spliced ​​data, wherein the difference between the number of the third effective datasets and the number of the second effective datasets is 1; Add all valid data in each group of third valid datasets to obtain multiple groups of third valid data sums. If the sum of third valid data is greater than a preset valid data sum threshold, then the third valid data sampled from the valid dataset corresponding to the third valid data sum is determined to be 1. Otherwise, the third valid data sampled from the third valid data sum and the corresponding third valid dataset is determined to be 0. Integrate the second valid data corresponding to all third valid datasets to obtain the third valid sampled data.

[0014] In one possible implementation, the valid sampled data is input into a bit-width conversion circuit so that the bit-width conversion circuit outputs valid data of a fixed bit width, specifically including: Configure the shift register; Obtain the effective data length of the effective sampled data, input the effective sampled data into the shift register, shift out the effective data length from the shift register, and update the shift register; A counter is set up, and based on the counter, the number of valid data in the shift register is recorded. When the number of valid data is not less than a preset fixed bit width, the fixed bit width valid data is extracted from the shift register and output based on the data bits corresponding to the number of valid data.

[0015] The present invention also provides an oversampled data recovery device, comprising: a sampled data splicing module, a sampled data sliding comparison module, an edge information shaping module, a sampling position calculation module, and a fixed bit width effective data output module; The sampling data splicing module is used to convert the received serial data into oversampled data, perform delay processing on the oversampled data to obtain first delayed oversampled data, and splice the first delayed oversampled data and the oversampled data to obtain first oversampled spliced ​​data. The sampling data sliding comparison module is used to perform a sliding comparison between the first oversampled spliced ​​data and the preset first binary string sequence data to obtain the transition edge information of the oversampled data, and to perform mapping processing on the transition edge information to obtain the transition edge position. The edge information shaping module is used to input the transition edge position into the edge information shaping circuit, so that the edge information shaping circuit can shape the transition edge position to obtain the edge position. The sampling position calculation module is used to calculate the sampling position of the oversampled data based on the edge position, and perform sampling processing on the oversampled data based on the sampling position to obtain valid sampling data; The fixed bit-width valid data output module is used to input the valid sampled data into the bit-width conversion circuit so that the bit-width conversion circuit outputs fixed bit-width valid data.

[0016] In one possible implementation, the sampling data sliding comparison module is used to perform a sliding comparison between the first oversampled concatenated data and a preset first binary string sequence data to obtain the transition edge information of the oversampled data, specifically including: Obtain the preset sequence length of the first binary string sequence data, and select multiple data segments from the first oversampled concatenated data in a preset order based on the sequence length; Each data segment is compared with the first binary string sequence data. If the data segment is the same as the first binary string sequence data, it is considered that the first data bit in the current data segment has the oversampled data transition edge, and the first data bit is assigned the value 1. Otherwise, it is considered that the first data bit in the current data segment does not have the oversampled data transition edge, and the first data bit is assigned the value 0. By integrating the first data bit assignment data corresponding to each data segment, the transition edge information of the oversampled data is obtained.

[0017] In one possible implementation, the sampling data sliding comparison module is used to map the transition edge information to obtain the transition edge position, specifically including: The transition edge information is divided into multiple transition edge granularity segments. Each transition edge granularity segment is compared with multiple preset second binary string sequences of data. Based on the comparison results, the phase position of the transition edge in each transition edge granularity segment is determined. By integrating all phase positions, the transition edge position of the oversampled data is obtained.

[0018] In one possible implementation, the edge information shaping module, used to input the transition edge position to the edge information shaping circuit, further includes: Extract the transition edge position segment from the transition edge position, compare the transition edge position segment with multiple third binary string sequences, and if there is a third binary string sequence that is the same as the transition edge position segment, then delay the transition edge position to obtain a first delayed transition edge position, and update the first delayed transition edge position to the current transition edge position.

[0019] In one possible implementation, the edge information shaping module is used to input the transition edge position into the edge information shaping circuit, so that the edge information shaping circuit shapes the transition edge position to obtain the edge position, specifically including: The transition edge position is input into the edge information shaping circuit so that the edge information shaping circuit performs a delay processing on the transition edge position to obtain a second delayed transition edge position. The second delayed transition edge position is then further delayed to obtain a third delayed transition edge position. The second delayed transition edge position and the third delayed transition edge position are incremented by 1 respectively to obtain the second incremented delayed transition edge position and the third incremented delayed transition edge position; If the position of the second plus one delay transition edge is the same as the position of the third delay transition edge, or the position of the third plus one delay transition edge is the same as the position of the second delay transition edge, then the transition edge is considered to be in invalid oscillation, and the transition edge position is taken as the edge position.

[0020] In one possible implementation, the sampling position calculation module is used to calculate the sampling position of the oversampled data based on the edge position, specifically including: Set a preset phase offset value and obtain the current sampling position. Subtract the current sampling position from the edge position and add the phase offset value to obtain the sampling phase offset value. Determine whether the sampling phase offset value is 0. If it is, then directly use the current sampling position as the sampling position. Otherwise, adjust the current sampling position according to the sampling phase offset value to obtain the sampling position of the oversampled data.

[0021] In one possible implementation, the sampling position calculation module is used to adjust the current sampling position according to the sampling phase offset value, specifically including: Set the first sampling phase offset threshold, the second sampling phase offset threshold, and the third sampling phase offset threshold; When it is determined that the sampling phase offset value is not less than the first sampling phase offset threshold, the current sampling position is decremented by 1 to obtain the first adjustment position, and the first adjustment position is updated to the current sampling position; When it is determined that the sampling phase offset value is not less than the second sampling phase offset threshold and is less than the first sampling phase offset threshold, the current sampling position is reduced by 2 to obtain the second adjustment position, and the second adjustment position is updated to the current sampling position; When it is determined that the sampling phase offset value is greater than the third sampling phase offset threshold and less than the second sampling phase offset threshold, the current sampling position is incremented by 2 to obtain the third adjustment position, and the third adjustment position is updated to the current sampling position; When it is determined that the sampling phase offset value is not greater than the third sampling phase offset threshold, the current sampling position is incremented by 1 to obtain the fourth adjustment position, and the fourth adjustment position is updated to the current sampling position.

[0022] In one possible implementation, the sampling location calculation module is used to perform sampling processing on the oversampled data based on the sampling location to obtain valid sampled data, specifically including: The oversampled data is then subjected to delay processing to obtain second delayed oversampled data, third delayed oversampled data, and fourth delayed oversampled data; First sample data is extracted from the second delayed oversampled data, and second sample data is extracted from the fourth delayed oversampled data. The first sample data, the second sample data, and the third delayed oversampled data are then concatenated to obtain second oversampled concatenated data. The sampling position is delayed to obtain the current sampling position and the sampling position of the previous clock cycle; When it is determined that the current sampling position is within a preset first range, multiple sets of first valid datasets are extracted from the second oversampled spliced ​​data according to the current sampling position. All valid data in each set of first valid datasets are added together to obtain multiple sets of first valid data sums. If the sum of first valid data is greater than a preset valid data sum threshold, the first valid data sampled from the first valid data sum and the corresponding valid dataset is determined to be 1. Otherwise, the first valid data sampled from the first valid data sum and the corresponding first valid dataset is determined to be 0. The first valid data corresponding to all first valid datasets are integrated to obtain the first valid sampled data. When it is determined that the sampling position of the previous clock cycle is at a preset first target position and the current sampling position is 0, then according to the sampling position of the previous clock cycle, multiple sets of second effective datasets are extracted from the second oversampled spliced ​​data. All effective data in each set of second effective datasets are added together to obtain multiple sets of second effective data sums. If the second effective data sum is greater than a preset effective data sum threshold, then the second effective data sampled from the second effective data sum and the corresponding effective dataset is determined to be 1. Otherwise, the second effective data sampled from the second effective data sum and the corresponding second effective dataset is determined to be 0. The second sampled data and the second effective data corresponding to all second effective datasets are integrated to obtain the second effective sampled data. When it is determined that the sampling position of the previous clock cycle is at the preset second target position and the current sampling position is 1, then according to the sampling position of the previous clock cycle, multiple sets of third effective datasets are extracted from the second oversampled spliced ​​data, wherein the difference between the number of the third effective datasets and the number of the second effective datasets is 1; Add all valid data in each group of third valid datasets to obtain multiple groups of third valid data sums. If the sum of third valid data is greater than a preset valid data sum threshold, then the third valid data sampled from the valid dataset corresponding to the third valid data sum is determined to be 1. Otherwise, the third valid data sampled from the third valid data sum and the corresponding third valid dataset is determined to be 0. Integrate the second valid data corresponding to all third valid datasets to obtain the third valid sampled data.

[0023] In one possible implementation, the fixed bit-width valid data output module is used to input the valid sampled data into the bit-width conversion circuit, so that the bit-width conversion circuit outputs fixed bit-width valid data, specifically including: Configure the shift register; Obtain the effective data length of the effective sampled data, input the effective sampled data into the shift register, shift out the effective data length from the shift register, and update the shift register; A counter is set up, and based on the counter, the number of valid data in the shift register is recorded. When the number of valid data is not less than a preset fixed bit width, the fixed bit width valid data is extracted from the shift register and output based on the data bits corresponding to the number of valid data.

[0024] The present invention also provides a terminal device, including a processor, a memory, and a computer program stored in the memory and configured to be executed by the processor, wherein the processor, when executing the computer program, implements the oversampled data recovery method as described in any of the preceding claims.

[0025] The present invention also provides a computer-readable storage medium comprising a stored computer program, wherein, when the computer program is executed, it controls the device on which the computer-readable storage medium is located to perform the oversampled data recovery method as described in any of the preceding claims.

[0026] The method, apparatus, device, and storage medium for recovering oversampled data according to embodiments of the present invention have the following advantages compared with the prior art: By converting received serial data into oversampled data, delaying the oversampled data to obtain first delayed oversampled data, and concatenating it with the oversampled data to obtain first oversampled concatenated data, the first oversampled concatenated data is then compared with a first binary string sequence to obtain the transition edge information of the oversampled data. This transition edge information is then mapped to obtain the transition edge position. The transition edge position is input into an edge information shaping circuit for shaping to obtain the edge position. Based on the edge position, the sampling position of the oversampled data is calculated, and the oversampled data is sampled based on the sampling position to obtain valid sampled data. The valid sampled data is input into a bit-width conversion circuit to output fixed-width valid data. Compared with existing technologies, the present invention concatenates the first delayed oversampled data with the oversampled data to obtain first oversampled concatenated data, and compares it with a first binary string sequence to obtain transition edge information. This effectively filters out irregular jumps in data transition edges and misjudgments of jitter in the middle of the oversampled data, improving the accuracy of subsequent oversampled data recovery. Attached Figure Description

[0027] Figure 1 This is a flowchart illustrating an embodiment of the oversampling data recovery method provided by the present invention; Figure 2 This is a schematic diagram of an embodiment of the oversampling data recovery device provided by the present invention. Detailed Implementation

[0028] The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0029] Example 1, see Figure 1 , Figure 1 This is a flowchart illustrating an embodiment of the oversampling data recovery method provided by the present invention, as shown below. Figure 1 As shown, the method includes steps 101-103, as detailed below: Step 101: Convert the received serial data into oversampled data, perform delay processing on the oversampled data to obtain first delayed oversampled data, and concatenate the first delayed oversampled data and the oversampled data to obtain first oversampled concatenated data.

[0030] In one embodiment, an oversampler is used to oversample the serial data to obtain oversampled data. Preferably, the oversampler is a high-speed SERDES circuit.

[0031] Specifically, the rate of the original serial data is 1.24416Gbps, and the rate of the high-speed SERDES circuit is configured to 9.95328Gbps, which is 8 times that of the serial data. Therefore, each valid data will be repeatedly sampled 8 times and sent to the user-side data interface set to 32 bits. Inside the high-speed SERDES circuit, the sampling clock is 4.97664GHz, and finally outputs parallel oversampled data data_in[31:0] and its synchronization clock clk. The format of the parallel oversampled data data_in[31:0] is AAAA_AAAA_BBBB_BBBB_CCCC_CCCC_DDDD_DDDD, where A, B, C, and D are the four original serial data.

[0032] In one embodiment, the oversampled data is delayed to obtain first delayed oversampled data, and the first delayed oversampled data and the oversampled data are concatenated to obtain first oversampled concatenated data.

[0033] Specifically, the oversampled data data_in[31:0] is processed for one clk cycle to obtain the first delayed oversampled data data_din_1dly[31:0]. The data before and after the delay are concatenated to obtain the first oversampled concatenated data data_tmp_1dly[63:0]. The first oversampled concatenated data data_tmp_1dly = {first delayed oversampled data data_din_1dly, oversampled data data_din}.

[0034] Step 102: Perform a sliding comparison between the first oversampled spliced ​​data and the preset first binary string sequence data to obtain the transition edge information of the oversampled data, and perform mapping processing on the transition edge information to obtain the transition edge position.

[0035] Specifically, the sequence length of the preset first binary string sequence data is obtained, and multiple data segments are selected from the first oversampled concatenated data in a preset order based on the sequence length; each data segment is compared with the first binary string sequence data. If the data segment is the same as the first binary string sequence data, it is considered that the first data bit in the current data segment has a transition edge of the oversampled data, and the first data bit is assigned a value of 1; otherwise, it is considered that the first data bit in the current data segment does not have a transition edge of the oversampled data, and the first data bit is assigned a value of 0; the first data bit assignment data corresponding to each data segment is integrated to obtain the transition edge information of the oversampled data.

[0036] Preferably, the preset first binary string sequence data is 4'b0001, where 4 represents the sequence length of the first binary string, 0001 is the first binary string itself, and b indicates that it is a binary string.

[0037] As an example of performing a sliding comparison between the first oversampled concatenated data and the preset first binary string sequence data in this embodiment, the comparison is made by checking whether the current bit position is a data transition edge; if so, it is recorded as 1, otherwise as 0. The comparison method is as follows: 1) Starting from bit 0 of the first oversampled spliced ​​data data_tmp_1dly, take 4 bits upwards to obtain the first data segment data_tmp_1dly[3:0]. Compare the first data segment with the first binary string sequence data 4'b0001. If they are equal, the first data bit bit0 in the current data segment is considered to be the transition edge of the original data. The data_edge_2dly[0] register is assigned a value of 1, that is, the first data bit is assigned a value of 1. Otherwise, it is assigned a value of 0.

[0038] 2) Starting from 1 bit of the first oversampled spliced ​​data data_tmp_1dly, take 4 bits up to get the second data segment data_tmp_1dly[4:1]. Compare the second data segment with the first binary string sequence data 4'b0001. If they are equal, the first data bit bit1 in the current data segment is considered to be the transition edge of the original data. The data_edge_2dly[1] register is assigned a value of 1, that is, the first data bit is assigned a value of 1. Otherwise, it is assigned a value of 0.

[0039] 3) Starting from the 2nd bit of the first oversampled spliced ​​data data_tmp_1dly, take 4 bits upward to obtain the third data segment data_tmp_1dly[5:2]. Compare the third data segment with the first binary string sequence data 4'b0001. If they are equal, the position of the first data bit bit2 in the current data segment is considered to be the transition edge of the original data. The data_edge_2dly[2] register is assigned a value of 1, that is, the first data bit is assigned a value of 1. Otherwise, it is assigned a value of 0.

[0040] 4) Following this pattern, finally, starting from the 31st bit of the first oversampled spliced ​​data data_tmp_1dly, take 4 bits upwards to obtain the 32nd data segment data_tmp_1dly[34:31]. Compare the 32nd data segment with the first binary string sequence data 4'b0001. If they are equal, then the first data bit bit31 in the current data segment is considered to be the transition edge of the original data. Record the result in the data_edge_2dly

[31] register. Thus, the transition edge information in the 32-bit data of the current clock cycle has been obtained.

[0041] In one embodiment, the parallel oversampled data A is delayed by one parallel clock cycle to obtain data A1. A and A1 are concatenated to obtain parallel oversampled data with twice the bit width. The transition edges are then found using a sliding comparison between the sequence value and the current data. This effectively filters out irregular jumps in the data transition edges, reducing the probability of misjudgment due to jitter in the middle of the oversampled data. This avoids the situation in the prior art where the parallel data output from the high-speed SERDES circuit is shifted by 1 bit and then XORed pairwise to find the data edges, which is prone to edge misjudgment when the signal is poor or the sampling clock is jittery.

[0042] Specifically, the transition edge information is divided into multiple transition edge granularity segments; each transition edge granularity segment is compared with multiple preset second binary string sequences of data, and the phase position of the transition edge in each transition edge granularity segment is determined based on the comparison results; all phase positions are integrated to obtain the transition edge position of the oversampled data.

[0043] Preferably, since the data is oversampled eight times during oversampling, when performing granular segmentation on the edge information, the edge information data_edge_2dly[31:0] is divided into four edge granularity segments according to 8-bit granularity: data_edge_2dly[7:0], data_edge_2dly[15:8], data_edge_2dly[23:16], and data_edge_2dly[31:24]. Each bit within the granularity can be considered as a data phase. It is determined whether there is an edge within each granularity. If there is, the phase of the edge is then determined.

[0044] Preferably, the preset multiple second binary string sequences are 8'b0000_0001, 8'b0000_0010, 8'b0000_0100, 8'b0000_1000, 8'b0001_000?, 8'b0010_00??, 8'b0100_0???, and 8'b1000_????; where "?" indicates that the data is 0 or 1 and is not of interest.

[0045] As an example of obtaining the transition edge position of the oversampled data in this embodiment, 1) the transition edge granularity segment data_edge_2dly[7:0] and the second binary string sequence data 8'b0000_0001 are compared. If they are equal, the transition edge is considered to be in the 0th phase, and edge_offset_3dly[2:0] is assigned the value 0.

[0046] 2) Compare the transition edge granularity segment data_edge_2dly[7:0] with the second binary string sequence data 8'b0000_0010. If they are equal, the transition edge is considered to be in the first phase, and edge_offset_3dly[2:0] is assigned the value 1.

[0047] 3) Compare the transition edge granularity segment data_edge_2dly[7:0] with the second binary string sequence data 8'b0000_0100. If they are equal, the transition edge is considered to be in the second phase, and the transition edge position edge_offset_3dly[2:0] is assigned the value 2.

[0048] 4) Compare the transition edge granularity segment data_edge_2dly[7:0] with the second binary string sequence data 8'b0000_1000. If they are equal, the transition edge is considered to be in the 3rd phase, and the transition edge position edge_offset_3dly[2:0] is assigned the value 3.

[0049] 5) Compare the transition edge granularity segment data_edge_2dly[7:0] with the second binary string sequence data 8'b0001_000?. If they are equal, the transition edge is considered to be in the 4th phase, and the transition edge position edge_offset_3dly[2:0] is assigned the value 4.

[0050] 6) Compare the transition edge granularity segment data_edge_2dly[7:0] with the second binary string sequence data 8'b0010_00??. If they are equal, the transition edge is considered to be in the 5th phase, and the transition edge position edge_offset_3dly[2:0] is assigned the value 5.

[0051] 7) Compare the transition edge granularity segment data_edge_2dly[7:0] with the second binary string sequence data 8'b0100_0???. If they are equal, the transition edge is considered to be in the 6th phase, and the transition edge position edge_offset_3dly[2:0] is assigned the value 6.

[0052] 8) Compare the transition edge granularity segment data_edge_2dly[7:0] with the second binary string sequence data 8'b1000_????. If they are equal, the transition edge is considered to be in the 7th phase, and the transition edge position edge_offset_3dly[2:0] is assigned the value 7.

[0053] Similarly, the transition edge granularity segments data_edge_2dly[15:8], data_edge_2dly[23:16], and data_edge_2dly[31:24] are compared according to the above method to obtain the transition edge positions edge_offset_3dly[5:3], edge_offset_3dly[8:6], and edge_offset_3dly[11:9].

[0054] In one embodiment, the edge-offset_3dly[2:0], edge-offset_3dly[5:3], edge-offset_3dly[8:6], and edge-offset_3dly[11:9] of the oversampled data are integrated to obtain the edge-offset_3dly of the oversampled data.

[0055] Step 103: Input the transition edge position into the edge information shaping circuit so that the edge information shaping circuit can shape the transition edge position to obtain the edge position.

[0056] In one embodiment, before inputting the transition edge position to the edge information shaping circuit, the method further includes extracting a transition edge position segment from the transition edge position, comparing the transition edge position segment with multiple third binary string sequence data respectively, and if there is a third binary string sequence data that is the same as the transition edge position segment, then the transition edge position is delayed to obtain a first delayed transition edge position, and the first delayed transition edge position is updated to the current transition edge position.

[0057] Preferably, the plurality of third binary string sequences include 4'b0001, 4'b001?, 4'b01?? and 4'b1???.

[0058] Preferably, the first 4 bits of the transition edge position are extracted to obtain the transition edge position segment data_edge_3dly[3:0].

[0059] As an example of comparing the transition edge position segment with multiple third binary string sequence data in this embodiment, if the transition edge position segment data_edge_3dly[3:0] is 4'b0001, then the transition edge position edge_offset_3dly[2:0] is assigned to edge_offset_4dly after a delay of 1 clk cycle.

[0060] If the transition edge position segment data_edge_3dly[3:0] is 4'b001?, then the transition edge position edge_offset_3dly[5:3] is delayed by 1 clk cycle and assigned to the current transition edge position edge_offset_4dly.

[0061] If the transition edge position segment data_edge_3dly[3:0] is 4'b01??, then the transition edge position edge_offset_3dly[8:6] is delayed by 1 clk cycle and assigned to the current transition edge position edge_offset_4dly.

[0062] If the transition edge position segment data_edge_3dly[3:0] is 4'b1???, then the transition edge position edge_offset_3dly[11:9] is delayed by 1 clk cycle and assigned to the current transition edge position edge_offset_4dly.

[0063] If there are no bits set to 1 in the transition edge position segment data_edge_3dly[3:0], then the current transition edge position edge_offset_4dly remains unchanged.

[0064] In one embodiment, after obtaining the edge position `edge_offset_4dly` contained in the oversampled data, some high-speed SERDES circuits, when not using CDR, cannot completely lock the sampling clock to a fixed frequency point; that is, the sampling clock will jitter within a range. In this embodiment, this range is set to ±400ppm. Therefore, the obtained data edge may repeatedly transition between two data points. If the repeated edge transition happens to cause the sampling position to swing between phase 0 and phase 7, multiple bits of data insertion or deletion can easily occur in a short period of time, leading to subsequent data errors. Therefore, it is necessary to filter out such invalid edge transition information through an edge information shaping circuit.

[0065] In one embodiment, the transition edge position is input to an edge information shaping circuit, so that the edge information shaping circuit performs a delay processing on the transition edge position to obtain a second delayed transition edge position; and the second delayed transition edge position is further delayed to obtain a third delayed transition edge position.

[0066] Preferably, the transition edge position edge_offset_4dly is delayed by 1 clk cycle to obtain the second delayed transition edge position edge_offset_5dly, and the second delayed transition edge position edge_offset_5dly is delayed by 1 clk cycle to obtain the third delayed transition edge position edge_offset_6dly.

[0067] In one embodiment, the delay edge position is determined by comparing whether the current delay edge position is equal to the previous delay edge position, and the edge position is determined based on the oscillation result.

[0068] Specifically, the second delayed transition edge position and the third delayed transition edge position are incremented by 1 to obtain the second plus-one delayed transition edge position and the third plus-one delayed transition edge position. If the second plus-one delayed transition edge position is the same as the third delayed transition edge position, or the third plus-one delayed transition edge position is the same as the second delayed transition edge position, then the transition edge is considered to be in invalid oscillation, and the transition edge position is taken as the edge position.

[0069] Specifically, it is determined whether the third delayed transition edge position is equal to the second delayed transition edge position, and whether the second delayed transition edge position is equal to the transition edge position. If the third delayed transition edge position is equal to the second delayed transition edge position and equal to the transition edge position, then the transition edge state is considered stable, the current transition edge position is updated, and the updated transition edge position is used as the edge position.

[0070] Preferably, when comparing whether the delayed transition edge position at the current moment is equal to the delayed transition edge position at the previous moment, except for the two cases mentioned above, all others are considered to be normal transitions, the current transition edge position is updated, and the updated transition edge position is used as the edge position.

[0071] As an example in this embodiment, comparing the current delay edge position with the previous delay edge position to determine whether the delay edge position is oscillating: 1) If the current clock cycle edge position is equal to the previous clock cycle and equal to the clock cycle before that, that is, the third delay edge position edge_offset_6dly is equal to the second delay edge position edge_offset_5dly and equal to the edge position edge_offset_4dly, then the edge position is considered to have remained unchanged for 3 cycles and is stable. At this time, the edge information is updated normally to the current edge position edge_offset_7dly; wherein, the current edge position edge_offset_7dly is the filtered edge position obtained by filtering the second delay edge position edge_offset_5dly and the third delay edge position edge_offset_6dly.

[0072] 2) If the value of the edge position of the clock cycle before last plus 1 is equal to that of the previous clock cycle, or the value of the edge position of the clock cycle before last plus 1 is equal to that of the clock cycle before last, that is, if the value of the third delay edge position edge_offset_6dly plus 1 equals the value of the second delay edge position edge_offset_5dly, or if the value of the second delay edge position edge_offset_5dly plus 1 equals the value of the third delay edge position edge_offset_6dly, then the edge is considered to be oscillating invalidly, and the current edge position edge_offset_7dly remains unchanged. 3) In other cases, the edge is considered to be a normal transition, and the edge information is updated normally to the current transition edge position edge_offset_7dly.

[0073] In one embodiment, by using an edge information shaping circuit, invalid edge information with continuous left and right transitions can be filtered out, reducing the frequency of data insertion and deletion, and reducing data jitter and bit error rate; at the same time, the edge position can be obtained by directly mapping the edge information, which can quickly obtain the edge position information, making it easier to reduce the number of logic levels and convergence timing.

[0074] Step 104: Calculate the sampling position of the oversampled data based on the edge position, and perform sampling processing on the oversampled data based on the sampling position to obtain valid sampled data.

[0075] In one embodiment, a preset phase offset value is set.

[0076] Specifically, the sampling phase offset value is set to 4 or N / 2 (N is the oversampling factor), that is, when the transition edge position is in the nth phase (n=0 to 7), the sampling position is n+N / 2.

[0077] In one embodiment, the current sampling position is obtained, the edge position is subtracted from the current sampling position, and the phase offset value is added to obtain the sampling phase offset value; it is determined whether the sampling phase offset value is 0. If it is, the current sampling position is directly used as the sampling position; otherwise, the current sampling position is adjusted according to the sampling phase offset value to obtain the sampling position of the oversampled data.

[0078] Specifically, the sampling phase offset value ph_delta is obtained by subtracting the current sampling position from the edge position and adding the preset phase offset value. If the sampling phase offset value is 0, it means that the current sampling position is exactly at the position farthest from the transition edge position, and there is no need to adjust the sampling position. If the calculation result is not 0, it means that the current sampling position is not the most ideal situation, and the current sampling position should be adjusted to make the calculation result 0.

[0079] In one embodiment, when adjusting the current sampling position based on the sampling phase offset value, a first sampling phase offset threshold, a second sampling phase offset threshold, and a third sampling phase offset threshold are set. When it is determined that the sampling phase offset value is not less than the first sampling phase offset threshold, the current sampling position is decremented by 1 to obtain a first adjusted position, and the first adjusted position is updated to the current sampling position. When it is determined that the sampling phase offset value is not less than the second sampling phase offset threshold and is less than the first sampling phase offset threshold, the current sampling position is decremented by 2 to obtain a second adjusted position, and the second adjusted position is updated to the current sampling position. When it is determined that the sampling phase offset value is greater than the third sampling phase offset threshold and is less than the second sampling phase offset threshold, the current sampling position is incremented by 2 to obtain a third adjusted position, and the third adjusted position is updated to the current sampling position. When it is determined that the sampling phase offset value is not greater than the third sampling phase offset threshold, the current sampling position is incremented by 1 to obtain a fourth adjusted position, and the fourth adjusted position is updated to the current sampling position.

[0080] Preferably, the first sampling phase offset threshold is set to 6, the second sampling phase offset threshold is set to 4, and the third sampling phase offset threshold is set to 2.

[0081] Specifically, the current sampling position is adjusted in stages based on the magnitude of the sampling phase offset value, as shown below: 1) If the sampling phase offset value is greater than or equal to the first sampling phase offset threshold of 6, then decrement the current sampling position by 1; otherwise, proceed to the next condition. 2) If the sampling phase offset value is greater than or equal to the second sampling phase offset threshold 4 and less than the first sampling phase offset threshold 6, then decrease the current sampling position by 2; otherwise, proceed to the next condition. 3) If the sampling phase offset value is greater than the third sampling phase offset threshold 2 and less than the second sampling phase offset threshold 4, then increment the current sampling position by 2; otherwise, proceed to the next condition. 4) If the sampling phase offset value is less than or equal to the third sampling phase offset threshold 2, then increment the current sampling position by 1; 5) Take the adjusted sampling position as the current sampling position, return to the current sampling position, subtract the current sampling position from the edge position, and add the phase offset value to obtain the sampling phase offset value; determine whether the sampling phase offset value is 0.

[0082] In one embodiment, a negative feedback sampling position calculation circuit with hierarchical processing is used to obtain the phase difference value by subtracting the preset sampling position from the edge position. The larger the phase difference value, the larger the step size when adjusting the next sampling position; otherwise, the step size is reduced. This can achieve fast convergence and facilitate the convergence timing, thereby enabling the data to be locked quickly and reducing the probability of sampling position misjudgment.

[0083] In one embodiment, since the process of calculating the sampling position takes approximately M clock cycles, the obtained sampling position corresponds to the data after a delay of M cycles. Based on the above, the oversampled data is delayed to obtain second delayed oversampled data, third delayed oversampled data, and fourth delayed oversampled data.

[0084] Specifically, the parallel oversampled data data_din output by the high-speed SERDES circuit is delayed to M+1 clock cycles to obtain the second delayed oversampled data data_din_(M-1)dly, the third delayed oversampled data data_din_Mdly, and the fourth delayed oversampled data data_din_(M+1)dly.

[0085] In one embodiment, first sampled data is extracted from the second delayed oversampled data, and second sampled data is extracted from the fourth delayed oversampled data. The first sampled data, the second sampled data, and the third delayed oversampled data are then concatenated to obtain second oversampled concatenated data.

[0086] Specifically, the first bit of sampled data is extracted from the second delayed oversampled data as the first sampled data data_din_(M+1)dly[0], and the last bit of sampled data is extracted from the fourth delayed oversampled data as the second sampled data data_din_(M-1)dly

[31] . The first sampled data data_din_(M+1)dly[0], the third delayed oversampled data data_din_Mdly[31:0], and the second sampled data data_din_(M-1)dly

[31] are concatenated to obtain the second oversampled concatenated data data_sample_din[33:0]. When taking a value each time, 3 bits are taken continuously starting from the bit before the sampling position. This bit width can ensure that the index value will not overflow when taking data each time.

[0087] In one embodiment, the sampling position is delayed to obtain the current sampling position and the sampling position of the previous clock cycle.

[0088] Specifically, the sampling position smp_pos_f is delayed by 2 clock cycles to obtain the current sampling position samp_loc_1dly and the sampling position samp_loc_2dly of the previous clock cycle.

[0089] In one embodiment, to improve the accuracy of the judgment when sampling data, multiple bits of data are sampled, and the majority decision method is used to obtain the final result, which can optimize the bit error rate when the signal quality is poor. At the same time, when the sampling position changes from 7 to 0 or from 0 to 7, the circuit needs to insert 1 bit and delete 1 bit of data respectively.

[0090] Specifically, when the current sampling position is determined to be within a preset first range, multiple sets of first valid datasets are extracted from the second oversampled spliced ​​data based on the current sampling position. All valid data in each set of first valid datasets are added together to obtain a sum of multiple sets of first valid data. If the sum of the first valid data is greater than a preset threshold for the sum of the first valid data, the first valid data sampled from the first valid data and the corresponding valid dataset is determined to be 1. Otherwise, the first valid data sampled from the first valid data and the corresponding first valid dataset is determined to be 0. The first valid data corresponding to all the first valid datasets are integrated to obtain the first valid sampled data.

[0091] Preferably, the first range position is a preset integer from 1 to 6, and the preset valid data and threshold are 2. If the current sampling position X is an integer from 1 to 6, the first valid dataset data_sample_din [0*8+X+2:0*8+X] is extracted, resulting in 3 bits of valid data. These 3 bits are added together. If the sum of the first valid data is greater than or equal to 2, the first valid data obtained is considered to be 1; otherwise, it is considered to be 0. Similarly, valid data from the first valid datasets data_sample_din[1*8+X+2:1*8+X], data_sample_din[2*8+X+2:2*8+X], and data_sample_din [3*8+X+2:3*8+X] are extracted. The first valid sampled data output in the current clock cycle is 4 bits of valid data.

[0092] Specifically, when it is determined that the sampling position of the previous clock cycle is at a preset first target position and the current sampling position is 0, then according to the sampling position of the previous clock cycle, multiple sets of second effective datasets are extracted from the second oversampled spliced ​​data. All effective data in each set of second effective datasets are added together to obtain multiple sets of second effective data sums. If the second effective data sum is greater than a preset effective data sum threshold, then the second effective data sampled from the second effective data sum and the corresponding effective dataset is determined to be 1. Otherwise, the second effective data sampled from the second effective data sum and the corresponding second effective dataset is determined to be 0. The second sampled data and the second effective data corresponding to all second effective datasets are integrated to obtain the second effective sampled data.

[0093] Preferably, the first target position is preset to 7. If the sampling position of the previous clock cycle is 7 and the sampling position of the current clock cycle is 0, it is considered that there is 1 bit of valid data between these two valid data. At this time, the 0th bit of the fourth delayed oversampled data data_din_(M+1)dly is taken out to obtain 1 valid data. Then, 4 bits of valid data are taken out from data_sample_din[33:0] according to the above steps. That is, the second valid sampled data output in the current clock cycle is 5 bits of valid data.

[0094] Specifically, when it is determined that the sampling position of the previous clock cycle is at a preset second target position and the current sampling position is 1, then according to the sampling position of the previous clock cycle, multiple sets of third valid datasets are extracted from the second oversampled spliced ​​data, wherein the difference in the number of the third valid datasets and the second valid datasets is 1; all valid data in each set of third valid datasets are added together to obtain multiple sets of third valid data sums; if the third valid data sum is greater than a preset valid data sum threshold, then the third valid data sampled from the third valid data sum and the corresponding valid dataset is determined to be 1; otherwise, the third valid data sampled from the third valid data sum and the corresponding third valid dataset is determined to be 0; and the second valid data corresponding to all third valid datasets are integrated to obtain the third valid sampled data.

[0095] Preferably, the second target position is preset to 0. If the sampling position in the previous clock cycle is 0 and the sampling position in the current clock cycle is 1, it is considered that the two valid data samples are duplicated, and 1 bit of data needs to be discarded. At this time, the valid data in the first valid dataset data_sample_din[0*8+X+2:0*8+X], the first valid dataset data_sample_din[1*8+X+2:1*8+X], and the first valid dataset data_sample_din[2*8+X+2:2*8+X] are extracted according to the above steps. That is, the third valid sampled data output in the current clock cycle is 3 bits of valid data.

[0096] Step 105: Input the valid sampled data into the bit width conversion circuit so that the bit width conversion circuit outputs valid data with a fixed bit width.

[0097] In one embodiment, since the effective sampled data output in each clock cycle may be 3 bits, 4 bits, or 5 bits, it needs to be converted into fixed-width effective data output; preferably, the fixed-width effective data is 8 bits.

[0098] In one embodiment, a shift register is provided; preferably, a 12-bit wide shift register data_shift[11:0] is provided.

[0099] In one embodiment, the effective data length of the effective sampled data is obtained, the effective sampled data is input into the shift register, and the effective data length is shifted out of the shift register to update the shift register.

[0100] Specifically, when the effective data length of the obtained effective sampled data is 3 bits, the effective data is shifted from the low bit into the shift register, and the effective data length is shifted out from the high bit of the shift register, that is, the high 3 bits of the shift register are shifted out.

[0101] Specifically, when the effective data length of the obtained effective sampled data is 4 bits, the effective data is shifted from the low bit into the shift register, and the effective data length is shifted out from the high bit of the shift register, that is, the high 4 bits of the shift register are shifted out.

[0102] Specifically, when the effective data length of the obtained effective sampled data is 5 bits, the effective data is shifted into the shift register from the low bit and the effective data length is shifted out from the high bit of the shift register, that is, the high 5 bits of the shift register are shifted out.

[0103] In one embodiment, a counter is set up to record the number of valid data in the shift register. When the number of valid data is not less than a preset fixed bit width, the fixed bit width valid data is extracted from the shift register and output based on the data bits corresponding to the number of valid data.

[0104] Specifically, a counter `bit_cnt` is set to record the number of valid data bits in the shift register. When the number of valid data bits recorded by `bit_cnt` is less than 8, if 3 bits of valid data are shifted in, the number of valid data bits recorded by `bit_cnt` is incremented by 3; if 4 bits of valid data are shifted in, the number of valid data bits recorded by `bit_cnt` is incremented by 4; and if 5 bits of valid data are shifted in, the number of valid data bits recorded by `bit_cnt` is incremented by 5. When the number of valid data bits recorded by `bit_cnt` is greater than or equal to 8, if 3 bits of valid data are shifted in, the number of valid data bits recorded by `bit_cnt` is decremented by 5; if 4 bits of valid data are shifted in, the number of valid data bits recorded by `bit_cnt` is decremented by 4; and if 5 bits of valid data are shifted in, the number of valid data bits recorded by `bit_cnt` is decremented by 3. When the number of valid data recorded by the counter bit_cnt is greater than or equal to 8, 8 bits of data are taken from the bit position represented by the current value of the counter bit_cnt in the shift register data_shift and output. At the same time, the data valid signal is pulled high, that is, when the data valid signal is high, 8 bits of valid data are output.

[0105] Example 2, see Figure 2 , Figure 2This is a schematic diagram of one embodiment of the oversampling data recovery device provided by the present invention, as shown below. Figure 2 As shown, the device includes a sampling data splicing module 201, a sampling data sliding comparison module 202, an edge information shaping module 203, a sampling position calculation module 204, and a fixed bit width effective data output module 205, as detailed below: The sampling data splicing module 201 is used to convert the received serial data into oversampled data, perform delay processing on the oversampled data to obtain first delayed oversampled data, and splice the first delayed oversampled data and the oversampled data to obtain first oversampled spliced ​​data.

[0106] The sampling data sliding comparison module 202 is used to perform a sliding comparison between the first oversampled spliced ​​data and the preset first binary string sequence data to obtain the transition edge information of the oversampled data, and to perform mapping processing on the transition edge information to obtain the transition edge position.

[0107] The edge information shaping module 203 is used to input the transition edge position into the edge information shaping circuit so that the edge information shaping circuit can shape the transition edge position to obtain the edge position.

[0108] The sampling position calculation module 204 is used to calculate the sampling position of the oversampled data based on the edge position, and perform sampling processing on the oversampled data based on the sampling position to obtain valid sampling data.

[0109] The fixed bit-width valid data output module 205 is used to input the valid sampled data into the bit-width conversion circuit so that the bit-width conversion circuit outputs fixed bit-width valid data.

[0110] In one embodiment, the sampling data sliding comparison module 202 is used to perform a sliding comparison between the first oversampled spliced ​​data and a preset first binary string sequence data to obtain the transition edge information of the oversampled data. Specifically, it includes: obtaining the sequence length of the preset first binary string sequence data; selecting multiple data segments from the first oversampled spliced ​​data in a preset order based on the sequence length; comparing each data segment with the first binary string sequence data; if the data segment is the same as the first binary string sequence data, it is considered that the first data bit in the current data segment has a transition edge of the oversampled data, and the first data bit is assigned a value of 1; otherwise, it is considered that the first data bit in the current data segment does not have a transition edge of the oversampled data, and the first data bit is assigned a value of 0; integrating the first data bit assignment data corresponding to each data segment to obtain the transition edge information of the oversampled data.

[0111] In one embodiment, the sampling data sliding comparison module 202 is used to map the transition edge information to obtain the transition edge position. Specifically, it includes: performing granular division processing on the transition edge information to divide the transition edge information into multiple transition edge granularity segments; comparing each transition edge granularity segment with a preset multiple second binary string sequence data, and determining the phase position of the transition edge in each transition edge granularity segment based on the comparison result; and integrating all phase positions to obtain the transition edge position of the oversampled data.

[0112] In one embodiment, the edge information shaping module 203, used to input the transition edge position to the edge information shaping circuit, further includes: extracting a transition edge position segment from the transition edge position, comparing the transition edge position segment with multiple third binary string sequence data respectively, and if there is a third binary string sequence data that is the same as the transition edge position segment, then performing delay processing on the transition edge position to obtain a first delayed transition edge position, and updating the first delayed transition edge position to the current transition edge position.

[0113] In one embodiment, the edge information shaping module 203 is used to input the transition edge position into the edge information shaping circuit, so that the edge information shaping circuit shapes the transition edge position to obtain the edge position. Specifically, this includes: inputting the transition edge position into the edge information shaping circuit, so that the edge information shaping circuit delays the transition edge position to obtain a second delayed transition edge position; further delaying the second delayed transition edge position to obtain a third delayed transition edge position; incrementing the second delayed transition edge position and the third delayed transition edge position by 1 respectively to obtain a second plus-one delayed transition edge position and a third plus-one delayed transition edge position; if the second plus-one delayed transition edge position is the same as the third delayed transition edge position, or the third plus-one delayed transition edge position is the same as the second delayed transition edge position, then the transition edge is considered to be ineffective, and the transition edge position is taken as the edge position.

[0114] In one embodiment, the sampling position calculation module 204 is used to calculate the sampling position of the oversampled data based on the edge position, specifically including: setting a preset phase offset value and obtaining the current sampling position; subtracting the current sampling position from the edge position and adding the phase offset value to obtain a sampling phase offset value; determining whether the sampling phase offset value is 0; if so, directly using the current sampling position as the sampling position; otherwise, adjusting the current sampling position according to the sampling phase offset value to obtain the sampling position of the oversampled data.

[0115] In one embodiment, the sampling position calculation module 204 is used to adjust the current sampling position according to the sampling phase offset value, specifically including: setting a first sampling phase offset threshold, a second sampling phase offset threshold, and a third sampling phase offset threshold; when it is determined that the sampling phase offset value is not less than the first sampling phase offset threshold, subtracting 1 from the current sampling position to obtain a first adjusted position, and updating the first adjusted position to the current sampling position; when it is determined that the sampling phase offset value is not less than the second sampling phase offset threshold and is less than the first sampling phase offset threshold, subtracting 2 from the current sampling position to obtain a second adjusted position, and updating the second adjusted position to the current sampling position; when it is determined that the sampling phase offset value is greater than the third sampling phase offset threshold and is less than the second sampling phase offset threshold, adding 2 to the current sampling position to obtain a third adjusted position, and updating the third adjusted position to the current sampling position; when it is determined that the sampling phase offset value is not greater than the third sampling phase offset threshold, adding 1 to the current sampling position to obtain a fourth adjusted position, and updating the fourth adjusted position to the current sampling position.

[0116] In one embodiment, the sampling position calculation module 204 is used to perform sampling processing on the oversampled data based on the sampling position to obtain valid sampled data. Specifically, this includes: delaying the oversampled data to obtain second delayed oversampled data, third delayed oversampled data, and fourth delayed oversampled data; extracting first sampled data from the second delayed oversampled data and simultaneously extracting second sampled data from the fourth delayed oversampled data; concatenating the first sampled data, the second sampled data, and the third delayed oversampled data to obtain second oversampled concatenated data; delaying the sampling position to obtain the current sampling position and the sampling position of the previous clock cycle; and determining the current sampling position... When the current sampling position is within a preset first range, multiple sets of first valid datasets are extracted from the second oversampled concatenated data based on the current sampling position. All valid data in each set of first valid datasets are summed to obtain a sum of multiple sets of first valid data. If the sum of the first valid data is greater than a preset threshold, the first valid data sampled from the first valid data and its corresponding valid dataset is determined to be 1; otherwise, the first valid data sampled from the first valid data and its corresponding first valid dataset is determined to be 0. All first valid datasets are then integrated to obtain the first valid sampled data. When the sampling position of the previous clock cycle is determined to be at a preset first target position, and the current sampling position... When the value is set to 0, multiple sets of second valid datasets are extracted from the second oversampled concatenated data based on the sampling position of the previous clock cycle. All valid data in each set of second valid datasets are summed to obtain a sum of multiple sets of second valid data. If the sum of the second valid data is greater than a preset threshold, the second valid data sampled from the second valid data and its corresponding valid dataset is determined to be 1; otherwise, the second valid data sampled from the second valid data and its corresponding second valid dataset is determined to be 0. The second sampled data and the second valid data corresponding to all second valid datasets are integrated to obtain the second valid sampled data. When the sampling position of the previous clock cycle is determined to be at a preset second target position… When the current sampling position is 1, multiple sets of third valid datasets are extracted from the second oversampled spliced ​​data according to the sampling position of the previous clock cycle. The difference in the number of the third valid datasets and the second valid datasets is 1. All valid data in each set of third valid datasets are added together to obtain multiple sets of third valid data sums. If the sum of the third valid data is greater than a preset valid data sum threshold, the third valid data sampled from the third valid data sum and the corresponding valid dataset is determined to be 1. Otherwise, the third valid data sampled from the third valid data sum and the corresponding third valid dataset is determined to be 0. The second valid data corresponding to all third valid datasets are integrated to obtain the third valid sampled data.

[0117] In one embodiment, the fixed bit-width valid data output module 205 is used to input the valid sampled data into the bit-width conversion circuit so that the bit-width conversion circuit outputs fixed bit-width valid data. Specifically, it includes: setting a shift register; obtaining the valid data length of the valid sampled data, inputting the valid sampled data into the shift register, shifting out the valid data length from the shift register, and updating the shift register; setting a counter, recording the number of valid data in the shift register based on the counter, and when the number of valid data is not less than a preset fixed bit width, extracting and outputting fixed bit-width valid data from the shift register based on the data bits corresponding to the number of valid data.

[0118] Those skilled in the art will understand that, for the sake of convenience and brevity, the specific working process of the device described above can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here.

[0119] It should be noted that the embodiments of the oversampled data recovery device described above are merely illustrative. The modules described as separate components may or may not be physically separate, and the components shown as modules may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs.

[0120] Based on the above-described embodiments of the oversampled data recovery method, another embodiment of the present invention provides an oversampled data recovery terminal device, which includes a processor, a memory, and a computer program stored in the memory and configured to be executed by the processor. When the processor executes the computer program, it implements the oversampled data recovery method of any embodiment of the present invention.

[0121] For example, in this embodiment, the computer program can be divided into one or more modules, which are stored in the memory and executed by the processor to complete the present invention. The one or more modules can be a series of computer program instruction segments capable of performing specific functions, which describe the execution process of the computer program in the oversampled data recovery terminal device.

[0122] The terminal device for recovering oversampled data can be a computing device such as a desktop computer, laptop, handheld computer, or cloud server. The terminal device for recovering oversampled data may include, but is not limited to, a processor and a memory.

[0123] The processor can be a Central Processing Unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor can be a microprocessor or any conventional processor. This processor is the control center of the oversampled data recovery terminal device, connecting all parts of the device via various interfaces and lines.

[0124] The memory can be used to store the computer programs and / or modules. The processor, by running or executing the computer programs and / or modules stored in the memory and calling the data stored in the memory, realizes various functions of the oversampled data recovery terminal device. The memory may mainly include a program storage area and a data storage area. The program storage area may store the operating system, at least one application required for a function, etc.; the data storage area may store data created based on the use of the mobile phone, etc. In addition, the memory may include high-speed random access memory, and may also include non-volatile memory, such as hard disk, memory, plug-in hard disk, smart media card (SMC), secure digital (SD) card, flash card, at least one disk storage device, flash memory device, or other volatile solid-state storage device.

[0125] Based on the embodiments of the oversampled data recovery method described above, another embodiment of the present invention provides a storage medium including a stored computer program, wherein, when the computer program is running, it controls the device where the storage medium is located to execute the oversampled data recovery method of any embodiment of the present invention.

[0126] In this embodiment, the storage medium is a computer-readable storage medium, and the computer program includes computer program code, which can be in the form of source code, object code, executable file, or some intermediate form. The computer-readable medium can include any entity or device capable of carrying the computer program code, recording media, USB flash drive, portable hard drive, magnetic disk, optical disk, computer memory, read-only memory (ROM), random access memory (RAM), electrical carrier signals, telecommunication signals, and software distribution media, etc. It should be noted that the content included in the computer-readable medium can be appropriately added or removed according to the requirements of legislation and patent practice in the jurisdiction. For example, in some jurisdictions, according to legislation and patent practice, computer-readable media do not include electrical carrier signals and telecommunication signals.

[0127] In summary, the oversampled data recovery method, apparatus, device, and storage medium provided by this invention convert received serial data into oversampled data, delay the oversampled data to obtain first delayed oversampled data, and concatenate it with the oversampled data to obtain first oversampled concatenated data; perform a sliding comparison between the first oversampled concatenated data and a first binary string sequence data to obtain the transition edge information of the oversampled data, and perform mapping processing on the transition edge information to obtain the transition edge position; input the transition edge position into an edge information shaping circuit for shaping processing to obtain the edge position; and then, based on the edge... The method involves calculating the sampling position of the oversampled data, processing the oversampled data based on the sampling position to obtain valid sampled data, inputting the valid sampled data into a bit-width conversion circuit, and outputting fixed-width valid data. Compared with the prior art, the technical solution of this invention concatenates the first delayed oversampled data with the oversampled data to obtain the first oversampled concatenated data, and performs a sliding comparison with the first binary string sequence data to obtain the transition edge information. This effectively filters out irregular jumps at the data transition edges and misjudgments of jitter in the middle of the oversampled data, improving the accuracy of subsequent oversampled data recovery.

[0128] The above description is only a preferred embodiment of the present invention. It should be noted that for those skilled in the art, several improvements and substitutions can be made without departing from the technical principles of the present invention, and these improvements and substitutions should also be considered within the scope of protection of the present invention.

Claims

1. A method for recovering oversampled data, characterized in that, include: The received serial data is converted into oversampled data, the oversampled data is delayed to obtain first delayed oversampled data, and the first delayed oversampled data and the oversampled data are concatenated to obtain first oversampled concatenated data. The first oversampled spliced ​​data is compared with the preset first binary string sequence data to obtain the transition edge information of the oversampled data, and the transition edge information is mapped to obtain the transition edge position. The transition edge position is input to the edge information shaping circuit so that the edge information shaping circuit can shape the transition edge position to obtain the edge position; Based on the edge position, the sampling position of the oversampled data is calculated, and the oversampled data is sampled based on the sampling position to obtain valid sampled data; The valid sampled data is input into the bit-width conversion circuit so that the bit-width conversion circuit outputs valid data with a fixed bit width.

2. The method for recovering oversampled data as described in claim 1, characterized in that, The first oversampled concatenated data is compared with a preset first binary string sequence data to obtain the transition edge information of the oversampled data, specifically including: Obtain the preset sequence length of the first binary string sequence data, and select multiple data segments from the first oversampled concatenated data in a preset order based on the sequence length; Each data segment is compared with the first binary string sequence data. If the data segment is the same as the first binary string sequence data, it is considered that the first data bit in the current data segment has the oversampled data transition edge, and the first data bit is assigned the value 1. Otherwise, it is considered that the first data bit in the current data segment does not have the oversampled data transition edge, and the first data bit is assigned the value 0. By integrating the first data bit assignment data corresponding to each data segment, the transition edge information of the oversampled data is obtained.

3. The method for recovering oversampled data as described in claim 1, characterized in that, The transition edge information is mapped to obtain the transition edge position, specifically including: The transition edge information is divided into multiple transition edge granularity segments. Each transition edge granularity segment is compared with multiple preset second binary string sequences of data. Based on the comparison results, the phase position of the transition edge in each transition edge granularity segment is determined. By integrating all phase positions, the transition edge position of the oversampled data is obtained.

4. The method for recovering oversampled data as described in claim 1, characterized in that, Before inputting the transition edge position to the edge information shaping circuit, the method further includes: Extract the transition edge position segment from the transition edge position, compare the transition edge position segment with multiple third binary string sequences, and if there is a third binary string sequence that is the same as the transition edge position segment, then delay the transition edge position to obtain a first delayed transition edge position, and update the first delayed transition edge position to the current transition edge position.

5. The method for recovering oversampled data as described in claim 4, characterized in that, The transition edge position is input to the edge information shaping circuit, so that the edge information shaping circuit shapes the transition edge position to obtain the edge position, specifically including: The transition edge position is input into the edge information shaping circuit so that the edge information shaping circuit performs a delay processing on the transition edge position to obtain a second delayed transition edge position. The second delayed transition edge position is then further delayed to obtain a third delayed transition edge position. The second delayed transition edge position and the third delayed transition edge position are incremented by 1 respectively to obtain the second incremented delayed transition edge position and the third incremented delayed transition edge position; If the position of the second plus one delay transition edge is the same as the position of the third delay transition edge, or the position of the third plus one delay transition edge is the same as the position of the second delay transition edge, then the transition edge is considered to be in invalid oscillation, and the transition edge position is taken as the edge position.

6. The method for recovering oversampled data as described in claim 1, characterized in that, Calculating the sampling position of the oversampled data based on the edge position specifically includes: Set a preset phase offset value and obtain the current sampling position. Subtract the current sampling position from the edge position and add the phase offset value to obtain the sampling phase offset value. Determine whether the sampling phase offset value is 0. If it is, then directly use the current sampling position as the sampling position. Otherwise, adjust the current sampling position according to the sampling phase offset value to obtain the sampling position of the oversampled data.

7. The method for recovering oversampled data as described in claim 6, characterized in that, Adjusting the current sampling position based on the sampling phase offset value specifically includes: Set the first sampling phase offset threshold, the second sampling phase offset threshold, and the third sampling phase offset threshold; When it is determined that the sampling phase offset value is not less than the first sampling phase offset threshold, the current sampling position is decremented by 1 to obtain the first adjustment position, and the first adjustment position is updated to the current sampling position; When it is determined that the sampling phase offset value is not less than the second sampling phase offset threshold and is less than the first sampling phase offset threshold, the current sampling position is reduced by 2 to obtain the second adjustment position, and the second adjustment position is updated to the current sampling position; When it is determined that the sampling phase offset value is greater than the third sampling phase offset threshold and less than the second sampling phase offset threshold, the current sampling position is incremented by 2 to obtain the third adjustment position, and the third adjustment position is updated to the current sampling position; When it is determined that the sampling phase offset value is not greater than the third sampling phase offset threshold, the current sampling position is incremented by 1 to obtain the fourth adjustment position, and the fourth adjustment position is updated to the current sampling position.

8. The method for recovering oversampled data as described in claim 1, characterized in that, Based on the sampling location, the oversampled data is sampled to obtain valid sampled data, specifically including: The oversampled data is then subjected to delay processing to obtain second delayed oversampled data, third delayed oversampled data, and fourth delayed oversampled data; First sample data is extracted from the second delayed oversampled data, and second sample data is extracted from the fourth delayed oversampled data. The first sample data, the second sample data, and the third delayed oversampled data are then concatenated to obtain second oversampled concatenated data. The sampling position is delayed to obtain the current sampling position and the sampling position of the previous clock cycle; When it is determined that the current sampling position is within a preset first range, multiple sets of first valid datasets are extracted from the second oversampled spliced ​​data according to the current sampling position. All valid data in each set of first valid datasets are added together to obtain multiple sets of first valid data sums. If the sum of first valid data is greater than a preset valid data sum threshold, the first valid data sampled from the first valid data sum and the corresponding valid dataset is determined to be 1. Otherwise, the first valid data sampled from the first valid data sum and the corresponding first valid dataset is determined to be 0. The first valid data corresponding to all first valid datasets are integrated to obtain the first valid sampled data. When it is determined that the sampling position of the previous clock cycle is at a preset first target position and the current sampling position is 0, then according to the sampling position of the previous clock cycle, multiple sets of second effective datasets are extracted from the second oversampled spliced ​​data. All effective data in each set of second effective datasets are added together to obtain multiple sets of second effective data sums. If the second effective data sum is greater than a preset effective data sum threshold, then the second effective data sampled from the second effective data sum and the corresponding effective dataset is determined to be 1. Otherwise, the second effective data sampled from the second effective data sum and the corresponding second effective dataset is determined to be 0. The second sampled data and the second effective data corresponding to all second effective datasets are integrated to obtain the second effective sampled data. When it is determined that the sampling position of the previous clock cycle is at the preset second target position and the current sampling position is 1, then according to the sampling position of the previous clock cycle, multiple sets of third effective datasets are extracted from the second oversampled spliced ​​data, wherein the difference between the number of the third effective datasets and the number of the second effective datasets is 1; Add all valid data in each group of third valid datasets to obtain multiple groups of third valid data sums. If the sum of third valid data is greater than a preset valid data sum threshold, then the third valid data sampled from the valid dataset corresponding to the third valid data sum is determined to be 1. Otherwise, the third valid data sampled from the third valid data sum and the corresponding third valid dataset is determined to be 0. Integrate the second valid data corresponding to all third valid datasets to obtain the third valid sampled data.

9. The method for recovering oversampled data as described in claim 1, characterized in that, The valid sampled data is input into the bit-width conversion circuit so that the bit-width conversion circuit outputs valid data with a fixed bit width, specifically including: Configure the shift register; Obtain the effective data length of the effective sampled data, input the effective sampled data into the shift register, shift out the effective data length from the shift register, and update the shift register; A counter is set up, and based on the counter, the number of valid data in the shift register is recorded. When the number of valid data is not less than a preset fixed bit width, the fixed bit width valid data is extracted from the shift register and output based on the data bits corresponding to the number of valid data.

10. A device for recovering oversampled data, characterized in that, include: The module includes a sampling data splicing module, a sampling data sliding comparison module, an edge information shaping module, a sampling position calculation module, and a fixed bit width effective data output module. The sampling data splicing module is used to convert the received serial data into oversampled data, perform delay processing on the oversampled data to obtain first delayed oversampled data, and splice the first delayed oversampled data and the oversampled data to obtain first oversampled spliced ​​data. The sampling data sliding comparison module is used to perform a sliding comparison between the first oversampled spliced ​​data and the preset first binary string sequence data to obtain the transition edge information of the oversampled data, and to perform mapping processing on the transition edge information to obtain the transition edge position. The edge information shaping module is used to input the transition edge position into the edge information shaping circuit, so that the edge information shaping circuit can shape the transition edge position to obtain the edge position. The sampling position calculation module is used to calculate the sampling position of the oversampled data based on the edge position, and perform sampling processing on the oversampled data based on the sampling position to obtain valid sampling data; The fixed bit-width valid data output module is used to input the valid sampled data into the bit-width conversion circuit so that the bit-width conversion circuit outputs fixed bit-width valid data.

11. A terminal device, characterized in that, The system includes a processor, a memory, and a computer program stored in the memory and configured to be executed by the processor, wherein the processor, when executing the computer program, implements the method for recovering oversampled data as described in any one of claims 1 to 9.

12. A computer-readable storage medium, characterized in that, The computer-readable storage medium includes a stored computer program, wherein, when the computer program is executed, it controls the device on which the computer-readable storage medium is located to perform the oversampled data recovery method as described in any one of claims 1 to 9.

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