A semiconductor structure and its manufacturing method

Abstract

This disclosure provides a semiconductor structure and its manufacturing method. The semiconductor structure includes a substrate, a dielectric layer, a gate structure, and a capping layer. The substrate includes discrete semiconductor pillars disposed on the top of the substrate and extending vertically. The dielectric layer covers the sidewalls of the semiconductor pillars. The gate structure is disposed in the central region of the semiconductor pillars. The gate structure includes a ring gate structure surrounding the semiconductor pillars. A first portion of the dielectric layer is located between the gate structure and the semiconductor pillars. The capping layer covers the top of the semiconductor pillars and a portion of the sidewalls near the top. The capping layer is made of a boron-containing compound. This disclosure improves the overall electrical performance of the semiconductor structure.

Description

Technical Field

[0001] This disclosure relates to, but is not limited to, a semiconductor structure and a method for manufacturing the same. Background Technology

[0002] As the integration density of dynamic memory continues to increase, while researching the arrangement of transistors in dynamic memory array structures and how to reduce the size of individual functional devices in dynamic memory array structures, it is also necessary to improve the electrical performance of small-sized functional devices.

[0003] Higher density efficiency can be achieved when using a vertical gate all around (VGAA) transistor structure as the access transistor for dynamic memory. However, the performance of semiconductor structures associated with the access transistor in related technologies is relatively low. Summary of the Invention

[0004] In view of this, the present disclosure provides a semiconductor structure and a method for manufacturing the same, which can improve the overall electrical performance of the semiconductor structure.

[0005] The technical solution of this disclosure embodiment is implemented as follows:

[0006] This disclosure provides a semiconductor structure, including:

[0007] A substrate, including discrete semiconductor pillars; the semiconductor pillars are disposed on the top of the substrate and extend in a vertical direction;

[0008] A dielectric layer covering the sidewalls of the semiconductor pillar;

[0009] A gate structure is disposed in the middle region of the semiconductor pillar; the gate structure includes a ring gate structure that surrounds the semiconductor pillar; a first portion of the dielectric layer is located between the gate structure and the semiconductor pillar;

[0010] A capping layer covers the top of the semiconductor pillar and a portion of the sidewalls near the top; the material of the capping layer includes a boron-containing compound.

[0011] In the above scheme, the material of the covering layer includes silicon boron material.

[0012] In the above scheme, the silicon-boron material is silicon boron nitride SiBxNy, and the value of nitrogen content ratio y minus boron content ratio x is less than or equal to 2.

[0013] In the above scheme, the silicon boron material is silicon borosilicate glass or borosilicate glass.

[0014] In the above scheme, the gate structure further includes at least one bridge gate structure; the at least one bridge gate structure penetrates the semiconductor pillar and extends along the penetration direction to the inner wall of the ring gate structure; the at least one bridge gate structure is located inside the semiconductor pillar and is disposed corresponding to the middle region of the ring gate structure.

[0015] In the above scheme, the width of each bridge gate structure is smaller than the width of the semiconductor pillar.

[0016] In the above scheme, the gate structure further includes at least two bridge gate structures, which are stacked at intervals along the vertical direction and are directly isolated by the semiconductor pillars.

[0017] In the above scheme, the top of the ring gate structure is lower than the top of the semiconductor pillar; the second part of the dielectric layer covers the top of the ring gate structure and is located between the ring gate structure and the cover layer; the thickness of the second part of the dielectric layer is greater than the thickness of the first part of the dielectric layer.

[0018] In the above scheme, the semiconductor structure further includes: a first isolation layer; the first isolation layer is located between adjacent semiconductor pillars, and the gate structure is located between the first isolation layer and the semiconductor pillars.

[0019] In the above scheme, the semiconductor structure further includes: a bit line; the bit line is located inside the substrate; and the bottom of the semiconductor pillar is connected to the bit line.

[0020] This disclosure also provides a method for manufacturing a semiconductor structure, including:

[0021] A substrate is provided, the substrate is patterned, and discrete semiconductor pillars are formed on the substrate; the semiconductor pillars are disposed on the top of the substrate and extend in a vertical direction;

[0022] A dielectric layer is formed; the dielectric layer covers the sidewalls of the semiconductor pillar;

[0023] A gate structure is formed in the central region of the semiconductor pillar; the gate structure includes a ring gate structure surrounding the semiconductor pillar; a first portion of the dielectric layer is located between the gate structure and the semiconductor pillar;

[0024] A capping layer is formed; the capping layer covers the top of the semiconductor pillar and a portion of the sidewalls near the top; the material of the capping layer includes a boron-containing compound.

[0025] In the above scheme, if the gate structure further includes a bridge gate structure, the step of forming the gate structure includes: forming a groove in the semiconductor pillar; forming a sacrificial layer in the groove; forming a filling layer in the groove, wherein the filling layer is located on the sacrificial layer and the filling layer fills the remaining groove.

[0026] In the above scheme, if the gate structure further includes at least two bridge gate structures, the steps of forming the gate structure include: forming a groove in the semiconductor pillar; forming a sacrificial layer in the groove; etching back a portion of the sacrificial layer to form a filling layer in the groove, the filling layer being located on the remaining sacrificial layer; and continuing to form the sacrificial layer and the filling layer sequentially in the groove, the filling layer filling to the top of the groove.

[0027] In the above scheme, the step of forming the gate structure further includes: removing the sacrificial layer to form a through-hole; the through-hole penetrating the semiconductor pillar; forming a first initial dielectric layer on the sidewall of the semiconductor pillar and the inner wall of the through-hole; the portion of the first initial dielectric layer located in the middle region of the semiconductor pillar forming a first portion of the dielectric layer; surrounding the sidewall of the first initial dielectric layer and filling the through-hole to form a gate layer; wherein the portion of the gate layer filling the through-hole forms the bridge gate structure; etching the portion of the gate layer surrounding the sidewall of the first initial dielectric layer to form the ring gate structure.

[0028] In the above scheme, after forming the through hole and before forming the first initial dielectric layer, the manufacturing method further includes: etching a portion of the sidewall of the semiconductor pillar so that the width of the middle region of the semiconductor pillar is smaller than the bottom width of the semiconductor pillar.

[0029] In the above scheme, the step of forming the capping layer includes: forming a second initial dielectric layer on the gate structure and the semiconductor pillar; etching the second initial dielectric layer until the top of the semiconductor pillar and a portion of the sidewalls near the top are exposed; the remaining second initial dielectric layer forms a second portion of the dielectric layer; and covering the top of the semiconductor pillar and a portion of the sidewalls near the top to form the capping layer.

[0030] Therefore, this disclosure provides a semiconductor structure and its manufacturing method. The semiconductor structure includes a substrate, a gate structure, a dielectric layer, and a capping layer. The substrate includes discrete semiconductor pillars; the semiconductor pillars are disposed on the top of the substrate and extend vertically; the dielectric layer covers the sidewalls of the semiconductor pillars; the gate structure is disposed in the central region of the semiconductor pillars; the gate structure includes a ring gate structure surrounding the semiconductor pillars; a first portion of the dielectric layer is located between the gate structure and the semiconductor pillars; the capping layer covers the top of the semiconductor pillars and a portion of the sidewalls near the top; the material of the capping layer includes a boron-containing compound. Thus, vias can be formed on the capping layer, and a portion of a capacitor electrode can be placed within the via, allowing an electrical connection between the semiconductor pillars and the capacitor. Because the capping layer material includes a boron-containing compound, it is easier to etch than a typical insulating dielectric layer, resulting in a larger inner wall area for the etched vias. This increases the contact area between the capacitor and the semiconductor pillars, reducing contact resistance, and also increases the surface area of ​​the capacitor electrode, increasing capacitance. Therefore, this disclosure improves the overall electrical performance of the semiconductor structure. Attached Figure Description

[0031] Figure 1 A schematic diagram of a semiconductor structure provided in this disclosure embodiment. Figure 1 ;

[0032] Figure 2 A schematic diagram of a semiconductor structure provided in this disclosure embodiment. Figure 2 ;

[0033] Figure 3 A schematic diagram of a semiconductor structure provided in this disclosure embodiment. Figure 3 ;

[0034] Figure 4 A schematic diagram of a semiconductor structure provided in this disclosure embodiment. Figure 4 ;

[0035] Figure 5 A schematic diagram of a semiconductor structure provided in this disclosure embodiment. Figure 5 ;

[0036] Figure 6 A schematic diagram of a semiconductor structure provided in this disclosure embodiment. Figure 6 ;

[0037] Figure 7 A schematic diagram of a semiconductor structure provided in this disclosure embodiment. Figure 7 ;

[0038] Figure 8 A schematic diagram of a semiconductor structure provided in this disclosure embodiment. Figure 8 ;

[0039] Figure 9 A schematic diagram of a semiconductor structure provided in this disclosure embodiment. Figure 9 ;

[0040] Figure 10 A schematic diagram of a semiconductor structure provided in this disclosure embodiment. Figure 10 ;

[0041] Figure 11 A schematic diagram of a semiconductor structure manufacturing method provided in this disclosure embodiment. Figure 1 ;

[0042] Figure 12 A schematic diagram of a semiconductor structure manufacturing method provided in this disclosure embodiment. Figure 2 ;

[0043] Figure 13 A schematic diagram of a semiconductor structure manufacturing method provided in this disclosure embodiment. Figure 3 ;

[0044] Figure 14 A schematic diagram of a semiconductor structure manufacturing method provided in this disclosure embodiment. Figure 4 ;

[0045] Figure 15 A schematic diagram of a semiconductor structure manufacturing method provided in this disclosure embodiment. Figure 5 ;

[0046] Figure 16 A schematic diagram of a semiconductor structure manufacturing method provided in this disclosure embodiment. Figure 6 ;

[0047] Figure 17 A schematic diagram of a semiconductor structure manufacturing method provided in this disclosure embodiment. Figure 7 ;

[0048] Figure 18 A schematic diagram of a semiconductor structure manufacturing method provided in this disclosure embodiment. Figure 8 ;

[0049] Figure 19 A schematic diagram of a semiconductor structure manufacturing method provided in this disclosure embodiment. Figure 9 ;

[0050] Figure 20 A schematic diagram of a semiconductor structure manufacturing method provided in this disclosure embodiment. Figure 10 ;

[0051] Figure 21 A schematic diagram of a semiconductor structure manufacturing method provided in this disclosure embodiment. Figure 10 one;

[0052] Figure 22 A schematic diagram of a semiconductor structure manufacturing method provided in this disclosure embodiment. Figure 10 two;

[0053] Figure 23 A schematic diagram of a semiconductor structure manufacturing method provided in this disclosure embodiment. Figure 10 three;

[0054] Figure 24 A schematic diagram of a semiconductor structure manufacturing method provided in this disclosure embodiment. Figure 10 Four;

[0055] Figure 25 A schematic diagram of a semiconductor structure manufacturing method provided in this disclosure embodiment. Figure 10 five. Detailed Implementation

[0056] To make the objectives, technical solutions, and advantages of this disclosure clearer, the technical solutions of this disclosure are further described in detail below with reference to the accompanying drawings and embodiments. The described embodiments should not be regarded as limitations on this disclosure. All other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0057] In the following description, references are made to “some embodiments,” which describe a subset of all possible embodiments. However, it is understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0058] If the application documents contain similar descriptions such as "first / second", the following explanation shall be added: In the following description, the terms "first / second / third" are used only to distinguish similar objects and do not represent a specific order of objects. It is understood that "first / second / third" may be interchanged in a specific order or sequence where permitted, so that the embodiments of this disclosure described herein can be implemented in an order other than that illustrated or described herein.

[0059] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing embodiments of this disclosure only and is not intended to be limiting of this disclosure.

[0060] Figure 1 This is an optional structural diagram of the semiconductor structure provided in the embodiments of this disclosure, such as... Figure 1 As shown, the semiconductor structure 80 includes: a substrate 00, a gate structure 10, a capping layer 20, and a dielectric layer 40. Wherein:

[0061] The substrate 00 includes discrete semiconductor pillars 01; the semiconductor pillars 01 are disposed on the top of the substrate 00 and extend in the vertical direction Z;

[0062] The dielectric layer 40 covers the sidewalls of the semiconductor pillar 01;

[0063] The gate structure 10 is disposed in the middle region of the semiconductor pillar 01; the gate structure 10 includes a ring gate structure 101, which surrounds the semiconductor pillar 01; the first portion 401 of the dielectric layer 40 is located between the gate structure 10 and the semiconductor pillar 01.

[0064] The capping layer 20 covers the top of the semiconductor pillar 01 and a portion of the sidewalls near the top; the material of the capping layer 20 includes a boron-containing compound.

[0065] In this embodiment of the disclosure, the substrate 00 may include at least one of the semiconductor materials, such as group IV elements such as silicon (Si), germanium (Ge), and silicon-germanium (SiGe), or group III-V compounds such as gallium arsenide (GaAs), aluminum gallium arsenide (AlGaAs), indium arsenide (InAs), and indium gallium arsenide (InGaAs). The following description exemplifies the inclusion of silicon in the substrate 00.

[0066] The semiconductor pillar 01 may contain doping elements to improve its conductivity. The doping elements may be P-type or N-type doping elements. The N-type doping element may be at least one of arsenic (As), phosphorus (P), or antimony (Sb), and the P-type doping element may be at least one of boron (B), indium (In), or gallium (Ga).

[0067] The gate structure 10 can be made of titanium nitride (TiN), or at least one of conductive materials such as polycrystalline silicon, tantalum nitride (TaN), copper (Cu), or tungsten (W). Titanium nitride will be used as an example in the following description. The dielectric layer 40 can be made of silicon oxide (SiO).

[0068] In this embodiment, a single semiconductor pillar 01, a gate structure 10 surrounding the semiconductor pillar 01, and a first portion 401 of the dielectric layer 40 located between the semiconductor pillar 01 and the gate structure 10 can collectively constitute a first transistor. The central region of the semiconductor pillar 01 corresponding to the gate structure 10 forms a channel region, and the gate structure 10 serves as the gate of the first transistor. The upper and lower ends of the central region of the semiconductor pillar 01 form the source and drain, respectively. It should be noted that the central region of the semiconductor pillar 01 is the middle portion of the semiconductor pillar 01 along the vertical direction Z, located between the top and bottom of the semiconductor pillar 01, and is a certain distance from both the top and bottom. The first portion 401 of the dielectric layer 40 serves as the gate dielectric of the first transistor.

[0069] The first transistor is a VGAA transistor, meaning that the channel formed by the semiconductor pillar 01 extends vertically, and the gate structure 101 of the gate structure 10 surrounds the channel. Therefore, under the same size, compared with transistor structures such as FinFET (Fin Field Effect Transistor), the gate of the first transistor can more fully cover the channel, thus providing stronger gate control capability.

[0070] In this embodiment, the first transistor can serve as the selection transistor for the dynamic memory. Therefore, one of the source and drain terminals of the first transistor needs to be electrically connected to a capacitor, meaning the top of the semiconductor pillar 01 needs to be electrically connected to the capacitor. The capping layer 20 is an insulating material, thus avoiding unnecessary electrical connections and preventing short circuits. Furthermore, multiple vias can be formed on the capping layer 20, each via corresponding to a semiconductor pillar 01, exposing the top of the semiconductor pillar 01. The inner walls of the vias can form part of a capacitor plate, thus electrically connecting the top of the semiconductor pillar 01 to the capacitor. Since the material of the capping layer 20 includes boron-containing compounds, it is easier to etch than typical insulating dielectric layers (such as silicon nitride, silicon oxide, etc.), and the internal structure of the vias is more likely to exhibit isotropic etching results. Here, isotropic means that the etching direction can be along various directions, not just a single direction. In other words, the cross-sectional profile of the inner wall of a via exhibiting isotropic etching will not only contain straight lines, but also irregular lines such as arcs, thus resulting in a larger inner wall area. This increases the contact area between the capacitor and the semiconductor pillar 01, reducing contact resistance, and also increases the surface area of ​​the capacitor plates, thereby increasing the capacitance. Figure 2 and Figure 3 Example Figure 1 An alternative embodiment of the through-hole formed on the cover layer 20, wherein, Figure 3 This is a top view. Figure 2 For along Figure 3The sectional view taken along line A-A1. It should be noted that... Figure 3 The first direction X and the second direction Y shown are both perpendicular to Figure 1 and Figure 2 The vertical direction Z is shown in the figure. The first direction X and the second direction Y can be perpendicular to each other or form any angle. The following description uses the example of the first direction X being perpendicular to the second direction Y.

[0071] In some embodiments of this disclosure, such as Figure 2 and Figure 3 As shown, a first connecting hole 201 extending in the vertical direction Z is formed on the cover layer 20. The lower electrode of a capacitor can be formed in the first connecting hole 201 and electrically connected to the semiconductor pillar 01.

[0072] In this embodiment of the disclosure, reference is made to Figure 2 The first through hole 201 can expose the top of the semiconductor pillar 01 and part of the sidewall near the top, thereby increasing the contact area between the semiconductor pillar 01 and the capacitor subsequently formed, thereby reducing the contact resistance and improving the electrical performance.

[0073] In this embodiment of the disclosure, reference is made to Figure 2 The diameter of the middle portion of the first connecting hole 201 is larger than its top or bottom diameter. It should be noted that the middle portion of the first connecting hole 201 refers to the area between its top and bottom. Since the lower electrode of a capacitor can be formed in the first connecting hole 201, if the top or bottom diameter is too large, it will be difficult to protect the capacitor, increasing the risk of a short circuit. Therefore, the top or bottom diameter of the first connecting hole 201 should not be too large. Furthermore, increasing the diameter of the middle portion of the first connecting hole 201, making it larger than its top or bottom diameter, not only avoids increasing the risk of a short circuit but also increases the surface area of ​​the capacitor electrode, thereby increasing the capacitance.

[0074] In some embodiments of this disclosure, such as Figure 4 As shown, each semiconductor pillar 01 has a contact portion 02 at its top, covering the top and part of the sidewall of the semiconductor pillar 01. The contact portion 02 is used to contact a capacitor. The semiconductor pillar 01 makes electrical contact with the capacitor through the contact portion 02, effectively increasing the electrical contact area between the semiconductor pillar 01 and the capacitor, thereby reducing the contact resistance between the semiconductor pillar 01 and the capacitor. A capping layer 20 isolates adjacent semiconductor pillars 01 and adjacent contact portions 02. The capping layer 20 is an insulating material, thus achieving insulation between the discrete semiconductor pillars 01 and the contact portions 02 on each semiconductor pillar 01. Furthermore, the capping layer 20 can form large through-holes, thereby increasing the contact area between the contact portion 02 and the subsequently formed capacitor, further reducing the contact resistance and improving the performance of the semiconductor device.

[0075] The height of the contact portion 02 covering the sidewall of the semiconductor pillar 01 is 1 / 12 to 1 / 8 of the height of the semiconductor pillar 01. This height setting can ensure that the contact portion 02 and the top surface of the gate structure 10 have sufficient safety distance, reduce the generation of parasitic resistance between the gate structure 10 and the side of the contact portion, and increase the conductivity of the semiconductor pillar 01.

[0076] In some embodiments of this disclosure, reference is made to Figure 1 The material of the capping layer 20 includes silicon boron material.

[0077] In some embodiments of this disclosure, the silicon-boron material may be silicon boron nitride (SiB). x N y In this context, the ratio of nitrogen content (y) to boron content (x) is less than or equal to 2, i.e., yx ≤ 2. Here, the ratio of x to y also represents the ratio of the number of boron to nitrogen atoms in boron nitride silicon, and satisfies 4 ≥ y > x > 0. It should be noted that SiB... x N y The notation does not indicate that the number of silicon atoms is 1.

[0078] In some embodiments of this disclosure, the borosilicate material may be borosilicate phosphor glass (BPSG) or borosilicate glass.

[0079] Compared to general materials, silicon boron materials such as boron nitride silicon, borosilicate glass, or borosilicate glass have a higher etching rate, meaning they are easier to etch. Therefore, using these silicon boron materials for the capping layer 20 makes it easier to form through-holes with larger inner wall areas. This increases the contact area between the capacitor and the semiconductor pillar 01, reducing contact resistance, and also increases the surface area of ​​the capacitor plates, thus increasing the capacitance.

[0080] In some embodiments of this disclosure, reference is made to Figure 1 The top of the gate ring structure 101 is lower than the top of the semiconductor pillar 01. The second portion 402 of the dielectric layer 40 covers the top of the gate ring structure 101 and is located between the gate ring structure 101 and the capping layer 20. The thickness of the second portion 402 of the dielectric layer 40 is greater than the thickness of the first portion 401 of the dielectric layer 40.

[0081] Figure 5 and Figure 6 This shows a portion of the semiconductor structure located beneath the capping layer. Figure 6 This is a top view. Figure 5 For along Figure 6 The sectional view taken from the mid-section line A-A1.

[0082] In this embodiment of the disclosure, reference is made to Figure 6 From a top-down view, the dimensions of semiconductor pillar 01 satisfy 4F. 2 (F: Minimum pattern size achievable under given process conditions), meaning that the distance between the center points of two adjacent semiconductor pillars 01 in the first direction X is 2F, and the distance between the center points of two adjacent semiconductor pillars 01 in the second direction Y is also 2F. Therefore, the integration density of the semiconductor structure 80 is improved. In some embodiments, when forming memory cells on the semiconductor pillars 01, the memory cells can also be arranged according to 4F. 2 arrangement.

[0083] In some embodiments of this disclosure, reference is made to Figure 5 and Figure 6 The gate structure 10 further includes at least one bridge gate structure 102. The at least one bridge gate structure 102 penetrates the semiconductor pillar 01 and extends along the penetration direction to the inner wall of the ring gate structure 101. The at least one bridge gate structure 102 is located within the semiconductor pillar 01 and is disposed corresponding to the central region of the ring gate structure 101. In some embodiments of this disclosure, reference is made to... Figure 5 and Figure 6 The width of each bridge gate structure 102 is smaller than the width of the semiconductor pillar 01. The width of the bridge gate structure 102 and the width of the semiconductor pillar 01 are the distance in the X direction.

[0084] In this embodiment of the disclosure, combined with Figure 5 and Figure 6 The bridge gate structure 102 of the gate structure 10 penetrates the semiconductor pillar 01 and extends along the penetration direction (i.e., the second direction Y) to the inner wall of the ring gate structure 101. The semiconductor pillar 01 is penetrated to form a through hole, which is filled by the bridge gate structure 102, that is, the inner wall of the through hole is covered by the bridge gate structure 102. In this way, the bridge gate structure 102 covers a portion of the channel, the coverage area of ​​the gate structure 10 over the channel is increased, the channel is easier to control, and thus further improves the control capability of the gate of the formed first transistor.

[0085] In some embodiments of this disclosure, reference is made to Figure 5 and Figure 6 The semiconductor structure 80 further includes a first isolation layer 41. The first isolation layer 41 is located between adjacent semiconductor pillars 01, and the gate structure 10 is located between the first isolation layer 41 and the semiconductor pillars 01.

[0086] In this embodiment, the first isolation layer 41 extends along the second direction Y to isolate adjacent semiconductor pillars 01. Additionally, the gate structures 10 arranged along the second direction Y are interconnected to form word lines extending along the Y direction, and the first isolation layer 41 also serves to isolate adjacent word lines 50. The material of the first isolation layer 41 may be silicon nitride (SiN).

[0087] It is understandable that since the gate structure 10 is part of the word line 50, the word line 50 contacts the semiconductor pillar 01 through the gate structure 10. Simultaneously, due to the arrangement of the ring gate structure 101 and the bridge gate structure 102, the contact area between the gate structure 10 and the semiconductor pillar 01 is increased. Therefore, the contact area between the word line 50 and the semiconductor pillar 01 is increased, the contact resistance between the word line 50 and the semiconductor pillar 01 is reduced, the electrical stability of the word line 50 is improved, and in other words, the control capability of the word line 50 over the first transistor is enhanced.

[0088] Figure 7 A cross-sectional view of the semiconductor structure 80 is shown when there are two bridge gate structures 102.

[0089] In some embodiments of this disclosure, such as Figure 7 As shown, the gate structure 10 also includes at least two bridge gate structures 102, which are stacked at a Z-distance along the vertical direction, and are directly isolated by semiconductor pillars.

[0090] Understandably, each bridge gate structure 102 covers the inner wall of a through hole on the semiconductor pillar 01, that is, it covers a portion of the channel. Using at least two bridge gate structures 102 can increase the coverage area of ​​the channel, thereby further improving the control capability of the gate of the formed first transistor.

[0091] In this embodiment of the disclosure, reference is made to Figure 7 Each bridge gate structure 102 has a width smaller than the width of the semiconductor pillar 01. The semiconductor pillar 01 is penetrated by the bridge gate structure 102, which covers the inner wall of the through hole. This increases the contact area between the gate structure 10 and the semiconductor pillar 01, thereby increasing the control capability of the gate structure 10 over the semiconductor pillar 01 and reducing the contact resistance between the gate structure 10 and the semiconductor pillar 01.

[0092] In some embodiments of this disclosure, such as Figure 8 As shown, the semiconductor structure 80 also includes a bit line 51. The bit line 51 is located inside the substrate 00, and the bottom of the semiconductor pillar 01 is electrically connected to the bit line 51.

[0093] In this embodiment of the disclosure, Figure 8 This is a sectional view. Figure 9The positional relationship between word line 50 and bit line 51 is shown from a top-down view, combined with Figure 8 and Figure 9 Bit line 51 extends along the first direction X, while word line 50 extends along the second direction Y. Word line 50 is located above bit line 51. Figure 9 In the diagram, the edge of word line 50 is represented by a solid line, while the edge of bit line 51 is represented by a dashed line. Bit line 51 is partially obscured by word line 50. From a top-down view, word line 50 and bit line 51 intersect (but are not directly electrically connected), and the intersection point is located at the position of semiconductor pillar 01.

[0094] refer to Figure 8 The substrate 00 may also include metal silicide structures 03 (area surrounded by a circular dashed frame), and each metal silicide structure 03 is interconnected in the first direction X to form a bit line 51, which is electrically connected to the bottom of the semiconductor pillar 01.

[0095] In this embodiment of the disclosure, the material of the metal silicide structure 03 includes at least one of cobalt silicide, nickel silicide, molybdenum silicide, titanium silicide, tungsten silicide, tantalum silicide, or platinum silicide.

[0096] It is understandable that the metal silicide structure 03 has a relatively low resistivity compared to the unmetallized semiconductor material, which helps to reduce the resistance of bit line 51 and the contact resistance between bit line 51 and semiconductor pillar 01, thereby further improving the electrical performance of semiconductor structure 80.

[0097] In some embodiments of this disclosure, such as Figure 10 As shown, the semiconductor structure 80 further includes a sacrificial structure 30, which is located above the capping layer 20. The sacrificial structure 30 includes an additional doped region 302 and a body region 303, which are arranged alternately along the vertical direction Z. The doping concentration in the additional doped region 302 is higher than the doping concentration in the body region 303. For example, if the material of the sacrificial structure 30 is boron-doped borosilicate glass (BPSG), then the boron content in the additional doped region 302 is higher than the boron content in the body region 303. Of course, in some embodiments, the body region 303 can also be undoped BPSG.

[0098] In this embodiment of the disclosure, the sacrificial structure 30 can be doped using an ion implantation (IMP) process to form additional doped regions 302. By controlling the ion implantation to use different energies, regions at different depths in the sacrificial structure 30 can be doped, thereby forming alternating additional doped regions 302 and bulk regions 303.

[0099] In some embodiments of this disclosure, such as Figure 10As shown, the sacrificial structure 30 can be processed to form a second via 301. In subsequent processes, a capacitor can be formed in the second via 301, and the capacitor is electrically connected to the semiconductor pillar 01.

[0100] In this embodiment, the second via 301 is formed by etching based on a mask. Since the boron doping concentration in the additional doped region 302 is higher than that in the bulk region 303, the additional doped region 302 is easier to etch than the bulk region 303, and the additional doped region 302 is more likely to form an isotropic etched structure. (Reference) Figure 7 The diameter of the second through hole 301 located in the additional doped region 302 is larger than that located in the body region 303, so that the cross-sectional profile of the inner wall of the second through hole 301 is wavy.

[0101] Understandably, since the capacitor formed in the second through-hole 301 has its plates covering the inner wall of the second through-hole 301, the wavy profile of the inner wall of the second through-hole 301 increases the area of ​​the capacitor plates, thereby increasing the capacitance. Simultaneously, the first connecting hole 201 exposes the top of the semiconductor pillar 01 and a portion of its sidewall near the top, thus increasing the contact area between the semiconductor pillar 01 and the capacitor, reducing contact resistance, and improving electrical performance.

[0102] This disclosure also provides a method for manufacturing a semiconductor structure, including steps S101 to S104, which will be described in conjunction with each step.

[0103] It should be noted that, Figures 11 to 20 These are partial structural diagrams of the semiconductor structure in each step, used to describe and clearly illustrate the steps of the semiconductor structure manufacturing method. Figures 11 to 20 The first direction X and the second direction Y shown are both perpendicular to the vertical direction Z. The first direction X and the second direction Y can be perpendicular to each other or form any angle. The following explanation uses the example of the first direction X being perpendicular to the second direction Y.

[0104] S101. Provide a substrate, pattern the substrate, and form discrete semiconductor pillars on the substrate.

[0105] In this embodiment of the disclosure, such as Figure 11 As shown, after the substrate 00 is patterned, discrete semiconductor pillars 01 are formed. The semiconductor pillars 01 are disposed on the top of the substrate 00 and extend in the vertical direction Z. The substrate 00 may include at least one semiconductor material, such as group IV elements such as silicon (Si), germanium (Ge), and silicon-germanium (SiGe), or group III-V compounds such as gallium arsenide (GaAs), aluminum gallium arsenide (AlGaAs), indium arsenide (InAs), and indium gallium arsenide (InGaAs). The following description exemplifies the inclusion of silicon in the substrate 00.

[0106] Semiconductor pillar 01 may contain doping elements to improve its conductivity. The doping elements may be P-type or N-type doping elements. The N-type doping element may be at least one of arsenic (As), phosphorus (P), or antimony (Sb), while the P-type doping element may be at least one of boron (B), indium (In), or gallium (Ga).

[0107] In this embodiment of the disclosure, reference is made to Figure 11 The substrate 00 also includes a bit line 51 extending along a first direction X. The substrate 00 further includes metal silicide structures 03 (area enclosed by a circular dashed frame), which are interconnected to form the bit line 51. The bottom of the semiconductor pillar 01 is electrically connected to the bit line 51. The material of the metal silicide structure 03 includes at least one of cobalt silicide, nickel silicide, molybdenum silicide, titanium silicide, tungsten silicide, tantalum silicide, or platinum silicide.

[0108] refer to Figure 11 A mask layer 60 is also applied to the semiconductor pillar 01. A first portion 601 of the mask layer 60 covers the sidewalls and top of the semiconductor pillar 01, and a second portion 602 of the mask layer 60 fills the middle of the first portion 601. The first portion 601 and the second portion 602 of the mask layer 60 are made of different materials; for example, the first portion 601 is made of silicon oxide, while the second portion 602 is made of silicon nitride. Thus, combined with... Figure 12 and Figure 13 The etching can be performed according to a certain selection ratio, removing only the second part 602 and the part of the semiconductor channel 01 it covers, forming a groove 61 in the middle of the semiconductor channel 01.

[0109] Figure 14 A top view of a single semiconductor pillar 01, as shown below. Figure 14 As shown, the groove 61 extends along the second direction Y and passes through the semiconductor pillar 01.

[0110] In this embodiment of the disclosure, reference is made to Figure 12 Before etching to form the grooves, a first isolation layer 41 can be deposited. The first isolation layer 41 extends along the second direction Y and isolates adjacent semiconductor pillars 01. The material of the first isolation layer 41 can be silicon nitride.

[0111] In this embodiment of the disclosure, combined with Figure 13 and Figure 15 After etching to form the groove 61, an epitaxial layer 62 can be formed on the inner wall of the groove 61 to reduce the width of the groove 61 and repair the defects on the inner wall of the groove 61.

[0112] In this embodiment of the disclosure, combined with Figure 15 and Figure 16 After the groove 61 is formed, a sacrificial layer 63 can be formed within the groove 61. The height of the sacrificial layer 63 is 1 / 3 to 1 / 2 of the height of the groove 61. The material of the sacrificial layer 63 can be silicon-germanium (SiGe), which makes it easy to remove in subsequent processes, providing a basis for forming the bridge gate structure in the gate structure in subsequent processes. Furthermore, referring to... Figure 16 A filling layer 64 can be formed in the groove 61, the filling layer 64 is located on the sacrificial layer 63, and the filling layer 64 fills the remaining groove 61.

[0113] In this embodiment of the disclosure, combined with Figure 12 and Figure 17 The first portion 601 of the mask layer 60, which covers the sidewall portion of the semiconductor pillar 01, can be etched down to the bottom region of the semiconductor pillar 01, such as... Figure 17 As shown, the remaining first part 601 can protect the sidewall of the bottom of the semiconductor pillar 01 to prevent short circuits between subsequent word lines and bit lines.

[0114] S102, forming a dielectric layer.

[0115] In this embodiment of the disclosure, combined with Figure 17 and Figure 18 A wet etching process can be used to remove the sacrificial layer 63 filled within the semiconductor pillar 01, forming... Figure 18 Through hole 013.

[0116] In this embodiment of the disclosure, combined with Figure 18 and Figure 19 After the through-hole 013 is formed, a first initial dielectric layer can be formed on the sidewall of the central region of the semiconductor pillar 01 and the inner wall of the through-hole 013 using a chemical vapor deposition (CVD) process. The first initial dielectric layer covers a portion of the semiconductor pillar 01 with reduced dimensions, forming a first portion 401 of the dielectric layer 40. A gap exists between the first portion 401 of the dielectric layer 40 and the first isolation layer 41 for forming the gate layer of the ring gate structure 101.

[0117] Furthermore, combined with Figure 18 and Figure 19 After the ring gate structure 101 is formed, a second initial dielectric layer can be deposited. The portion of the second initial dielectric layer covering the top of the ring gate structure 101 forms the second portion 402 of the dielectric layer 40, thus forming the dielectric layer 40. The dielectric layer 40 covers the sidewalls of the semiconductor pillar 01. The thickness of the second portion 402 of the dielectric layer 40 is greater than the thickness of the first portion 401 of the dielectric layer 40.

[0118] S103. A gate structure is formed in the middle region of the semiconductor pillar.

[0119] In this embodiment of the disclosure, combined with Figure 18 and Figure 19 After forming the first initial dielectric layer, a gate layer can be formed around the sidewalls of the first initial dielectric layer and filling the through-hole 013, wherein the portion of the gate layer filling the through-hole 013 forms a bridge gate structure 102. The material of the gate layer can be conductive materials such as titanium nitride, polysilicon, or tungsten. The gate layer covers the sidewalls of the first initial dielectric layer, and then the portion of the gate layer surrounding the sidewalls of the first initial dielectric layer can be etched back, and the remaining gate layer after etching back forms a ring gate structure 101. In this way, a gate structure 10 including a ring gate structure 101 and a bridge gate structure 102 is formed, wherein the ring gate structure 101 surrounds the semiconductor pillar 01, and the bridge gate structure 102 penetrates the semiconductor pillar 01 and extends along the penetration direction to the inner wall of the ring gate structure 101. The first portion 401 of the dielectric layer 40 is located between the gate structure 10 and the semiconductor pillar 01.

[0120] It is understandable that the semiconductor pillar 01 is penetrated to form a through hole 013, and the through hole 013 is filled by the bridge gate structure 102, that is, the inner wall of the through hole 013 is covered by the bridge gate structure 102. In this way, the coverage area of ​​the gate structure 10 on the semiconductor pillar 01 is increased, thereby further improving the control capability of the gate of the formed transistor.

[0121] S104, forming a covering layer.

[0122] In this embodiment of the disclosure, combined with Figure 19 and Figure 20 First, the second portion 402 of the dielectric layer 40 can be etched back so that the top of the second portion 402 of the dielectric layer 40 is lower than the top of the semiconductor pillar 01. Then, refer to... Figure 20 A capping layer 20 can be deposited, which covers the top of the semiconductor pillar 01 and a portion of the sidewalls near the top. The material of the capping layer 20 includes a boron-containing compound, meaning that the material of the capping layer 20 has a higher etching rate than general materials.

[0123] In this embodiment, the material of the capping layer 20 can be boron nitride silicon SiBxNy, where the ratio of x to y represents the ratio of the number of boron to nitrogen atoms in the boron nitride silicon, and 4 ≥ y > x > 0, yx ≤ 2. In some embodiments, the boron nitride silicon SiBxNy can be SiB2N4 or SiB2.6N4. It should be noted that the representation of SiBxNy does not indicate that the number of silicon atoms is 1. Compared with general materials, boron nitride silicon has a higher etching rate, that is, boron nitride silicon is easier to etch.

[0124] In this embodiment, boron can be introduced into the cavity during the formation of silicon nitride, thereby forming boron silicon nitride, i.e., the capping layer 20. Simultaneously, by controlling the flow rate ratio of nitrogen and boron atoms, the ratio of boron to nitrogen atoms in the boron silicon nitride can be adjusted. It should be noted that since boron silicon nitride is easier to etch than silicon nitride, and doping it with boron atoms reduces its stress, meaning lower stress and less internal interaction forces, it is less prone to structural damage, thus improving device performance. When the difference between the number of nitrogen and boron atoms is less than or equal to 2, the nitrogen atom content in the boron silicon nitride can be increased, thereby increasing the etching rate and reducing stress.

[0125] Understandably, on the one hand, because the material of the capping layer 20 has a higher etching rate than ordinary materials, etching the capping layer 20 makes it easier to form a through-hole with a larger central aperture, and expose the top of the semiconductor pillar 01 and part of the sidewall near the top. (Refer to...) Figure 2 and Figure 3 Therefore, the capacitor formed in the through hole has a larger surface area of ​​electrode plate and a larger capacitance. At the same time, its contact area with semiconductor pillar 01 is larger and its contact resistance is smaller.

[0126] In some embodiments of this disclosure, combined with Figures 12 to 19 The steps for forming the gate structure 10 include S201 to S207, which will be explained in conjunction with each step.

[0127] S201, A groove 61 is formed in the semiconductor pillar 01.

[0128] In this embodiment of the disclosure, such as Figure 12 As shown, a mask layer 60 is covered on the semiconductor pillar 01. The first part 601 of the mask layer 60 covers the sidewalls and top of the semiconductor pillar 01, and the second part 602 of the mask layer 60 fills the middle of the first part 601.

[0129] Combination Figure 12 and Figure 13 The etching can be performed according to a certain selection ratio, removing only the second part 602 and the part of the semiconductor pillar 01 it covers, forming a groove 61 in the middle of the semiconductor pillar 01. Figure 14 A top view of a single semiconductor pillar 01, as shown below. Figure 14 As shown, the groove 61 extends along the second direction Y and passes through the semiconductor pillar 01.

[0130] In this embodiment of the disclosure, combined with Figure 13 and Figure 15After etching to form the groove 61, an epitaxial layer 62 can be formed on the inner wall of the groove 61 to reduce its width. Since smaller mask patterns increase the manufacturing difficulty, the second portion 602 of the wider mask layer is etched first, followed by the formation of the epitaxial layer 62 to reduce the width of the groove 61. This allows a smaller groove to be formed using a larger mask pattern, reducing manufacturing complexity. Simultaneously, the etching process may introduce defects and damage to the inner wall of the groove 61. The epitaxial layer 62 can repair these defects and damage, thereby reducing defects in the semiconductor pillar 01 and improving the performance of the formed semiconductor structure.

[0131] S202, forming a sacrificial layer 63 within the groove 61.

[0132] In this embodiment of the disclosure, combined with Figure 15 and Figure 16 After the groove 61 is formed, a sacrificial layer 63 can be formed within the groove 61. The material of the sacrificial layer 63 can be silicon germanium (SiGe), which makes it easy to remove in subsequent processes.

[0133] S203. A filling layer 64 is formed in the groove 61. The filling layer 64 is located on the sacrificial layer 63 and fills the remaining groove 61.

[0134] In this embodiment of the disclosure, if the gate structure to be formed includes only a bridge gate structure, then after forming the sacrificial layer 63, a fill layer 64 is formed in the groove 61. The fill layer 64 is located on the sacrificial layer 63, and the fill layer 64 directly fills the remaining groove 61. Figure 16 As shown.

[0135] If the gate structure to be formed includes at least two bridge gate structures, after forming the sacrificial layer 63, a portion of the sacrificial layer 63 is etched back to form a fill layer 64 within the groove 61, with the fill layer 64 located on the remaining sacrificial layer 63. That is, after a fill layer 64 is formed on the sacrificial layer 63, the sacrificial layer 63 and the fill layer 64 are formed sequentially within the groove 61, ultimately filling the top of the groove 61 with the fill layer 64.

[0136] It is understandable that a sacrificial layer 63 and a fill layer 64 are formed sequentially within the groove 61, providing a basis for the subsequent process to form the bridge gate structure in the gate structure.

[0137] S204. Remove the sacrificial layer 63 to form a through hole 013.

[0138] In this embodiment of the disclosure, combined with Figure 17 and Figure 18 A wet etching process can be used to remove the sacrificial layer 63 filled within the semiconductor pillar 01, forming... Figure 18 Through hole 013. Through hole 013 penetrates semiconductor pillar 01 along the second direction Y.

[0139] S205. A first initial dielectric layer is formed on the sidewall of the semiconductor pillar 01 and the inner wall of the through hole 013.

[0140] In this embodiment of the disclosure, combined with Figure 18 and Figure 19 After the through-hole 013 is formed, a first initial dielectric layer can be formed on the sidewall of the central region of the semiconductor pillar 01 and the inner wall of the through-hole 013 using a chemical vapor deposition (CVD) process. The portion of the first initial dielectric layer located in the central region forms the first portion 401 of the dielectric layer 40, which is situated between the gate structure 10 and the semiconductor pillar 01. The material of the first initial dielectric layer can be silicon oxide.

[0141] S206, a gate layer is formed by surrounding the sidewalls of the first initial dielectric layer and filling the through-hole 013. The portion of the gate layer filling the through-hole 013 forms a bridge gate structure 102.

[0142] In this embodiment of the disclosure, combined with Figure 18 and Figure 19 After the first initial dielectric layer is formed, a gate layer can be formed around the sidewalls of the first initial dielectric layer and filling the through-hole 013, wherein the portion of the gate layer filling the through-hole 013 forms a bridge gate structure 102. The material of the gate layer can be a conductive material such as titanium nitride.

[0143] S207. Etch the portion of the gate layer surrounding the sidewall of the first initial dielectric layer to form a ring gate structure 101.

[0144] In this embodiment of the disclosure, reference is made to Figure 19 After the gate layer is formed, the portion of the gate layer surrounding the sidewall of the first initial dielectric layer can be etched back. After the etch back, the remaining gate layer forms a ring gate structure 101. In this way, a gate structure 10 including a ring gate structure 101 and a bridge gate structure 102 is formed.

[0145] It is understood that the gate structure 10 includes a ring gate structure 101 and a bridge gate structure 102, which increases the coverage area of ​​the semiconductor pillar 01, thereby further improving the control capability of the gate of the formed transistor.

[0146] In this embodiment of the disclosure, combined with Figures 18 to 19 Before forming the first initial dielectric layer, the semiconductor structure manufacturing method also includes step S208, which will be explained in conjunction with each step.

[0147] S208. Etch part of the sidewall of the semiconductor pillar 01 so that the width of the middle region of the semiconductor pillar 01 is smaller than the width of the bottom of the semiconductor pillar 01.

[0148] In this embodiment of the disclosure, before forming the first initial dielectric layer, the dielectric layer can be pre-formed. Figure 18 The area of ​​the semiconductor pillar 01 not covered by the mask layer 601 and the sidewalls above the bottom of the semiconductor pillar 01 are etched (e.g., dry etching) so that the width of the middle region of the semiconductor pillar 01 is smaller than the width of the bottom of the semiconductor pillar 01, providing more space for the subsequent formation of the gate structure. The aforementioned width can be the width along the first direction X.

[0149] In this embodiment of the disclosure, combined with Figures 19 to 20 The 20 steps for forming the cover layer include S301 to S303, which will be explained in conjunction with each step.

[0150] S301. A second initial dielectric layer is formed on the gate structure 10 and the semiconductor pillar 01.

[0151] In this embodiment of the disclosure, reference is made to Figure 19 After the gate structure 10 is formed, a second initial dielectric layer can be deposited on the gate structure 10 and the semiconductor pillar 01.

[0152] S302, Etch the second initial dielectric layer until the top of the semiconductor pillar 01 and a portion of the sidewalls near the top are exposed.

[0153] In this embodiment of the disclosure, combined with Figure 19 and Figure 20 After the initial dielectric layer is deposited, the second initial dielectric layer can be etched until the top of the semiconductor pillar 01 and a portion of the sidewalls near the top are exposed. The remaining second initial dielectric layer then forms the second portion 402 of the dielectric layer 40.

[0154] S303, covering the top of the semiconductor pillar 01 and a portion of the sidewall near the top, forming a cover layer 20.

[0155] In this embodiment of the disclosure, reference is made to Figure 20 After exposing the top of the semiconductor pillar 01 and a portion of its sidewalls near the top, a capping layer 20 can be deposited to cover the top of the semiconductor pillar 01 and the portion of its sidewalls near the top. The material of the capping layer 20 includes a boron-containing compound, meaning that the material of the capping layer 20 has a higher etching rate than ordinary materials.

[0156] In some embodiments of this disclosure, reference is made to Figure 19 ,as well as Figures 21 to 25 Before forming the cover layer 20, a contact portion 02 may be formed on the top surface and the side surface near the top surface of the semiconductor pillar 01.

[0157] refer to Figure 19 and Figure 21 After the dielectric layer 40 is formed, a wet etching process or a dry etching process can be used to remove part of the dielectric layer 40 at the top of the semiconductor pillar 01, exposing the top of the semiconductor pillar 01, so that the second part 402 of the remaining dielectric layer 40 is flush with the top of the semiconductor pillar 01.

[0158] Then, refer to Figure 21 and Figure 22 A wet etching process can be used to remove part of the top of the semiconductor pillar 01, so that the top surface of the semiconductor pillar 01 is lower than the top surface of the dielectric layer 40 and the first isolation layer 41. The removal height of the semiconductor pillar 01 is 1 / 12 to 1 / 8 of the remaining semiconductor pillar.

[0159] Then, refer to Figure 22 and Figure 23 A conductive layer 70 can be covered on the top of the semiconductor pillar 01, the dielectric layer 40 and the first isolation layer 41.

[0160] Then, refer to Figure 23 and Figure 24 The conductive layer 70 can be polished until the tops of the dielectric layer 40 and the first isolation layer 41 are exposed. In this way, the remaining conductive layer on the semiconductor pillar 01 forms the contact portion 02. The contact portion 02 can be made of a metallic material, such as titanium nitride or tungsten, to reduce the contact resistance between the semiconductor pillar 01 and the capacitor.

[0161] refer to Figure 24 and Figure 25 After the contact portion 02 is formed, a wet etching process can be used to remove part of the dielectric layer 40, so that the top of the second portion 402 of the dielectric layer 40 is lower than the top of the semiconductor pillar 01. Then, a capping layer 20 can be deposited, which covers the top of the semiconductor pillar 01 and part of the sidewalls near the top.

[0162] It should be noted that, in this disclosure, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0163] The sequence numbers of the embodiments disclosed above are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments. The methods disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined to obtain new method embodiments without conflict. The features disclosed in the several product embodiments provided in this disclosure can be arbitrarily combined to obtain new product embodiments without conflict. The features disclosed in the several method or device embodiments provided in this disclosure can be arbitrarily combined to obtain new method embodiments or device embodiments without conflict.

[0164] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A semiconductor structure, characterized in that, include: A substrate, including discrete semiconductor pillars; the semiconductor pillars are disposed on the top of the substrate and extend in a vertical direction; A dielectric layer covering the sidewalls of the semiconductor pillar; A gate structure is disposed in the middle region of the semiconductor pillar; the gate structure includes a ring gate structure that surrounds the semiconductor pillar; a first portion of the dielectric layer is located between the gate structure and the semiconductor pillar; A capping layer covers the top of the semiconductor pillar and a portion of the sidewalls near the top; the material of the capping layer includes a boron-containing compound. The gate structure further includes at least one bridge gate structure; The at least one bridge gate structure penetrates the semiconductor pillar and extends along the penetration direction to the inner wall of the annular gate structure; The at least one bridge gate structure is located within the semiconductor pillar and is disposed in the middle region corresponding to the ring gate structure.

2. The semiconductor structure according to claim 1, characterized in that, The material of the covering layer includes silicon boron.

3. The semiconductor structure according to claim 2, characterized in that, The silicon-boron material is silicon boron nitride (SiB). x N y The ratio of nitrogen content (y) to boron content (x) is less than or equal to 2.

4. The semiconductor structure according to claim 2, characterized in that, The silicon-boron material is either silicon-boron-phosphor glass or borosilicate glass.

5. The semiconductor structure according to claim 4, characterized in that, The width of each of the bridge gate structures is smaller than the width of the semiconductor pillar.

6. The semiconductor structure according to claim 1, characterized in that, The gate structure includes at least two bridge gate structures, which are stacked at intervals along the vertical direction and are directly isolated by the semiconductor pillars.

7. The semiconductor structure according to claim 1, characterized in that, The top of the ring gate structure is lower than the top of the semiconductor pillar; The second portion of the dielectric layer covers the top of the ring gate structure and is located between the ring gate structure and the cover layer; the thickness of the second portion of the dielectric layer is greater than the thickness of the first portion of the dielectric layer.

8. The semiconductor structure according to claim 1, characterized in that, The semiconductor structure further includes: a first isolation layer; The first isolation layer is located between adjacent semiconductor pillars, and the gate structure is located between the first isolation layer and the semiconductor pillars.

9. The semiconductor structure according to claim 1, characterized in that, The semiconductor structure further includes: bit lines; The bit line is located inside the substrate; the bottom of the semiconductor pillar is connected to the bit line.

10. A method for manufacturing a semiconductor structure, characterized in that, include: A substrate is provided, the substrate is patterned, and discrete semiconductor pillars are formed on the substrate; The semiconductor pillar is disposed on the top of the substrate and extends in a vertical direction; Forming a dielectric layer; The dielectric layer covers the sidewalls of the semiconductor pillar; A gate structure is formed in the central region of the semiconductor pillar; the gate structure includes a ring gate structure surrounding the semiconductor pillar; a first portion of the dielectric layer is located between the gate structure and the semiconductor pillar; Form a covering layer; The capping layer covers the top of the semiconductor pillar and a portion of the sidewalls near the top; the material of the capping layer includes a boron-containing compound; The gate structure further includes at least one bridge gate structure; The at least one bridge gate structure penetrates the semiconductor pillar and extends along the penetration direction to the inner wall of the annular gate structure; The at least one bridge gate structure is located within the semiconductor pillar and is disposed in the middle region corresponding to the ring gate structure.

11. The manufacturing method according to claim 10, characterized in that, The gate structure includes a bridge gate structure, and the steps for forming the gate structure include: A groove is formed within the semiconductor pillar; A sacrificial layer is formed within the groove; A filling layer is formed in the groove, the filling layer is located on the sacrificial layer, and the filling layer fills the remaining groove.

12. The manufacturing method according to claim 10, characterized in that, The gate structure includes at least two bridge gate structures, and the steps for forming the gate structure include: A groove is formed within the semiconductor pillar; A sacrificial layer is formed within the groove; A portion of the sacrificial layer is etched back to form a filling layer within the groove, the filling layer being located on the remaining sacrificial layer; The sacrificial layer and the filling layer are then formed sequentially within the groove, with the filling layer filling the top of the groove.

13. The manufacturing method according to claim 11 or 12, characterized in that, The step of forming the gate structure further includes: The sacrificial layer is removed to form a through-hole; the through-hole penetrates the semiconductor pillar. A first initial dielectric layer is formed on the sidewall of the semiconductor pillar and the inner wall of the through hole; the portion of the first initial dielectric layer located in the middle region of the semiconductor pillar forms the first portion of the dielectric layer. A gate layer is formed by surrounding the sidewalls of the first initial dielectric layer and filling the through-hole; wherein the portion of the gate layer filling the through-hole forms the bridge gate structure; The gate layer is etched to the portion surrounding the sidewall of the first initial dielectric layer to form the ring gate structure.

14. The manufacturing method according to claim 13, characterized in that, After the formation of the through hole and before the formation of the first initial dielectric layer, the manufacturing method further includes: Etch a portion of the sidewalls of the semiconductor pillar so that the width of the central region of the semiconductor pillar is smaller than the width of the bottom of the semiconductor pillar.

15. The manufacturing method according to claim 10, characterized in that, The steps for forming the cover layer include: A second initial dielectric layer is formed on the gate structure and the semiconductor pillar; The second initial dielectric layer is etched until the top of the semiconductor pillar and a portion of the sidewalls near the top are exposed; the remaining second initial dielectric layer forms a second portion of the dielectric layer. The capping layer is formed by covering the top of the semiconductor pillar and a portion of the sidewalls near the top.

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