Display device and method of manufacturing the same

Abstract

The second inspection portion (Rb) has a second inspection first terminal (18v), a second inspection second terminal (18w), a second inspection third terminal (18x), and a second inspection fourth terminal (18y) electrically connected to the second inspection semiconductor layer (12d) via each contact hole (Ch, Ci, Cj, Ck) formed in the laminated film of the gate insulating film and the interlayer insulating film (17), and an opening portion (M) opening upward is provided between at least one of the second inspection first terminal (18v), the second inspection second terminal (18w), the second inspection third terminal (18x), and the second inspection fourth terminal (18y) and the laminated film of the gate insulating film and the interlayer insulating film (17) in the second inspection portion (Rb).

Description

Technical Field

[0001] This invention relates to a display device and a method for manufacturing the same. Background Technology

[0002] In recent years, self-emissive organic EL (OLED) displays using organic electroluminescence (EL) elements have attracted attention as an alternative to liquid crystal displays. These OLED displays, for example, include a TFT layer in which thin-film transistors (TFTs) for driving the organic EL elements are disposed in each sub-pixel constituting the display area.

[0003] For example, in Patent Document 1, a semiconductor device is disclosed as an evaluation element (test element group, hereinafter also referred to as "TEG") for evaluating the characteristics of a TFT, which is a semiconductor element having a Si region that is not silicided by metal silicide, with a portion of the impurity region provided.

[0004] Existing technical documents

[0005] Patent documents

[0006] Patent Document 1: Japanese Patent Application Publication No. 2007-13125 Summary of the Invention

[0007] The technical problem to be solved by the present invention

[0008] However, in organic EL display devices that display grayscale via current control, unlike liquid crystal display devices that display grayscale via voltage control, TFTs with a flat current-voltage characteristic (Id-Vg curve) waveform, i.e., a large S-value (subthreshold coefficient), are desired. However, if the S-value of the TFT increases, the deviation of the S-value also increases. Therefore, even if a TEG is placed in the bezel area around the display area, and for example, the characteristics of the TFTs in the display area are managed through process checks by measuring the resistance value of the TEG, it is difficult to manage the TFT characteristics through process checks because the resistance value of the TEG has poor reproducibility.

[0009] The present invention was made in view of this purpose, and its object is to reliably manage the characteristics of thin-film transistors through process inspection.

[0010] Technical solutions for solving technical problems

[0011] To achieve the above objectives, the display device of the present invention comprises: a substrate; a thin-film transistor layer disposed on the substrate, wherein a semiconductor layer, a gate insulating film, a first wiring layer, an interlayer insulating film, and a second wiring layer are sequentially stacked; and a light-emitting element layer disposed on the thin-film transistor layer, wherein a plurality of light-emitting elements are arranged corresponding to a plurality of sub-pixels constituting a display area, a border area is disposed around the display area, and an inspection portion is disposed in the border area. The inspection portion comprises a first inspection portion and a second inspection portion disposed adjacent to each other. The first inspection portion comprises: a first inspection semiconductor layer formed on the same layer as the semiconductor layer; the gate insulating film and the interlayer insulating film disposed to cover the first inspection semiconductor layer; and a first inspection first terminal, a first inspection second terminal, a first inspection third terminal, and a first inspection fourth terminal disposed in the interlayer insulating film. The second inspection portion comprises: a second inspection semiconductor layer formed on the same layer as the semiconductor layer using the same material; the gate insulating film and the interlayer insulating film disposed to cover the second inspection semiconductor layer; and a second inspection first terminal, a second inspection second terminal, a second inspection third terminal, and a second inspection fourth terminal disposed on the interlayer insulating film and electrically connected to the second inspection semiconductor layer via contact holes formed on the stacked film of the gate insulating film and the interlayer insulating film. An upwardly opening portion is provided on the stacked film of the gate insulating film and the interlayer insulating film of the second inspection portion between at least one of the second inspection first terminal, the second inspection second terminal, the second inspection third terminal, and the second inspection fourth terminal.

[0012] Beneficial effects

[0013] According to the present invention, the characteristics of thin-film transistors can be reliably managed through process inspection. Attached Figure Description

[0014] Figure 1 This is a plan view showing the schematic configuration of an organic EL display device according to the first embodiment of the present invention.

[0015] Figure 2 This is a plan view of the display area of ​​the organic EL display device according to the first embodiment of the present invention.

[0016] Figure 3 This is a cross-sectional view of the display area of ​​the organic EL display device according to the first embodiment of the present invention.

[0017] Figure 4This is an equivalent circuit diagram of the TFT layer of the organic EL display device constituting the first embodiment of the present invention.

[0018] Figure 5 This is a cross-sectional view showing the organic EL layer of the organic EL display device constituting the first embodiment of the present invention.

[0019] Figure 6 This is a plan view of the first inspection section of the organic EL display device constituting the first embodiment of the present invention.

[0020] Figure 7 It is along Figure 6 A sectional view of the first inspection section along line VII-VII.

[0021] Figure 8 This is a plan view of the second inspection section of the organic EL display device constituting the first embodiment of the present invention.

[0022] Figure 9 It is along Figure 8 A cross-sectional view of the second inspection section along line IX-IX.

[0023] Figure 10 This is a graph showing the waveform of the current-voltage characteristics in an embodiment of the organic EL display device according to the first embodiment of the present invention.

[0024] Figure 11 This is a graph showing the waveform of the current-voltage characteristics in a comparative example of the organic EL display device according to the first embodiment of the present invention.

[0025] Figure 12 This is a plan view showing the schematic configuration of the organic EL display device according to the second embodiment of the present invention. Detailed Implementation

[0026] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the following embodiments.

[0027] First Implementation Method

[0028] Figures 1 to 11 This describes a first embodiment of the display device and its manufacturing method according to the present invention. Furthermore, in the following embodiments, an organic EL display device equipped with an organic EL element is exemplified as a display device equipped with a light-emitting element. Here, Figure 1 This is a plan view showing the schematic configuration of the organic EL display device 50a according to this embodiment. Furthermore, Figure 2 and Figure 3 This is a plan view and a cross-sectional view of the display area D of the organic EL display device 50a. Furthermore,

[0029] Figure 4 This is an equivalent circuit diagram of the TFT layer 20 constituting the organic EL display device 50a. Furthermore, Figure 5 This is a cross-sectional view showing the organic EL layer 23 constituting the organic EL display device 50a. Furthermore, Figure 6 This is a plan view of the first inspection section Ra, which constitutes the organic EL display device 50a. Furthermore, Figure 7 It is along Figure 6 A cross-sectional view of the first inspection section Ra along line VII-VII. Furthermore, Figure 8 This is a plan view of the second inspection section Rb that constitutes the organic EL display device 50a. Furthermore, Figure 9 It is along Figure 8 A cross-sectional view of the second inspection section Rb along line IX-IX. Furthermore, Figure 10 and Figure 11 This is a graph showing the waveforms of the current-voltage characteristics in embodiments and comparative examples of the organic EL display device 50a.

[0030] like Figure 1 As shown, the organic EL display device 50a includes, for example, a display area D for displaying images, which is set in a rectangle, and a border area F, which is set in a frame shape around the display area D. In addition, in this embodiment, a rectangular display area D is exemplified, but the rectangle also includes, for example, a shape with rounded sides, a shape with rounded corners, or a shape with a cutout on part of the side, etc., which are generally rectangular.

[0031] like Figure 2 As shown, in display area D, multiple sub-pixels P are arranged in a matrix. Furthermore, in display area D, as... Figure 2 As shown, for example, sub-pixels P having a red emitting area Lr for red display, sub-pixels P having a green emitting area Lg for green display, and sub-pixels P having a blue emitting area Lb for blue display are arranged adjacent to each other. Furthermore, in the display area D, for example, a pixel is formed by three adjacent sub-pixels P having the red emitting area Lr, the green emitting area Lg, and the blue emitting area Lb.

[0032] In the border area F Figure 1 The lower end of the display area has a terminal section T with multiple terminals arranged thereon. Furthermore, in the bezel area F, between the display area D and the terminal section T, a... Figure 1 The horizontal axis in the diagram serves as the bending axis, allowing the bent portion B to bend 180° (U-shaped) and extend in one direction (horizontally in the diagram). Furthermore, as... Figure 1 As shown, within the border area F, inspection sections R are respectively provided at the four corners corresponding to the display area D. Here, as... Figure 1As shown, the inspection section R includes, for example, a first inspection section Ra and a second inspection section Rb arranged adjacent to each other as TEG at intervals of approximately 0.5 mm. The specific configurations of the first inspection section Ra and the second inspection section Rb will be explained later.

[0033] like Figure 3 As shown, the organic EL display device 50a includes: a resin substrate layer 10 provided as a substrate, a TFT layer 20 provided on the resin substrate layer 10, an organic EL element layer 30 provided on the TFT layer 20 as a light-emitting element layer, and a sealing film 35 provided on the organic EL element layer 30.

[0034] The resin substrate layer 10 is made of, for example, polyimide resin.

[0035] like Figure 3 As shown, the TFT layer 20 includes: a base coating film 11 disposed on the resin substrate layer 10; a plurality of first TFTs 9a, a plurality of second TFTs 9b, and a plurality of capacitors 9c disposed on the base coating film 11; and a planarization film 19 disposed on each of the first TFTs 9a, each of the second TFTs 9b, and each of the capacitors 9c. Here, as... Figure 3 As shown, in the TFT layer 20, a base coating film 11, semiconductor layers 12a and 12b, a gate insulating film 13, and a gate line 14 (see reference) are sequentially stacked on the resin substrate layer 10. Figure 2 ), gates 14a and 14b and lower conductive layer 14c, first wiring layer, first interlayer insulating film 15, upper conductive layer 16, second interlayer insulating film 17, source line 18f (refer to Figure 2 The second wiring layer includes source electrodes 18a and 18c, drain electrodes 18b and 18d, and power lines 18g, as well as a planarization film 19. Furthermore, in the TFT layer 20, such as... Figure 2 and Figure 4 As shown, multiple gate lines 14 are arranged in a manner that extends parallel to each other in the horizontal direction as depicted in the figure. Furthermore, in the TFT layer 20, as... Figure 2 and Figure 4 As shown, multiple source lines 18f are arranged in a manner that extends parallel to each other in the vertical direction of the figure. Furthermore, in the TFT layer 20, as... Figure 2 and Figure 4 As shown, multiple power lines 18g are arranged in a manner that extends parallel to each other along the vertical direction in the figure. Additionally, as... Figure 2 As shown, each power line 18g is positioned adjacent to each source line 18f. Furthermore, as... Figure 4 As shown, in the TFT layer 20, each sub-pixel P is provided with a first TFT 9a, a second TFT 9b, and a capacitor 9c.

[0036] The substrate coating film 11, the gate insulating film 13, the first interlayer insulating film 15, and the second interlayer insulating film 17 are, for example, composed of a single layer or a stack of inorganic insulating films such as silicon nitride, silicon oxide, and silicon oxynitride.

[0037] The first TFT 9a and the second TFT 9b are, for example, p-type TFTs in which impurities such as boron are doped in the semiconductor layers 12a and 12b described later.

[0038] like Figure 4 As shown, the first TFT 9a is electrically connected to the corresponding gate line 14 and source line 18f in each sub-pixel P. Furthermore, as... Figure 3 As shown, the first TFT 9a includes a semiconductor layer 12a, a gate insulating film 13, a gate 14a, a first interlayer insulating film 15, a second interlayer insulating film 17, a source 18a, and a drain 18b, which are sequentially disposed on the base coating film 11. Here, as Figure 3 As shown, the semiconductor layer 12a is disposed in an island-like pattern on the base coating film 11, and for example has a channel region, a source region, and a drain region. Furthermore, as... Figure 3 As shown, the gate insulating film 13 is provided in a manner that covers the semiconductor layer 12a. Furthermore, as... Figure 3 As shown, the gate 14a is disposed on the gate insulating film 13 in a manner that overlaps with the channel region of the semiconductor layer 12a. Furthermore, as... Figure 3 As shown, the first interlayer insulating film 15 and the second interlayer insulating film 17 are sequentially disposed such that they cover the gate 14a. Furthermore, as... Figure 3 As shown, the source 18a and drain 18b are arranged separately from each other on the second interlayer insulating film 17. Furthermore, as... Figure 3 As shown, the source 18a and drain 18b are electrically connected to the source region and drain region of the semiconductor layer 12a, respectively, via contact holes formed in the stacked film of the gate insulating film 13, the first interlayer insulating film 15 and the second interlayer insulating film 17.

[0039] like Figure 4 As shown, the second TFT 9b is electrically connected to the corresponding first TFT 9a and power line 18g in each sub-pixel P. Furthermore, as... Figure 3 As shown, the second TFT 9b includes a semiconductor layer 12b, a gate insulating film 13, a gate 14b, a first interlayer insulating film 15, a second interlayer insulating film 17, a source electrode 18c, and a drain electrode 18d, which are sequentially disposed on the base coating film 11. Here, as Figure 3 As shown, the semiconductor layer 12b is arranged in an island-like pattern on the base coating film 11, and for example, has a channel region, a source region, and a drain region. Furthermore, as... Figure 3 As shown, the gate insulating film 13 is provided in a manner that covers the semiconductor layer 12b. Furthermore, as... Figure 3As shown, the gate 14b is disposed on the gate insulating film 13 in a manner that overlaps with the channel region of the semiconductor layer 12b. Furthermore, as... Figure 3 As shown, the first interlayer insulating film 15 and the second interlayer insulating film 17 are sequentially disposed to cover the gate 14b. Furthermore, as... Figure 3 As shown, the source 18c and drain 18d are arranged separately from each other on the second interlayer insulating film 17. Furthermore, as... Figure 3 As shown, the source 18c and drain 18d are electrically connected to the source region and drain region of the semiconductor layer 12b, respectively, via contact holes formed in the stacked film of the gate insulating film 13, the first interlayer insulating film 15 and the second interlayer insulating film 17.

[0040] In addition, in this embodiment, a top-gate type first TFT 9a and a second TFT 9b are illustrated, but the first TFT 9a and the second TFT 9b may also be bottom-gate type TFTs.

[0041] like Figure 4 As shown, capacitor 9c is electrically connected to the corresponding first TFT 9a and power line 18g in each sub-pixel P. Here, as... Figure 3 As shown, the capacitor 9c includes: a lower conductive layer 14c; a first interlayer insulating film 15 disposed to cover the lower conductive layer 14c; and an upper conductive layer 16 disposed on the first interlayer insulating film 15 to overlap with the lower conductive layer 14c. Additionally, as... Figure 3 As shown, the upper conductive layer 16 is electrically connected to the power line 18g via a contact hole formed in the second interlayer insulating film 17.

[0042] The planarization film 19 has a flat surface in the display area D, and is made of organic resin materials such as polyimide resin.

[0043] like Figure 3 As shown, the organic EL element layer 30 has a plurality of organic EL elements 25 as a plurality of light-emitting elements arranged in a matrix corresponding to a plurality of sub-pixels P.

[0044] like Figure 3 As shown, the organic EL element 25 includes: a first electrode 21 disposed on each sub-pixel P on a planarization film 19, an organic EL layer 23 disposed on the first electrode 21 on each sub-pixel P, and a second electrode 24 disposed on the organic EL layer 23 on a plurality of sub-pixels P.

[0045] like Figure 3As shown, the first electrode 21 is electrically connected to the drain 18d of the second TFT 9b of each sub-pixel P via a contact hole formed on the planarization film 19. Furthermore, the first electrode 21 has the function of injecting holes into the organic EL layer 23. Moreover, to improve the efficiency of hole injection into the organic EL layer 23, it is more preferable to form the first electrode 21 with a material having a high work function. Examples of materials constituting the first electrode 21 include, for example, metallic materials such as silver (Ag), aluminum (Al), vanadium (V), cobalt (Co), nickel (Ni), tungsten (W), gold (Au), titanium (Ti), ruthenium (Ru), manganese (Mn), indium (In), ytterbium (Yb), lithium fluoride (LiF), platinum (Pt), palladium (Pd), molybdenum (Mo), iridium (Ir), and tin (Sn). Additionally, the material constituting the first electrode 21 can also be an alloy of astatine (At) / atstatine oxide (AtO2). Furthermore, the material constituting the first electrode 21 can be, for example, a conductive oxide such as tin oxide (SnO), zinc oxide (ZnO), indium tin oxide (ITO), or indium zinc oxide (IZO). Additionally, the first electrode 21 can be formed by stacking multiple layers composed of the aforementioned materials. Furthermore, compound materials with high work functions can be, for example, indium tin oxide (ITO) or indium zinc oxide (IZO). Moreover, the peripheral end of the first electrode 21 is covered by an edge mask 22 that is shared on multiple sub-pixels P in a grid pattern. Here, the material constituting the edge mask 22 can be, for example, a positive photosensitive resin such as polyimide resin, acrylic resin, polysiloxane resin, or phenolic varnish resin.

[0046] like Figure 5 As shown, the organic EL layer 23 comprises a hole injection layer 1, a hole transport layer 2, a light emission layer 3, an electron transport layer 4, and an electron injection layer 5 sequentially disposed on the first electrode 21.

[0047] Hole injection layer 1, also known as anolyte buffer layer, functions to bring the energy levels of the first electrode 21 and the organic EL layer 23 closer together, thereby improving the hole injection efficiency from the first electrode 21 to the organic EL layer 23. Examples of materials constituting hole injection layer 1 include triazole derivatives, oxadiazole derivatives, imidazole derivatives, polyarylalkane derivatives, pyrazoline derivatives, phenylenediamine derivatives, oxazole derivatives, styrene-anthracene derivatives, fluorenone derivatives, hydrazone derivatives, and stilbene derivatives.

[0048] The hole transport layer 2 has the function of improving the hole transport efficiency from the first electrode 21 to the organic EL layer 23. Examples of materials constituting the hole transport layer 2 include porphyrin derivatives, aromatic tertiary amine compounds, styrene-based amine derivatives, polyvinylcarbazole, poly-p-phenylene vinylene, polysilane, triazole derivatives, oxadiazole derivatives, imidazole derivatives, polyarylalkane derivatives, pyrazoline derivatives, pyrazolone derivatives, phenylenediamine derivatives, arylamine derivatives, amine-substituted chalcone derivatives, oxazole derivatives, styrene-based anthracene derivatives, fluorenone derivatives, hydrazone derivatives, uranium derivatives, hydrogenated amorphous silicon, amorphous hydrogenated silicon carbide, zinc sulfide, or zinc selenide.

[0049] The light-emitting layer 3 is the region in which holes and electrons are injected from the first electrode 21 and the second electrode 24 respectively when a voltage is applied to the first electrode 21 and the second electrode 24, and the holes and electrons recombine. Here, the light-emitting layer 3 is formed of a material with high luminous efficiency. Furthermore, examples of materials constituting the light-emitting layer 3 include: metal hydroxyquinoline ketone compounds [8-hydroxyquinoline metal complexes], naphthalene derivatives, anthracene derivatives, diphenylethylene derivatives, vinyl acetone derivatives, triphenylamine derivatives, butadiene derivatives, coumarin derivatives, benzoxazole derivatives, oxadiazole derivatives, oxazole derivatives, benzimidazole derivatives, thiadiazole derivatives, benzothiazole derivatives, styryl derivatives, styrylamine derivatives, bis(Styryl)Benzene derivatives, tristyrylbenzene derivatives, perylene derivatives, pyrene derivatives, aminopyrene derivatives, pyridine derivatives, rhodamine derivatives, acridine derivatives, phenoxazone, quinacridone derivatives, rubrene, poly(p-phenylenevinylene), or polysilanes, etc.

[0050] The electron transport layer 4 has the function of enabling electrons to move efficiently to the light-emitting layer 3. Here, as materials constituting the electron transport layer 4, examples of organic compounds include: oxadiazole derivatives, triazole derivatives, benzoquinone derivatives, naphthoquinone derivatives, anthraquinone derivatives, tetracyanoanthraquinone dimethane derivatives, biphenylquinone derivatives, fluorenone derivatives, thiophene derivatives, metaloxinoid compounds, etc.

[0051] The electron injection layer 5 functions to bring the energy levels of the second electrode 24 and the organic EL layer 23 closer together, thereby improving the efficiency of electron injection from the second electrode 24 to the organic EL layer 23. This function reduces the driving voltage of the organic EL element 25. The electron injection layer 5 is also referred to as a cathode buffer layer. Examples of materials constituting the electron injection layer 5 include inorganic alkali compounds such as lithium fluoride (LiF), magnesium fluoride (MgF2), calcium fluoride (CaF2), strontium fluoride (SrF2), and barium fluoride (BaF), as well as alumina (Al2O3) and strontium oxide (SrO).

[0052] like Figure 3 As shown, the second electrode 24 is configured to cover the organic EL layer 23 and the edge mask 22 of each sub-pixel P. Furthermore, the second electrode 24 has the function of injecting electrons into the organic EL layer 23. In addition, to improve the electron injection efficiency into the organic EL layer 23, the second electrode 24 is more preferably made of a material with a low work function. Examples of materials constituting the second electrode 24 include silver (Ag), aluminum (Al), vanadium (V), cobalt (Co), nickel (Ni), tungsten (W), gold (Au), calcium (Ca), titanium (Ti), yttrium (Y), sodium (Na), ruthenium (Ru), manganese (Mn), indium (In), magnesium (Mg), lithium (Li), ytterbium (Yb), and lithium fluoride (LiF). Furthermore, the second electrode 34 may also be formed of alloys such as magnesium (Mg) / copper (Cu), magnesium (Mg) / silver (Ag), sodium (Na) / potassium (K), astatine (At) / astatine oxide (AtO2), lithium (Li) / aluminum (Al), lithium (Li) / calcium (Ca) / aluminum (Al), and lithium fluoride (LiF) / calcium (Ca) / aluminum (Al). Additionally, the second electrode 24 may also be formed of conductive oxides such as tin oxide (SnO), zinc oxide (ZnO), indium tin oxide (ITO), and indium zinc oxide (IZO). Furthermore, the second electrode 24 may also be formed by stacking multiple layers of the above-mentioned materials. In addition, materials with low work functions include, for example, magnesium (Mg), lithium (Li), lithium fluoride (LiF), magnesium (Mg) / copper (Cu), magnesium (Mg) / silver (Ag), sodium (Na) / potassium (K), lithium (Li) / aluminum (Al), lithium (Li) / calcium (Ca) / aluminum (Al), lithium fluoride (LiF) / calcium (Ca) / aluminum (Al), etc.

[0053] like Figure 3 As shown, the sealing film 35 is disposed on the organic EL element layer 30 in such a way as to cover each organic EL element 25. Here, as... Figure 3As shown, the sealing film 35 comprises: a first inorganic sealing film 31 disposed to cover the second electrode 24, an organic sealing film 32 disposed on the first inorganic sealing film 31, and a second inorganic sealing film 33 disposed to cover the organic sealing film 32, and has the function of protecting the organic EL layer 23 from the influence of moisture, oxygen, etc. Here, the first inorganic sealing film 31 and the second inorganic sealing film 33 are, for example, made of silicon nitride (SiN) such as silicon oxide (SiO2), aluminum oxide (Al2O3), or silicon tetranitride (Si3N). x (x is a positive number)) and inorganic materials such as silicon carbonitride (SiCN). In addition, the organic sealing film 32 is composed of organic materials such as acrylic resin, polyurea resin, parylene resin, polyimide resin, and polyamide resin.

[0054] like Figure 6 and Figure 7 As shown, the first inspection section Ra includes a first inspection semiconductor layer 12c disposed on the base coating film 11, a gate insulating film 13, a first interlayer insulating film 15, and a second interlayer insulating film 17 sequentially stacked on the first inspection semiconductor layer 12c, and a first inspection first terminal 18h, a first inspection second terminal 18i, a first inspection third terminal 18j, and a first inspection fourth terminal 18k disposed on the second interlayer insulating film 17. Here, the first inspection semiconductor layer 12c is formed on the same layer as semiconductor layers 12a and 12b using the same material. Furthermore, as Figure 6 As shown, the first inspected semiconductor layer 12c is formed in a swastika shape branching in four directions when viewed from above. Furthermore, as... Figure 6 and Figure 7 As shown, the first inspection first terminal 18h, the first inspection second terminal 18i, the first inspection third terminal 18j, and the first inspection fourth terminal 18k are electrically connected to the front ends of branches of the first inspection semiconductor layer 12c via contact holes Ch, Ci, Cj, and Ck formed in the stacked film of the gate insulating film 13, the first interlayer insulating film 15, and the second interlayer insulating film 17. Furthermore, the first inspection section Ra can accurately measure the resistance of, for example, the first inspection semiconductor layer 12c composed of polycrystalline silicon doped with impurities such as boron using the first inspection first terminal 18h, the first inspection second terminal 18i, the first inspection third terminal 18j, and the first inspection fourth terminal 18k via a four-terminal resistance measurement method. Here, in the first inspection section Ra, as... Figure 7 As shown, hydrogen (H) generated from the stacked film of the gate insulating film 13, the first interlayer insulating film 15 and the second interlayer insulating film 17 invades the Si film of the first inspection semiconductor layer 12c. The dangling bonds in the Si film are replaced by hydrogen, and the defects in the Si film are reduced. Therefore, the resistance of the first inspection semiconductor layer 12c is relatively low.

[0055] like Figure 8 and Figure 9As shown, the second inspection section Rb includes: a second inspection semiconductor layer 12d disposed on the base coating film 11; a gate insulating film 13, a first interlayer insulating film 15, and a second interlayer insulating film 17 sequentially stacked on the second inspection semiconductor layer 12d; and a second inspection first terminal 18v, a second inspection second terminal 18w, a second inspection third terminal 18x, and a second inspection fourth terminal 18y disposed on the second interlayer insulating film 17. Here, the second inspection semiconductor layer 12d is formed of the same material as the semiconductor layers 12a and 12b on the same layer. Furthermore, as Figure 8 As shown, the second inspection semiconductor layer 12d is formed in a swastika shape branching in four directions when viewed from above. Furthermore, as... Figure 8 and Figure 9 As shown, the second inspection first terminal 18v, the second inspection second terminal 18w, the second inspection third terminal 18x, and the second inspection fourth terminal 18y are electrically connected to the front end of the branch of the second inspection semiconductor layer 12d via contact holes Cv, Cw, Cx, and Cy formed in the stacked film of the gate insulating film 13, the first interlayer insulating film 15, and the second interlayer insulating film 17. Furthermore, as... Figure 8 and Figure 9 As shown, in the stacked film of the gate insulating film 13, the first interlayer insulating film 15, and the second interlayer insulating film 17 in the second inspection section Rb, an opening M is provided in the region between each of the second inspection first terminal 18v, the second inspection second terminal 18w, the second inspection third terminal 18x, and the second inspection fourth terminal 18y, in a manner that penetrates the stacked film of the gate insulating film 13, the first interlayer insulating film 15, and the second interlayer insulating film 17. Furthermore, using the second inspection first terminal 18v, the second inspection second terminal 18w, the second inspection third terminal 18x, and the second inspection fourth terminal 18y, the second inspection section Rb can accurately measure the resistance of, for example, the second inspection semiconductor layer 12d composed of polycrystalline silicon doped with impurities such as boron, by means of the four-terminal resistance measurement method. Here, in the second inspection section Rb, as... Figure 9 As shown, since hydrogen H generated from the stacked film of gate insulating film 13, first interlayer insulating film 15 and second interlayer insulating film 17 is discharged from the opening M, the dangling bonds in the Si film of the second inspection semiconductor layer 12d are difficult to be replaced by hydrogen, suppressing the reduction of defects in the Si film. Therefore, the resistance of the second inspection semiconductor layer 12d becomes relatively high.

[0056] In addition, in the present embodiment, when observing the cross section, the opening M of the stacked film passing through the gate insulating film 13, the first interlayer insulating film 15, and the second interlayer insulating film 17 is illustrated. However, the opening M may be provided to open upward without passing through the stacked film of the gate insulating film 13, the first interlayer insulating film 15, and the second interlayer insulating film 17. Further, in the present embodiment, although the opening M provided in the entire region between the second inspection first terminal 18v, the second inspection second terminal 18w, the second inspection third terminal 18x, and the second inspection fourth terminal 18y is illustrated in the plan view, the opening M may be provided in a part of the region between at least one of the second inspection first terminal 18v, the second inspection second terminal 18w, the second inspection third terminal 18x, and the second inspection fourth terminal 18y in a dot shape.

[0057] The above-described organic EL display device 50a is configured such that in each sub-pixel P, by inputting a gate signal to the first TFT 9a via the gate line 14, the first TFT ⑨a is turned on, and a voltage corresponding to the source signal is written to the gate 14b of the second TFT 9b and the capacitor 9c via the source line 18f, and a current of the power supply line 18g regulated by the gate voltage of the second TFT 9b is supplied to the organic EL layer 23, so that the light-emitting layer 3 of the organic EL layer 23 emits light to perform image display. In addition, in the organic EL display device 50a, even when the first TFT 9a is turned off, the gate voltage of the second TFT 9b is held by the capacitor 9c. Therefore, the light emission of the light-emitting layer 3 is maintained before the gate signal of the next frame is input. Further, in the process inspection of the manufacturing process described later, the organic EL display device 50a manages the characteristics of the first TFT 9a and the second TFT 9b of each sub-pixel P by measuring the resistance of the first inspection semiconductor layer 12c provided in the first inspection portion Ra in the frame region F and the resistance of the second inspection semiconductor layer 12d provided in the second inspection portion Rb, respectively.

[0058] Next, a method for manufacturing the organic EL display device 50a of the present embodiment will be described. In addition, the method for manufacturing the organic EL display device 50a of the present embodiment includes a TFT layer forming process, an organic EL element layer forming process, and a sealing film forming process.

[0059] <TFT layer forming process>

[0060] First, for example, after coating a non-photosensitive polyimide resin (about 6 μm thick) on a glass substrate, the coated film is pre-baked and post-baked to form the resin substrate layer 10.

[0061] Next, for example, a silicon oxide film (about 500 nm thick) and a silicon nitride film (about 100 nm thick) are sequentially formed on the surface of the substrate on which the resin substrate layer 10 is formed by plasma CVD (chemical vapor deposition) to form an undercoat film 11.

[0062] Then, using plasma CVD, an amorphous silicon film (about 50 nm thick) is formed on the surface of the substrate on which the base coating film 11 is formed. After the amorphous silicon film is crystallized by laser annealing or the like to form a polycrystalline silicon semiconductor film, the semiconductor film is patterned to form semiconductor layers 12a and 12b, a first inspection semiconductor layer 12c, and a second inspection semiconductor layer 12d (semiconductor layer formation process).

[0063] Furthermore, on the surface of the substrate on which the semiconductor layer 12a is formed, an inorganic insulating film (about 100 nm thick) such as a silicon oxide film is formed by, for example, plasma CVD, to cover the semiconductor layer 12a, thereby forming a gate insulating film 13 (gate insulating film formation process).

[0064] Next, on the substrate surface on which the gate insulating film 13 is formed, a molybdenum film (with a thickness of about 250 nm) is formed, for example by sputtering, and the molybdenum film is patterned to form the first wiring layer, such as the gate line 14, gate 14a and 14b.

[0065] Then, using gates 14a and 14b as masks, a portion of semiconductor layers 12a and 12b is conductiveized, for example, by doping with impurity ions such as boron, and the first inspection semiconductor layer 12c and the second inspection semiconductor layer 12d are integrated (doping process).

[0066] Furthermore, for example, a silicon nitride film (about 100 nm thick) is formed on the substrate surface where at least a portion of the semiconductor layer 12a is conductive by plasma CVD, thereby forming a first interlayer insulating film 15 (interlayer insulating film formation process).

[0067] Then, the substrate with the first interlayer insulating film 15 formed thereon is subjected to heat treatment at about 400°C (first annealing process).

[0068] Next, for example, a molybdenum film (about 250 nm thick) is formed on the surface of a heat-treated substrate by sputtering, and then the molybdenum film is patterned to form an upper conductive layer 16.

[0069] Furthermore, a second interlayer insulating film 17 is formed by sequentially depositing a silicon oxide film (approximately 300 nm thick) and a silicon nitride film (approximately 200 nm thick) on the surface of the substrate on which the upper conductive layer 16 is formed, for example, by plasma CVD.

[0070] Subsequently, by patterning the gate insulating film 13, the first interlayer insulating film 15, and the second interlayer insulating film 17, contact holes Ch, Ci, Cj, Ck, Cv, Cw, Cx, and Cy, as well as openings M, are formed (layer film patterning process).

[0071] Then, the substrate with the contact holes and openings M formed thereon is subjected to heat treatment at approximately 400°C (second annealing process). Alternatively, the heat treatment temperature in the second annealing process can be lower than the heat treatment temperature in the first annealing process.

[0072] Then, on the surface of the heat-treated substrate, for example, titanium film (thickness of about 50 nm), aluminum film (thickness of about 600 nm) and titanium film (thickness of about 50 nm) are sequentially formed by sputtering. These metal layers are then patterned to form a third wiring layer consisting of source electrodes 18a and 18c, drain electrodes 18b and 18d, source line 18f, power line 18g, first inspection first terminal 18h, first inspection second terminal 18i, first inspection third terminal 18j, first inspection fourth terminal 18k, second inspection first terminal 18v, second inspection second terminal 18w, second inspection third terminal 18x, and second inspection fourth terminal 18y. Thus, a first TFT 9a, a second TFT 9b, a first inspection section Ra, and a second inspection section Rb are formed. After this process, a probe of, for example, a resistance measuring device is appropriately brought into contact with the first inspection first terminal 18h, the first inspection second terminal 18i, the first inspection third terminal 18j, and the first inspection fourth terminal 18k of the first inspection section Ra, and the second inspection first terminal 18v, the second inspection second terminal 18w, the second inspection third terminal 18x, and the second inspection fourth terminal 18y of the second inspection section Rb. The resistance of the first inspection semiconductor layer 12c of the first inspection section Ra and the second inspection semiconductor layer 12d of the second inspection section Rb are measured respectively. By detecting the difference in their resistances, the characteristics of the first TFT 9a and the second TFT 9b can be managed. Furthermore, although the manufacturing method of this embodiment (the example) can detect the difference between the resistance value of the first inspection semiconductor layer 12c of the first inspection section Ra and the resistance value of the second inspection semiconductor layer 12d of the second inspection section Rb, the manufacturing method of the comparative example described later cannot detect the difference between the resistance value of the first inspection semiconductor layer (12c) of the first inspection section (Ra) and the resistance value of the second inspection semiconductor layer (12d) of the second inspection section (Rb).

[0073] Finally, for example, after coating a photosensitive polyimide resin (approximately 2.5 μm thick) onto the substrate surface on which the third wiring layer is formed using spin coating or slot coating, a planarization film 19 is formed by pre-baking, exposing, developing, and post-baking the coated film.

[0074] As described above, a TFT layer 20 can be formed. Here, in an embodiment where the gate insulating film formation process, the interlayer insulating film formation process, the first annealing process, the laminated film patterning process, and the second annealing process are performed sequentially, the current-voltage characteristics of the first TFT 9a and the second TFT 9b formed in the TFT layer 20 are as follows: Figure 10 As shown, this waveform exhibits a gentler slope and a relatively large S-value. In contrast, in a comparative example where the gate insulating film formation process, the first annealing process, the interlayer insulating film formation process, the second annealing process, and the laminated film patterning process are performed sequentially, the current-voltage characteristics of the first TFT (9a) and the second TFT (9b) are as follows: Figure 11 As shown, it becomes a waveform with a steep inclination and a relatively small S value.

[0075] <Organic EL Component Layer Formation Process>

[0076] On the planarization film 19 of the TFT layer 20 formed in the above-mentioned TFT layer formation process, a first electrode 21, an edge mask 22, an organic EL layer 23 (hole injection layer 1, hole transport layer 2, light emission layer 3, electron transport layer 4, electron injection layer 5) and a second electrode 24 are formed using known methods to form an organic EL element 25, thereby forming an organic EL element layer 30.

[0077] <Sealing film formation process>

[0078] On the organic EL element layer 30 formed in the above-mentioned organic EL element layer formation process, an inorganic insulating film such as a silicon nitride film, a silicon oxide film, or a silicon oxynitride film is formed by using a mask to cover each organic EL element 25 and by plasma CVD to form a first inorganic sealing film 31.

[0079] Next, for example, an organic resin material such as acrylic resin is formed on the first inorganic sealing film 31 by inkjet printing to form an organic sealing film 32.

[0080] Then, using a mask, an inorganic insulating film such as a silicon nitride film, silicon oxide film, or silicon oxynitride film is formed by plasma CVD in a manner that covers the organic sealing film 32, thereby forming the sealing film 35.

[0081] Finally, after attaching a protective sheet (not shown) to the substrate surface on which the sealing film 35 is formed, a laser is irradiated from the glass substrate side of the resin substrate layer 10, thereby peeling the glass substrate off from the lower surface of the resin substrate layer 10, and then attaching a protective sheet (not shown) to the lower surface of the resin substrate layer 10 after the glass substrate has been peeled off.

[0082] As described above, the organic EL display device 50a of this embodiment can be manufactured.

[0083] As described above, the organic EL display device 50a and its manufacturing method according to this embodiment include a first inspection section Ra and a second inspection section Rb arranged adjacent to each other in the frame region F. In the first inspection section Ra, hydrogen H generated from the stacked film of the gate insulating film 13, the first interlayer insulating film 15, and the second interlayer insulating film 17 invades the Si film of the first inspection semiconductor layer 12c. Dangling bonds in the Si film are replaced by hydrogen, reducing defects in the Si film. Therefore, the resistance of the first inspection semiconductor layer 12c is relatively low. Furthermore, in the second inspection section Rb, an upwardly opening M is provided on the stacked film of the gate insulating film 13, the first interlayer insulating film 15, and the second interlayer insulating film 17, between at least one of the second inspection first terminal 18v, the second inspection second terminal 18w, the second inspection third terminal 18x, and the second inspection fourth terminal 18y. Therefore, in the second inspection section Rb, since hydrogen H generated from the stacked film of the gate insulating film 13, the first interlayer insulating film 15, and the second interlayer insulating film 17 is discharged from the opening M, the dangling bonds in the Si film of the second inspection semiconductor layer 12d are difficult to be replaced by hydrogen, suppressing the reduction of defects in the Si film. As a result, the resistance of the second inspection semiconductor layer 12d becomes relatively high. Thus, since the difference between the resistance of the first inspection semiconductor layer 12c of the first inspection section Ra and the resistance of the second inspection semiconductor layer 12d of the second inspection section Rb can be reliably detected, hydrogen detachment in the Si film of the semiconductor layer 12a of the first TFT 9a and the semiconductor layer 12b of the second TFT 9b of each sub-pixel P can be identified, and the characteristics of the first TFT 9a and the second TFT 9b of the TFT layer 20 can be reliably managed through process inspection. Furthermore, by detecting the difference between the resistance of the first inspection semiconductor layer 12c of the first inspection section Ra and the resistance of the second inspection semiconductor layer 12d of the second inspection section Rb, the manufacturing process performed when manufacturing the first organic EL display device 50a can be deduced, namely, the manufacturing process of sequentially performing the gate insulating film formation process, the interlayer insulating film formation process, the first annealing process, the laminated film patterning process, and the second annealing process.

[0084] Furthermore, according to the organic EL display device 50a and its manufacturing method of this embodiment, in the second inspection section Rb, an opening M is provided on the stacked film of the gate insulating film 13, the first interlayer insulating film 15 and the second interlayer insulating film 17, in the entire area between each of the second inspection first terminal 18v, the second inspection second terminal 18w, the second inspection third terminal 18x and the second inspection fourth terminal 18y, so as to penetrate the stacked film of the gate insulating film 13, the first interlayer insulating film 15 and the second interlayer insulating film 17. Therefore, since hydrogen H generated from the stacked film of the gate insulating film 13, the first interlayer insulating film 15 and the second interlayer insulating film 17 is further discharged from the opening M, it is more difficult for dangling bonds in the Si film of the second inspection semiconductor layer 12d to be replaced by hydrogen, suppressing the reduction of defects in the Si film. Therefore, the resistance of the second inspection semiconductor layer 12d becomes relatively high. Therefore, the difference between the resistance of the first inspection semiconductor layer 12c of the first inspection section Ra and the resistance of the second inspection semiconductor layer 12d of the second inspection section Rb can be detected more reliably.

[0085] Furthermore, according to the organic EL display device 50a and its manufacturing method of this embodiment, since the gate insulating film formation process, interlayer insulating film formation process, first annealing process, stacked film patterning process, and second annealing process are performed sequentially in the TFT layer formation process, defects generated in the doping process of the Si film in semiconductor layers 12a and 12b can be repaired in the first annealing process, and hydrogen replacement of dangling bonds present in the Si film can be performed simultaneously. Furthermore, hydrogen removal from the Si film in semiconductor layers 12a and 12b can be performed in the second annealing process. Here, hydrogen removal in the second annealing process is performed uniformly within the substrate surface, thus reducing the deviation of the S value.

[0086] Furthermore, according to the organic EL display device 50a and its manufacturing method of this embodiment, if the temperature of the heat treatment performed in the second annealing process is lower than the temperature of the heat treatment performed in the first annealing process, it is possible to suppress the excessive S value.

[0087] Second Implementation Method

[0088] Figure 12 This describes a second embodiment of the display device and its manufacturing method according to the present invention. Here, Figure 12 This is a plan view showing the schematic configuration of the organic EL display device 50b according to this embodiment. Furthermore, in the following embodiments, [the following text refers to...]. Figures 1 to 11 Identical parts are labeled with the same reference numerals, and their detailed descriptions are omitted.

[0089] In the first embodiment described above, an organic EL display device 50a is shown in which an inspection unit R is provided in the portion of the border area F corresponding to the corner of the display area D. However, in this embodiment, an organic EL display device 50b is shown in which an inspection unit R is provided near the peripheral circuit E of the border area F.

[0090] The organic EL display device 50b is similar to the organic EL display device 50a of the first embodiment described above, including a display area D and a border area F disposed around the display area D.

[0091] like Figure 2 As shown, the corners of the display area D are set as roughly rectangular arcs.

[0092] Within the bezel area F, peripheral circuitry E, including a gate driver (gate drive circuit) and a gearbox driver, is monolithically mounted. Here, the peripheral circuitry E is positioned, for example, along two opposite sides of a roughly rectangular display area D, whose corners are formed into arcs. The arc-shaped portions at the ends of these two sides, such as... Figure 12 As shown, along the arc-shaped section, it is set in a stepped, buckling manner when viewed from above. Furthermore, as... Figure 12 As shown, the inspection section R, which includes a first inspection section Ra and a second inspection section Rb, is located in the valley portion outside the curved portion of the peripheral circuit E.

[0093] The organic EL display device 50b is similar to the organic EL display device 50a of the first embodiment described above, and includes a resin substrate layer 10, a TFT layer 20 disposed on the resin substrate layer 10, an organic EL element layer 30 disposed on the TFT layer 20, and a sealing film 35 disposed on the organic EL element layer 30 in the display area D.

[0094] The organic EL display device 50b described above, like the organic EL display device 50a of the first embodiment, is configured to be flexible. In each sub-pixel P, the light-emitting layer 3 of the organic EL layer 23 emits light appropriately via the first TFT 9a and the second TFT 9b, thereby displaying an image. Furthermore, similarly to the organic EL display device 50a of the first embodiment, the organic EL display device 50b manages the characteristics of the first TFT 9a and the second TFT 9b of each sub-pixel P by measuring the resistance of the first inspection semiconductor layer 12c of the first inspection section Ra and the resistance of the second inspection semiconductor layer 12d of the second inspection section Rb, respectively, provided in the border region F.

[0095] The organic EL display device 50b of this embodiment can be manufactured by changing the position of the forming inspection section R in the manufacturing method of the organic EL display device 50a of the first embodiment described above.

[0096] As described above, the organic EL display device 50b and its manufacturing method according to this embodiment include a first inspection section Ra and a second inspection section Rb arranged adjacent to each other in the frame region F. In the first inspection section Ra, hydrogen H generated from the stacked film of the gate insulating film 13, the first interlayer insulating film 15, and the second interlayer insulating film 17 invades the Si film of the first inspection semiconductor layer 12c. Dangling bonds in the Si film are replaced by hydrogen, reducing defects in the Si film. Therefore, the resistance of the first inspection semiconductor layer 12c is relatively low. Furthermore, in the second inspection section Rb, an upwardly opening section M is provided on the stacked film of the gate insulating film 13, the first interlayer insulating film 15, and the second interlayer insulating film 17, between at least one of the second inspection first terminal 18v, the second inspection second terminal 18w, the second inspection third terminal 18x, and the second inspection fourth terminal 18y. Therefore, in the second inspection section Rb, since hydrogen H generated from the stacked film of the gate insulating film 13, the first interlayer insulating film 15, and the second interlayer insulating film 17 is discharged from the opening M, the dangling bonds in the Si film of the second inspection semiconductor layer 12d are difficult to be replaced by hydrogen, suppressing the reduction of defects in the Si film. As a result, the resistance of the second inspection semiconductor layer 12d becomes relatively high. Thus, since the difference between the resistance of the first inspection semiconductor layer 12c of the first inspection section Ra and the resistance of the second inspection semiconductor layer 12d of the second inspection section Rb can be reliably detected, hydrogen detachment in the Si film of the semiconductor layer 12a of the first TFT 9a and the semiconductor layer 12b of the second TFT 9b of each sub-pixel P can be identified, and the characteristics of the first TFT 9a and the second TFT 9b of the TFT layer 20 can be reliably managed through process inspection. Furthermore, by detecting the difference between the resistance of the first inspection semiconductor layer 12c of the first inspection section Ra and the resistance of the second inspection semiconductor layer 12d of the second inspection section Rb, the manufacturing process performed when manufacturing the first organic EL display device 50b can be deduced, namely, the manufacturing process of sequentially performing the gate insulating film formation process, the interlayer insulating film formation process, the first annealing process, the laminated film patterning process, and the second annealing process.

[0097] Furthermore, according to the organic EL display device 50b and its manufacturing method of this embodiment, since an inspection section R is provided near the peripheral circuit E of the TFT formed in the frame region F, the density of the wiring pattern around the inspection section R is close to the density of the wiring pattern of each sub-pixel P, and the characteristics of the first TFT 9a and the second TFT 9b of the TFT layer 20 can be more reliably managed through process inspection.

[0098] Other Implementation Methods

[0099] In the above embodiments, an organic EL layer with a five-layer stacked structure of hole injection layer, hole transport layer, light emission layer, electron transport layer and electron injection layer is exemplified. However, the organic EL layer may also be a three-layer stacked structure of hole injection layer as hole transport layer, light emission layer and electron transport layer as electron injection layer.

[0100] Furthermore, in the above embodiments, an organic EL display device with the first electrode as the anode and the second electrode as the cathode was illustrated. However, the present invention can also be applied to an organic EL display device with the stacked structure of the organic EL layer reversed, with the first electrode as the cathode and the second electrode as the anode.

[0101] Furthermore, in the above embodiments, an organic EL display device is illustrated in which the electrode of the TFT connected to the first electrode is used as the drain electrode. However, the present invention can also be applied to organic EL display devices in which the electrode of the TFT connected to the first electrode is used as the source electrode.

[0102] Furthermore, in the above embodiments, an organic EL display device was described as an example of a display device, but the present invention can be applied to display devices having multiple light-emitting elements driven by current, for example, to display devices having light-emitting elements having a layer of quantum dots, i.e., QLED (Quantum-dot light emitting diode).

[0103] Industrial availability

[0104] As described above, the present invention is useful for flexible display devices.

[0105] Explanation of reference numerals in the attached figures

[0106] Ch, C1, Cj, Ck, Cv, Cw, Cx, Cy: Contact holes

[0107] D: Display area

[0108] E: Peripheral circuitry

[0109] F: Border area

[0110] M: Opening

[0111] P: Subpixel

[0112] R: Inspection Department

[0113] Ra: First Inspection Department

[0114] Rb: Second Inspection Department

[0115] 9a: First TFT (First Thin Film Transistor)

[0116] 9b: Second TFT (Second Thin Film Transistor)

[0117] 10: Resin substrate layer (substrate)

[0118] 12a, 12b: Semiconductor layers

[0119] 12c: First inspection of the semiconductor layer

[0120] 12d: Second inspection of semiconductor layer

[0121] 13: Gate insulating film

[0122] 14: Gate line (first wiring layer)

[0123] 14a, 14b: Gate (first wiring layer)

[0124] 14c: Lower conductive layer (first wiring layer)

[0125] 15: First interlayer insulating film

[0126] 17: Second interlayer insulating film

[0127] 18a, 18c: Source (second wiring layer)

[0128] 18b, 18d: Drain (second wiring layer)

[0129] 18f: Source line (second wiring layer)

[0130] 18g: Power cord (second wiring layer)

[0131] 18h: First inspection of the first terminal

[0132] 18i: First check the second terminal

[0133] 18j: First check the third terminal

[0134] 18k: First check, fourth terminal

[0135] 18V: Second check first terminal

[0136] 18w: Second inspection, second terminal

[0137] 18x: Second check, third terminal

[0138] 18y: Second check, fourth terminal

[0139] 20: TFT layer (Thin Film Transistor layer)

[0140] 25: Organic EL elements (organic electroluminescent elements, light-emitting elements)

[0141] 30: Organic EL element layer (light-emitting element layer)

[0142] 50a, 50b: Organic EL display devices

Claims

1. A display device, characterized in that, It possesses: Substrate; A thin-film transistor layer is disposed on the substrate, and a semiconductor layer, a gate insulating film, a first wiring layer, an interlayer insulating film and a second wiring layer are sequentially stacked thereon. as well as A light-emitting element layer is disposed above the thin-film transistor layer, and multiple light-emitting elements are arranged corresponding to the multiple sub-pixels constituting the display area. A border area is provided around the display area. An inspection section is provided in the border area. The inspection unit includes a first inspection unit and a second inspection unit arranged adjacent to each other. The first inspection unit includes: The first inspection layer is a semiconductor layer, which is formed in the same layer as the semiconductor layer using the same material; The gate insulating film and the interlayer insulating film are disposed in such a way that they cover the first inspection semiconductor layer; as well as The first inspection first terminal, the first inspection second terminal, the first inspection third terminal, and the first inspection fourth terminal are disposed on the interlayer insulating film and electrically connected to the first inspection semiconductor layer via contact holes formed in the stacked film of the gate insulating film and the interlayer insulating film. The second inspection department is equipped with: The second inspected semiconductor layer is formed in the same layer as the semiconductor layer using the same material. The gate insulating film and the interlayer insulating film are disposed in such a way that they cover the second inspection semiconductor layer; as well as The second inspection first terminal, the second inspection second terminal, the second inspection third terminal, and the second inspection fourth terminal are disposed on the interlayer insulating film and electrically connected to the second inspection semiconductor layer via contact holes formed in the laminated film of the gate insulating film and the interlayer insulating film. An upward-opening opening is provided on the stacked film of the gate insulating film and the interlayer insulating film of the second inspection section, between at least one of the second inspection first terminal, the second inspection second terminal, the second inspection third terminal and the second inspection fourth terminal.

2. The display device according to claim 1, characterized in that, The opening is provided in such a way that it passes through the stacked film of the gate insulating film and the interlayer insulating film in the second inspection section.

3. The display device according to claim 1 or 2, characterized in that, The opening is disposed in the entire area between each of the second inspection first terminal, the second inspection second terminal, the second inspection third terminal, and the second inspection fourth terminal.

4. The display device according to any one of claims 1 to 3, characterized in that, The first inspection semiconductor layer and the second inspection semiconductor layer are respectively formed to branch in four directions when viewed from above. The first inspection first terminal, the first inspection second terminal, the first inspection third terminal, and the first inspection fourth terminal are respectively electrically connected to the front end of the branch of the first inspection semiconductor layer. The second inspection first terminal, the second inspection second terminal, the second inspection third terminal, and the second inspection fourth terminal are electrically connected to the front end of the branch of the second inspection semiconductor layer, respectively.

5. The display device according to any one of claims 1 to 4, characterized in that, The thin-film transistors disposed on the thin-film transistor layer are P-type thin-film transistors.

6. The display device according to any one of claims 1 to 5, characterized in that, Multiple inspection sections are provided in the border area.

7. The display device according to claim 6, characterized in that, The display area is set to a rectangle. The inspection sections are respectively located in the border area corresponding to the four corners of the display area.

8. The display device according to any one of claims 1 to 5, characterized in that, The display area is set as a roughly rectangular shape with rounded corners. In the border area, peripheral circuitry is arranged around the display area. The peripheral circuitry is arranged in a stepped, buckling manner along the arc-shaped portion surrounding the display area when viewed from above. The inspection section is located in the valley portion outside the curved portion of the peripheral circuit.

9. The display device according to claim 8, characterized in that, The peripheral circuit is a gate drive circuit.

10. The display device according to any one of claims 1 to 9, characterized in that, Each of the light-emitting elements is an organic electroluminescent element.

11. A method for manufacturing a display device, comprising the method for manufacturing the display device according to any one of claims 1 to 10, characterized in that, The method for manufacturing the display device includes: In the semiconductor layer formation process, when forming the semiconductor layer, the first inspection semiconductor layer and the second inspection semiconductor layer are formed; The gate insulating film formation process forms the gate insulating film in such a way as to cover the semiconductor layer, the first inspection semiconductor layer and the second inspection semiconductor layer formed in the semiconductor layer formation process; The interlayer insulating film formation process forms an interlayer insulating film on the gate insulating film formed in the gate insulating film formation process; The first annealing process is a heat treatment performed after the interlayer insulating film formation process; The laminated film patterning process, following the first annealing process, involves patterning the laminated film of the gate insulating film and the interlayer insulating film to form the contact hole and the opening; and The second annealing process is a heat treatment performed after the patterning process of the laminated film.

12. The method for manufacturing a display device according to claim 11, characterized in that, Between the gate insulating film formation process and the interlayer insulating film formation process, there is a doping process in which impurities are doped into the semiconductor layer, the first inspection semiconductor layer and the second inspection semiconductor layer via the gate insulating film.

13. The method for manufacturing a display device according to claim 11 or 12, characterized in that, The heat treatment temperature in the second annealing process is lower than the heat treatment temperature in the first annealing process.

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