An arc striking circuit for EFO

Abstract

The application relates to the technical field of semiconductor production, and discloses an arc striking circuit for EFO, which comprises a first differential amplification circuit module, a second differential amplification circuit module, an arc striking circuit module and a voltage transformation circuit module; the first differential amplification circuit module and the second differential amplification circuit module are connected with the arc striking circuit module respectively, and the first differential amplification circuit module is connected with the second differential amplification circuit module; the arc striking circuit module is connected with the voltage transformation circuit module. The application uses closed-loop regulation to determine the energy input into a first transformer in the voltage transformation circuit module and is not dependent on time; the size of the energy input into the first transformer T1 in the voltage transformation circuit module can be controlled by using an analog quantity, so as to control the output voltage; the arc striking circuit has the protection function of automatically stopping and releasing energy when a specified voltage is reached without breakdown; and the arc striking circuit has the function of rapidly releasing the surplus energy after the air is broken down.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and more particularly to an arc-starting circuit for an EFO (Electronic Front-End). Background Technology

[0002] Wire bonding machines, as core equipment in semiconductor packaging, play an important role in sub-sectors such as optical communication, sensor industry, military industry, and power semiconductor.

[0003] The burning state of the EFO (Electronic Flame Off) in a wire bonding machine has a significant impact on the welding quality. The most important step in the EFO operation is to generate a sufficiently low negative high voltage to break down the air and open a path for subsequent current, which is called arc ignition.

[0004] Currently, there are various forms of existing arc-starting circuits, including common voltage doubler rectifier circuits and flyback boost circuits. The circuit diagram of a voltage doubler rectifier circuit is shown below. Figure 1 As shown. The working principle of the voltage doubler rectifier circuit is as follows: PWMA and PWMB are complementary PWM signals. They drive the transformer through switching transistors U12A and U12B to generate continuously changing voltages. The output voltage of the transformer is boosted by the voltage doubler rectifier circuit after the transformer, thus obtaining a negative high voltage at the RED terminal to break down the air. The circuit diagram of the flyback boost circuit is shown below. Figure 2 As shown. The working principle of the flyback boost circuit is as follows: One end of the primary winding of transformer T2 is connected to the power supply, and the other end is controlled by MOSFET Q5 to control whether the current is turned on or off. When MOSFET Q5 is turned on, current is generated in transformer T2, converting electrical energy into magnetic energy and storing it in the transformer. When MOSFET Q5 is turned off, the magnetic energy is converted into electrical energy through the secondary winding of the transformer to do work. Obviously, the output voltage of transformer T2 is related to the amount of electrical energy stored inside after the transformer turns ratio is determined. Before the transformer is magnetically saturated, the current in the primary coil of the transformer is proportional to time, so the amount of energy stored in the transformer can only be controlled by controlling the conduction time of MOSFET Q5. A closed loop is not formed, and the actual energy adjustment requires precise control of the switching of MOSFET Q5.

[0005] The two schemes mentioned above also have another problem: in reality, it is only necessary to achieve the function of arc initiation, and it is not necessary for the ability to continue to do work on the arc after the air is broken down, because doing so would input excess energy into the arc, introducing uncertainty into the burning ball. However, in the first scheme, after the air is broken down, the energy still remaining in the capacitor will affect the arc. Although the second scheme reduces the impact on the arc, the energy remaining in the transformer is not released suddenly, so when the air is broken down, there will inevitably be excess energy inside that has not been completely released.

[0006] Therefore, improvements to existing technologies are necessary.

[0007] The above information is provided as background information only to aid in understanding this disclosure and does not constitute an assertion or admission that any of the above content can be used as prior art relative to this disclosure. Summary of the Invention

[0008] This invention provides an arc-starting circuit for EFO to solve the problems existing in the prior art.

[0009] To achieve the above objectives, the present invention provides the following technical solution:

[0010] An arc-starting circuit for an EFO includes a first differential amplifier circuit module, a second differential amplifier circuit module, an arc-starting circuit module, and a transformer circuit module; wherein,

[0011] The first differential amplifier circuit module and the second differential amplifier circuit module are respectively connected to the arc-starting circuit module, and the first differential amplifier circuit module is connected to the second differential amplifier circuit module;

[0012] The arc-starting circuit module is connected to the transformer circuit module.

[0013] Furthermore, in the arc-starting circuit for EFO, the first differential amplifier circuit module includes a first dual operational amplifier U3 and a first peripheral circuit.

[0014] The first dual operational amplifier U3 is connected to the second differential amplifier circuit module and the arc-starting circuit module respectively through the first peripheral circuit.

[0015] Furthermore, in the arc-starting circuit for EFO, the first peripheral circuit includes a fourth capacitor C1, a sixth resistor R6, a seventh resistor R7, a ninth resistor R9, an eleventh resistor R11, a twelfth resistor R12, a fourteenth resistor R14, a fifteenth resistor R15, and a sixth capacitor C6.

[0016] The fourth capacitor C1 and the sixth resistor R6 are connected in parallel. One end of the connection is connected to the inverting input terminal of the first dual operational amplifier U3, and the other end is connected to the output terminal of the first dual operational amplifier U3.

[0017] One end of the eleventh resistor R11 is connected to the output terminal of the first dual operational amplifier U3, and the other end is connected to the arc-starting circuit module;

[0018] One end of the ninth resistor R9 is connected to the inverting input terminal of the first dual operational amplifier U3, and the other end is connected to the second differential amplifier circuit module.

[0019] The fifteenth resistor R15 and the sixth capacitor C6 are connected in parallel, with one end connected to the non-inverting input terminal of the first dual operational amplifier U3 and the other end grounded.

[0020] One end of the seventh resistor R7 is connected to the reference voltage REF, and the other end is connected to one end of the fourteenth resistor R14;

[0021] The other end of the fourteenth resistor R14 is grounded;

[0022] One end of the twelfth resistor R12 is connected between the seventh resistor R7 and the fourteenth resistor R14, and the other end is connected between the fifteenth resistor R15 and the non-inverting input of the first dual operational amplifier U3.

[0023] Furthermore, in the arc-starting circuit for EFO, the second differential amplifier circuit module includes a second dual operational amplifier U5 and a second peripheral circuit.

[0024] The second dual operational amplifier U5 is connected to the first differential amplifier circuit module and the arc-starting circuit module respectively through the second peripheral circuit.

[0025] Furthermore, in the arc-starting circuit for EFO, the second peripheral circuit includes an eighth capacitor C8, a twenty-fourth resistor R24, a twenty-sixth resistor R26, a twenty-seventh resistor R27, a twenty-eighth resistor R28, a twenty-ninth resistor R29, a thirtieth resistor R30, and a tenth capacitor C10.

[0026] The eighth capacitor C8 and the twenty-sixth resistor R26 are connected in parallel. One end of the connection is connected to the inverting input terminal of the second dual operational amplifier U5, and the other end is connected to the output terminal of the second dual operational amplifier U5.

[0027] The output of the second dual operational amplifier U5 is connected to the arc-starting circuit module;

[0028] One end of the 24th resistor R24 ​​is connected to the reference voltage REF, and the other end is connected to the 27th resistor R27;

[0029] The other end of the 27th resistor R27 is grounded;

[0030] One end of the 28th resistor R28 is connected to the inverting input of the second dual operational amplifier U5, and the other end is connected between the 24th resistor R24 ​​and the 27th resistor R27;

[0031] One end of the 29th resistor R29 is connected to the non-inverting input of the second dual operational amplifier U5, and the other end is connected to VOL_LEVEL;

[0032] The thirtieth resistor R30 and the tenth capacitor C10 are connected in parallel. One end of the parallel connection is connected to the non-inverting input of the second dual operational amplifier U5, and the other end is grounded.

[0033] Furthermore, in the arc-starting circuit for EFO, the arc-starting circuit module includes a first voltage comparator U4A, a second voltage comparator U4B, a first flip-flop U1A, a second flip-flop U1B, and a third peripheral circuit.

[0034] The third peripheral circuit is connected to the first voltage comparator U4A, the second voltage comparator U4B, the first flip-flop U1A, the second flip-flop U1B, the first differential amplifier circuit module, the second differential amplifier circuit module, and the transformer circuit module, respectively.

[0035] Furthermore, in the arc-starting circuit for EFO, the third peripheral circuit includes a first MOSFET Q1, a sixth diode D6, a twenty-fifth resistor R25, a ninth capacitor C9, a second resistor R2, a third resistor R3, a twenty-third resistor R23, a fourth MOSFET Q4, a thirty-second resistor R32, an eleventh capacitor C11, and a thirty-first resistor R31.

[0036] The 1D terminal of the first flip-flop U1A is connected to the power supply VCC, the C1 terminal of the first flip-flop U1A is connected to START_PRESPARK, and the O terminal of the first flip-flop U1A is connected to the INA terminal of the MOSFET driver U2. The R terminal of the first flip-flop U1A is connected to the R terminal of the second flip-flop U1B, and the R terminal of the first flip-flop U1A is connected to NO_CONFIG.

[0037] The drain of the first MOSFET Q1 is connected to the Y terminal of the first voltage comparator U4A, the source of the first MOSFET Q1 is grounded, and the gate of the first MOSFET Q1 is connected between the C1 terminal of the first flip-flop U1A and START_PRESPARK.

[0038] The X terminal of the first voltage comparator U4A is connected to the eleventh resistor R11, the O terminal of the first voltage comparator U4A is connected to the R terminal of the first flip-flop U1A, and the O terminal of the first voltage comparator U4A is connected to the S terminal of the second flip-flop U1B through the sixth diode D6.

[0039] The X terminal of the second voltage comparator U4B is connected to the output terminal of the second dual operational amplifier U5, the Y terminal of the second voltage comparator U4B is connected to PRESSARK_LEVEL, and the O terminal of the second voltage comparator U4B is connected to the C1 terminal of the second flip-flop U1B.

[0040] The 25th resistor R25 and the 9th capacitor C9 are connected in parallel. One end of the connection is connected to the power supply VCC, and the other end is connected between the O terminal of the second voltage comparator U4B and the C1 terminal of the second flip-flop U1B.

[0041] One end of the second resistor R2 is connected to the power supply VCC, and the other end is connected to the R terminal of the first flip-flop U1A;

[0042] One end of the third resistor R3 is connected to the power supply VCC, and the other end is connected to the S terminal of the first flip-flop U1A.

[0043] One end of the 23rd resistor R23 is connected to the power supply VCC, and the other end is connected to the drain of the fourth MOSFET Q4;

[0044] The source of the fourth MOS transistor Q4 is grounded, and the gate of the fourth MOS transistor Q4 is connected to the BREAK DOWM through the thirty-first resistor R31.

[0045] The thirty-second resistor R32 and the eleventh capacitor C11 are connected in parallel. One end of the connection is between the gate of the fourth MOS transistor Q4 and the thirty-first resistor R31, and the other end is grounded.

[0046] The 1D terminal of the second flip-flop U1B is connected to the power supply VCC, and the 0 terminal of the second flip-flop U1B is connected to the INB terminal of the MOSFET driver U2. The terminal connects to PRESSPARK ACTIVE.

[0047] Furthermore, in the arc-starting circuit for EFO, the transformer circuit module includes a first transformer T1 and a fourth peripheral circuit;

[0048] The first transformer T1 is connected to the arc-starting circuit module through the fourth peripheral circuit.

[0049] Furthermore, in the arc-starting circuit for EFO, the fourth peripheral circuit includes a first resistor R1, a first capacitor C1, a first diode D1, a second capacitor C2, a third capacitor C3, a fourth resistor R4, a fifth resistor R5, a second diode D2, a second MOSFET Q2, a thirteenth resistor R13, a sixteenth resistor R16, a fourth diode D4, a third MOSFET Q3, a seventeenth resistor R17, a sampling resistor circuit, a third diode D3, a fifth capacitor C5, and a tenth resistor R10;

[0050] The first end of the first winding W1 on the primary side of the first transformer T1 is connected to the power supply VCC.

[0051] The first resistor R1 and the first capacitor C1 are connected in parallel. One end of the first resistor R1 is connected to the negative terminal of the first diode D1, and the other end is connected between the first end of the primary winding W1 of the first transformer T1 and the power supply VCC.

[0052] The positive terminal of the first diode D1 is connected to the end of the first winding W1 of the primary side of the first transformer T1;

[0053] The second capacitor C2 and the third capacitor C3 are both connected at one end between the first end of the first winding W1 of the primary side of the first transformer T1 and the power supply VCC, and the other end is grounded.

[0054] The drain of the second MOS transistor Q2 is connected to the end of the first winding W1 of the primary side of the first transformer T1. The source of the second MOS transistor Q2 is connected to the drain of the first MOS transistor Q1 through the seventeenth resistor R17. The gate of the second MOS transistor Q2 is connected to the OA terminal of the MOSFET driver U2 through the fifth resistor R5.

[0055] The positive terminal of the second diode D2 is connected between the gate of the second MOSFET Q2 and the fifth resistor R5, and the negative terminal of the second diode D2 is connected to one end of the fourth resistor R4.

[0056] The other end of the fourth resistor R4 is connected between the fifth resistor R5 and the OA terminal of the MOSFET driver U2;

[0057] The first end of the second winding W2 of the primary side of the first transformer T1 is grounded, and the end of the second winding W2 of the primary side of the first transformer T1 is connected to the drain of the third MOS transistor Q3 through the third diode D3 and the fifth capacitor C5.

[0058] The tenth resistor R10 is connected in parallel across the fifth capacitor C5;

[0059] The source of the third MOSFET Q3 is grounded, and the gate of the third MOSFET Q3 is connected to the OB terminal of the MOSFET driver U2 through the sixteenth resistor R16.

[0060] The positive terminal of the fourth diode D4 is connected between the gate of the third MOS transistor Q3 and the sixteenth resistor R16, and the negative terminal of the fourth diode D4 is connected to one end of the thirteenth resistor R13.

[0061] The other end of the thirteenth resistor R13 is connected between the sixteenth resistor R16 and the OB terminal of the MOSFET driver U2;

[0062] One end of the sampling resistor circuit is connected between the source of the second MOS transistor Q2 and the seventeenth resistor R17, and the other end is grounded;

[0063] The first end of the secondary winding W3 of the first transformer T1 is connected to PRESSPARK through the eighth resistor R8 and the fifth diode D5; the positive terminal of the fifth diode D5 is connected to the eighth resistor R8; the end of the secondary winding W3 of the first transformer T1 is grounded.

[0064] Furthermore, in the arc-starting circuit for EFO, the sampling resistor circuit includes an eighteenth resistor R18, a nineteenth resistor R19, a twentieth resistor R20, and a twenty-first resistor R21.

[0065] The eighteenth resistor R18, the nineteenth resistor R19, the twentieth resistor R20, and the twenty-first resistor R21 are connected in parallel. One end of the parallel connection is between the source of the second MOS transistor Q2 and the seventeenth resistor R17, and the other end is grounded.

[0066] Compared with the prior art, the arc-starting circuit for EFO of the present invention has the following advantages:

[0067] 1. Using closed-loop regulation, the energy input to the first transformer in the transformer circuit module is determined, independent of time;

[0068] 2. The amount of energy input to the first transformer T1 in the transformer circuit module can be controlled by analog signals, thereby controlling the output voltage;

[0069] 3. It has a protection function that automatically stops and releases energy if it reaches the specified voltage without breaking down;

[0070] 4. It has the function of rapidly releasing excess energy after breaking down the air.

[0071] The present invention has other features and advantages, which will be apparent from or will be set forth in detail in the accompanying drawings and the following detailed description, which together serve to explain the particular principles of the invention. Attached Figure Description

[0072] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0073] Figure 1This is a schematic diagram of the circuit principle of a voltage doubler rectifier circuit in the prior art;

[0074] Figure 2 This is a schematic diagram of the circuit principle of a flyback boost circuit in the prior art;

[0075] Figure 3 This is a functional module diagram of an arc-starting circuit for an EFO provided in an embodiment of the present invention;

[0076] Figure 4 This is a schematic diagram of the arc-starting circuit for EFO provided in an embodiment of the present invention;

[0077] Figure 5 yes Figure 4 A magnified schematic diagram of the circuit principle of the first differential amplifier module;

[0078] Figure 6 yes Figure 4 A magnified schematic diagram of the circuit principle of the second differential amplifier module;

[0079] Figure 7 yes Figure 4 A magnified schematic diagram of the circuit principle of the arc-leading circuit module;

[0080] Figure 8 yes Figure 4 A magnified schematic diagram of the circuit principle of the medium-voltage transformer module. Detailed Implementation

[0081] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application. Furthermore, those skilled in the art will understand that with technological development and the emergence of new scenarios, the technical solutions provided by the embodiments of this application are also applicable to similar technical problems.

[0082] In the description of this application, it should be understood that, unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains. Furthermore, any terminology used is for the purpose of describing particular embodiments only and is not intended to be limiting of this application.

[0083] Furthermore, to better illustrate this application, numerous specific details are provided in the following detailed embodiments. Those skilled in the art should understand that this application can be implemented without certain specific details. In some instances, methods, means, components, and circuits well-known to those skilled in the art have not been described in detail in order to highlight the main points of this application.

[0084] The technical solution of the present invention will be further described below with reference to the accompanying drawings and specific embodiments.

[0085] Example 1

[0086] In view of the deficiencies in the existing technology, the applicant, based on years of practical experience and professional knowledge in the design and manufacture of such products, and in conjunction with the application of theoretical principles, actively conducted research and innovation in order to create a technology that could solve the deficiencies in the existing technology. After continuous research, design, and repeated prototype production and improvement, the present invention, which has practical value, was finally created.

[0087] Please refer to Figure 3 This invention provides an arc-starting circuit for an EFO (Electronic Flame-Off Circuit), comprising a first differential amplifier circuit module, a second differential amplifier circuit module, an arc-starting circuit module, and a transformer circuit module; wherein,

[0088] The first differential amplifier circuit module and the second differential amplifier circuit module are respectively connected to the arc-starting circuit module, and the first differential amplifier circuit module is connected to the second differential amplifier circuit module;

[0089] The arc-starting circuit module is connected to the transformer circuit module.

[0090] It should be noted that this embodiment uses a closed-loop adjustment method to solve the above problems, and at the same time adds protection and monitoring functions.

[0091] Please refer to this again. Figure 3 and in conjunction with references Figure 4 and Figure 5 In this embodiment, the first differential amplifier circuit module includes a first dual operational amplifier U3 and a first peripheral circuit;

[0092] The first dual operational amplifier U3 is connected to the second differential amplifier circuit module and the arc-starting circuit module respectively through the first peripheral circuit.

[0093] Please refer to this again. Figure 4-5 In this embodiment, the first peripheral circuit includes a fourth capacitor C1, a sixth resistor R6, a seventh resistor R7, a ninth resistor R9, an eleventh resistor R11, a twelfth resistor R12, a fourteenth resistor R14, a fifteenth resistor R15, and a sixth capacitor C6.

[0094] The fourth capacitor C1 and the sixth resistor R6 are connected in parallel. One end of the connection is connected to the inverting input terminal of the first dual operational amplifier U3, and the other end is connected to the output terminal of the first dual operational amplifier U3.

[0095] One end of the eleventh resistor R11 is connected to the output terminal of the first dual operational amplifier U3, and the other end is connected to the arc-starting circuit module;

[0096] One end of the ninth resistor R9 is connected to the inverting input terminal of the first dual operational amplifier U3, and the other end is connected to the second differential amplifier circuit module.

[0097] The fifteenth resistor R15 and the sixth capacitor C6 are connected in parallel, with one end connected to the non-inverting input terminal of the first dual operational amplifier U3 and the other end grounded.

[0098] One end of the seventh resistor R7 is connected to the reference voltage REF, and the other end is connected to one end of the fourteenth resistor R14;

[0099] The other end of the fourteenth resistor R14 is grounded;

[0100] One end of the twelfth resistor R12 is connected between the seventh resistor R7 and the fourteenth resistor R14, and the other end is connected between the fifteenth resistor R15 and the non-inverting input of the first dual operational amplifier U3.

[0101] Please refer to this again. Figure 3 and in conjunction with references Figure 4 and Figure 6 In this embodiment, the second differential amplifier circuit module includes a second dual operational amplifier U5 and a second peripheral circuit.

[0102] The second dual operational amplifier U5 is connected to the first differential amplifier circuit module and the arc-starting circuit module respectively through the second peripheral circuit.

[0103] Please refer to this again. Figure 4 and 6 In this embodiment, the second peripheral circuit includes an eighth capacitor C8, a twenty-fourth resistor R24, a twenty-sixth resistor R26, a twenty-seventh resistor R27, a twenty-eighth resistor R28, a twenty-ninth resistor R29, a thirtieth resistor R30, and a tenth capacitor C10.

[0104] The eighth capacitor C8 and the twenty-sixth resistor R26 are connected in parallel. One end of the connection is connected to the inverting input terminal of the second dual operational amplifier U5, and the other end is connected to the output terminal of the second dual operational amplifier U5.

[0105] The output of the second dual operational amplifier U5 is connected to the arc-starting circuit module;

[0106] One end of the 24th resistor R24 ​​is connected to the reference voltage REF, and the other end is connected to the 27th resistor R27;

[0107] The other end of the 27th resistor R27 is grounded;

[0108] One end of the 28th resistor R28 is connected to the inverting input of the second dual operational amplifier U5, and the other end is connected between the 24th resistor R24 ​​and the 27th resistor R27;

[0109] One end of the 29th resistor R29 is connected to the non-inverting input of the second dual operational amplifier U5, and the other end is connected to VOL_LEVEL;

[0110] The thirtieth resistor R30 and the tenth capacitor C10 are connected in parallel. One end of the parallel connection is connected to the non-inverting input of the second dual operational amplifier U5, and the other end is grounded.

[0111] It should be noted that VOL_LEVEL is the analog input terminal of the entire arc-starting circuit, and a DA or PWM+RC structure can be used to provide control input for the arc-starting circuit. The purpose of the first differential amplifier circuit module is to adjust the analog voltage input to VOL_LEVEL, and then use the adjusted voltage as a reference to compare it with the voltage drop across the sampling resistor of the transformer primary current measuring current.

[0112] The purpose of the second differential amplifier circuit module is to adjust the analog voltage input VOL_LEVEL, and then use the adjusted voltage as a reference to input into the second voltage comparator U4B to compare with the value of the actual generated negative high voltage after voltage division (PRESPARK_LEVEL), so as to determine whether the set negative voltage value has been reached.

[0113] Please refer to this again. Figure 3 and in conjunction with references Figure 4 and Figure 7 In this embodiment, the arc-starting circuit module includes a first voltage comparator U4A, a second voltage comparator U4B, a first flip-flop U1A, a second flip-flop U1B, and a third peripheral circuit.

[0114] The third peripheral circuit is connected to the first voltage comparator U4A, the second voltage comparator U4B, the first flip-flop U1A, the second flip-flop U1B, the first differential amplifier circuit module, the second differential amplifier circuit module, and the transformer circuit module, respectively.

[0115] Please refer to this again. Figure 4 and 7 In this embodiment, the third peripheral circuit includes a first MOSFET Q1, a sixth diode D6, a twenty-fifth resistor R25, a ninth capacitor C9, a second resistor R2, a third resistor R3, a twenty-third resistor R23, a fourth MOSFET Q4, a thirty-second resistor R32, an eleventh capacitor C11, and a thirty-first resistor R31.

[0116] The 1D terminal of the first flip-flop U1A is connected to the power supply VCC, the C1 terminal of the first flip-flop U1A is connected to START_PRESPARK, and the O terminal of the first flip-flop U1A is connected to the INA terminal of the MOSFET driver U2. The R terminal of the first flip-flop U1A is connected to the R terminal of the second flip-flop U1B, and the R terminal of the first flip-flop U1A is connected to NO_CONFIG.

[0117] The drain of the first MOSFET Q1 is connected to the Y terminal of the first voltage comparator U4A, the source of the first MOSFET Q1 is grounded, and the gate of the first MOSFET Q1 is connected between the C1 terminal of the first flip-flop U1A and START_PRESPARK.

[0118] The X terminal of the first voltage comparator U4A is connected to the eleventh resistor R11, the O terminal of the first voltage comparator U4A is connected to the R terminal of the first flip-flop U1A, and the O terminal of the first voltage comparator U4A is connected to the S terminal of the second flip-flop U1B through the sixth diode D6.

[0119] The X terminal of the second voltage comparator U4B is connected to the output terminal of the second dual operational amplifier U5, the Y terminal of the second voltage comparator U4B is connected to PRESSARK_LEVEL, and the O terminal of the second voltage comparator U4B is connected to the C1 terminal of the second flip-flop U1B.

[0120] The 25th resistor R25 and the 9th capacitor C9 are connected in parallel. One end of the connection is connected to the power supply VCC, and the other end is connected between the O terminal of the second voltage comparator U4B and the C1 terminal of the second flip-flop U1B.

[0121] One end of the second resistor R2 is connected to the power supply VCC, and the other end is connected to the R terminal of the first flip-flop U1A;

[0122] One end of the third resistor R3 is connected to the power supply VCC, and the other end is connected to the S terminal of the first flip-flop U1A.

[0123] One end of the 23rd resistor R23 is connected to the power supply VCC, and the other end is connected to the drain of the fourth MOSFET Q4;

[0124] The source of the fourth MOS transistor Q4 is grounded, and the gate of the fourth MOS transistor Q4 is connected to the BREAK DOWM through the thirty-first resistor R31.

[0125] The thirty-second resistor R32 and the eleventh capacitor C11 are connected in parallel. One end of the connection is between the gate of the fourth MOS transistor Q4 and the thirty-first resistor R31, and the other end is grounded.

[0126] The 1D terminal of the second flip-flop U1B is connected to the power supply VCC, and the 0 terminal of the second flip-flop U1B is connected to the INB terminal of the MOSFET driver U2. The terminal connects to PRESSPARK ACTIVE.

[0127] It should be noted that the two flip-flops in the arc-starting circuit module are the key to realizing the arc-starting system logic. After the main controller (MCU or FPGA) is initialized, it will set NO_CONFIG to a high level. At startup, only one pulse needs to be given in START_PRESPARK to complete the charging of the entire arc-starting circuit and release the arc-starting operation.

[0128] Please refer to this again. Figure 3 and in conjunction with references Figure 4 and Figure 8 In this embodiment, the transformer circuit module includes a first transformer T1 and a fourth peripheral circuit;

[0129] The first transformer T1 is connected to the arc-starting circuit module through the fourth peripheral circuit.

[0130] Please refer to this again. Figure 4 and Figure 8 In this embodiment, the fourth peripheral circuit includes a first resistor R1, a first capacitor C1, a first diode D1, a second capacitor C2, a third capacitor C3, a fourth resistor R4, a fifth resistor R5, a second diode D2, a second MOSFET Q2, a thirteenth resistor R13, a sixteenth resistor R16, a fourth diode D4, a third MOSFET Q3, a seventeenth resistor R17, a sampling resistor circuit, a third diode D3, a fifth capacitor C5, and a tenth resistor R10.

[0131] The first end of the first winding W1 on the primary side of the first transformer T1 is connected to the power supply VCC.

[0132] The first resistor R1 and the first capacitor C1 are connected in parallel. One end of the first resistor R1 is connected to the negative terminal of the first diode D1, and the other end is connected between the first end of the primary winding W1 of the first transformer T1 and the power supply VCC.

[0133] The positive terminal of the first diode D1 is connected to the end of the first winding W1 of the primary side of the first transformer T1;

[0134] The second capacitor C2 and the third capacitor C3 are both connected at one end between the first end of the first winding W1 of the primary side of the first transformer T1 and the power supply VCC, and the other end is grounded.

[0135] The drain of the second MOS transistor Q2 is connected to the end of the first winding W1 of the primary side of the first transformer T1. The source of the second MOS transistor Q2 is connected to the drain of the first MOS transistor Q1 through the seventeenth resistor R17. The gate of the second MOS transistor Q2 is connected to the OA terminal of the MOSFET driver U2 through the fifth resistor R5.

[0136] The positive terminal of the second diode D2 is connected between the gate of the second MOSFET Q2 and the fifth resistor R5, and the negative terminal of the second diode D2 is connected to one end of the fourth resistor R4.

[0137] The other end of the fourth resistor R4 is connected between the fifth resistor R5 and the OA terminal of the MOSFET driver U2;

[0138] The first end of the second winding W2 of the primary side of the first transformer T1 is grounded, and the end of the second winding W2 of the primary side of the first transformer T1 is connected to the drain of the third MOS transistor Q3 through the third diode D3 and the fifth capacitor C5.

[0139] The tenth resistor R10 is connected in parallel across the fifth capacitor C5;

[0140] The source of the third MOSFET Q3 is grounded, and the gate of the third MOSFET Q3 is connected to the OB terminal of the MOSFET driver U2 through the sixteenth resistor R16.

[0141] The positive terminal of the fourth diode D4 is connected between the gate of the third MOS transistor Q3 and the sixteenth resistor R16, and the negative terminal of the fourth diode D4 is connected to one end of the thirteenth resistor R13.

[0142] The other end of the thirteenth resistor R13 is connected between the sixteenth resistor R16 and the OB terminal of the MOSFET driver U2;

[0143] One end of the sampling resistor circuit is connected between the source of the second MOS transistor Q2 and the seventeenth resistor R17, and the other end is grounded;

[0144] The first end of the secondary winding W3 of the first transformer T1 is connected to PRESSPARK through the eighth resistor R8 and the fifth diode D5; the positive terminal of the fifth diode D5 is connected to the eighth resistor R8; the end of the secondary winding W3 of the first transformer T1 is grounded.

[0145] Please refer to this again. Figure 4 and Figure 8 In this embodiment, the sampling resistor circuit includes an eighteenth resistor R18, a nineteenth resistor R19, a twentieth resistor R20, and a twenty-first resistor R21.

[0146] The eighteenth resistor R18, the nineteenth resistor R19, the twentieth resistor R20, and the twenty-first resistor R21 are connected in parallel. One end of the parallel connection is between the source of the second MOS transistor Q2 and the seventeenth resistor R17, and the other end is grounded.

[0147] The detailed working process of this circuit is as follows:

[0148] NO_CONFIG is set to high level, so the R terminal of the first flip-flop U1A is high level. At this time, the O terminal of the first flip-flop U1A is low level, so the second MOSFET Q2 is turned off, and no current flows into the first transformer T1.

[0149] VOL_LEVEL has a defined analog voltage, such as 4.5V output through DA. Then the X terminal of the first voltage comparator U4A and the second voltage comparator U4B will have a corresponding voltage value.

[0150] START_PRESPARK is connected to the main controller. When preparing for arc ignition (pre-ignition), a rising edge will appear on START_PRESPARK. This rising edge will change the state of the O terminal of the first flip-flop U1A to a high level, turning on the second MOSFET Q2. The first transformer T1 enters the charging state, and the current in the first transformer T1 increases with time and is proportional to time. The current flowing through the first transformer T1 forms a voltage drop in the sampling resistor circuit composed of the eighteenth resistor R18, the nineteenth resistor R19, the twentieth resistor R20, and the twenty-first resistor R21 connected in parallel. Therefore, the current flowing through the first transformer T1 becomes a voltage value, which is sent to the Y terminal of the first voltage comparator U4A for comparison with the X terminal.

[0151] As time goes on, when the voltage at the Y terminal of the first voltage comparator U4A is greater than X, the output O of the first voltage comparator U4A flips, causing the R terminal of the first flip-flop U1A to go low. Therefore, the O terminal of the first flip-flop U1A will also flip, turning off the second MOSFET Q2 and stopping charging.

[0152] After the second MOSFET Q2 is turned off, the first transformer T1 begins to convert the stored energy to the auxiliary winding and secondary winding. At this time, the second primary winding W2 and the secondary winding W3 of the first transformer T1 will induce corresponding voltages. Because of the presence of the sixth diode D6, the source (S) terminal of the second flip-flop U1B is still at a high level, indicating that the output (O) terminal of the second flip-flop U1B is at a low level. Therefore, the second primary winding W2 of the first transformer T1 has no external energy release path, and the induced voltage in the secondary winding W3 will rise rapidly. At this time, two situations will occur:

[0153] A: If the breakdown fails due to excessive air gap or other reasons, but the negative high voltage has reached the set value, the second voltage comparator U4B will flip, causing a rising edge at the C1 input of the second flip-flop U1B. As a result, the O terminal of the second flip-flop U1B becomes high, turning on the third MOS transistor Q3. At this time, the energy stored in the first transformer T1 will be released through the second primary winding W2 of the first transformer T1, achieving the function described in point 3 of the above beneficial effects.

[0154] B: If a breakdown occurs before the protection operating voltage is reached (arc ignition successful), BREAK_DOWN will receive a pulse, causing the fourth MOSFET Q4 to conduct for a certain period. The conduction of the fourth MOSFET Q4 will cause the input S terminal of the second flip-flop U1B to go low. According to the logic table, this will also cause the O terminal of the second flip-flop U1B to output a high level, thereby turning on the third MOSFET Q3 and releasing energy. This achieves the internal function described in point 4 above.

[0155] When an arc ignition fails or succeeds, at the next start, with the pulse edge on the input C1 of the first flip-flop U1A, the output O of the second flip-flop U1B will be turned off, thereby turning off the third MOS transistor Q3.

[0156] The above is a brief description of the entire workflow, which may be a bit messy or complex. You can easily understand it by simply writing out the logic tables for the first flip-flop U1A and the second flip-flop U1B.

[0157] Although this application frequently uses terms such as first differential amplifier circuit module, second differential amplifier circuit module, arc ignition circuit module, and transformer circuit module, the possibility of using other terms is not excluded. These terms are used merely for the convenience of describing and explaining the essence of the invention; interpreting them as any additional limitation would contradict the spirit of the invention.

[0158] This invention provides an arc-starting circuit for an EFO (Electronic Optimizer), which uses closed-loop regulation to determine the energy input to the first transformer in the transformer circuit module, independent of time. It can use analog signals to control the amount of energy input to the first transformer T1 in the transformer circuit module, thereby controlling the output voltage. It has a protection function that automatically stops and releases energy if the specified voltage is reached without breakdown. It also has a function to quickly release excess energy after air breakdown.

[0159] In summary, after reading this detailed disclosure, those skilled in the art will understand that the foregoing detailed disclosure is presented by way of example only and is not restrictive. Although not explicitly stated herein, those skilled in the art will understand that this application is intended to encompass various reasonable changes, improvements, and modifications to the embodiments. These changes, improvements, and modifications are intended to be made by this application and are within the spirit and scope of the exemplary embodiments of this application.

[0160] Furthermore, certain terms used in this application have been used to describe embodiments of this application. For example, "an embodiment," "an embodiment," and / or "some embodiments" mean that a particular feature, structure, or characteristic described in connection with that embodiment may be included in at least one embodiment of this application. Therefore, it is to be emphasized and understood that two or more references to "an embodiment" or "an embodiment" or "an alternative embodiment" in various parts of this specification do not necessarily refer to the same embodiment. Moreover, specific features, structures, or characteristics may be appropriately combined in one or more embodiments of this application.

[0161] It should be understood that in the foregoing description of the embodiments of this application, various features are combined in a single embodiment, drawing, or description for the purpose of simplifying the understanding of a feature. However, this does not mean that the combination of these features is necessary, and those skilled in the art may extract some features as separate embodiments when reading this application. That is, the embodiments in this application can also be understood as an integration of multiple sub-embodiments. It is also valid when the content of each sub-embodiment contains fewer than all the features of a single foregoing disclosed embodiment.

[0162] Finally, it should be understood that the embodiments disclosed herein are illustrative of the principles of the embodiments of this application. Other modified embodiments are also within the scope of this application. Therefore, the embodiments disclosed herein are merely examples and not limitations. Those skilled in the art can adopt alternative configurations to implement the applications in this application based on the embodiments in this application. Therefore, the embodiments of this application are not limited to the embodiments precisely described in the application.

Claims

1. An arc-starting circuit for an EFO, characterized in that, It includes a first differential amplifier circuit module, a second differential amplifier circuit module, an arc-starting circuit module, and a transformer circuit module; among which, The first differential amplifier circuit module includes a first dual operational amplifier U3 and a first peripheral circuit; The first dual operational amplifier U3 is connected to the second differential amplifier circuit module and the arc-starting circuit module respectively through the first peripheral circuit; The second differential amplifier circuit module includes a second dual operational amplifier U5 and a second peripheral circuit with a twenty-ninth resistor R29; The second dual operational amplifier U5 is connected to the first differential amplifier circuit module and the arc-starting circuit module respectively through the second peripheral circuit; the non-inverting input terminal of the second dual operational amplifier U5 is connected to VOL_LEVEL through the twenty-ninth resistor R29. The arc-starting circuit module includes a first voltage comparator U4A, a second voltage comparator U4B, a first flip-flop U1A, a second flip-flop U1B, and a third peripheral circuit. The third peripheral circuit is connected to the first voltage comparator U4A, the second voltage comparator U4B, the first flip-flop U1A, the second flip-flop U1B, the first differential amplifier circuit module, the second differential amplifier circuit module, and the transformer circuit module, respectively. The transformer circuit module includes a first transformer T1 and a fourth peripheral circuit; The first transformer T1 is connected to the arc-starting circuit module through the fourth peripheral circuit; The third peripheral circuit includes the first MOSFET Q1, the sixth diode D6, the fourth MOSFET Q4, the twenty-third resistor R23, the thirty-second resistor R32, the eleventh capacitor C11, and the thirty-first resistor R31; The fourth peripheral circuit includes the fifth resistor R5, the second MOSFET Q2, the third MOSFET Q3, the sixteenth resistor R16, the seventeenth resistor R17, and a sampling resistor circuit; The 1D terminal of the first flip-flop U1A is connected to the power supply VCC, the C1 terminal of the first flip-flop U1A is connected to START_PRESPARK, and the O terminal of the first flip-flop U1A is connected to the INA terminal of the MOSFET driver U2. The R terminal of the first flip-flop U1A is connected to the R terminal of the second flip-flop U1B, and the R terminal of the first flip-flop U1A is connected to NO_CONFIG. The drain of the first MOSFET Q1 is connected to the Y terminal of the first voltage comparator U4A, and one end of the seventeenth resistor R17 is connected to the drain of the first MOSFET Q1 and the Y terminal of the first voltage comparator U4A at the same point. The source of the first MOSFET Q1 is grounded, and the gate of the first MOSFET Q1 is connected between the C1 terminal of the first flip-flop U1A and START_PRESPARK. The X terminal of the first voltage comparator U4A is connected to the first peripheral circuit of the first differential amplifier circuit module, the O terminal of the first voltage comparator U4A is connected to the R terminal of the first flip-flop U1A, and the O terminal of the first voltage comparator U4A is connected to the S terminal of the second flip-flop U1B through the sixth diode D6. The X terminal of the second voltage comparator U4B is connected to the output terminal of the second dual operational amplifier U5, the Y terminal of the second voltage comparator U4B is connected to PRESSPARK_LEVEL, and the O terminal of the second voltage comparator U4B is connected to the C1 terminal of the second flip-flop U1B. One end of the twenty-third resistor R23 is connected to the power supply VCC, and the other end is connected to the drain of the fourth MOSFET Q4. The source of the fourth MOSFET Q4 is grounded, and the gate of the fourth MOSFET Q4 is connected to BREAK DOWN through the thirty-first resistor R31; The thirty-second resistor R32 and the eleventh capacitor C11 are connected in parallel. One end is connected between the gate of the fourth MOSFET Q4 and the thirty-first resistor R31, and the other end is grounded. The drain of the fourth MOSFET Q4 is connected between the sixth diode D6 and the S terminal of the second flip-flop U1B. The 1D terminal of the second flip-flop U1B is connected to the power supply VCC, and the 0 terminal of the second flip-flop U1B is connected to the INB terminal of the MOSFET driver U2. The terminal connects to PRESSPARK ACTIVE; The first end of the first winding W1 on the primary side of the first transformer T1 is connected to the power supply VCC. The drain of the second MOSFET Q2 is connected to the end of the first winding W1 of the primary side of the first transformer T1. The source of the second MOSFET Q2 is connected to the drain of the first MOSFET Q1 through the seventeenth resistor R17. The gate of the second MOSFET Q2 is connected to the OA terminal of the MOSFET driver U2 through the fifth resistor R5. The first end of the second winding W2 on the primary side of the first transformer T1 is grounded, and the end of the second winding W2 on the primary side of the first transformer T1 is connected to the drain of the third MOSFET Q3. The source of the third MOSFET Q3 is grounded, and the gate of the third MOSFET Q3 is connected to the OB terminal of the MOSFET driver U2 through the sixteenth resistor R16. One end of the sampling resistor circuit is connected between the source of the second MOSFET Q2 and the seventeenth resistor R17, and the other end is grounded; The first end of the secondary winding W3 of the first transformer T1 is connected to PRESSARK; the end of the secondary winding W3 of the first transformer T1 is grounded.

2. The arc-starting circuit for EFO according to claim 1, characterized in that, The first peripheral circuit includes the fourth capacitor C4, the sixth resistor R6, the seventh resistor R7, the ninth resistor R9, the eleventh resistor R11, the twelfth resistor R12, the fourteenth resistor R14, the fifteenth resistor R15 and the sixth capacitor C6. The fourth capacitor C4 and the sixth resistor R6 are connected in parallel. One end of the connection is connected to the inverting input terminal of the first dual operational amplifier U3, and the other end is connected to the output terminal of the first dual operational amplifier U3. One end of the eleventh resistor R11 is connected to the output terminal of the first dual operational amplifier U3, and the other end is connected to the X terminal of the first voltage comparator U4A. One end of the ninth resistor R9 is connected to the inverting input of the first dual operational amplifier U3, and the other end is connected between VOL_LEVEL and the twenty-ninth resistor R29; The fifteenth resistor R15 and the sixth capacitor C6 are connected in parallel. One end of the connection is connected to the non-inverting input of the first dual operational amplifier U3, and the other end is grounded. One end of the seventh resistor R7 is connected to the reference voltage REF, and the other end is connected to one end of the fourteenth resistor R14; The other end of the fourteenth resistor R14 is grounded; One end of the twelfth resistor R12 is connected between the seventh resistor R7 and the fourteenth resistor R14, and the other end is connected between the fifteenth resistor R15 and the non-inverting input of the first dual operational amplifier U3.

3. The arc-starting circuit for EFO according to claim 2, characterized in that, The second peripheral circuit includes the eighth capacitor C8, the twenty-fourth resistor R24, the twenty-sixth resistor R26, the twenty-seventh resistor R27, the twenty-eighth resistor R28, the twenty-ninth resistor R29, the thirtieth resistor R30, and the tenth capacitor C10. The eighth capacitor C8 and the twenty-sixth resistor R26 are connected in parallel. One end of the connection is connected to the inverting input terminal of the second dual operational amplifier U5, and the other end is connected to the output terminal of the second dual operational amplifier U5. The output of the second dual operational amplifier U5 is connected to the X terminal of the second voltage comparator U4B; One end of the twenty-fourth resistor R24 ​​is connected to the reference voltage REF, and the other end is connected to the twenty-seventh resistor R27; The other end of the twenty-seventh resistor R27 is grounded; One end of the twenty-eighth resistor R28 is connected to the inverting input of the second dual operational amplifier U5, and the other end is connected between the twenty-fourth resistor R24 ​​and the twenty-seventh resistor R27. One end of the twenty-ninth resistor R29 is connected to the non-inverting input of the second dual operational amplifier U5, and the other end is connected to VOL_LEVEL; The thirtieth resistor R30 and the tenth capacitor C10 are connected in parallel. One end of the parallel connection is connected to the non-inverting input of the second dual operational amplifier U5, and the other end is grounded.

4. The arc-starting circuit for EFO according to claim 3, characterized in that, The third peripheral circuit also includes the twenty-fifth resistor R25, the ninth capacitor C9, the second resistor R2, and the third resistor R3; The twenty-fifth resistor R25 and the ninth capacitor C9 are connected in parallel. One end is connected to the power supply VCC, and the other end is connected between the O terminal of the second voltage comparator U4B and the C1 terminal of the second flip-flop U1B. One end of the second resistor R2 is connected to the power supply VCC, and the other end is connected to the R terminal of the first flip-flop U1A. One end of the third resistor R3 is connected to the power supply VCC, and the other end is connected to the S terminal of the first flip-flop U1A.

5. The arc-starting circuit for EFO according to claim 4, characterized in that, The fourth peripheral circuit also includes a first resistor R1, a first capacitor C1, a first diode D1, a second capacitor C2, a third capacitor C3, a fourth resistor R4, a second diode D2, a thirteenth resistor R13, a fourth diode D4, a third diode D3, a fifth capacitor C5, and a tenth resistor R10. The first resistor R1 and the first capacitor C1 are connected in parallel. One end of the first resistor R1 is connected to the negative terminal of the first diode D1, and the other end is connected between the beginning of the first winding W1 of the primary side of the first transformer T1 and the power supply VCC. The positive terminal of the first diode D1 is connected to the end of the first winding W1 of the primary side of the first transformer T1. The second capacitor C2 and the third capacitor C3 are both connected at one end between the first end of the first winding W1 of the primary side of the first transformer T1 and the power supply VCC, and the other end is grounded. The positive terminal of the second diode D2 is connected between the gate of the second MOSFET Q2 and the fifth resistor R5, and the negative terminal of the second diode D2 is connected to one end of the fourth resistor R4. The other end of the fourth resistor R4 is connected between the fifth resistor R5 and the OA terminal of the MOSFET driver U2; The end of the second winding W2 on the primary side of the first transformer T1 is connected to the drain of the third MOSFET Q3 through the third diode D3 and the fifth capacitor C5. The tenth resistor R10 is connected in parallel across the fifth capacitor C5; The positive terminal of the fourth diode D4 is connected between the gate of the third MOSFET Q3 and the sixteenth resistor R16, and the negative terminal of the fourth diode D4 is connected to one end of the thirteenth resistor R13. The other end of the thirteenth resistor R13 is connected between the sixteenth resistor R16 and the OB terminal of the MOSFET driver U2; The first end of the secondary winding W3 of the first transformer T1 is connected to PRESSPARK through the eighth resistor R8 and the fifth diode D5; the positive terminal of the fifth diode D5 is connected to the eighth resistor R8.

6. The arc-starting circuit for EFO according to claim 5, characterized in that, The sampling resistor circuit includes the eighteenth resistor R18, the nineteenth resistor R19, the twentieth resistor R20, and the twenty-first resistor R21; The eighteenth resistor R18, the nineteenth resistor R19, the twentieth resistor R20, and the twenty-first resistor R21 are connected in parallel. One end of the parallel connection is between the source of the second MOSFET Q2 and the seventeenth resistor R17, and the other end is grounded.

Images