An instruction analysis method and device, equipment and storage medium

Abstract

The present disclosure provides an instruction analysis method and device, equipment and a storage medium, the method comprising: disassembling a received first preset bit number signal into a plurality of third preset bit number vectors, and generating a fourth preset bit number vector corresponding to the plurality of third preset bit number vectors according to the plurality of third preset bit number vectors; dividing the plurality of third preset bit number vectors into a first vector group and a second vector group; generating a one-hot code corresponding to the first vector group according to a received second preset bit number vector, and sequentially placing valid vectors in the first vector group into an output vector in order according to the one-hot code and the fourth preset bit number vector; generating a logic operation vector corresponding to the second vector group according to the second preset bit number vector, and sequentially placing valid vectors in the second vector group into the output vector in order according to the logic operation vector and the fourth preset bit number vector, thereby solving the problem of a large path delay in the prior art.

Description

Technical Field

[0001] This disclosure relates to the field of processor core technology, and in particular to an instruction parsing method, apparatus, device, and storage medium. Background Technology

[0002] The processor core needs to break down the fetched instructions. High-performance processors typically require instructions with higher bit widths, and the circuitry for breaking down these instructions incurs significant latency. In processors with high performance requirements, this latency can lead to performance degradation. Summary of the Invention

[0003] In order to solve the above-mentioned technical problems, or at least partially solve the above-mentioned technical problems, embodiments of this disclosure provide an instruction parsing method, apparatus, device and storage medium.

[0004] In a first aspect, embodiments of this disclosure provide an instruction parsing method, including: The system receives an input first preset bit count signal and a second preset bit count vector. According to a preset rule, the first preset bit count signal is decomposed into multiple third preset bit count vectors. A fourth preset bit count vector is generated based on these multiple third preset bit count vectors. The number of third preset bits is less than the number of first preset bits. Both the second and fourth preset bit counts are the number of third preset bit count vectors. Each 1-bit vector in the second preset bit count vector indicates whether its corresponding third preset bit count vector is a valid signal. Each 1-bit vector in the fourth preset bit count vector indicates whether its corresponding third preset bit count vector is a fifth preset bit count instruction. Multiple third preset bit count vectors are divided into a first vector group and a second vector group, wherein the first vector group includes the least bit of the first preset bit count signal and the second vector group includes the most bit of the first preset bit count signal. For the first vector group, a one-hot code corresponding to the first vector group is generated according to the second preset bit number vector. According to the one-hot code and the fourth preset bit number vector, the valid vectors in the first vector group are placed into the output vector in sequence. For the second vector group, a logical operation vector corresponding to the second vector group is generated based on the second preset bit number vector and the fourth preset bit number vector. The valid vectors in the second vector group are then placed into the output vector in sequence according to the logical operation vector and the fourth preset bit number vector.

[0005] In one possible implementation, generating a one-hot code corresponding to the first vector group based on a second preset number of bits includes: Based on the second preset bit count vector, generate the first one-hot code of the first vector group; Based on the second preset bit count vector and the Nth one-hot code, generate the Nth intermediate vector. Based on the Nth intermediate vector, generate the (N+1)th one-hot code, until all one-hot codes of the first vector group are generated, where N is an integer greater than or equal to 1.

[0006] In one possible implementation, generating the first one-hot code of the first vector group based on the second preset bit count vector includes: In the second preset bit number vector from low to high bits, the first bit that is 1 is used as the first bit that is 1 in the first one-hot encoding.

[0007] In one possible implementation, the step of generating the Nth intermediate vector based on the second preset bit count vector and the Nth one-hot code, and generating the (N+1)th one-hot code based on the Nth intermediate vector, includes: Let M be the number of bits that are 1 in the Nth one-hot encoding; Set the first M bits of the second preset bit number vector from low to high to 0, and use them as the Nth intermediate vector; In the Nth intermediate vector, the first bit that is 1 is used as the bit that is 1 in the (N+1)th one-hot encoding.

[0008] In one possible implementation, the step of sequentially placing the valid vectors in the first vector group into the output vector according to one-hot encoding and a fourth preset number of bits includes: Obtain all one-hot encodings corresponding to the first vector group; The number of bits corresponding to the third preset number of bits in the one-hot encoding that are 1 are sequentially placed into the corresponding output vector according to a preset order. Among them, the third preset bit quantity vector placed in the output vector is determined based on the fourth preset bit quantity vector to determine whether it needs to be combined with the vector before it to form the fifth preset bit quantity instruction. When the current third preset bit number vector needs to be combined with the preceding vector to form the fifth preset bit number instruction, the high bits of the current third preset bit number vector are added to the preceding vector and then placed into the corresponding output vector. If the current third preset bit count vector does not need to be combined with the preceding vectors to form the fifth preset bit count instruction, the high bits of the current third preset bit count vector are padded with 0 and then placed into the corresponding output vector.

[0009] In one possible implementation, generating a logical operation vector corresponding to the second vector group based on the second preset bit count vector and the fourth preset bit count vector includes: Compare the values ​​of the corresponding bits in the second preset bit count vector and the fourth preset bit count vector; When the same bit in both the second preset bit count vector and the fourth preset bit count vector is 0, the current bit of the logical operation vector is 0, and the other bits of the logical operation vector are 1.

[0010] In one possible implementation, the step of sequentially placing the valid vectors in the second vector group into the output vector according to the logical operation vector and the fourth preset bit count vector includes: For the Pth segment output vector, if the sum of the first Q bits in the logical operation vector is P-1 and the value of the Q+1th bit is 1, then the Q+1th third preset bit number vector is placed into the Pth segment output vector. The order of the third preset bit number vector is obtained by sorting the bits from low to high.

[0011] Secondly, embodiments of this disclosure provide an instruction parsing apparatus, comprising: The generation module is used to receive the input first preset bit count signal and second preset bit count vector, decompose the first preset bit count signal into multiple third preset bit count vectors according to preset rules, and generate a corresponding fourth preset bit count vector based on the multiple third preset bit count vectors. The number of third preset bits is less than the number of first preset bits. The number of second preset bits and fourth preset bits are both the number of third preset bit count vectors. Each 1-bit vector in the second preset bit count vector is used to indicate whether the corresponding third preset bit count vector is a valid signal. Each 1-bit vector in the fourth preset bit count vector is used to indicate whether the corresponding third preset bit count vector is a fifth preset bit count instruction. The partitioning module is used to divide multiple third preset bit number vectors into a first vector group and a second vector group, wherein the first vector group includes the least bit of the first preset bit number signal and the second vector group includes the most bit of the first preset bit number signal. The first output module is used to generate a one-hot code corresponding to the first vector group based on the second preset number of bits vector, and to put the valid vectors in the first vector group into the output vector in sequence according to the one-hot code and the fourth preset number of bits vector. The second output module is used to generate a logical operation vector corresponding to the second vector group based on the second preset bit number vector and the fourth preset bit number vector, and to put the valid vectors in the second vector group into the output vector in sequence according to the logical operation vector and the fourth preset bit number vector.

[0012] Thirdly, embodiments of this disclosure provide an electronic device, including a processor, a communication interface, a memory, and a communication bus, wherein the processor, the communication interface, and the memory communicate with each other via the communication bus; Memory, used to store computer programs; The processor, when executing programs stored in memory, implements the instruction parsing method described above.

[0013] Fourthly, embodiments of this disclosure provide a computer-readable storage medium having a computer program stored thereon, characterized in that the computer program, when executed by a processor, implements the above-described instruction parsing method.

[0014] Compared with the prior art, the technical solutions provided in this disclosure have at least some or all of the following advantages: The instruction parsing method described in this embodiment receives an input first preset bit count signal and a second preset bit count vector. It decomposes the first preset bit count signal into multiple third preset bit count vectors according to preset rules, and generates a corresponding fourth preset bit count vector based on these vectors. The multiple third preset bit count vectors are divided into a first vector group and a second vector group, where the first vector group includes the least significant bit of the first preset bit count signal, and the second vector group includes the most significant bit of the first preset bit count signal. For the first vector group, a one-hot encoding corresponding to the first vector group is generated based on the second preset bit count vector. The valid vectors in the first vector group are then sequentially placed into the output vector according to the one-hot encoding and the fourth preset bit count vector. For the second vector group, a logical operation vector corresponding to the second vector group is generated based on the second preset bit count vector and the fourth preset bit count vector. The valid vectors in the second vector group are then sequentially placed into the output vector according to the logical operation vector and the fourth preset bit count vector. This method can solve the problem of large path delays in the prior art. Attached Figure Description

[0015] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure.

[0016] To more clearly illustrate the technical solutions in the embodiments of this disclosure or the prior art, the accompanying drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, those skilled in the art can obtain other drawings based on these drawings without creative effort.

[0017] Figure 1 This illustration schematically shows a flowchart of an instruction parsing method according to an embodiment of the present disclosure; Figure 2 A schematic diagram illustrating the disassembly vector of input instructions according to an embodiment of the present disclosure is shown. Figure 3 A schematic diagram illustrating a second preset bit count vector according to an embodiment of the present disclosure is shown. Figure 4 A schematic diagram illustrating a fourth preset bit count vector according to an embodiment of the present disclosure is shown. Figure 5 A schematic diagram of the output signal according to an embodiment of the present disclosure is shown; Figure 6 This schematically illustrates the vector placement of a first vector group into an output signal according to an embodiment of the present disclosure; Figure 7 This schematically illustrates the vector placement of a first vector group into an output signal according to another embodiment of the present disclosure; Figure 8 This schematically illustrates the effect of a fourth preset bit count vector on the output signal according to an embodiment of the present disclosure. Figure 9 This schematically illustrates a diagram where the fourth field of the output according to an embodiment of the present disclosure is derived from the fourth field of the input; Figure 10 This schematically illustrates that the fourth segment of the output according to an embodiment of the present disclosure originates from the sixth segment of the input; Figure 11 This schematically illustrates that the fifth segment of the output according to an embodiment of the present disclosure originates from the seventh segment of the input; Figure 12 A schematic block diagram of an instruction parsing apparatus according to an embodiment of the present disclosure is shown; and Figure 13 A schematic block diagram of an electronic device according to an embodiment of the present disclosure is shown. Detailed Implementation

[0018] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. Based on the embodiments of this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0019] See Figure 1 The embodiments of this disclosure provide an instruction parsing method, including: S1, receive the input first preset bit count signal and second preset bit count vector, decompose the first preset bit count signal into multiple third preset bit count vectors according to preset rules, and generate a corresponding fourth preset bit count vector based on the multiple third preset bit count vectors. The number of third preset bits is less than the number of first preset bits. The number of second preset bits and the number of fourth preset bits are both the number of third preset bit count vectors. Each 1-bit vector in the second preset bit count vector is used to indicate whether the corresponding third preset bit count vector is a valid signal. Each 1-bit vector in the fourth preset bit count vector is used to indicate whether the corresponding third preset bit count vector is a fifth preset bit count instruction.

[0020] In this embodiment, taking a first preset number of bits of 128 as an example, the input 128-bit signal is decomposed into a total of 8 signals, each with a bit width of 32 bits. The input 128-bit signal is named in_opcode, and the output signal is named pick_opcode. The in_opcode signal is divided into 8 16-bit vectors, as follows: Figure 2 As shown. It is divided into 7 segments, each 16 bits long. Segment 0 is the lowest 16 bits of in_opcode.

[0021] See Figure 2 The 0th segment is in_opcode[15:0], the 1st segment is in_opcode[31:16], the 3rd segment is in_opcode[47:32]... and the 7th segment is in_opcode[127:112].

[0022] In this embodiment, since the input 128-bit signal is decomposed into a total of 8 signals, the second preset bit count is 8. The vector representing the second preset bit count is named `opcode_mask`. This vector indicates which segments in the `in_opcode` vector are valid and which are invalid. This vector is as follows: Figure 3 As shown.

[0023] See Figure 3 The `in_opcode` vector is divided into 8 segments, and the `opcode_mask` also has 8 corresponding segments, each 1 bit. When the 1 bit in each segment is 1, the corresponding 16-bit segment in the `in_opcode` vector is valid; otherwise, the segment is invalid. That is, when `opcode_mask` is 11111111, then the data in segments 0, 1, 2, 3, 4, 5, 6, and 7 of the corresponding `in_opcode` is valid. When `opcode_mask` is 11111100, then the data in segments 2, 3, 4, 5, 6, and 7 of the corresponding `in_opcode` is valid. The data in segments 0 and 1 is invalid.

[0024] In this embodiment, since the input 128-bit signal is decomposed into a total of 8 signals, the fourth preset bit count is 8, and the vector representing the fourth preset bit count is named rv32_vec. Figure 4 As shown.

[0025] The rv32_vec vector is generated based on the data of the eight 16-bit segments of the in_opcode vector. When the second bit of the 16-bit data in each segment is 11, it is 0; otherwise, it is 1.

[0026] See Figure 4 When the second digit of the first segment of in_opcode is 11, that is, when in_opcode[1:0]=11, then rv32_vec[0]=0, otherwise it is 1.

[0027] And so on: When the second bit of the second segment of in_opcode is 11, that is, in_opcode[17:16]=11, rv32_vec[1]=0; in_opcode[17:16]≠11, rv32_vec[1]=1 When the second digit of the third segment of in_opcode is 11, that is, in_opcode[33:32]=11, rv32_vec[2]=0; in_opcode[33:32]≠11, rv32_vec[2]=1 When the second digit of the fourth segment of in_opcode is 11, that is, in_opcode[49:48]=11, rv32_vec[3]=0; in_opcode[49:48]≠11, rv32_vec[3]=1 … When the second bit in the 8th segment of in_opcode is 11, that is, in_opcode[113:112]=11, rv32_vec[7]=0; in_opcode[113:112]≠11, rv32_vec[7]=1 The rv32_vec vector indicates whether the current corresponding field is a 32-bit instruction. A value of 1 in the corresponding field indicates that the current in_opcode field is 32-bit and needs to be concatenated with the preceding in_opcode field.

[0028] In some embodiments, when rv32_vec is 00000101, it indicates that segments 0 and 1 of in_opcode need to be combined to form a 32-bit vector, and segments 2 and 3 need to be combined to form a 32-bit vector. The remaining segments remain 16-bit vectors.

[0029] In some embodiments, the output signal is as follows: Figure 5 As shown, it is also divided into 7 segments, but each segment is 32-bit. The output signal is named pick_opcode.

[0030] See Figure 5 The 0th segment is pick_opcode[31:0], the 1st segment is pick_opcode[63:32], the 2nd segment is pick_opcode[95:64], ..., the 7th segment is pick_opcode[255:224]. S2, divide the multiple third preset bit number vectors into a first vector group and a second vector group, wherein the first vector group includes the lowest bit of the first preset bit number signal and the second vector group includes the highest bit of the first preset bit number signal.

[0031] In this embodiment, when the multiple third preset bit number vectors can be 8 16-bit vectors, the first vector group can be the 0th to 3rd segments of in_opcode, the second vector group can be the 4th to 7th segments of in_opcode, or the first vector group can be the 0th to 2nd segments of in_opcode, the second vector group can be the 3rd to 7th segments of in_opcode, and so on.

[0032] S3. For the first vector group, generate a one-hot code corresponding to the first vector group according to the second preset bit number vector. Then, according to the one-hot code and the fourth preset bit number vector, put the valid vectors in the first vector group into the output vector in sequence.

[0033] In this embodiment, the opcode_mask vector is first examined to determine which segments of the in_opcode vector are valid and which are invalid. Then, the rv32_vec vector is examined to determine which segments need to be merged with the preceding fields into a 32-bit field. Finally, the valid fields are sequentially placed into the output vector.

[0034] In some embodiments, taking the first vector group as the 0th to 3rd segments of in_opcode as an example, opcode_mask = 11111111, rv32_vec = 00000000. This indicates that segments 0 to 3 in the first vector group are all valid, and these fields do not need to be merged with the fields preceding them. Therefore, the 0th segment of the in_opcode vector is placed into the 0th field of the output signal pick_opcode, and so on. Figure 6 As shown.

[0035] In some embodiments, taking the first vector group as the 0th to 3rd segments of in_opcode as an example, opcode_mask = 11111100, rv32_vec = 00000000. This indicates that the 3rd and 2nd segments in the first vector group are valid, and these fields do not need to be merged with the preceding fields. Therefore, the 2nd segment of the in_opcode vector is placed into the 0th segment of the output signal pick_opcode. Figure 7 As shown.

[0036] However, since each field of `in_opcode` is 16-bit, while each segment of `pick_opcode` is 32-bit, and there is no 32-bit merging in this example, it is necessary to pad the valid segment of `in_opcode` with zeros. That is, 16 bits of zeros are added to the valid segment of `in_opcode` to form 32 bits of data. For example, if the second segment of `in_opcode` is valid, then 16 bits of zeros are placed before the `in_opcode` field, and then placed into the 0th segment of `pick_opcode`.

[0037] In some embodiments, taking the first vector group as the 0th to 3rd segments of in_opcode as an example, opcode_mask = 11111100, rv32_vec = 01010000, this indicates that the 3rd and 2nd segments in the first vector group are valid. However, unlike the example above, the 4th and 6th segments need to be concatenated with the preceding fields to form a 32-bit field. Figure 8 As shown.

[0038] In this embodiment, the step of generating a one-hot code corresponding to the first vector group based on the second preset number of bits includes: Based on the second preset bit count vector, generate the first one-hot code of the first vector group; Based on the second preset bit count vector and the Nth one-hot code, generate the Nth intermediate vector. Based on the Nth intermediate vector, generate the (N+1)th one-hot code, until all one-hot codes of the first vector group are generated, where N is an integer greater than or equal to 1.

[0039] In this embodiment, generating the first one-hot code of the first vector group based on the second preset bit count vector includes: In the second preset bit number vector from low to high bits, the first bit that is 1 is used as the first bit that is 1 in the first one-hot encoding.

[0040] In this embodiment, the step of generating the Nth intermediate vector based on the second preset bit count vector and the Nth one-hot code, and generating the (N+1)th one-hot code based on the Nth intermediate vector, includes: Let M be the number of bits that are 1 in the Nth one-hot encoding; Set the first M bits of the second preset bit number vector from low to high to 0, and use them as the Nth intermediate vector; In the Nth intermediate vector, the first bit that is 1 is used as the bit that is 1 in the (N+1)th one-hot encoding.

[0041] In this embodiment, the step of sequentially placing the valid vectors in the first vector group into the output vector according to one-hot encoding and the fourth preset number of bits includes: Obtain all one-hot encodings corresponding to the first vector group; The number of bits corresponding to the third preset number of bits in the one-hot encoding that are 1 are sequentially placed into the corresponding output vector according to a preset order. Among them, the third preset bit quantity vector placed in the output vector is determined based on the fourth preset bit quantity vector to determine whether it needs to be combined with the vector before it to form the fifth preset bit quantity instruction. When the current third preset bit number vector needs to be combined with the preceding vector to form the fifth preset bit number instruction, the high bits of the current third preset bit number vector are added to the preceding vector and then placed into the corresponding output vector. If the current third preset bit count vector does not need to be combined with the preceding vectors to form the fifth preset bit count instruction, the high bits of the current third preset bit count vector are padded with 0 and then placed into the corresponding output vector.

[0042] In this embodiment, taking the first vector group as the 0th to 3rd segments of in_opcode as an example, opcode_mask = 11111111, rv32_vec = 00000000. The one-hot encoding of the first vector group is generated based on opcode_mask, which means splitting opcode_mask. Each one-hot encoding is 8 bits, and only one bit is allowed to be valid in each one-hot encoding; that is, each one-hot encoding contains only one 1, and the rest are 0.

[0043] Generate the first one-hot code lead1_vec0: 00000001, and then generate the intermediate vector 11111110, which is equivalent to removing the first 1 from the opcode_mask vector.

[0044] Generate the second onehot encoding lead1_vec1: 00000010, then generate the intermediate vector 11111100, and remove the second 1.

[0045] Generate the third one-hot encoding lead1_vec2: 00000100, then generate the intermediate vector 11111000, and remove the third 1.

[0046] Generate the fourth one-hot encoding lead1_vec3: 00001000, then generate the intermediate vector 11110000, and remove the fourth 1.

[0047] The first vector corresponds to segment 0 of the output signal pick_opcode, the second vector corresponds to segment 1 of the output signal pick_opcode, and so on. When a bit in a vector is 1, the value of in_opcode at the corresponding bit position is placed into the output field of that vector.

[0048] In the above example, lead1_vec0 is 00000001, and the position of 1 is the 0th segment. Since it starts from 0, it is 0. Therefore, the data in the 0th segment of the in_opcode vector is padded with 16 bits of 0 and then placed into the 0th field of the output signal pick_opcode vector.

[0049] If lead1_vec1 is 00000010, the position 1 corresponds to the first segment. Therefore, the data of the first segment in the in_opcode vector is padded with 16 bits of 0 and then placed into the first segment of the output signal pick_opcode vector.

[0050] If lead1_vec2 is 00000100, and the position of 1 corresponds to the second segment, then the high-order bits of the second segment data in the in_opcode vector are padded with 16 bits of 0 and then placed into the second segment of the output signal pick_opcode vector. For example... Figure 6 .

[0051] S4. For the second vector group, generate a logical operation vector corresponding to the second vector group based on the second preset bit number vector and the fourth preset bit number vector. Then, according to the logical operation vector and the fourth preset bit number vector, put the valid vectors in the second vector group into the output vector in sequence.

[0052] In this embodiment, step S4, generating a logical operation vector corresponding to the second vector group based on the second preset bit count vector and the fourth preset bit count vector, includes: Compare the values ​​of the corresponding bits in the second preset bit count vector and the fourth preset bit count vector; When the same bit in both the second preset bit count vector and the fourth preset bit count vector is 0, the current bit of the logical operation vector is 0, and the other bits of the logical operation vector are 1.

[0053] In this embodiment, the step of sequentially placing the valid vectors in the second vector group into the output vector according to the logical operation vector and the fourth preset bit count vector includes: For the Pth segment output vector, if the sum of the first Q bits in the logical operation vector is P-1 and the value of the Q+1th bit is 1, then the Q+1th third preset bit number vector is placed into the Pth segment output vector. The order of the third preset bit number vector is obtained by sorting the bits from low to high.

[0054] Taking the second vector group as an example where the 5th to 7th segments of in_opcode, for segments 4, 5, 6, and 7, the opcode_mask method is no longer used. Instead, an additional vector mask_real is generated based on the opcode_mask and the rv32_vec vector. opcode_mask = 11111111, rv32_vec = 00000000.

[0055] This indicates that each segment of in_opcode is valid and there are no 32-bit instructions, so the corresponding mask_real is also 11111111.

[0056] opcode_mask = 11111111, rv32_vec = 01010000.

[0057] This indicates that each segment of in_opcode is valid, and there are two 32-bit instructions, namely the 4th and 6th segments, so the corresponding mask_real is also 11111111.

[0058] The fourth segment of the output signal is selected through the following steps: First, add up the first four, five, six, and seven segments of the mask_real vector to calculate their sums. Then, select the segment based on the calculation results. For example, if the first four segments of the mask_real vector are 4 and the fourth segment of mask_real is 1, then the fourth segment of the output signal comes from the fourth segment of the input signal. Otherwise, if the first five segments of the mask_real vector are 4 and the fifth segment of mask_real is 1, then the fourth segment of the output signal comes from the fifth segment of the input signal, and so on.

[0059] In some embodiments, opcode_mask = 11111111, rv32_vec = 00000000, mask_real = 11111111. There are a total of 8 valid mask_real values. The generated lead1_vec will output the first 4, that is, the first 4 segments from segment 0 to segment 3. To determine which field of the input vector the output 4th segment comes from, it is necessary to check which of the first 4, 5, 6, and 7 segments of the mask_real vector sums to 4, and whether the corresponding 4th field is valid. It can be seen that the first 4 fields of mask_real sum to 4, and the 4th field of opcode_mask is valid. Therefore, the output 4th field comes from the 4th field of the input. Figure 9 .

[0060] In some embodiments, opcode_mask = 11111100, rv32_vec = 00000000, mask_real = 11111100. There are a total of 6 valid mask_real values. The first 4 outputs are selected by lead1_vec. The 0th to 3rd segments of the output are derived from the 2nd to 5th segments of the input signal, as shown below. Figure 7 Then there are two more to output. At this point, we need to determine which of the first 4, 5, 6, and 7 segments of the `mask_real` vector adds up to 4. According to the calculation, the first 6 segments of `mask_real` add up to 4, and the 6th segment of `opcode_mask` is 1, which is valid. Therefore, the 4th segment of the output comes from the 6th segment of the input. Figure 10 Similarly, the first 7 segments of mask_real add up to 5, and the 7th segment of opcode_mask is 1, which is valid. Therefore, the 5th segment of the output comes from the 7th segment of the input, as shown below. Figure 11 .

[0061] See Figure 12 The embodiments of this disclosure provide an instruction parsing apparatus, including: The generation module 11 is used to receive the input first preset bit number signal and second preset bit number vector, decompose the first preset bit number signal into multiple third preset bit number vectors according to preset rules, and generate a corresponding fourth preset bit number vector based on the multiple third preset bit number vectors. The number of third preset bits is less than the number of first preset bits. The number of second preset bits and the number of fourth preset bits are both the number of third preset bit number vectors. Each 1-bit vector in the second preset bit number vector is used to indicate whether the corresponding third preset bit number vector is a valid signal. Each 1-bit vector in the fourth preset bit number vector is used to indicate whether the corresponding third preset bit number vector is a fifth preset bit number instruction. The partitioning module 12 is used to divide multiple third preset bit number vectors into a first vector group and a second vector group, wherein the first vector group includes the least bit of the first preset bit number signal and the second vector group includes the most bit of the first preset bit number signal. The first output module 13 is used to generate a one-hot code corresponding to the first vector group according to the second preset number of bits vector, and to put the valid vectors in the first vector group into the output vector in sequence according to the one-hot code and the fourth preset number of bits vector. The second output module 14 is used to generate a logical operation vector corresponding to the second vector group based on the second preset bit number vector and the fourth preset bit number vector, and to put the valid vectors in the second vector group into the output vector in sequence according to the logical operation vector and the fourth preset bit number vector.

[0062] The specific implementation process of the functions and roles of each unit in the above device can be found in the implementation process of the corresponding steps in the above method, and will not be repeated here.

[0063] For the device embodiments, since they basically correspond to the method embodiments, the relevant parts can be referred to in the description of the method embodiments. The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of the present invention according to actual needs. Those skilled in the art can understand and implement this without creative effort.

[0064] In the above embodiments, any and more of the generation module 11, partitioning module 12, first output module 13, and second output module 14 can be combined into one module, or any one of these modules can be split into multiple modules. Alternatively, at least part of the functionality of one or more of these modules can be combined with at least part of the functionality of other modules and implemented in one module. At least one of the generation module 11, partitioning module 12, first output module 13, and second output module 14 can be at least partially implemented as hardware circuitry, such as a field-programmable gate array (FPGA), a programmable logic array (PLA), a system-on-a-chip, a system-on-a-substrate, a system-on-package, an application-specific integrated circuit (ASIC), or implemented in hardware or firmware by any other reasonable means of integrating or packaging the circuitry, or implemented in software, hardware, or firmware, or in any appropriate combination of any of these three implementation methods. Alternatively, at least one of the generation module 11, partitioning module 12, first output module 13, and second output module 14 can be at least partially implemented as a computer program module, which can perform corresponding functions when the computer program module is run.

[0065] See Figure 13 The electronic device provided in the embodiments of this disclosure includes a processor 1110, a communication interface 1120, a memory 1130 and a communication bus 1140, wherein the processor 1110, the communication interface 1120 and the memory 1130 communicate with each other through the communication bus 1140. Memory 1130 is used to store computer programs; When processor 1110 executes a program stored in memory 1130, it implements the following instruction parsing method: The system receives an input first preset bit count signal and a second preset bit count vector. According to a preset rule, the first preset bit count signal is decomposed into multiple third preset bit count vectors. A fourth preset bit count vector is generated based on these multiple third preset bit count vectors. The number of third preset bits is less than the number of first preset bits. Both the second and fourth preset bit counts are the number of third preset bit count vectors. Each 1-bit vector in the second preset bit count vector indicates whether its corresponding third preset bit count vector is a valid signal. Each 1-bit vector in the fourth preset bit count vector indicates whether its corresponding third preset bit count vector is a fifth preset bit count instruction. Multiple third preset bit count vectors are divided into a first vector group and a second vector group, wherein the first vector group includes the least bit of the first preset bit count signal and the second vector group includes the most bit of the first preset bit count signal. For the first vector group, a one-hot code corresponding to the first vector group is generated according to the second preset bit number vector. According to the one-hot code and the fourth preset bit number vector, the valid vectors in the first vector group are placed into the output vector in sequence. For the second vector group, a logical operation vector corresponding to the second vector group is generated based on the second preset bit number vector and the fourth preset bit number vector. The valid vectors in the second vector group are then placed into the output vector in sequence according to the logical operation vector and the fourth preset bit number vector.

[0066] The aforementioned communication bus 1140 can be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. This communication bus 1140 can be divided into an address bus, a data bus, a control bus, etc. For ease of illustration, it is represented by only one thick line in the figure, but this does not indicate that there is only one bus or one type of bus.

[0067] The communication interface 1120 is used for communication between the above-mentioned electronic device and other devices.

[0068] The memory 1130 may include random access memory (RAM) or non-volatile memory, such as at least one disk storage device. Optionally, the memory 1130 may also be at least one storage device located remotely from the aforementioned processor 1110.

[0069] The processor 1110 mentioned above can be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), etc.; it can also be a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components.

[0070] Embodiments of this disclosure also provide a computer-readable storage medium. The computer-readable storage medium stores a computer program that, when executed by a processor, implements the end-to-end speech spoofing emotion detection method based on the original audio waveform as described above.

[0071] The computer-readable storage medium may be included in the device / apparatus described in the above embodiments; or it may exist independently and not assembled into the device / apparatus. The computer-readable storage medium carries one or more programs that, when executed, implement the end-to-end voice spoofing emotion detection method based on the original audio waveform according to the embodiments of this disclosure.

[0072] According to embodiments of this disclosure, the computer-readable storage medium can be a non-volatile computer-readable storage medium, such as including, but not limited to: portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof. In this disclosure, the computer-readable storage medium can be any tangible medium that contains or stores a program that can be used by or in conjunction with an instruction execution system, apparatus, or device.

[0073] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0074] The above description is merely a specific embodiment of this disclosure, enabling those skilled in the art to understand or implement it. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this disclosure. Therefore, this disclosure is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features claimed herein.

Claims

1. An instruction parsing method, characterized in that, The method includes: The system receives an input first preset bit count signal and a second preset bit count vector. According to a preset rule, the first preset bit count signal is decomposed into multiple third preset bit count vectors. A fourth preset bit count vector is generated based on these multiple third preset bit count vectors. The number of third preset bits is less than the number of first preset bits. Both the second and fourth preset bit counts are the number of third preset bit count vectors. Each 1-bit vector in the second preset bit count vector indicates whether its corresponding third preset bit count vector is a valid signal. Each 1-bit vector in the fourth preset bit count vector indicates whether its corresponding third preset bit count vector is a fifth preset bit count instruction. Multiple third preset bit count vectors are divided into a first vector group and a second vector group, wherein the first vector group includes the least bit of the first preset bit count signal and the second vector group includes the most bit of the first preset bit count signal. For the first vector group, a one-hot code corresponding to the first vector group is generated according to the second preset bit number vector. According to the one-hot code and the fourth preset bit number vector, the valid vectors in the first vector group are placed into the output vector in sequence. For the second vector group, a logical operation vector corresponding to the second vector group is generated based on the second preset bit number vector and the fourth preset bit number vector. The valid vectors in the second vector group are then placed into the output vector in sequence according to the logical operation vector and the fourth preset bit number vector.

2. The method according to claim 1, characterized in that, The step of generating a one-hot code corresponding to the first vector group based on the second preset number of bits includes: Based on the second preset bit count vector, generate the first one-hot code of the first vector group; Based on the second preset bit count vector and the Nth one-hot code, generate the Nth intermediate vector. Based on the Nth intermediate vector, generate the (N+1)th one-hot code, until all one-hot codes of the first vector group are generated, where N is an integer greater than or equal to 1.

3. The method according to claim 2, characterized in that, The step of generating the first one-hot code of the first vector group based on the second preset bit number vector includes: In the second preset bit number vector from low to high bits, the first bit that is 1 is used as the first bit that is 1 in the first one-hot encoding.

4. The method according to claim 2, characterized in that, The step of generating the Nth intermediate vector based on the second preset bit count vector and the Nth one-hot code, and generating the (N+1)th one-hot code based on the Nth intermediate vector, includes: Let M be the number of bits that are 1 in the Nth one-hot encoding; Set the first M bits of the second preset bit number vector from low to high to 0, and use them as the Nth intermediate vector; In the Nth intermediate vector, the first bit that is 1 is used as the bit that is 1 in the (N+1)th one-hot encoding.

5. The method according to claim 2, characterized in that, The step of sequentially placing the valid vectors in the first vector group into the output vector according to one-hot encoding and the fourth preset number of bits includes: Obtain all one-hot encodings corresponding to the first vector group; The number of bits corresponding to the third preset number of bits in the one-hot encoding that are 1 are sequentially placed into the corresponding output vector according to a preset order. Among them, the third preset bit count vector placed in the output vector is determined based on the fourth preset bit count vector to determine whether it needs to be combined with the vector before it to form the fifth preset bit count instruction. When the current third preset bit number vector needs to be combined with the preceding vector to form the fifth preset bit number instruction, the high bits of the current third preset bit number vector are added to the preceding vector and then placed into the corresponding output vector. If the current third preset bit count vector does not need to be combined with the preceding vectors to form the fifth preset bit count instruction, the high bits of the current third preset bit count vector are padded with 0 and then placed into the corresponding output vector.

6. The method according to claim 1, characterized in that, The step of generating a logical operation vector corresponding to the second vector group based on the second preset bit count vector and the fourth preset bit count vector includes: Compare the values ​​of corresponding bits in the second preset bit count vector and the fourth preset bit count vector; When the same bit in both the second preset bit count vector and the fourth preset bit count vector is 0, the current bit of the logical operation vector is 0, and the other bits of the logical operation vector are 1.

7. The method according to claim 6, characterized in that, The step of sequentially placing the valid vectors in the second vector group into the output vector according to the logical operation vector and the fourth preset bit count vector includes: For the Pth segment output vector, if the sum of the first Q bits in the logical operation vector is P-1 and the value of the Q+1th bit is 1, then the Q+1th third preset bit number vector is placed into the Pth segment output vector. The order of the third preset bit number vector is obtained by sorting the bits from low to high.

8. An instruction parsing device, characterized in that, include: The generation module is used to receive the input first preset bit count signal and second preset bit count vector, decompose the first preset bit count signal into multiple third preset bit count vectors according to preset rules, and generate a corresponding fourth preset bit count vector based on the multiple third preset bit count vectors. The number of third preset bits is less than the number of first preset bits. The number of second preset bits and fourth preset bits are both the number of third preset bit count vectors. Each 1-bit vector in the second preset bit count vector is used to indicate whether the corresponding third preset bit count vector is a valid signal. Each 1-bit vector in the fourth preset bit count vector is used to indicate whether the corresponding third preset bit count vector is a fifth preset bit count instruction. The partitioning module is used to divide multiple third preset bit number vectors into a first vector group and a second vector group, wherein the first vector group includes the least bit of the first preset bit number signal and the second vector group includes the most bit of the first preset bit number signal. The first output module is used to generate a one-hot code corresponding to the first vector group based on the second preset number of bits vector, and to put the valid vectors in the first vector group into the output vector in sequence according to the one-hot code and the fourth preset number of bits vector. The second output module is used to generate a logical operation vector corresponding to the second vector group based on the second preset bit number vector and the fourth preset bit number vector, and to put the valid vectors in the second vector group into the output vector in sequence according to the logical operation vector and the fourth preset bit number vector.

9. An electronic device, characterized in that, It includes a processor, a communication interface, a memory, and a communication bus, wherein the processor, the communication interface, and the memory communicate with each other through the communication bus; Memory, used to store computer programs; A processor, when executing a program stored in memory, implements the instruction parsing method according to any one of claims 1-7.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the instruction parsing method according to any one of claims 1-7.

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