Multiline data prefetching using dynamic prefetch depth

Abstract

This application relates to multi-line data prefetching using dynamic prefetch depth. A system for prefetching data for a processor is disclosed, including a processor core, a memory configured to store information for use by the processor core, a cache memory configured to fetch and store information from the memory, and a prefetch circuit. The prefetch circuit can be configured to issue a multi-cluster prefetch request to retrieve information from the memory using a predicted address for storage in the cache memory. The multi-cluster prefetch request can include a depth value indicating a number of fetch clusters to retrieve. The prefetch circuit can also be configured to generate an accuracy value based on a cache hit rate of prefetched information over a particular time interval, and modify the depth value based on the accuracy value.

Description

[0001] This application is a divisional application of invention patent application 201880056109.3, filed on August 13, 2018, entitled "Multi-row data prefetching using dynamic prefetch depth". Technical Field

[0002] The embodiments disclosed herein generally relate to processors, and more specifically, to the implementation of a data prefetching system. Background Technology

[0003] To improve execution performance, the processor may include prefetch circuitry for one or more cache memories to reduce memory access time; this prefetch circuitry is also referred to herein as a prefetcher. A prefetcher for a given cache can predict upcoming requests from that cache and thus read data from a lower-level cache or system memory—that is, fetch data before the core requests data. The prefetcher can track memory access patterns corresponding to one of the multiple software processes running in the processing core. Using these patterns, the prefetcher can then read data before the cache requests data.

[0004] In some cases, applications running on a processor may access data in a stream-like pattern, where they access many contiguous addresses, but not in a continuous sequence. Prefetching large amounts of data when encountering such a pattern can improve cache efficiency until an exception to that contiguous memory address is accessed. Summary of the Invention

[0005] Various embodiments of a system for prefetching data for a processor may include a processor core, memory configured to store information for use by the processor core, a cache memory configured to fetch and store information from memory, and prefetch circuitry. The prefetch circuitry may be configured to issue multi-group prefetch requests to retrieve information from memory using predicted addresses for storage in the cache memory. The multi-group prefetch request may include a depth value indicating the number of prefetch clusters to be retrieved. The prefetch circuitry may also be configured to generate an accuracy value based on the cache hit rate of information prefetched within a specific time interval, and to modify the depth value based on that accuracy value.

[0006] In one embodiment, to modify the depth value, the prefetch circuit can also be configured to increase the depth value in response to determining that the accuracy value meets an upper threshold, and to decrease the depth value in response to determining that the accuracy value meets a lower threshold. In another embodiment, to increase the depth value, the prefetch circuit can also be configured to maintain the current depth value in response to determining that the current depth value is equal to the maximum permissible depth value.

[0007] In another embodiment, to reduce the depth value, the prefetch circuit may also be configured to suspend issuing prefetch requests for at least the next time interval in response to determining that the current depth value is equal to the minimum allowed depth value. In another embodiment, to generate an accuracy value, the prefetch circuit may also be configured to track a first value within a specific time interval, the first value indicating the amount of information stored in cache memory in response to one or more prefetch requests. The prefetch circuit may also be configured to track a second value within that specific time interval, the second value indicating the number of cache hits for cache lines including information stored in cache memory in response to at least one prefetch request.

[0008] In another embodiment, the prefetch circuit may also be configured to determine an accuracy value based on a weighted moving average of a first value, a second value, and the total amount of information stored in response to one or more prefetch requests. In one embodiment, to issue multiple cluster prefetch requests, the prefetch circuit may also be configured to issue multiple single-cluster prefetch requests, wherein the number of single-cluster prefetch requests is based on a depth value. Attached Figure Description

[0009] The following detailed description refers to the accompanying drawings, which will now be briefly described.

[0010] Figure 1 This is a block diagram of an embodiment of the memory subsystem in the illustrated processor.

[0011] Figure 2 A block diagram of an embodiment of a memory prefetch subsystem in a processor is shown.

[0012] Figure 3 An example of a data table associated with a cache and an accuracy monitor is described.

[0013] Figure 4 An example of a data table associated with the processor memory subsystem is illustrated.

[0014] Figure 5 This includes an operational timeline for an embodiment of a memory prefetch subsystem in a processor.

[0015] Figure 6 A flowchart is depicted illustrating an embodiment of a method for performing multi-cluster prefetch requests based on a determined accuracy.

[0016] Figure 7 The illustration shows a flowchart of another embodiment of a method for performing a multi-cluster prefetch request based on a determined accuracy.

[0017] Figure 8A flowchart illustrating an embodiment of a method for determining the accuracy of a memory prefetch subsystem is shown.

[0018] Figure 9 A block diagram illustrating an embodiment of a multi-core processor is provided.

[0019] While this disclosure may have various modifications and alternatives, specific embodiments thereof are illustrated by way of example in the accompanying drawings and will be described in detail herein. However, it should be understood that the drawings and their detailed description are not intended to limit this disclosure to the specific forms shown, but rather are intended to cover all modifications, equivalents, and alternatives falling within the spirit and scope of this disclosure as defined by the appended claims. The headings used herein are for organizational purposes only and are not intended to limit the scope of this specification. As used throughout this application, the word “may” is used in a permissible sense (i.e., meaning possible) rather than in a mandatory sense (i.e., must). Similarly, the words “comprising” or “including” mean, but are not limited to, those included in the present invention. Detailed Implementation

[0020] Generally speaking, a processor core (or simply "core") refers to a processor unit that can execute program instructions and process data independently of other processor cores within the processor, allowing multiple cores to execute instructions simultaneously. The performance of a processor core can be affected by several factors, including but not limited to the processor clock speed, the number of cores in the processor, the amount of cache memory (or simply "cache") in the processor, and the size of the cache.

[0021] In some computing systems, prefetchers can be utilized. As used herein, a "prefetcher" refers to circuitry configured to fetch one or more instructions before an execution unit or other processing circuitry in a processor core requests them. When used in conjunction with a cache, a prefetcher can improve the flow of information to the processor by predicting which memory addresses a particular software process (also referred to herein as a "processing thread") might access and reading information from those addresses before the processor issues a request for those addresses. If the prefetcher has accurately predicted the processor's data needs, then the requested information can be available to the processor with little or no delay in response to a memory request from the processor. As used herein, "information" refers to instructions and / or data values ​​used by the processor or other processing logic in a computing system.

[0022] Data can be fetched from various memories by any of the various requesters. Each core in a multi-core processor can generate memory requests from a fetch unit or prefetcher. Some caches that can be shared between two or more cores may include fetch circuitry and prefetchers. The effectiveness of a prefetcher can be based at least in part on the ability of the prefetch circuitry to identify patterns in memory accesses by processing threads and to correctly predict when that pattern will be repeated. For example, if a large media file is being played, some processing threads may access memory in large, contiguous blocks of addresses. In this case, prefetching information in larger prefetch clusters (i.e., a set of contiguous memory addresses to be prefetched) can improve the efficiency of memory access resources, thereby improving the performance of the computing system.

[0023] However, if the processing thread accesses memory outside these contiguous addresses, some of the information requested by the prefetcher will not be utilized. This situation can be called a prefetch address misprediction or a prefetch miss.

[0024] Various embodiments of prefetchers and methods for managing prefetch operations are discussed in this disclosure. The embodiments illustrated in the accompanying drawings and described below provide techniques for managing the size of memory prefetch operations in a computing system, which can reduce the occurrence of erroneous predictions by the prefetcher.

[0025] Figure 1 The diagram illustrates a block diagram of an embodiment of the computing system. The computing system 100 includes a processor core 101 coupled to a cache memory 102. The cache memory 102 is also coupled to a memory 103 and a prefetch circuit 104.

[0026] Processor core 101 can be configured to execute instructions and process data according to a specific instruction set architecture (ISA). In various embodiments, processor core 101 can be configured to implement any suitable ISA, such as, for example, V9, x86 or Furthermore, in some embodiments, processor core 101 may be configured to execute multiple threads simultaneously (referred to herein as "multithreaded"), wherein each thread may include a set of instructions that can be executed independently of instructions from another thread. Although a single processor core 101 is illustrated, in other embodiments, it is contemplated that any suitable number of cores may be included within the processor, and each such core may be multithreaded.

[0027] Cache memory 102 may reside within processor core 101 or may reside between processor core 101 and other memories. In one embodiment, cache memory 102 may be configured to temporarily store, or “cache”, instructions and data for use by processor core 101. Cache memory 102 may correspond to any of various levels of cache memory, such as, for example, L1, L2, and L3. For example, one embodiment of the processor may include an L1 cache within processor core 101, while an L2 cache may be represented by cache memory 102, and an L3 cache may be included as part of memory 103. In a multi-core processor, each core may have one or more L1 cache memories and may share one or more L2 and / or L3 cache memories. In various embodiments, cache memory 102 may be implemented using set-associative or direct-mapped techniques.

[0028] Note that entries in cache memory 102 can be referred to as cache lines. Each cache line in cache memory 102 may include the data being stored, a flag corresponding to a consistency state, and an address tag. A cache tag may include all or part of the original address of the data being stored in the cache line, an index indicating which cache line the cached data is stored in, and an offset indicating the location of the specific data in each cache line. A given processor core can access the cache using direct addresses of memory locations, lookup table-based translations, or addresses computed using instruction-based address patterns.

[0029] In the illustrated embodiment, memory 103 includes system memory for storing information that can be used by processor core 101, including active software such as applications or operating systems being executed by processor core 101. In some embodiments, memory 103 may also include reserved locations for storing information in L2 and / or L3 caches. In some embodiments, memory 103 may include one or more memory interfaces for accessing one or more types of system memory included on an integrated circuit (IC) separate from the integrated circuit (IC) including processor core 101. Such memory interfaces may be configured to manage data transfers between cache memory 102 and memory 103 in response to cache fetch requests. Memory 103 may include any suitable type of memory, such as fully buffered dual in-line memory modules (FB-DIMM), dual data rate synchronous dynamic random access memory (DDR / DDR2 / DDR3 / DDR4 SDRAM), or reduced latency dynamic random access memory (RLDRAM).

[0030] In the illustrated embodiment, prefetch circuitry 104 uses predicted addresses to generate memory prefetch requests to populate one or more cache lines in cache memory 102 with information (i.e., data and / or instructions) to be used by processor core 101. In systems with more than one level of cache memory, prefetch circuitry 104 may generate memory prefetch requests for a single cache memory (such as, for example, L2 cache). In some embodiments, multiple prefetch circuits may be included, each generating a memory request for a specific cache memory. Prefetch circuitry 104 may generate memory prefetch requests that result in information being retrieved from higher-level caches. For example, if prefetch circuitry 104 generates prefetch requests for L2 caches, these prefetch requests may be sent to L3 caches. As used herein, “higher” caches or “higher” memories refer to caches and memories that are further away from processor core 101, and “lower” caches refer to the opposite. For example, system memory is above L3 cache, and L2 cache is below L3 cache. If a specific prefetch request misses in the L3 cache, the L3 cache generates a memory fetch request to retrieve the requested information from the system memory contained in memory 103. As used herein, a cache "hit" means a request for information from a cache memory that currently stores the requested information, while a cache "miss" means that the cache memory does not currently store the requested information and therefore the information must be retrieved from a higher-level cache or system memory. Furthermore, as used herein, "cache hit rate" can refer to the number of cache hits occurring within a specific time interval.

[0031] A successful prefetch request allows cache memory 102 to receive information before processor core 101 requests it, thus allowing processor core 101 to execute instructions without waiting for memory access to return the requested information. In some cases, the information retrieved in response to a prefetch request (i.e., the "prefetched information") may not have arrived at cache memory 102 before processor core 101 is ready to use it; however, prefetching can still reduce the time from when processor core 101 is ready for the information to when the information becomes available. Incorrect address prediction can cause prefetch requests to fail. Address prediction is based on observations of address patterns used for memory access over time. If processor core 101 deviates from this pattern, or if the pattern is incorrectly identified, incorrect prediction can occur, causing information to be retrieved when it is not currently needed. Incorrect prediction can negatively impact performance by unnecessarily consuming processor resources and replacing useful information in the cache.

[0032] In some cases, prefetch circuitry 104 may issue “multi-row” or “multi-cluster” prefetch requests. As used herein, “fetch group” refers to a memory location retrieved in a single prefetch operation. In some embodiments, a fetch group may correspond to information to fill a cache line of cache memory 102. In this case, “fetch line” and “fetch group” may be used interchangeably. In other cases, a fetch group may not correspond to a cache line size but may contain less or more information than is stored in a given cache line. As used herein, a “multi-cluster” prefetch request refers to a single prefetch request that results in multiple prefetch operations for retrieving multiple consecutively addressed fetch groups. In the illustrated embodiment, to issue a multi-cluster prefetch request, prefetch circuitry 104 stores a depth value in a memory location or register. This depth value corresponds to the number of fetch groups that can be prefetched with a single multi-cluster prefetch request. For example, if the depth value currently has a value of four, then prefetch circuitry 104 may issue a multi-cluster prefetch request to retrieve information from four fetch groups with consecutive fetch addresses. In various embodiments, consecutive addresses may be in ascending or descending order of address values.

[0033] In the illustrated embodiment, the prefetch circuit 104 also includes a circuitry for monitoring the accuracy of the prefetcher. Using this monitoring circuitry, the prefetch circuit 104 can adjust the depth value. The accuracy monitor tracks the usage of information cached as a result of prefetch requests. If the prefetched information is used frequently, the corresponding accuracy of the prefetch circuit 104 is high, and the depth value can be increased to utilize the current accuracy of the prefetch circuit 104 by retrieving more information in each multi-cluster prefetch request. Conversely, if less prefetched information is used, the corresponding accuracy may be lower, and the depth value will decrease accordingly. Additional details corresponding to multi-cluster prefetch adjustments are given below.

[0034] Note that, Figure 1 This is merely an example. The illustrated embodiments include components relevant to the disclosed concepts. In other embodiments, additional components may be included. For example, other embodiments may include several levels of cache memory and / or multiple processor cores.

[0035] Go to Figure 2 A block diagram of an embodiment of a memory prefetch subsystem in a processor IC is shown. The memory subsystem 200 includes a cache memory 202 and a prefetch circuit 204. Furthermore, a fetch pipeline 216 is coupled to the cache memory 202 and the prefetch circuit 204. In some embodiments, the fetch pipeline 216 may be included as part of the cache memory 202 or as a separate circuit coupled to the cache memory 202. This may correspond to... Figure 1The prefetch circuit 204 of the prefetch circuit 104 includes various sub-circuits, such as a depth adjuster 210, a prefetch generator 212, and an accuracy monitor 214. In other embodiments, the depth adjuster 210, the prefetch generator 212, and the accuracy monitor 214 may be coupled to the prefetch circuit 204, rather than being included within the prefetch circuit 204.

[0036] In the illustrated embodiment, the fetch pipeline 216 includes hardware resources for fetching information from higher-level memory and populating cache lines in cache memory 202. In response to information from processor cores (such as, for example, ...) Figure 1 A cache miss in cache memory 202 caused by a memory request from processor core 101 causes fetch pipe 216 to request the missed information from higher memory (i.e., higher-level cache, system memory, or non-volatile memory). Similarly, in the illustrated embodiment, prefetch circuitry 204 may utilize fetch pipe 216 to issue a prefetch request to populate cache memory 202 with information that has been predicted to be accessed by processor core 101.

[0037] In the illustrated embodiment, prefetch generator 212 issues prefetch requests based on predicted addresses to populate cache lines in cache memory 202. Prefetch generator 212 can issue single-cluster prefetch requests or multi-cluster prefetch requests. To issue a multi-cluster prefetch request, prefetch generator 212 issues multiple single-cluster requests to fetch pipeline 216. The number of single-cluster prefetch requests corresponds to the depth value at which the multi-cluster prefetch request is initiated. Prefetch generator 212 may include registers for tracking the multiple single-cluster fetch requests issued for a particular multi-cluster prefetch request. Furthermore, prefetch generator 212 may include a queue in which the multiple single-cluster prefetch requests are stored until they are issued to fetch pipeline 216.

[0038] In the illustrated embodiment, the memory subsystem 200 includes an accuracy monitor 214. The accuracy monitor 214 includes circuitry for monitoring cache lines prefetched into cache memory 202 due to prefetch requests issued by prefetch circuitry 204. The accuracy monitor 214 may increment two count values. A first count value corresponds to a total value and is incremented for each cache line fetched by prefetch circuitry 204. A second count value corresponds to a used count value and is incremented when one of these prefetched cache lines is accessed by lower memory (e.g., L1 cache or fetch unit in processor core 101). The accuracy monitor 214 increments both count values ​​over a specific time interval. At the end of the specific time interval, the accuracy monitor 214 uses these two count values ​​to determine a value indicative of the accuracy of the prefetch request generated by prefetch circuitry 204. For example, the accuracy monitor 214 may generate an accuracy ratio by dividing the used count value by the total value. In some embodiments, the accuracy monitor 214 may additionally multiply the quotient by a predetermined value to generate a result having values ​​within a specific range. The accuracy value can then be sent to the depth adjuster 210. The accuracy monitor 214 can clear both count values ​​and restart incrementing each value as described during the next time interval.

[0039] In some embodiments, the accuracy monitor 214 can track moving averages of the total value and the used count value. In such embodiments, at the end of a specific time interval, the current total value and the current used value can each be added to their respective running averages. For example, at the end of a specific time interval, both the current total value and the average total value can be divided by 2 (e.g., shifted right by one bit for each binary value) and then added together to generate a new average total value. Such a running average can make the average total value more biased towards the most recent total value while maintaining some influence on older total values. A similar process can be used to generate an average used count value using the current used count value. After determining the average total value and the average used count value, the current total value and the current used count value can be cleared for the next time interval, while the newly determined average count value maintains its current value into the next time interval. These average count values ​​can then be used to determine an accuracy value, for example, using the process described above for accuracy ratios.

[0040] In the illustrated embodiment, depth adjuster 210 receives an accuracy value and determines, based on the accuracy value, whether to adjust the depth value for the next time interval. Depth adjuster 210 compares the received accuracy value with an upper threshold and a lower threshold. If the accuracy value is higher than the upper threshold, depth adjuster 210 can increment the depth value to increase the number of acquire clusters retrieved with each multi-cluster prefetch request. By prefetching more acquire clusters in a single multi-cluster request, the efficiency of memory subsystem 200 can be improved during periods when active processing threads are accessing large amounts of continuous data. Conversely, if the accuracy value is lower than the lower threshold, depth adjuster 210 can decrement the depth value to reduce the number of acquire clusters retrieved with each multi-cluster prefetch request. By prefetching fewer acquire clusters in a single multi-cluster request, prefetch error prediction in memory subsystem 200 can be reduced during periods when active processing threads are requesting non-contiguous memory access.

[0041] To identify cache lines that have been prefetched in cache memory 202, these prefetched cache lines can be marked while they are stored in cache memory 202. For example, a cache line may include one or more bits (referred to herein as a “prefetch identifier” or “prefetch ID”) that are set to a specific value after a prefetch occurs to indicate that the cache line has been fetched in response to a prefetch request issued by prefetch circuitry 204, or otherwise reset to an alternative value. When an identified prefetched cache line is used, the prefetch ID can be reset in addition to incrementing the current used count. By resetting the prefetch ID after the first use of the corresponding cache line, each prefetched cache line can be counted once when determining the accuracy value. Otherwise, if a software process being executed by processor core 101 repeatedly accesses the address associated with a particular cache line, the current used count may be incremented for each access. This could potentially generate a high accuracy value even if no other prefetched cache lines are used. Counting each prefetched cache line only once can improve the usefulness of the accuracy value. Note that if a prefetched cache line is used and then evicted (i.e., removed) and then prefetched again, the prefetch ID will be set after the second prefetch operation.

[0042] It should also be noted that, Figure 2 The system described is merely an example, and the functional circuitry is limited to highlighting the functionality of the memory prefetch system. In other embodiments, additional and / or different functional circuitry may be included.

[0043] Other operating details of the accuracy monitor are in Figure 3 The diagram below illustrates an example of a data table associated with a cache and an accuracy monitor. In the illustrated embodiment, processor core 301 may correspond to... Figure 1 The image shows processor core 101 and a portion of the instruction pipeline within the core. Cache memory 302 depicts a logical representation of how data is organized within a cache memory (such as, for example, cache memory 102 or 202). Accuracy monitor 314 shows four values ​​that can be tracked by accuracy monitoring circuitry (such as accuracy monitor 214).

[0044] Cache memory 302 can correspond to any suitable cache memory in the processing system. In the illustrated embodiment, cache memory 302 corresponds to an L1 cache memory coupled to a prefetch circuit, such as, for example... Figure 2 The cache memory 302 can be organized into multiple cache lines as indicated by lines _0 to _6, each line including cached information and flags. Each line can hold any suitable number of bytes of information corresponding to a series of memory addresses. In the illustrated embodiment, four pieces of information are shown for each cache line, but any suitable number can be used in other embodiments. The cached information includes information retrieved in response to a prefetch request from the prefetch circuit 204, and information retrieved by the fetch circuit in the cache memory 302. Each cache line includes information about that cache line, including a bit to indicate whether the corresponding cache line was retrieved by the fetch circuit in the cache memory 302 (represented herein by the value "0") or by the prefetch circuit 204 (represented herein by the value "1"). The cache line may include additional flags, as well as a tag that includes a reference to the original address of the information in system memory. The additional flags may include consistency data and / or the type of information stored, such as instructions or data, associated with other memory where the same information may be stored. For clarity, this additional information is not shown in Figure 3 middle.

[0045] When the software program is executed, the processor core 301 can retrieve chip information from the cache memory 302. As shown in the figure, the processor core 301 retrieves item D2 from line _0, item D5 from line _1, item D8 from line _2, and item D12 from line _3. As indicated by the flags of each cache line, lines _0 and _3 are fetched by the fetch circuitry of the cache memory 302, while lines _1 and _2 are fetched by the prefetch circuitry 204.

[0046] In the illustrated embodiment, accuracy monitor 314 functions as described above for accuracy monitor 214. Accuracy monitor 314 tracks four values: current total count, average total count, current used count, and average used count. In some embodiments, the current total count and current used count can be implemented as corresponding counter circuits. In the illustrated example, it is assumed that cache lines 0 through 6 have been fetched within the current time interval. Four of the fetched cache lines in this current time interval have been fetched by prefetch circuit 204, including lines 1, 2, 4, and 5. The remaining cache lines have been fetched by the fetch circuit of cache memory 302. In the current time interval, information from two of the prefetched cache lines (lines 1 and 2) has been used by processor core 301. Note that the flag indicating that lines 1 and 2 were prefetched is... Figure 3 The value is kept set to "1". As shown in the figure, after the accuracy monitor 314 increments the current used value to "2", the flag values ​​of the two used prefetched cache lines will be reset to "0".

[0047] As shown, the values ​​of the average total count and the average used count can reflect the values ​​after a previous time interval has ended. At the end of the current time interval, the accuracy monitor 314 determines new values ​​for both the average total count and the average used count based on the values ​​of the current total count and the current used count at the end of that time interval. In one embodiment, if the values ​​shown reflect the count values ​​at the end of that time interval, the accuracy monitor 314 determines a new average count value by dividing each value by 2 and then adding the current total count (i.e., "2") that has been divided to the average count (i.e., "1") that has been divided to set a new average total count ("3"). A new average used count can be determined similarly, resulting in a new average used count "1". The accuracy monitor 314 can then use these new values ​​to determine an accuracy value. In one embodiment, the accuracy monitor 314 divides the new average used count ("1") by the new average total count ("3") to obtain an accuracy value of 0.3333. This value can be multiplied by an appropriate value to generate an integer value, such as multiplying by 100 to generate an accuracy value of 33 or multiplying by 1000 to generate an accuracy value of 333. In the illustrated embodiment, this accuracy value is sent to other circuits (such as, for example, Figure 2 The depth adjuster 210 in the middle determines whether the depth value should be adjusted in the next time interval.

[0048] Note that, Figure 3 The table shown is merely an example. In other embodiments, additional information (such as related address information) may be included in cache memory 302. Figure 3The table is not intended to represent the physical arrangement of data stored in cache memory or other circuitry, but rather to illustrate only the logical organization of the data.

[0049] Go to Figure 4 It describes the relationship with the processor memory subsystem (such as, for example, Figure 2 The memory subsystem 400 (400) includes an additional data table associated with it. The memory subsystem 400 includes a cache memory 402, a memory 403, a depth regulator 410, and a prefetch generator 412. The cache memory 402 and memory 403 each describe the logical representation of how data is organized within the cache memory and system memory, respectively. The depth regulator 410 includes four values: a depth value and a maximum depth (each an integer value), and an upper threshold and a lower threshold (each a percentage value). The prefetch generator 412 includes six entries in the processing queue, as well as the current address and the current count value.

[0050] In the illustrated embodiment, prefetch generator 412 generates and issues prefetch requests to populate cache lines in cache memory 402. In some embodiments, prefetch generator 412 corresponds to Figure 2 The prefetch generator 212 is thus able to generate multi-cluster prefetch requests. In this example, one fetch cluster corresponds to one row of cache memory 402, and the prefetch generator 412 generates six multi-cluster prefetch commands, each with an address and depth value, and stores them in a processing queue, with the earliest request located on the left side of the queue.

[0051] To generate the first multi-cluster prefetch request, the prefetch generator reads a depth value from the depth regulator 410 when generating the request. In this example, the earliest request in the processing queue includes address "A0" and a depth value "3", which corresponds to the depth value at the time the request was generated. To process the request, the prefetch generator 412 copies the address value into the current address register and copies the depth value into the current count value. In the illustrated embodiment, the prefetch generator 412 issues a single-cluster prefetch request to the fetch circuitry (such as, for example, fetch pipe 216) in cache memory 402. This single-cluster prefetch request is issued using the current address. In response to issuing the single-cluster prefetch request, the prefetch generator 412 increments the current address by a value corresponding to the size of the fetch cluster, which in this example is a cache line, i.e., 4 address locations. The prefetch generator 412 also decrements the current count value. When the current count value reaches "0", the multi-cluster prefetch request has been completed, and the next multi-cluster prefetch request is processed.

[0052] exist Figure 4In the example, a multi-cluster prefetch request with address "A24" is being processed. The current address is A28, which reflects that a second single-cluster prefetch request has been issued to cache memory 402, and cache line _7 is being filled with the corresponding data. The count value is "0", indicating that the last single-cluster prefetch request is being executed for the current multi-cluster prefetch request, and the prefetch generator 412 can move to the next request with address value "A32". By issuing multi-cluster prefetch requests in this way, the number of cache lines in cache memory 402 that can be filled by prefetch requests in the processing queue can be increased. In this example, the six requests shown in the processing queue can fill 14 cache lines. If these six multi-cluster prefetch requests were replaced with single-cluster prefetch requests, then these six requests could only fill six cache lines. By issuing multi-cluster prefetch requests for information stored in contiguous addresses, the accessed memory (memory 403 in this example) can also be able to provide data in a more timely manner.

[0053] Note that the depth value decreases from three to two between generating the request with address "A12" and the request with address "A24". The prefetch generator 412 receives an accuracy value corresponding to less than 30% of the total prefetched cache lines being used within a specific time interval. In response, when the accuracy falls below a lower threshold, the depth value is reduced to limit the number of prefetches issued by the prefetch generator 412. If, in a subsequent time interval, the accuracy value rises above an upper threshold, the depth value can be increased. As previously described, in some embodiments, the accuracy value may remain below the lower threshold or above the upper threshold for two or more consecutive time intervals before the depth value is adjusted. If the accuracy value remains high, the depth adjuster 410 can continue to increase the depth value until a maximum value is reached. The maximum value corresponds to the maximum allowed value of the depth value. The depth value can be limited to a maximum value for various reasons, such as to prevent prefetch requests from overloading memory fetch resources (such as, for example, fetch pipeline 216). Furthermore, if the depth value is set too high, the risk of prefetch misprediction may increase.

[0054] In some embodiments, the depth adjuster 410 may further include a minimum permissible depth value. If the current depth value is at the minimum permissible depth value and the accuracy value is below a lower threshold, the prefetch request can be paused instead of continuing to decrease the depth value. Such a pause can last for a predetermined number of time intervals. In the illustrated embodiment, the minimum permissible depth value can be fixed to "1" such that if the depth value decreases to "0", the prefetch request is paused.

[0055] Note that, Figure 4 The table is just an example. Figure 4The tables shown are intended to illustrate the logical organization of data, not the physical arrangement of data stored in associated circuitry. In other embodiments, additional information, such as associated address information, may be included in cache memory 402. The amount of actual data stored in any of the tables shown may be greater than [amount missing]. Figure 4 The amount of data shown in the figure.

[0056] Progressing to Figure 5 This illustrates an operational timeline for an embodiment of a processor memory prefetch system. Timeline 500 can be applied to various applications. Figure 1 and Figure 2 An embodiment of the computing system 100 or memory subsystem 200 is shown. In the illustrated embodiment, timeline 500 includes five time intervals; time intervals 521 to 525. These time intervals may correspond to the time intervals discussed above. (See reference...) Figure 2 The memory subsystem 200 and Figure 5 Timeline 500 begins with a time interval of 521.

[0057] During time interval 521, prefetch circuit 204 is active, and the accuracy of prefetch requests from prefetch circuit 204 is monitored by accuracy monitor 214. The depth value is currently set to 2. At the end of time interval 521, accuracy monitor 214 sends a newly determined accuracy value to depth adjuster 210. In the illustrated embodiment, depth adjuster 210 determines that the accuracy value meets an upper accuracy threshold and, in response, increments the depth value from two to three.

[0058] During time interval 522, accuracy monitor 214 continues to operate, while prefetch circuit 204 can continue to issue prefetch requests. At the end of time interval 522, accuracy monitor 214 sends a new accuracy value to depth adjuster 210. In the current example, depth adjuster determines that the accuracy value meets the lower accuracy threshold and, in response, decrements the depth value back to the value two. The operation of accuracy monitor 214 in time intervals 523 and 524 can be the same as its operation in time interval 522, and depth adjuster 210 can decrease the depth value from two to one at the end of time interval 523, and then decrease it again to the value zero at the end of time interval 524. The decrease in accuracy during time intervals 522 to 524 may be due to a change in the operation of the currently executing processing thread. For example, the processing thread may transition from reading a large file to performing different tasks that access different memory locations, resulting in a decrease in the accuracy of prefetch requests from prefetch circuit 204. By monitoring the accuracy of the prefetch operation, the depth adjuster 210 can increase the depth value during periods of high accuracy, resulting in higher efficiency of the memory subsystem, and can also react to changes in the operation of the processing thread and decrease the depth value during periods of low accuracy, resulting in fewer prefetch error predictions.

[0059] In some embodiments, the accuracy value may need to meet an upper or lower threshold for two or more consecutive time intervals before the depth adjuster 210 modifies the depth value. In the illustrated embodiment, meeting the threshold within one time interval is sufficient to change the depth value.

[0060] Note that, Figure 5 The timelines are examples used to illustrate the concepts disclosed. Although time intervals are shown as similar lengths, the amount of time within any given time interval may vary based on the data being monitored. For example, if accuracy values ​​vary significantly between consecutive time intervals, the length of future time intervals may be shortened until the accuracy values ​​are more consistent across the intervals.

[0061] Turn now Figure 6 The diagram depicts a flowchart of an embodiment of a method for performing multi-cluster prefetch requests based on a determined accuracy. In various embodiments, method 600 can be applied to a memory subsystem, such as, for example... Figure 2 The memory subsystem 200 is included. (Common Reference) Figure 2 and Figure 6 Method 600 begins in box 601.

[0062] A multi-cluster prefetch request is generated (box 602). The prefetch generator 212 generates a multi-cluster prefetch request that includes an address value and a current depth value, the current depth value corresponding to the number of clusters to be processed for the request. Each multi-cluster prefetch request can be stored in a processing queue, such as a first-in-first-out (FIFO) queue. In the illustrated embodiment, the prefetch generator 212 initializes an address register based on the corresponding address value and a count value based on the stored depth value. The prefetch generator 212 continues to issue a series of single-cluster prefetch requests to the fetch pipeline 216 to execute the multi-cluster prefetch request, thereby decrementing the count value for each single-cluster prefetch request issued. After the count value reaches zero, the multi-cluster prefetch request is considered complete, and the next prefetch request in the processing queue can be processed.

[0063] An accuracy value is generated (box 603). Accuracy monitor 214 determines the accuracy value over a specific time interval. During this specific time interval, in the illustrated embodiment, accuracy monitor 214 tracks a total value and a used value, the total value corresponding to the number of fetch clusters retrieved in response to a prefetch request, and the used value corresponding to the number of cache line hits in cache memory 202 that were filled in response to a prefetch request. By using these values, accuracy monitor 214 determines the accuracy value for the prefetch request. The following is about... Figure 8 Additional details regarding the determination of accuracy values ​​are presented.

[0064] Further operations may depend on the accuracy value (box 604). In the illustrated embodiment, the accuracy value is sent to depth adjuster 210. Depth adjuster 210 compares the received accuracy value with one or more thresholds. In one embodiment, an upper threshold and a lower threshold are used for these comparisons. If at least one threshold is met, for example, if the accuracy value is less than the lower threshold or greater than the upper threshold, the method moves to box 605 to adjust the depth value. Otherwise, the method returns to box 602 to generate another multi-cluster prefetch request.

[0065] The depth value is adjusted based on the accuracy value (box 605). In the illustrated embodiment, the depth adjuster 210 modifies the depth value if at least one threshold is met. For example, if the accuracy value is greater than an upper threshold, the depth value can be increased, allowing more information to be acquired in the next multi-cluster prefetch request. Conversely, if the accuracy value is less than a lower threshold, the depth value can be decreased, reducing the amount of information acquired for the next multi-cluster prefetch request. Additional details for adjusting the depth value are described below. Figure 7 The method can return to box 602 to generate another prefetch request.

[0066] Note that, Figure 6Method 600 is an example. Figure 6 The operations shown are depicted as being performed sequentially. However, in other embodiments, some operations may be performed in parallel or in a different order. For example, blocks 602 and 603 may be performed in parallel. In some embodiments, additional operations may be included.

[0067] Now go to Figure 7 The illustration shows a flowchart of another embodiment of a method for performing a multi-cluster prefetch request based on a determined accuracy. Method 700 is similar to... Figure 6 Method 600, but with additional details regarding the adjustment of the depth value. Similar to Method 600, Method 700 can be applied to memory subsystems, such as, for example... Figure 2 The memory subsystem 200 is included. (Common Reference) Figure 2 and Figure 7 Method 700 begins in box 701.

[0068] In the illustrated embodiment, a multi-cluster prefetch request and an accuracy value are generated (box 702). Similar to method 600, method 700 begins with prefetch generator 212 generating a multi-cluster prefetch request with corresponding address and depth values ​​and storing the request in a processing queue. As prefetch generator 212 creates the multi-cluster prefetch request, accuracy monitor 214 tracks the total and used values ​​associated with the prefetch request. Accuracy monitor 214 tracks the total and used values ​​over a specific time interval. This time interval may correspond to tens of processor cycles or thousands of processor cycles or more. In some embodiments, prefetch generator 212 may generate tens, thousands, or more prefetch requests within this specific time interval. At the end of this time interval, as described in box 603 for method 600, accuracy monitor 214 determines an accuracy value based on the tracked total and used values.

[0069] Further operation of the method may depend on the accuracy value and an upper threshold (box 703). In the illustrated embodiment, the depth adjuster 210 receives the determined accuracy value from the accuracy monitor 214 and compares that value with the upper threshold. If the accuracy value meets the upper threshold, for example, if the accuracy value is greater than or equal to the upper threshold, the method moves to box 704 to determine whether the current depth value is set to its maximum value. Otherwise, the method moves to box 706 to determine whether the accuracy value meets a lower threshold.

[0070] If the accuracy value meets the upper threshold, further action may depend on the current value of the depth value (box 704). In the illustrated embodiment, the depth adjuster 210 compares the current depth value with the maximum value. If the current depth value is equal to the maximum value, or in some embodiments exceeds the maximum value, the method returns to box 702 without adjusting the current depth value. Otherwise, the method moves to box 705 to increase the depth value.

[0071] In response to determining that the accuracy value meets the upper limit threshold and the current depth value is lower than the maximum depth value, the depth value is incremented (box 705). If the current depth value is not already set to the maximum value, and the accuracy value indicates that the current accuracy of the prefetch generator 212 meets the upper limit threshold, then in the illustrated embodiment, the current depth value is incremented. In some embodiments, the depth value may be incremented by one, while in other embodiments, any suitable increment may be used. The method then returns to box 702 to generate the next prefetch request using the new depth value.

[0072] If the accuracy value does not meet the upper threshold in box 703, subsequent operations may depend on the value of the lower threshold (box 706). In the illustrated embodiment, if the upper threshold is not met, the depth adjuster 210 compares the accuracy value with the lower threshold. If the lower threshold is met, for example, if the accuracy value is less than or equal to the lower threshold, the method moves to box 707 to determine whether the current depth value is set to the minimum. Otherwise, the method returns to box 702 to generate another prefetch request.

[0073] If the lower threshold is met, subsequent operations of method 700 may depend on the current value of the depth value (box 707). In one embodiment, depth adjuster 210 compares the current depth value with a minimum depth value. If the current depth value is equal to or, in some embodiments, less than the minimum depth value, prefetching can be paused for the next time interval by disabling prefetch generator 212. The minimum value can be set to any suitable value, such as, for example, one. If the depth value is higher than the minimum value, the method moves to box 708 to decrement the depth value. Otherwise, the method moves to box 709 to pause the prefetch request.

[0074] If the current accuracy value meets the lower threshold and the current depth value is greater than the minimum value, the depth value is reduced (box 708). Depth adjuster 210 decrements the depth value by an appropriate amount, such as one or two. The method returns to box 702 to generate the next prefetch request using the new depth value.

[0075] If the current accuracy value meets the lower threshold and the current depth value is less than or equal to the minimum value, prefetching is paused (box 709). Prefetch generator 212 pauses the generation of new prefetch requests in the next time interval. In some embodiments, depth adjuster 210 may assert a pause signal, which may cause prefetch generator 212 to pause the generation of new prefetch requests. In other embodiments, depth adjuster 210 may set the depth value to a specific value to indicate a pause in new prefetch requests. For example, depth adjuster 210 may set the depth value to zero to indicate a pause. Logic in prefetch generator 212 may recognize this zero value and stop generating new requests until the depth value is greater than zero. At the end of the next time interval after the pause in prefetching requests, or in other embodiments, two or more time intervals after the pause, depth adjuster 210 may indicate the resumption of prefetching requests. In various embodiments, depth adjuster 210 may indicate resumption by de-asserting the pause signal or by setting the depth value to a value greater than zero. Depth adjuster 210 can reset the depth value to any suitable value for resuming the prefetch request, such as, for example, one, two, four, etc. This method ends at box 710.

[0076] Note that, Figure 7 The method shown is merely an example embodiment. Although in Figure 7 The operations illustrated in the method are depicted as being performed sequentially, but in other embodiments, some operations may be performed in parallel or in a different order. For example, in some embodiments, the operation of block 708 may be performed before the operation of block 707. In some embodiments, additional operations may be included.

[0077] Now go to Figure 8 A flowchart of a method for determining the accuracy of a memory prefetch subsystem is shown. Method 800 can be performed by an accuracy monitor (such as, for example, accuracy monitor 214). In some embodiments, method 800 can correspond to... Figure 6 and Figure 7 The operations performed in block 603 of method 600 or block 702 of method 700. In other embodiments, method 800 may be executed in parallel with method 600 or method 700. (See Common References) Figure 2 and Figure 8 The flowchart in the diagram shows that the method can begin in box 801.

[0078] In response to issuing a prefetch request, a first count value is incremented (box 802). In the illustrated embodiment, when the prefetch generator 212 issues a prefetch request to the fetch pipeline 216 to fill one or more cache lines in cache memory 202, the accuracy monitor 214 increments the current total value. In some embodiments, the accuracy monitor 214 may include a first counter circuit that increments in response to issuing a prefetch request. When the fetch pipeline 216 fulfills a prefetch request, one or more flag bits of the prefetched cache line are set to indicate that the line was prefetched.

[0079] For each cache hit of a prefetched cache line, a second count value is incremented (box 803). In the illustrated embodiment, when a cache line in cache memory 202 is hit and one or more flag bits of the hit cache line are set (indicating that the line was prefetched), the accuracy monitor 214 increments the currently used count value. In some embodiments, the one or more flag bits may be reset to an alternative value after the count value is incremented to avoid counting the prefetched cache lines multiple times when determining prefetch accuracy. To increment the currently used count value, in some embodiments, the accuracy monitor 214 may increment a second counter circuit.

[0080] In response to the end of the time interval, a new average is determined for the first and second values ​​(box 804). In some embodiments, the average of the total value and the used count value can be calculated and stored. In the illustrated embodiment, the weighted average total value is determined by adding the current total value to the average total value and dividing the sum by two, thus biasing the average value towards the current total value. In other embodiments, any suitable method for calculating the average can be used. A similar method can be used to determine the average used count value.

[0081] Subsequent operations of this method may depend on the average total value (box 805). In the illustrated embodiment, accuracy monitor 214 determines whether the average total value is greater than zero. If the average total value is greater than zero, the method moves to box 806 to determine an accuracy value based on the average total value and the average used value. Otherwise, the method moves to box 807 to set the accuracy value to a specific value.

[0082] If the average total is greater than zero, the average total and the average used count are used to determine the accuracy value (box 806). In the illustrated embodiment, the accuracy monitor 214 uses the average total and the average used count to determine the accuracy value by, for example, determining the ratio of the average total to the average used count. In some embodiments, the average used count is divided by the average total. The result can then be scaled to a desired range by multiplying it by a specific value (e.g., 1000). In some embodiments, the calculation can be simplified by shifting the binary value left or right instead of performing multiplication or division.

[0083] If the average total is zero, the accuracy value is set to a specific value (box 807). If the average total is zero, it may be impossible to determine the ratio of the average used counts to the average total. In this case, the accuracy value can be set to a default value, such as, for example, zero.

[0084] The determined average total value and average used count value are stored (box 808). When new current total value and used count value are available at the end of the next time interval, the average total value and average used count value determined in box 804 are stored for use in the next time interval. These two average count values ​​can be stored in a register within the accuracy monitor 214, or in a location within a memory array accessible to the accuracy monitor 214. Furthermore, the current total value and used count value can be initialized to appropriate starting values ​​in preparation for use in the next time interval. The accuracy value determined in boxes 806 or 807 can be sent to other circuitry, such as, for example, the depth adjuster 210. The method returns to box 802 to repeat the process in the next time interval.

[0085] Note that, Figure 8 The method described is merely an example. Figure 8 The operations illustrated in the method are depicted as being executed serially. However, in other embodiments, some of these operations may be executed in parallel or in a different order. In some embodiments, additional operations may be included.

[0086] exist Figure 9 The example of a multi-core processor is described herein as an example of a processor that may include one or more memory subsystems as described herein. In the illustrated embodiment, processor 900 includes sixteen instances of processor cores, referred to as cores 901a to 901p (or simply 901a-p for brevity), but for clarity, ... Figure 1Not all instances are shown. Cores 901a-p may each include corresponding L1 caches 902a-902p. Cores 901a-p can be coupled to L2 caches 920a-920d via bus 910. Furthermore, cores 901a-p can be coupled to memory interface 930 via L2 caches 920a-d. Memory interface 930 can be further coupled to L3 cache 940 and system memory 950. Note that in various embodiments, Figure 1 The organization can represent a logical organization rather than a physical organization, and can also employ other components. For example, in some embodiments, the cores 901a-p and L2 caches 920a-d may not be directly connected to the bus 910, but may instead interface with the bus through intermediate logic. The L3 cache 940 and system memory may reside outside the processor 900.

[0087] Core 901a-p can be configured to execute instructions and process data according to a specific instruction set architecture (ISA). In one embodiment, core 901a-p can be configured to implement... V9 ISA, but in other embodiments, it is conceivable that any desired ISA can be used, such as x86, or Furthermore, as described in more detail below, in some embodiments, each instance of core 901 can be configured to execute multiple threads concurrently, wherein each thread may include a set of instructions that can be executed independently of instructions from another thread. In various embodiments, it is contemplated that the processor may include any suitable number of cores 901a-p, and each of the cores 901a-p may handle some number of threads concurrently.

[0088] L1 cache 902a-p may reside within core 901a-p, or it may reside between core 901a-p and bus 910. L1 cache 902a-p may be configured to cache instructions and data for use by their respective cores 901a-p. In some embodiments, each individual cache 902a-p may be implemented using set-association or direct mapping techniques. For example, in one embodiment, L1 cache 902a-p may be a 16 kilobyte (KB) cache, where each L1 cache 902a-p is a 2-way setup associated with a 16-byte line size; however, other cache sizes and geometries are also possible and anticipated.

[0089] Each cache line in the cache can include the data being stored, a flag corresponding to the coherence state, and an address tag. The cache tag can include all or part of the original address of the data being stored in the cache line, an index indicating which cache line the cached data is stored in, and an offset indicating the location of the specific data in each cache line. A given processor core can access the cache using a direct address of the memory location, a lookup table-based translation address, or an address calculated using an instruction-based address pattern. In addition to the cache line coherence state, the flag can include one or more bits indicating whether the information stored in the corresponding cache line was fetched in response to a cache miss or prefetched by a prefetch circuit.

[0090] Bus 910 can be configured to manage data flow between cores 901a-p and the shared L2 caches 920a-d. In one embodiment, bus 910 may include logic (e.g., a multiplexer or switching architecture) that allows any core 901a-p to access any block bank of L2 cache 920a-d and conversely allows data to return from any block bank of L2 cache 920a-d to any core 901a-p. Bus 910 can be configured to simultaneously handle data requests from cores 901a-p to L2 cache 920a-d and data responses from L2 cache 920a-d to cores 901a-p. In some embodiments, bus 910 may include logic that queues data requests and / or responses so that requests and responses do not block other activities while waiting for service. Furthermore, in one embodiment, bus 910 may be configured to arbitrate conflicts that may occur when multiple cores 901a-p attempt to access a single block bank of L2 cache 920a-d (or vice versa). It should be noted that in various embodiments, any suitable type of interconnection network can be used to implement bus 910, and in some embodiments, the interconnection network may correspond to a physical bus interconnection.

[0091] L2 caches 920a-d can be configured to cache instructions and data for use by a corresponding set of cores 901a-p. For example, L2 cache 920a can store data for cores 901a-d, L2 cache 920b can store data for cores 901e-h, L2 cache 920c can store data for cores 901i-l, and L2 cache 920b can be similarly coupled to cores 901m-p. As the number of cores 901 increases, the size and / or number of L2 caches 920 can also increase to accommodate additional cores 901. For example, in an embodiment including 16 cores, L2 cache 920 can be configured as four caches, each 2MB, each cache comprising four separate cache block sets of 512KB, where each block set can be a 16-way configuration associated with 512 sets and a line size of 64 bytes, but can also employ any other suitable cache size or geometry.

[0092] In some embodiments, L2 caches 920a-b may include various queues and buffers configured to manage data flows to and from bus 910 and to and from L3 cache 940. For example, such embodiments of L2 caches 920a-b may implement a fill buffer configured to store fill data arriving from memory interface 930, a write-back buffer configured to store dirty evicted data to be written to memory, and / or a miss buffer configured to store L2 cache accesses that cannot be treated as simple cache hits (e.g., L2 cache misses, cache accesses matching earlier misses, accesses to atomic operations that may require multiple cache accesses, etc.). In some embodiments, multiple block groups of L2 cache 920 may share a single instance of certain data structures or other features. For example, a single instance of a fill buffer may be shared by multiple block groups of L2 cache 920 to simplify the physical implementation of L2 caches 920a-b (e.g., routing and planarization). Despite this sharing, the individual block groups of the L2 cache 920a-b can be configured to handle access to data stored within the block group simultaneously and independently when such concurrency is possible.

[0093] Like L1 caches 901a-p and L2 caches 920a-b, L3 cache 940 can be configured to cache instructions and data for use by cores 901a-p. In some embodiments, the L3 cache can be implemented on a separate memory chip external to processor 900 and accessed via memory interface 930. In other embodiments, the L3 cache can be implemented on the same die as processor 900, in which case L3 cache 940 can be directly accessed. Similar to L1 caches 902a-p, L3 cache 940 can be implemented using set-associative or direct mapping techniques. For example, in one embodiment, L3 cache 940 can be an 8-megabyte (MB) cache, where the 8MB block set is a 16-way configuration associated with a 16-byte line size, but other cache sizes and geometries are also possible and anticipated.

[0094] A cache hierarchy can be established so that any core 901 can first access its corresponding L1 cache 902. If the access to L1 cache 902 is missed, the corresponding L2 cache 920 can be accessed. If the access to L2 cache 920 is missed, the L3 cache 940 can be accessed next. If all three cache levels are missed, system memory 950 can be accessed through memory interface 930.

[0095] The memory interface 930 can be configured to manage data transfers between L2 caches 920a-b and L3 cache 940 and / or system memory 950, for example, in response to L2 fill requests and data evicting. In some embodiments, multiple instances of the memory interface 930 can be implemented, each configured to control a corresponding block group of the L3 cache 940 or system memory 950. The memory interface 930 can be configured to interface with any suitable type of memory, such as fully buffered dual in-line memory modules (FB-DIMM), double data rate or double data rate 2 synchronous dynamic random access memory (DDR / DDR2 SDRAM), or... DRAM In some embodiments, memory interface 930 may be configured to support interfacing with multiple different types of memory, such that L3 cache 940 and system memory 950 may consist of two or more of the listed types. In other embodiments, L3 cache 940 may correspond to a reserved portion of system memory 950.

[0096] The corresponding prefetching circuit system, such as, for example, in Figure 1 and Figure 2The prefetch circuitry 104 or 204 in the processor 900 can be coupled to any appropriate level of cache memory. In one embodiment, for example, the corresponding prefetch circuitry 204 can be coupled to each of the L2 caches 920a-d. The corresponding depth adjuster 210, prefetch generator 212, and accuracy monitor 214 can be coupled to each of the L2 caches 920a-920d. In such an example, the prefetch circuitry 204 can issue prefetch requests, including multi-cluster prefetch requests, for each of the four cores 901 supported by a particular L2 cache 920. For example, with reference to L2 cache 920a, accuracy data can be tracked for each of the cores 901a-d. The accuracy monitor 214 and the depth adjuster 210 can include a set of counters and / or registers corresponding to each core in the cores 901a-d. In some embodiments, the prefetch generator 212 can generate multi-cluster prefetch requests with different depth values ​​for each core 901a-d based on the corresponding accuracy data. In other embodiments, the depth adjuster 210 can adjust the individual depth values ​​of all four cores 901a-d based on the overall accuracy of the prefetch circuit 204.

[0097] It should be noted that, Figure 9 This is merely an example of a multi-core processor. In other embodiments, processor 900 may include a network and / or peripheral interface. This physical architecture may not be determined by... Figure 9 This is because many other physical arrangements are possible and anticipated.

[0098] It should also be noted that the systems and circuits described herein can be implemented using any suitable digital logic processing. For example, some embodiments may utilize complementary metal-oxide-semiconductor field-effect transistor (CMOS) processing. Such CMOS logic processing can utilize planar devices, non-planar devices, or a combination of both. Circuits designed in CMOS processing can include various combinations of smaller logic circuits such as, for example, inverters, AND gates, OR gates, NAND gates, NOR gates, and data capture circuits such as flip-flops and latches.

[0099] Once the foregoing disclosure is fully understood, many variations and modifications will become apparent to those skilled in the art. It is intended that the following claims be construed as encompassing all such variations and modifications.

Claims

1. A system for data prefetching, comprising: Processor core; A memory configured to store information for use by the processor core; A cache memory configured to retrieve and store information from the memory; and Prefetch circuit, the prefetch circuit being configured to: A multi-cluster prefetch request is generated for retrieving information from the memory using a predicted address for storage in the cache memory, wherein the prefetch circuitry is further configured to assign a current depth value to the multi-cluster prefetch request, the current depth value indicating the number of fetch clusters to be retrieved; In response to a hit of a specific cache line in one or more cache lines, increment a count value indicating that the specific cache line has been used; The count value is used to generate an accuracy value for the cache hit rate of prefetched information within a specific time interval; In response to determining that the accuracy value has changed by more than a threshold amount compared to a previous accuracy value, the specific time interval is reduced; In response to determining that the accuracy value is outside a certain accuracy value range, the current depth value is modified to an updated depth value; as well as The updated depth value is assigned to subsequently generated multi-cluster prefetch requests.

2. The system according to claim 1, wherein, In order to modify the current depth value, the prefetch circuit is also configured to: The current depth value is increased in response to determining that the accuracy value meets an upper threshold of the specific accuracy value range; as well as The current depth value is reduced in response to determining that the accuracy value meets a lower threshold of the specific accuracy value range.

3. The system of claim 1, wherein the prefetch circuitry is further configured to increment the total prefetch value for each cache line populated using the multi-cluster prefetch request.

4. The system according to claim 3, wherein, The prefetch circuit is also configured to perform the following operation in response to the end of the specific time interval: The average count value and the average prefetch total value are determined using the count value and the prefetch total value; and Clear the count value and the prefetch total value.

5. The system according to claim 4, wherein, To determine the average count value, the prefetch circuit is further configured to: Divide each of the count values ​​and the previously determined average count value by two; and The values ​​obtained from the division are added together to determine the updated average count value.

6. The system according to claim 4, wherein, In order to generate the accuracy value, the prefetch circuit is configured to divide the average count value by the average prefetch total value.

7. The system according to claim 1, wherein, The prefetch circuit is also configured to process the multi-cluster prefetch request by issuing a single-cluster prefetch request for each of the indicated number of acquisition clusters.

8. A method for data prefetching, comprising: The current depth value is assigned by the prefetch circuit to a multi-cluster prefetch request, which is used to retrieve information from memory for storage in one or more cache lines of a cache memory, wherein the current depth value indicates the number of fetch clusters to be retrieved; In response to a hit of a specific cache line in one or more cache lines, the prefetch circuit increments a count value indicating that the specific cache line has been used; The prefetch circuit generates an accuracy value based on the count value within a specific time interval; In response to determining that the accuracy value has changed by more than a threshold amount compared to a previous accuracy value, the prefetch circuit reduces the specific time interval; In response to determining that the accuracy value is outside a certain accuracy value range, the prefetch circuit modifies the current depth value to an updated depth value; and The updated depth value is assigned to subsequently generated multi-cluster prefetch requests by the prefetch circuit.

9. The method according to claim 8, further comprising: In response to using prefetch requests to populate cache lines, the total prefetch value is incremented by the prefetch circuit.

10. The method of claim 9, further comprising, in response to the end of the specific time interval: The average count value and the average total prefetch value are determined using the count value and the total prefetch value; and Clear the count value and the total prefetch value.

11. The method according to claim 10, wherein, Determining the average total prefetch value includes the prefetch circuit determining the average of the count value and a previously determined average count value.

12. The method of claim 10, further comprising: The accuracy value is generated by dividing the average count value by the average total prefetch value using the prefetch circuit.

13. The method of claim 8, further comprising: The prefetching circuit processes the multi-cluster prefetching request by issuing a single-cluster prefetching request for each of the indicated number of acquisition clusters.

14. The method of claim 8, further comprising: The current depth value is increased in response to determining that the accuracy value meets an upper threshold of the specific accuracy value range; as well as The current depth value is reduced in response to determining that the accuracy value meets a lower threshold of the specific accuracy value range.

15. An apparatus for data prefetching, comprising: The prefetch generator circuit is configured as follows: Generate a multi-cluster prefetch request that includes a current depth value, which indicates the number of clusters to be retrieved from memory and stored in one or more cache lines of cache memory; An accuracy monitor circuit, wherein the accuracy monitor circuit is configured to: In response to a hit of a specific cache line in one or more cache lines, increment a count value indicating that the specific cache line has been used; An accuracy value corresponding to the cache hit rate of prefetched cache lines within a specific time interval is generated based on the count value. and In response to determining that the accuracy value has changed by more than a threshold amount compared to a previous accuracy value, the specific time interval is reduced; and Depth adjuster circuit, the depth adjuster circuit being configured as follows: In response to determining that the accuracy value is outside a specific accuracy value range, the current depth value is modified; and The modified depth value is assigned to the subsequently generated prefetch request.

16. The apparatus according to claim 15, wherein, The accuracy monitor circuit is also configured to: The total prefetch value is incremented for each cache line populated using the multi-cluster prefetch request; and In response to the end of the specified time interval, perform the following operations: The average count value and the average prefetch total value are determined using the count value and the prefetch total value; and Clear the count value and the prefetch total value.

17. The apparatus according to claim 16, wherein, To determine the average count value, the accuracy monitor circuit is further configured to: Determine the average of the count value and the previously determined average count value.

18. The apparatus according to claim 16, wherein, In order to generate the accuracy value, the accuracy monitoring circuit is configured to divide the average count value by the average prefetch total value.

19. The apparatus according to claim 15, wherein, The prefetch generator circuit is also configured to process the multi-cluster prefetch request by issuing a single-cluster prefetch request for each of the indicated number of acquisition clusters.

20. The apparatus according to claim 15, wherein, In order to modify the current depth value, the depth adjuster circuit is further configured to: In response to determining that the accuracy value meets an upper threshold of the specific accuracy value range, the current depth value is increased; and The current depth value is reduced in response to determining that the accuracy value meets a lower threshold of the specific accuracy value range.

Images