Storage system

Abstract

This invention relates to a storage system. It includes a non-volatile memory and a controller. The controller receives from a host a first write request associated with first data having a size smaller than a first data unit, the first data unit being a write unit to the non-volatile memory; the host does not initiate write processing of the first data to the non-volatile memory if it does not issue subsequent write requests after issuing the first write request; write processing of second data having a size of at least the first data unit, based on a first time elapsed from the acceptance of the first write request (obtained by subtracting a third time from a second time); upon completion of the write processing, a first response to the first write request is sent to the host, the second time being a time limit specified by the host from the acceptance of the first write request to the sending of the first response, and the third time corresponding to the time from the start of the write processing of the second data to the point where the second data becomes readable.

Description

[0001] This application is a divisional application of application number 202110955721.8, filed on August 19, 2021, entitled "Storage System". Technical Field

[0002] Embodiments of the present invention relate to techniques for controlling non-volatile memory. Background Technology

[0003] In recent years, memory systems with non-volatile memory have become widely used. One type of such memory system is the solid-state drive (SSD), which incorporates NAND flash memory. SSDs are used as the main storage in various computing devices.

[0004] For example, when a write request is received from the host, the storage system will write the user data received from the host to non-volatile memory at the same time as the write request is received, and return a response to the host.

[0005] Alternatively, the storage system may sometimes write a specific data unit of user data to non-volatile memory after the total amount of user data requested to be written based on multiple write requests received from the host reaches a specific data unit, and then return responses to the host corresponding to each of the multiple write requests. A specific data unit is, for example, the amount of data that can be written to non-volatile memory in a single write operation. In other words, the storage system can use a mechanism that does not immediately execute the write corresponding to a single write request, but instead executes the writes corresponding to the multiple write requests after the total amount of user data requested to be written based on multiple write requests reaches a specific data unit. This mechanism will also be referred to below as Delayed Write Completion.

[0006] In a delayed write-complete mechanism, the storage area of ​​non-volatile memory can be effectively utilized, for example, by writing user data containing multiple write units corresponding to multiple write requests to non-volatile memory. However, in a delayed write-complete mechanism, the writing and response to each write request may be delayed until multiple write requests corresponding to the write units of user data are accepted.

[0007] Because the storage system does not immediately perform the write and response corresponding to a write request as soon as it receives a write request from the host, the host may not receive a response to the write request within the expected time. Summary of the Invention

[0008] One embodiment of the present invention provides a storage system capable of responding to write requests within a timeframe expected by the host.

[0009] According to one implementation, the storage system includes non-volatile memory and a controller. The controller receives from the host a first write request associated with first data having a size smaller than a first data unit, the first data unit being a write unit to the non-volatile memory; if the host does not issue a subsequent write request after issuing the first write request, the write process for the first data to the non-volatile memory is not initiated; based on a first time elapsed from the receipt of the first write request, a write process for second data, at least containing the first data, to the non-volatile memory, the second data having the size of the first data unit, is initiated; upon completion of the write process, a first response to the first write request is sent to the host, the first time being a time obtained by subtracting a third time from a second time, the second time being a time limit specified by the host from the receipt of the first write request to the sending of the first response, and the third time corresponding to the time from the start of the write process for the second data to the non-volatile memory until the second data becomes readable from the non-volatile memory. Attached Figure Description

[0010] Figure 1 This is a block diagram illustrating an example configuration of an information processing system that includes the storage system described in the implementation.

[0011] Figure 2 This is a diagram illustrating an example of the structure of the zoned namespace managed in the storage system of this implementation.

[0012] Figure 3 This is a diagram illustrating an example of the time taken in a storage system of this implementation to execute processing corresponding to a write command by initiating (triggering) a forced response.

[0013] Figure 4 This is a diagram illustrating an example of the parameters used to control the initiation of a forced response in the storage system of this embodiment.

[0014] Figure 5 This is a diagram illustrating an example of the configuration of the logical-physical address translation table used in the storage system of this embodiment.

[0015] Figure 6 This is a diagram illustrating an example of the structure of the namespace response management table used in the storage system of this implementation.

[0016] Figure 7 This is a diagram illustrating an example of the configuration of the command response management table used in the storage system of this implementation.

[0017] Figure 8 This is a diagram illustrating an example of the structure of the write management table used in the storage system of this embodiment.

[0018] Figure 9 This is a block diagram representing an example of an action in the storage system corresponding to a write command in the first comparison example.

[0019] Figure 10 This is a block diagram representing an example of an action in the storage system corresponding to a write command in the second comparison example.

[0020] Figure 11 This is a block diagram illustrating an example of an action in the storage system of this embodiment that corresponds to a write-force response setting command.

[0021] Figure 12 This is a block diagram illustrating an example of an action in the storage system of this embodiment that corresponds to a write-force response confirmation command.

[0022] Figure 13 This is a block diagram illustrating an example of an action corresponding to a write command in the storage system of this embodiment.

[0023] Figure 14 This is a flowchart illustrating an example of the setup process steps performed in the storage system of this embodiment.

[0024] Figure 15 This is a flowchart illustrating an example of the confirmation process steps performed in the storage system of this embodiment.

[0025] Figure 16 It means Figure 1 The flowchart illustrates an example of the steps involved in processing a write request within a host system of an information processing system.

[0026] Figure 17 It means Figure 1 A flowchart illustrating an example of the response receiving and processing steps performed in a host within an information processing system.

[0027] Figure 18 This is a flowchart illustrating an example of the steps of the write control processing performed in the storage system of this embodiment.

[0028] Figure 19 This is a flowchart illustrating an example of the command acceptance processing steps performed in the storage system of this embodiment.

[0029] Figure 20This is a flowchart illustrating an example of the response processing steps performed in the storage system of this embodiment.

[0030] Label Explanation

[0031] 1. Information processing system; 2. Host; 3. Storage system; 4. Controller; 5. NAND flash memory; 6. DRAM; 11. Host I / F (interface); 12. CPU (Central Processing Unit); 13. NAND I / F; 14. DRAM I / F; 121. Command receiving department; 122. Forced response management department; 123. Write control department; 124. Zone management department; 21. FW (firmware); 22. Logical-physical address translation table; 23. NS (namespace) response management table; 24. Command response management table; 25. Zone descriptor; 26. Write management table. Detailed Implementation

[0032] Hereinafter, the embodiments will be described with reference to the accompanying drawings.

[0033] First, refer to Figure 1 The following describes the configuration of the information processing system 1, which includes the storage system involved in the implementation. The information processing system 1 includes a host device 2 (hereinafter referred to as host 2) and a storage system 3.

[0034] Host 2 is an information processing device. Host 2 can be either a storage server that stores large amounts of diverse data in storage system 3, or a personal computer.

[0035] Storage system 3 is a semiconductor storage device configured to write data to and read data from non-volatile memory such as NAND flash memory. Storage systems are also referred to as storage devices. Storage systems are implemented, for example, as solid-state drives (SSDs).

[0036] Storage system 3 can be used as storage for host 2. Storage system 3 can be built into host 2 or connected to host 2 via cable or network.

[0037] The interface used to connect host 2 to storage system 3 conforms to standards such as SCSI (Small Computer System Interface Standard), SAS (Serial Attached SCSI), ATA (AT Attachment), SATA (Serial ATA), PCIe (PCI Express, High Speed ​​Serial Computer Expansion Bus Standard) (registered trademark), Ethernet (registered trademark), Fibre Channel, and NVMe (NVM Express, Non-Volatile Memory Standard) (registered trademark).

[0038] The storage system 3 includes, for example, a controller 4, NAND flash memory 5, and dynamic random access memory (DRAM) 6. The controller 4 can be implemented using a system-on-a-chip (SoC) circuit. The controller 4 can also have built-in static random access memory (SRAM). Additionally, DRAM 6 can also be integrated into the controller 4.

[0039] The RAM, such as DRAM6, contains a storage area for firmware (FW) 21, a cache area for logical physical address translation table 22, a namespace response management table (NS response management table) 23, a command response management table 24, a partition descriptor 25, and a write management table 26.

[0040] FW21 is a program used to control the operation of controller 4. FW21 is loaded, for example, from NAND flash memory 5 into DRAM 6.

[0041] The logical physical address translation table 22 manages the mapping between each logical address and each physical address of the NAND flash memory 5.

[0042] NS response management table 23, for example, manages information about when a response should be made to a write command (write request) by namespace.

[0043] Command Response Management Table 24 Management should force the start of the processing time corresponding to the accepted write command.

[0044] Partition descriptor 25 contains information representing the structure and / or status of each partition.

[0045] Write management table 26 manages information related to the write commands received.

[0046] The NAND flash memory 5 includes multiple blocks B0 to Bm-1. Each block B0 to Bm-1 contains multiple pages (here, pages P0 to Pn-1). Blocks B0 to Bm-1 serve as the smallest unit for data erasure operations. Blocks are sometimes referred to as "erasure blocks" or "physical blocks." Each page P0 to Pn-1 contains multiple memory cells connected to the same word line. Pages P0 to Pn-1 serve as the unit for both data write and data read operations. Additionally, word lines can also be used as the unit for both data write and data read operations.

[0047] There is an upper limit to the number of program / erase cycles (P / E cycles) for each block B0 to Bm-1, which is called the maximum number of P / E cycles. One P / E cycle for a block includes an erase operation to put all memory cells in the block into an erased state and a write operation to write data to each page of the block.

[0048] Controller 4 functions as a storage controller that controls the NAND flash memory 5.

[0049] Controller 4 can also function as a flash translation layer (FTL) that performs data management and block management for the NAND flash memory 5. Data management performed by this FTL includes (1) managing mapping information representing the correspondence between logical addresses and physical addresses of the NAND flash memory 5, and (2) handling to hide the differences between page-based read / write operations and block-based erase operations. Block management includes the management of bad blocks, wear-leveling, and garbage collection.

[0050] A logical address is an address used by host 2 for addressing storage system 3. A logical address is, for example, a logical block address (LBA). The following examples primarily illustrate the use of LBAs as logical addresses.

[0051] The logical physical address translation table 22 is used to manage the mapping between each LBA and each physical address. The controller 4 uses the logical physical address translation table 22 to manage the mapping between each LBA and each physical address in units of a specific management size. The physical address corresponding to a certain LBA indicates the physical storage location within the NAND flash memory 5 where the data of that LBA is written. The controller 4 uses the logical physical address translation table 22 to manage multiple storage regions obtained by logically dividing the storage area of ​​the NAND flash memory 5. These multiple storage regions each correspond to multiple LBAs. That is, each of these multiple storage regions is determined by one LBA. The logical physical address translation table 22 can also be loaded from the NAND flash memory 5 into the DRAM 6 when the storage system 3 is powered on.

[0052] Each P / E cycle can only perform one write to a page of data. Therefore, instead of writing the updated data corresponding to a certain LBA to the physical storage location that stores the previous data corresponding to that LBA, controller 4 writes the updated data to another physical storage location. Furthermore, controller 4 invalidates the previous data by updating the logical physical address translation table 22 in a way that associates the LBA with this other physical storage location. Data referenced from the logical physical address translation table 22 (i.e., data associated with an LBA) is called valid data. Data not associated with any LBA is called invalid data. Valid data is data that can be read from host 2 later. Invalid data is data that can no longer be read from host 2.

[0053] The controller 4 may also include a host interface (host I / F) 11, a CPU 12, a NAND interface (NAND I / F) 13, a DRAM interface (DRAM I / F) 14, and a timer 16. The aforementioned host I / F 11, CPU 12, NAND I / F 13, DRAM I / F 14, and timer 16 may also be connected via bus 10.

[0054] The host I / F11 functions as a circuit that receives various commands from the host 2, such as I / O commands and various control commands. I / O commands can include write commands, read commands, and verify commands. Control commands can include unmap commands (trim commands), format commands, set commands, and confirm commands. The format command is used to unmap the entire storage system 3. The set commands are used to set various parameters for the storage system 3. The confirm commands are used to confirm the various parameters set for the storage system 3.

[0055] NAND I / F13 electrically connects controller 4 to NAND flash memory 5. NAND I / F13 corresponds to interface standards such as ToggleDDR and ONFI (Open NAND Flash Interface).

[0056] The NAND I / F13 functions as a NAND control circuit that controls the NAND flash memory 5. The NAND I / F13 can also be connected to multiple memory chips within the NAND flash memory 5 via multiple channels (Ch). By driving multiple memory chips in parallel, broadband access to the entire NAND flash memory 5 can be achieved.

[0057] DRAM I / F14 functions as a DRAM control circuit configured to control access to DRAM6. The storage area of ​​DRAM6 is allocated as an area for storing FW21, logical physical address translation table 22, NS response management table 23, command response management table 24, partition descriptor 25, and write management table 26, and / or as a buffer area used as a read / write buffer.

[0058] Timer 16 measures the time. Timer 16 can provide the measured time to various parts within controller 4.

[0059] CPU 12 is a processor configured to control host I / F 11, NAND I / F 13, DRAM I / F 14, and timer 16. CPU 12 performs various processes by executing FW21 loaded from NAND flash memory 5 into DRAM 6. FW21 is a control program containing an instruction set for causing CPU 12 to perform various processes. CPU 12 is capable of command processing, such as handling various commands from host 2. The operation of CPU 12 is controlled by FW21 executed by CPU 12.

[0060] The functions of each part within controller 4 can be implemented either by dedicated hardware within controller 4 or by CPU 12 executing FW21.

[0061] CPU 12 functions, for example, as a command receiving unit 121, a forced response management unit 122, a write control unit 123, and a partition management unit 124. CPU 12 functions as these units, for example, by executing FW21. See below. Figures 11 to 13 The specific actions of the command receiving unit 121, the mandatory response management unit 122, the write control unit 123, and the partition management unit 124 are explained.

[0062] Here, namespaces and partitions are explained. The logical address space (LBA space) used by host 2 for accessing storage system 3 can be divided into multiple local spaces. Each local space is sometimes referred to as a namespace.

[0063] Controller 4 manages data stored in NAND flash memory 5, for example, by partition. Controller 4 uses partition namespaces (ZNS) as defined by the NVMe standard as a method for managing data stored in NAND flash memory 5 on a partition-by-partition basis.

[0064] Figure 2 This illustrates an example of the structure of a ZNS. In a ZNS, the entire LBA space of a namespace can be divided into multiple partitions. Each of these partitions can contain multiple LBAs. Each partition resulting from dividing a namespace corresponds to an LBA range consisting of multiple consecutive and non-overlapping LBAs. Each partition is used as a unit for accessing NAND flash memory.

[0065] exist Figure 2 In the example shown, the namespace corresponds to z LBA0 to LBA(z-1) and has x partitions 0 to partition(x-1). LBA0 is the smallest LBA of partition 0. In addition, LBA(z-1) is the largest LBA of partition(x-1).

[0066] Writes within a partition are performed sequentially. That is, writes within a partition are performed in a sequential LBA manner. A partition can correspond to any physical unit within the NAND flash memory 5. For example, a partition corresponds to a block within the NAND flash memory 5. In this case, the data within a block is accessed using consecutive LBAs contained within the LBA range allocated to a partition.

[0067] Each partition can be in one of three states: open, full, or closed. An open partition is one that can be written to. A full partition is one that has been completely written to. A closed partition is one where data writing has been interrupted.

[0068] In addition, the partition descriptor 25 corresponding to a certain partition contains information such as the starting LBA (i.e. the smallest LBA) of the partition, the amount of data that can be written to the partition, and the status of the partition.

[0069] The controller 4 is configured to perform writes based on a delayed write completion mechanism. At the same time, if there is a write command whose elapsed time after acceptance exceeds a threshold, it will forcibly perform the corresponding processing for the write command and respond to the host 2.

[0070] Hereinafter, the situation in which a write command is forcibly started to process the corresponding write command when there is a write command whose elapsed time after acceptance exceeds a threshold will be referred to as starting a forced response.

[0071] A write command is a command that requests the writing of user data associated with the write command into the NAND flash memory 5. The corresponding processing is the process of writing the user data associated with the write command into the NAND flash memory 5.

[0072] Delayed write completion works as follows: instead of immediately executing the write corresponding to a single accepted write command, the write is performed, for example, after the total amount of user data requested to be written to a partition by multiple write commands reaches a write unit, and a response is given to host 2. A write unit is equivalent to the amount of data that can be written to the NAND flash memory 5 in a single write operation. A write unit is, for example, equivalent to one page of data. In the case where multiple bits of data are stored in a single memory cell, a write unit can be equivalent to multiple pages of data.

[0073] Data can be written to NAND flash memory using Quad-Level Cells (QLC). In QLC, each cell stores 4 bits of data. QLC sometimes involves multi-step write operations. Examples of multi-step write operations include foggy / fine write operations.

[0074] A fuzzy / fine write operation is a write operation where data is written to one page of a block of pages, and reads occur after data has been written to one or more pages following that page. A fuzzy / fine write operation involves multiple write operations to a group of memory cells connected to the same word line. The first write operation, called a fuzzy write, roughly sets the threshold voltage for each memory cell. The second write operation, called a fine write, adjusts the threshold voltage for each memory cell. Fuzzy / fine write operations can reduce the impact of programming interference.

[0075] When writing data to the NAND flash memory 5 via fuzzy / fine write operations, the write unit is equivalent to 4 pages of data.

[0076] Reference Figure 3 as well as Figure 4 Specifically, the startup of the forced response in storage system 3 will be explained.

[0077] Figure 3This section illustrates an example of the time taken to execute the processing corresponding to a write command in storage system 3 by initiating a forced response. The following example illustrates the case where the initiation of forced responses is managed by namespace. However, the initiation of forced responses is not limited to namespaces; it can also be managed by various storage regions.

[0078] Controller 4 receives a write command issued by host 2. If time A has elapsed since receiving the write command, controller 4 forcibly begins processing corresponding to the write command (i.e., initiates a forced response). Thus, controller 4 is able to complete the response to the write command within the period from receiving the write command to the elapsed time B.

[0079] Figure 4 This section presents examples of parameters used to control the initiation of a forced response in storage system 3. Parameters used to control the initiation of a forced response include, for example, forced_completion_time (forced completion time) and process_time (processing time).

[0080] `forced_completion_time` is used to determine whether forced response is enabled, and if forced response is enabled, it sets an upper limit on the time from when controller 4 receives a write command to when it completes its response to that write command (equivalent to...). Figure 3 The parameter B) is the time. The upper limit of the time from accepting a write command to completing a response to that write command is also called the forced response completion time.

[0081] In storage system 3, the value of forced_completion_time is arbitrary. The value m of forced_completion_time represents the forced response completion time set by the user. The user sets the value m of forced_completion_time by issuing a write forced response setting command from host 2.

[0082] The write-force-completion-time (WCCOM) command requests the setting of when to initiate a forced response. The WCCOM command specifies namespace identification information (namespace ID) and the value m of `forced_completion_time`. The WCCOM command can be implemented, for example, as the `Set Features` command as defined in the NVMe standard. Hereinafter, the WCCOM command will also be referred to as the setting command.

[0083] For example, when the value of forced_completion_time m is 0, controller 4 does not initiate a forced response to write commands. Furthermore, if no settings are configured to initiate a forced response corresponding to the specified command (i.e., the default state), controller 4 also does not initiate a forced response to write commands.

[0084] Furthermore, when the value of `forced_completion_time` is 1 or higher, controller 4 uses the value of `forced_completion_time` `m` to determine the forced response completion time. The forced response completion time represents the upper limit of the response time expected by host 2 for a write command. The forced response completion time is, for example, m × 100 milliseconds (ms). That is, controller 4 completes the response to the write command within a period of m × 100 milliseconds from the time the write command is received. Controller 4 manages the value of `forced_completion_time` `m` jointly for each of the multiple partitions contained in a corresponding namespace. That is, a single value of `forced_completion_time` `m` is set for multiple partitions contained in a namespace.

[0085] `process_time` is used to determine the time from when controller 4 receives a write command to when forced response is initiated (equivalent to...) from when forced response is initiated until the corresponding processing for that write command is forcibly started. Figure 3 The time parameter (A) is also called the forced response trigger time, which is the time from when a write command is accepted until the corresponding processing for that write command is forcibly started.

[0086] In storage system 3, the value of process_time can be set arbitrarily. Alternatively, the value of process_time, n, can be set, for example, before storage system 3 leaves the factory.

[0087] With a set process_time value n, controller 4 determines the forced response start time based on the received and set command, using the forced_completion_time value m and the process_time value n. The forced response start time is, for example, (mn) × 100 milliseconds. That is, controller 4 forcibly begins processing corresponding to the write command after (mn) × 100 milliseconds have elapsed since the write command was received.

[0088] Furthermore, n×100 milliseconds corresponds, for example, to the time from the forced commencement of processing corresponding to the write command (write processing) to the point where the corresponding user data can be read from the NAND flash memory 5 (hereinafter also referred to as processing time). Thus, the forced response start time is the time obtained by subtracting the processing time from the forced response completion time.

[0089] The write process includes the transfer (forwarding) of user data from controller 4 to NAND flash memory 5 and the programming of user data in NAND flash memory 5 to memory cells. The write process is completed when it becomes possible to read user data from NAND flash memory 5.

[0090] Therefore, in storage system 3, the initiation of a forced response to an accepted write command can be controlled based on the user-defined value m of forced_completion_time. More specifically, controller 4 can use the values ​​m of forced_completion_time and n of process_time to determine the forced response completion time and forced response initiation time. If the forced response initiation time has elapsed since the host 2 received the write command, controller 4 forcibly begins writing the user data corresponding to the write command to the NAND flash memory 5. Thus, controller 4 can respond to the write command within the forced response completion time expected by host 2.

[0091] Next, refer to Figures 5 to 8 The following section describes several tables used in storage system 3.

[0092] Figure 5 This represents an example of a logical-to-physical address translation table 22. The logical-to-physical address translation table 22 manages the mapping between each LBA and each physical address of the NAND flash memory 5. The controller 4 can use the logical-to-physical address translation table 22 to translate LBAs into physical addresses. Additionally, the controller 4 can use the logical-to-physical address translation table 22 to translate physical addresses into LBAs.

[0093] exist Figure 5 In the example shown, LBA "0", LBA "1", and LBA "2" are mapped to physical addresses "X", "Y", and "Z", respectively.

[0094] Figure 6 This represents a configuration example of NS response management table 23. NS response management table 23 may include one or more entries, each corresponding to one or more namespaces. Each entry may include, for example, a namespace ID field, a forced response completion time field, and a forced response start time field.

[0095] In the entry corresponding to a namespace, the namespace ID field represents the identification information (namespace ID) assigned to that namespace. Controller 4 can identify a corresponding namespace through a namespace ID.

[0096] The Forced Response Completion Time field indicates the upper limit (i.e., the forced response completion time) of the time that controller 4 must take to respond to a write command if the corresponding namespace contains the write destination of the write command. A namespace containing the write destination of the write command means that the LBA specified by the write command is located within the LBA space of that namespace. Controller 4 is configured to send a response to the write command to host 2 during the period from accepting the write command to the time indicated by the Forced Response Completion Time field. The time is set in milliseconds, for example, in the Forced Response Completion Time field.

[0097] The Forced Response Start Time field indicates the time at which controller 4 begins processing the write command if the corresponding namespace contains the write destination of the write command (i.e., the Forced Response Start Time). In other words, controller 4 begins processing the write command if the time indicated by the Forced Response Start Time field has elapsed since the write command was received. The Forced Response Start Time field can be set in milliseconds, for example.

[0098] exist Figure 6 In the example shown, namespace ID "1" is associated with forced response completion time "20000" and forced response start time "15000".

[0099] In the following description of NS Response Management Table 23, the value shown in the Namespace ID field will also be referred to simply as Namespace ID. The same applies to the values ​​shown in the other fields of NS Response Management Table 23 and the fields of other tables.

[0100] Figure 7 This represents a configuration example of the command response management table 24. The command response management table 24 may include one or more entries, each corresponding to one or more write commands. Each entry may include, for example, a command ID field and a time field up to startup.

[0101] In the entry corresponding to a write command, the command ID field represents the identification information assigned to that write command. This identification information assigned to a write command is also called the command ID. Controller 4 can identify a corresponding write command through a command ID.

[0102] The "Time Until Startup" field represents the remaining time until the processing corresponding to the write command is forcibly initiated. Specifically, the "Time Until Startup" field may, for example, set the forced response start time for the namespace containing the write destination to an initial value. Controller 4 decrements the time set in the "Time Until Startup" field, for example, based on the elapsed time measured by timer 16. Furthermore, when the time set in the "Time Until Startup" field becomes 0, the processing corresponding to the write command is forcibly initiated. The "Time Until Startup" field may be set in milliseconds, for example.

[0103] exist Figure 7 In the example shown, command ID "11" is associated with time "1200" up to startup, and command ID "12" is associated with time "10000" up to startup.

[0104] Figure 8 This represents a configuration example of write management table 26. Write management table 26 may include one or more entries, each corresponding to one or more write commands. Each entry may include, for example, a command ID field, an LBA field, a data length field, a data buffer information field, and a partition field.

[0105] The command ID field represents the command ID of the corresponding write command.

[0106] The LBA field represents the LBA specified by the corresponding write command. This LBA represents the first LBA in the range of LBAs where user data should be written according to the write command.

[0107] The data length field indicates the data length specified by the corresponding write command. This data length represents the length of user data that should be written according to the write command. Therefore, using the LBA specified by the write command and the data length, the range of LBAs that should be written to the user data according to that write command can be determined.

[0108] The data buffer information field indicates the data buffer information specified by the corresponding write command. This data buffer information indicates the location in host 2 where the user data that should be written according to the write command is stored. In other words, controller 4 transfers user data from the storage location in host 2 indicated by the data buffer information to storage system 3.

[0109] The partition field represents a partition containing the LBA specified by the corresponding write command. A partition is represented, for example, by the first LBA (i.e., the smallest LBA) of the LBA range assigned to that partition. Write management table 26 can use the partition represented by the partition field to manage information related to write commands on a partition-by-partition basis. Alternatively, controller 4 can use multiple write management tables 26 for each partition instead of setting the partition field for each entry.

[0110] (The operation of the storage system involved in the comparative example)

[0111] Here, we use two comparative examples involving storage systems to illustrate the action examples corresponding to write commands.

[0112] Figure 9 This is a block diagram illustrating an example of an action corresponding to a write command in the storage system 3A involved in the first comparative example. The storage system 3A of the first comparative example has, for example, the same system configuration as the storage system 3 of this embodiment.

[0113] The storage system 3A is configured such that whenever it receives a write command issued by the host 2A, it executes the corresponding processing for the write command and returns a response to the host 2A. The CPU 12A of the storage system 3A functions as the command receiving unit 121A and the write control unit 123A.

[0114] Host 2A may include a submission queue (SQ) 401A, a completion queue (CQ) 402A, and a data buffer 403A.

[0115] Submission queue 401A includes multiple slots. Host 2A writes commands issued to storage system 3A to these slots. The position (i.e., slot) in submission queue 401A where host 2A is to write a command is indicated by the SQ tail pointer. The position in submission queue 401A where storage system 3A is to fetch a command is indicated by the SQ headpointer.

[0116] The completion queue 402A comprises multiple slots, and the storage system 3A writes the responses to commands to these slots. The position in the completion queue 402A where the storage system 3A is to write a response is indicated by the CQ tail pointer. The position in the completion queue 402A where the host 2A is to retrieve a response is indicated by the CQ head pointer.

[0117] Data buffer 403A is a storage area for temporarily storing user data to be written into the NAND flash memory 5A of storage system 3A.

[0118] The following describes specific operational examples of storage system 3A and host 2A. For ease of understanding, the example shown is a write command only, where the command to write to submission queue 401A is executed.

[0119] First, host 2A stores the user data to be written to the NAND flash memory 5A of storage system 3A in data buffer 403A. Then, host 2A writes a write command (i.e., issues a write command) to the position indicated by the SQ tail pointer in the commit queue 401A. This write command is a request to write the user data stored in data buffer 403A.

[0120] Next, host 2A increments the SQ tail pointer by 1. Furthermore, if the value obtained by incrementing the SQ tail pointer reaches the number of slots (i.e., the queue size) of the submission queue 401A, host 2A sets the SQ tail pointer to 0. Then, host 2A writes the updated SQ tail pointer value to the SQ Tail doorbell register in storage system 3A.

[0121] The command receiving unit 121A of storage system 3A retrieves a write command from the position indicated by the SQ header pointer in the submission queue 401A. Figure 9 (1) In the case of a difference between the SQ header pointer and the SQ tail pointer, the command receiving unit 121A can obtain a write command from the submission queue 401A. The command receiving unit 121A increments the SQ header pointer by 1. Furthermore, if the value obtained by incrementing the SQ header pointer by 1 reaches the number of slots in the submission queue 401A, the command receiving unit 121A sets the SQ header pointer to 0. The command receiving unit 121A sends the obtained write command to the write control unit 123A. Figure 9 (2) in the middle.

[0122] The write control unit 123A, based on the write command sent by the command receiving unit 121A, transmits the user data to be written to the NAND flash memory 5A from the data buffer 403A to the DRAM 6A. The write control unit 123A then writes the transmitted user data into the NAND flash memory 5A (i.e., performs programming). Figure 9 (3)). Then, when the write control unit 123A becomes capable of reading the written user data, it notifies the command receiving unit 121A of the completion of the processing corresponding to the write command. Figure 9 (4) in the middle.

[0123] According to the notification from the write control unit 123A, the command receiving unit 121A writes the completion notification of the corresponding write command to the position indicated by the CQ tail pointer in the completion queue 402A, and issues an interrupt. Figure 9(5)). The command receiving unit 121A notifies the host 2A by issuing an interrupt that a new completion notification that should be processed exists in the completion queue 402A. In addition, the command receiving unit 121A increments the CQ tail pointer by 1. Furthermore, if the value obtained by incrementing the CQ tail pointer by 1 reaches the number of slots in the completion queue 402A, the command receiving unit 121A sets the CQ tail pointer to 0.

[0124] Based on an interrupt issued by the command receiving unit 121A, host 2A retrieves a completion notification from the position indicated by the CQ head pointer in the completion queue 402A. Host 2A increments the CQ head pointer by 1. Furthermore, if the value obtained by incrementing the CQ head pointer reaches the number of slots in the completion queue 402A, host 2A sets the CQ head pointer to 0. Host 2A writes the updated CQ head pointer value to the CQ Head pointer register of the storage system 3A. Host 2A clears the interrupt received from the storage system 3A. Then, based on the retrieved completion notification, host 2A releases the area within the data buffer 403A that stores the user data that has been written successfully.

[0125] Through the above actions, whenever the storage system 3A of the first comparative example receives a write command from the host 2A, it performs the corresponding processing for the write command and returns a response (completion notification) to the host 2A. Thus, the storage system 3A of the first comparative example can respond to the write command within the time expected by the host 2A.

[0126] Figure 10 This is a block diagram illustrating an example of an action corresponding to a write command in the storage system 3B involved in the second comparative example. The storage system 3B of the second comparative example has, for example, the same system configuration as the storage system 3 of this embodiment.

[0127] The storage system 3B is configured such that, after the total amount of user data requested to be written to a partition by multiple write commands reaches a write unit, the user data of the write unit is written to the NAND flash memory 5B, and a response for each of the multiple write commands is returned to the host 2B. The CPU 12B of the storage system 3B functions as the command receiving unit 121B and the write control unit 123B.

[0128] The structure and operation of host 2B are the same as those described above. Figure 9 The host 2A in the first comparative example is the same. Furthermore, after issuing a write command, host 2B can issue subsequent write commands before receiving a response to that write command. This is because if host 2B is configured to wait for a response to a write command before issuing the next write command, a deadlock may occur between it and storage system 3B, which needs to respond after the total amount of user data requested by multiple write commands has reached a write unit.

[0129] The following explanation focuses on the differences between the operation of storage system 3B and the storage system 3A of the first comparative example.

[0130] The command receiving unit 121B of storage system 3B retrieves the write command from the position indicated by the SQ header pointer in the submission queue 401B. Figure 10 (1)). The command receiving unit 121B sends the received write command to the write control unit 123B ( Figure 10 (2) in the middle.

[0131] The write control unit 123B receives a write command sent by the command receiving unit 121B and obtains the command ID, LBA, data length, and data buffer information specified by the write command. The write control unit 123B determines the partition including the obtained LBA. Using the obtained command ID, LBA, data length, data buffer information, and the determined partition, the write control unit 123B updates the write management table 26B. Figure 10 (3)). The write control unit 123B uses the write management table 26B to determine whether the data buffer 403B of the host 2B stores user data for a write unit of a partition.

[0132] If the data buffer 403B of host 2B does not store user data for a write unit of a partition, the write control unit 123B does not write user data to the NAND flash memory 5B. During the period when the data buffer 403B of host 2B does not store user data for a write unit of a partition, the command receiving unit 121B can repeatedly retrieve write commands from the submission queue 401B.

[0133] When the data buffer 403B stores user data for a write unit of a partition, the write control unit 123B transfers the user data of the write unit from the data buffer 403B to the NAND flash memory 5B, and writes the transferred user data of the write unit into the NAND flash memory 5B (for programming). Figure 10 (4)). Furthermore, the user data of the transmitted write unit can also be cached in DRAM 6B. Moreover, in the event of a write command that enables the reading of corresponding user data from NAND flash memory 5B, write control unit 123B notifies command receiving unit 121B of the completion of the processing corresponding to that write command. Figure 10 (5)). The write control unit 123B notifies the command receiving unit 121B of the completion of the processing of multiple write commands corresponding to the user data of the writing unit.

[0134] According to the notification from the write control unit 123B, the command receiving unit 121B writes the completion notification of the corresponding write command to the position indicated by the CQ tail pointer in the completion queue 402B, and issues an interrupt. Figure 10 (6)). The operation of the command receiving unit 121B and the host 2B after the interruption is the same as the operation of the command receiving unit 121A and the host 2A in the first comparative example.

[0135] Through the above actions, when the total amount of user data requested to be written to a partition by the host 2B through multiple write commands reaches a write unit, the storage system 3B of the second comparative example writes the write unit of user data to the NAND flash memory 5B (more specifically, to the storage area of ​​the NAND flash memory 5B corresponding to the partition). Furthermore, the storage system 3B returns a response to each of the multiple write commands to the host 2B.

[0136] The size of the user data to be written according to a write command is, for example, smaller than the write unit corresponding to the NAND flash memory 5B. When the user data for a write unit of a partition is stored in the data buffer 403B, the storage system 3B writes the user data for that write unit to the partition. Thus, the storage system 3B can effectively utilize the storage area of ​​the NAND flash memory 5B.

[0137] The operation of storage system 3B is equivalent to a delayed write completion mechanism. In this mechanism, the writing and response to each write command may be delayed until multiple write commands corresponding to the user data to be written are received. For example, if host 2B issues a first write command requesting the writing of user data less than the write unit but does not issue subsequent write commands, the user data to be written will not be stored in data buffer 403B. Therefore, the data writing corresponding to the first write command will not begin, and the response to host 2B may be delayed.

[0138] Storage system 3B may not immediately perform the write operation and respond to a write command received from host 2B. Consequently, host 2B may not receive a response to the write command within the expected timeframe. In this case, the write command may stall, potentially resulting in a failure to write user data from host 2B to storage system 3B.

[0139] However, immediately performing the write and response corresponding to a write command upon receipt of a write command contradicts the delayed write completion mechanism.

[0140] Therefore, the storage system 3 in this embodiment is configured to perform writes based on a delayed write completion mechanism and respond to write commands within the time expected by the host 2. Specifically, when a write command is received and the elapsed time reaches the forced response start time, the controller 4 of the storage system 3 writes the user data corresponding to the write command to the shared write buffer of the NAND flash memory 5, instead of writing it to the storage area of ​​the NAND flash memory 5 corresponding to the partition including the LBA specified by the write command. Furthermore, the controller 4 turns the partition including the LBA specified by the write command into a closed state. The forced response start time is set so that the processing corresponding to the write command can be completed within the time expected by the host 2 (forced response completion time). Therefore, the controller 4 can respond to the write command within the time expected by the host 2.

[0141] Furthermore, if the total amount of user data stored in data buffer 403 that should be written to a partition reaches a write unit before the forced response start time is reached after the elapsed time following the receipt of the corresponding write command, then controller 4 writes the write unit of user data to the partition. In other words, controller 4 performs a write based on a delayed write completion mechanism.

[0142] Therefore, controller 4 can respond to write commands within the time expected by host 2, while effectively utilizing the storage area of ​​NAND flash memory 5. This provides a low-cost storage system 3 achieved by combining a delayed write completion mechanism with a flash memory such as QLC flash memory that requires multi-step write operations. Furthermore, it maintains interchangeability with existing software stacks.

[0143] Reference Figures 11 to 13 Here, a specific example of the operation of the storage system 3 in this embodiment will be explained.

[0144] Figure 11 This is a block diagram representing an example of an action in storage system 3 corresponding to a write-force response setting command (setting command).

[0145] Host 2 sends (issues) configuration commands to storage system 3. Figure 11 (1)). In the setting command, for example, the namespace ID and the value m of forced_completion_time are specified.

[0146] The command receiving unit 121 of the storage system 3 receives the setting command sent by the host 2. Furthermore, the command receiving unit 121 sends the setting command to the forced response management unit 122. Figure 11 (2) in the middle.

[0147] Forced Response Management Unit 122 updates NS Response Management Table 23 according to the set command. Figure 11 (3)). The Forced Response Management Unit 122 uses the value m of forced_completion_time specified by the setting command to determine the forced response completion time and the forced response start time. Moreover, the Forced Response Management Unit 122 generates entries representing the forced response completion time and the forced response start time associated with the namespace ID specified by the setting command, and appends them to the NS Response Management Table 23.

[0148] More specifically, firstly, the forced response management unit 122 obtains the namespace ID and the value m of forced_completion_time specified by the setting command. Here, the namespace determined by the obtained namespace ID is referred to as the object namespace.

[0149] When the value of forced_completion_time m is 1 or higher, the forced response management unit 122 updates the NS response management table 23 in a way that responds to write commands with the object namespace as the write destination within a forced response completion time based on the value of forced_completion_time m. More specifically, the forced response management unit 122 calculates, for example, m × 100 milliseconds as the forced response completion time.

[0150] The forced response management unit 122 obtains the value n of process_time. The value n of process_time is, for example, determined before the storage system 3 leaves the factory. The value n of process_time is, for example, stored in the NAND flash memory 5. Furthermore, the forced response management unit 122 calculates, for example, (mn) × 100 milliseconds as the forced response start time. Although this example shows m and n specified in units of 100 milliseconds, m and n can be expressed in any unit as long as the forced response completion time and forced response start time can be calculated.

[0151] Next, the Forced Response Management Unit 122 determines whether the calculated Forced Response Completion Time and Forced Response Start Time are valid values. For example, if the calculated Forced Response Completion Time is shorter than the programming time tProg for the NAND flash memory 5, the Forced Response Management Unit 122 determines that the Forced Response Completion Time is an invalid value. For example, if the calculated Forced Response Start Time is 0 or less (i.e., m is less than n), the Forced Response Management Unit 122 determines that the Forced Response Start Time is an invalid value. Furthermore, if the calculated Forced Response Completion Time exceeds the Finish Recommended Limit (FRL) specified according to the NVMe standard, the Forced Response Management Unit 122 determines that the Forced Response Completion Time is an invalid value. FRL is an internal parameter of the storage system 3. FRL represents the limit of time it takes for a partition transitioning to the open state to reach the write-full state.

[0152] If at least one of the calculated forced response completion time and forced response start time is invalid, the forced response management unit 122 notifies the host 2 of the error in the setting command.

[0153] If the calculated forced response completion time and forced response start time are valid values, the forced response management unit 122 appends the obtained namespace ID, along with the calculated forced response completion time and forced response start time, to the NS response management table 23. Furthermore, if an entry corresponding to the obtained namespace ID already exists in the NS response management table 23, the entry is updated using the calculated forced response completion time and forced response start time.

[0154] Furthermore, when the value of forced_completion_time m specified by the setting command is 0, the forced response management unit 122 updates the NS response management table 23 without initiating a forced response. More specifically, when the value of forced_completion_time m is 0 and an entry corresponding to the namespace ID specified by the setting command exists in the NS response management table 23, the forced response management unit 122 deletes that entry from the NS response management table 23. Additionally, when the value of forced_completion_time m is 0 and an entry corresponding to the namespace ID specified by the setting command does not exist in the NS response management table 23, the forced response management unit 122 does not append an entry corresponding to that namespace ID to the NS response management table 23.

[0155] Based on the above configuration, the storage system 3 can initiate the forced response to the write command according to the namespace control based on the setting command received from the host 2.

[0156] Figure 12 This is a block diagram representing an example of an action corresponding to a write force response acknowledgment command in storage system 3. A write force response acknowledgment command is a command that requests information about the time elapsed until a force response is initiated in response to a write command. The write force response acknowledgment command is implemented, for example, as the Get Features command as defined in the NVMe standard. Hereinafter, the write force response acknowledgment command will also be referred to as an acknowledgment command.

[0157] Host 2 sends an acknowledgment command to storage system 3. Figure 12 (1) in the confirmation command. For example, a namespace ID is specified in the confirmation command.

[0158] The command receiving unit 121 of the storage system 3 receives the confirmation command sent by the host 2. Furthermore, the command receiving unit 121 sends the confirmation command to the mandatory response management unit 122. Figure 12 (2) in the middle.

[0159] Based on the confirmation command, the mandatory response management unit 122 obtains information related to the time of initiating the mandatory response from the NS response management table 23. Figure 12 (3)). Specifically, firstly, the Forced Response Management Unit 122 obtains the namespace ID specified by the confirmation command. The Forced Response Management Unit 122 determines the entry in the NS Response Management Table 23 that contains the obtained namespace ID. Furthermore, the Forced Response Management Unit 122 obtains at least one of the forced response completion time and the forced response start time from the determined entry.

[0160] The mandatory response management unit 122 uses at least one of the acquired mandatory response completion time and mandatory response initiation time to generate information related to the time of initiation of the mandatory response and sends it to the command receiving unit 121. Figure 12 (4)). This information may represent, for example, at least one of the forced response completion time and the forced response start time. Alternatively, this information may also represent information associated with at least one of the forced response completion time and the forced response start time (e.g., the value m of forced_completion_time and the value n of process_time).

[0161] Then, the command receiving unit 121 sends a response containing information related to the time of initiating the forced response to the host 2. Figure 12 (5) in the middle.

[0162] Based on the above configuration, the storage system 3 can provide the host 2 with information about the time to initiate a forced response corresponding to the specified namespace, based on the confirmation command received from the host 2.

[0163] Figure 13 This is a block diagram representing an example of an action corresponding to a write command in storage system 3.

[0164] The controller 4 of the storage system 3 is configured to perform write operations based on a delayed write completion mechanism. Simultaneously, if the elapsed time after receiving a write command reaches the forced response start time, it forcibly begins writing the corresponding user data to the NAND flash memory 5. Once the controller 4 becomes capable of reading the written user data, it sends a response to the host 2 indicating that the processing corresponding to the write command has been completed.

[0165] Additionally, controller 4 manages at least one storage region (referred to as NAND partition 51) and at least one shared write buffer 52 within the NAND flash memory 5 corresponding to at least one partition. NAND partition 51 is a storage region obtained by logically dividing the storage region of NAND flash memory 5. Shared write buffer 52 is a storage region that non-volatilely stores user data to be written to at least one NAND partition 51.

[0166] Each of at least one NAND partition 51 is associated with, for example, any one of at least one shared write buffer 52. Furthermore, a shared write buffer 52 may be associated with more than one NAND partition 51. That is, a shared write buffer 52 may be shared by more than one NAND partition 51. Information indicating the correspondence between NAND partition 51 and shared write buffer 52 is stored, for example, in DRAM 6.

[0167] The configuration and operation of host 2 are the same as those of host 2A in the first comparative example and host 2B in the second comparative example.

[0168] The following explanation focuses on the differences between the operation of storage system 3 and the storage system 3A of the first comparative example and the storage system 3B of the second comparative example.

[0169] The command receiving unit 121 of storage system 3 retrieves the write command from the position indicated by the SQ head pointer in the submission queue 401. Figure 13 (1)). A write command is associated with user data that should be written to any of the at least one partition. More specifically, the write command specifies, for example, the command ID, LBA, data length, data buffer information, and namespace ID.

[0170] Command receiving unit 121 sends the acquired write command to write control unit 123. Figure 13 (2)). Hereinafter, the obtained write command will also be referred to as the first object write command.

[0171] The write control unit 123 obtains the command ID, LBA, data length, and data buffer information specified by the first object write command. The write control unit 123 determines the partition including the obtained LBA. Using the obtained command ID, LBA, data length, data buffer information, and the determined partition, the write control unit 123 updates the write management table 26. Figure 13 (3)). Furthermore, the write control unit 123 uses the write management table 26 to determine whether the host 2's data buffer 403 stores user data for a write unit of a partition.

[0172] When the data buffer 403 stores user data for a write unit of a partition, the write control unit 123 transfers the user data of the write unit from the data buffer 403 to the NAND flash memory 5, and writes (programs) the transferred user data of the write unit into the NAND partition 51 (here, NAND partition 511) within the NAND flash memory 5. Figure 13 (4)). Additionally, the user data of the written unit can be cached in DRAM6. The user data of the written unit is, for example, data combining multiple user data that should be written according to multiple write commands. The multiple write commands include a first object write command.

[0173] Then, if a write command exists that enables the reading of corresponding user data from the NAND flash memory 5, the write control unit 123 notifies the command receiving unit 121 of the completion of the processing corresponding to the write command. Figure 13 (5)). The write control unit 123 notifies the command receiving unit 121 of the completion of processing for multiple write commands corresponding to user data of the writing unit. In addition, the write control unit 123 deletes the entry corresponding to each of the multiple write commands from the write management table 26. Figure 13 (6) in the middle.

[0174] Whenever the command receiving unit 121 receives a notification from the write control unit 123, it sends a response to the host 2 indicating that the processing corresponding to the write command has been completed. More specifically, based on the notification from the write control unit 123, the command receiving unit 121 writes the completion notification of the corresponding write command to the position indicated by the CQ tail pointer in the completion queue 402 and issues an interrupt. Figure 13 (7)). The notification from the write control unit 123 includes, for example, the command ID of the completed write command. The actions of the command receiving unit 121 and the host 2 after the interruption are the same as those of the command receiving unit 121A and the host 2A in the first comparative example.

[0175] Furthermore, in the event of an error during the writing (programming) of user data, the write control unit 123 and the command receiving unit 121 send a response to the host 2 indicating that an error occurred during the processing corresponding to the write command. That is, the command receiving unit 121 writes an error notification for the write command to the position indicated by the CQ tail pointer in the completion queue 402.

[0176] Furthermore, if the data buffer 403 of host 2 does not store user data for a write unit of a partition, the write control unit 123 will not write user data to the NAND flash memory 5. Additionally, the write control unit 123 instructs the forced response management unit 122 to manage the first object write command ( Figure 13 (8) in the instruction. For example, the instruction includes the command ID and namespace ID specified by the write command of the first object.

[0177] The Forced Response Management Unit 122, based on the instructions of the Write Control Unit 123, determines the entry corresponding to the namespace ID in the NS Response Management Table 23. The Forced Response Management Unit 122 then retrieves the forced response start time from the determined entry. Figure 13 (9)). That is, the Forced Response Management Unit 122 obtains the Forced Response Start Time from the NS Response Management Table 23, which should force the start of the processing corresponding to the write command of the first object.

[0178] Next, the forced response management unit 122 adds an entry containing the command ID from the instruction issued by the write control unit 123 and the obtained forced response start time to the command response management table 24. Figure 13 (10)). The forced response start time is used as the initial value for the remaining time (i.e., the time until start) until the forced start of processing corresponding to the write command of the first object.

[0179] The forced response management unit 122 reduces the time up to the start date contained in each entry of the command response management table 24, for example, based on the elapsed time measured by the timer 16. Furthermore, when the time up to the start date becomes 0 (that is, when the forced response start time has elapsed from acceptance to the corresponding write command), the forced response management unit 122 instructs the write control unit 123 to forcibly begin processing corresponding to the write command. Figure 13 (11) in the instruction. For example, the command ID in the entry where the time until startup becomes 0 is included. Hereinafter, the write command represented by the entry where the time until startup becomes 0 (i.e., the write command that should force the start of the corresponding process) will be referred to as the second object write command.

[0180] The write control unit 123, based on the instructions of the mandatory response management unit 122, retrieves an entry containing the command ID from the write management table 26. Figure 13 (12)). Hereinafter, the entry containing the command ID in the instruction will be referred to as the first entry. In addition, it is assumed that the NAND partition 51 corresponding to the partition represented by the first entry is the NAND partition 512. The write control unit 123 uses the first entry to transfer the user data that should be written according to the second object write command from the data buffer 403 to the NAND flash memory 5. Figure 13 (13)). In addition, the transmitted user data can also be cached in DRAM6.

[0181] The write control unit 123 writes the transmitted user data into the shared write buffer 52 (here, shared write buffer 521) of the NAND flash memory 5 using a padding method. Figure 13 (13)). The write control unit 123 can determine the user data to be written according to the second object write command by using the LBA, data length and data buffer information contained in the first entry. The shared write buffer 521 to which the user data is written is associated with the NAND partition 51 (in this NAND partition 512) to which the user data should have been written. In addition, writing user data in a padded manner means writing data consisting of user data and padded data in write units.

[0182] For writing data to the shared write buffer 52, the QLC method can also be used. For writing data to the shared write buffer 52, the Single-Level Cell (SLC) method, which stores 1 bit of data in each memory cell, can also be used.

[0183] Furthermore, if there is one or more entries in the write management table 26 that include the same partition as the partition represented by the first entry, the write control unit 123 may also use the first entry and the aforementioned one or more entries to transfer multiple user data that should be written according to the corresponding multiple write commands from the data buffer 403 to the NAND flash memory 5, and write the transferred multiple user data into the shared write buffer 521 in a padded manner. Figure 13 (13) in the middle.

[0184] Here, the operation of the write control unit 123 will be described when NAND partition 511, which is different from NAND partition 512, is also associated with the shared write buffer 521. In this case, the write control unit 123 further uses one or more entries in the write management table 26 that respectively include the partition corresponding to the other NAND partition 511. The write control unit 123 may also determine one or more user data that should be written according to one or more corresponding write commands. Moreover, the write control unit 123 may include the determined one or more user data in the user data that is the object of transmission from the aforementioned data buffer 403 and writing to the shared write buffer 521. At this time, the time to startup corresponding to one or more write commands managed in the command response management table 24 may also be considered. For example, only the user data corresponding to write commands whose time to startup is less than a threshold may be included in the user data that is the object of transmission from the aforementioned data buffer 403 and writing to the shared write buffer 521.

[0185] For example, consider the following scenario: Before the mandatory response start time elapses after the second object write command is received, the command receiving unit 121 retrieves a write command from the submission queue 401 that targets a partition corresponding to NAND partition 511, which is different from NAND partition 512. Both NAND partitions 511 and 512 are associated with a shared write buffer 521. Hereinafter, the retrieved write command targeting the partition corresponding to NAND partition 511 will be referred to as the third object write command. The third object write command is managed using the write management table 26 and the command response management table 24.

[0186] If a forced response start time has elapsed since the second object write command was received, the write control unit 123 transfers the user data to be written according to the second object write command and the user data to be written according to the third object write command from the data buffer 403 to the NAND flash memory 5. Furthermore, the write control unit 123 writes data containing the transferred user data into the shared write buffer 521. More specifically, if the size of the transferred user data is equivalent to a write unit, the write control unit 123 writes the transferred user data into the shared write buffer 521. Conversely, if the size of the transferred user data is less than a write unit, the write control unit 123 writes the transferred user data into the shared write buffer 521 with padding.

[0187] Thus, when the NAND partition 51 (here, NAND partition 512) corresponding to the partition targeted by the second object write command that has undergone a forced response start time and another NAND partition 51 (here, NAND partition 511) corresponding to the partition targeted by the third object write command are both associated with the shared write buffer 521, the user data corresponding to the third object write command can also be included in the user data that becomes the object of transmission from the aforementioned data buffer 403 and writing to the shared write buffer 521.

[0188] Next, if a write command is issued that enables the reading of corresponding user data from the NAND flash memory 5, the write control unit 123 notifies the command receiving unit 121 and the forced response management unit 122 of the completion of the processing corresponding to the write command. Figure 13 (14)). Additionally, the write control unit 123 will delete entries corresponding to more than one write command from the write management table 26. Figure 13 (15)). Deleting more than one write command from the write management table 26 includes the write command for the second object corresponding to the first entry.

[0189] Whenever the command receiving unit 121 receives a notification from the write control unit 123, it sends a response to the host 2 indicating that the processing corresponding to the write command has been completed. More specifically, based on the notification from the write control unit 123, the command receiving unit 121 writes the completion notification of the corresponding write command to the position indicated by the CQ tail pointer in the completion queue 402 and issues an interrupt. Figure 13 (16)). The subsequent operation of the command receiving unit 121 and the host 2 is the same as that of the command receiving unit 121A and the host 2A in the first comparative example.

[0190] Furthermore, in the event of an error during the writing (programming) of user data, the write control unit 123 and the command receiving unit 121 send a response to the host 2 indicating that an error occurred during the processing corresponding to the write command. That is, the command receiving unit 121 writes an error notification for the write command to the position indicated by the CQ tail pointer in the completion queue 402.

[0191] Furthermore, based on the notification from the write control unit 123, the mandatory response management unit 122 deletes one or more entries corresponding to one or more write commands from the command response management table 24. Figure 13(17)). The notification from the write control unit 123 may include, for example, information indicating the command ID of each of the more than one write commands that have been processed, and information indicating the NAND partition 51 (here, for example, NAND partition 512). The NAND partition 51 included in the notification is the NAND partition 51 that was originally supposed to have user data corresponding to the more than one write command written to. The forced response management unit 122 instructs the partition management unit 124 to change the status of the partition corresponding to the NAND partition 51 included in the notification from the open state to the closed state. Figure 13 (18) in the middle.

[0192] According to the instructions of the forced response management unit 122, the partition management unit 124 changes the partition corresponding to NAND partition 51 from the open state to the closed state. Figure 13 (19)). The partition management unit 124, for example, updates the partition descriptor 25 so that the partition corresponding to NAND partition 512 is in a closed state. Then, the partition management unit 124 notifies the host 2 of the change in the state of the partition corresponding to NAND partition 512. Figure 13 (20)). Furthermore, when user data for a partition corresponding to another NAND partition 51 (here, NAND partition 511) is also written to the shared write buffer 521 that is associated with NAND partition 512, the write control unit 123, the forced response management unit 122, and the partition management unit 124 operate in such a way that the partition corresponding to the other NAND partition 511 is also changed from the open state to the closed state.

[0193] Furthermore, if the host 2's data buffer 403 does not store user data for a write unit of a region and there is no write command whose elapsed time after acceptance reaches the forced response start time (i.e., the time until start becomes 0), the command acceptance unit 121, the write control unit 123, and the forced response management unit 122 can repeatedly perform the actions of obtaining write commands from the submission queue 401 and updating the write management table 26 and the command response management table 24 based on the obtained write commands.

[0194] Through the above actions, in the storage system 3 of this embodiment, when the total amount of user data requested to be written to a partition by multiple write commands from the host 2 reaches a write unit, the controller 4 writes the write unit of user data to the NAND partition 51 corresponding to that partition. Furthermore, the controller 4 returns a response to each of the multiple write commands to the host 2. Thus, in the storage system 3, the storage area of ​​the NAND flash memory 5 can be effectively utilized.

[0195] Furthermore, if a write command is executed and the elapsed time reaches the mandatory response start time, controller 4 writes the corresponding user data to the shared write buffer 52 instead of writing it to the NAND partition 51. Additionally, controller 4 sends a completion notification of the write command to host 2.

[0196] Thus, in cases where (1) the user data to be written to the partition to which the write command is destined is stored in data buffer 403 before the mandatory response start time is reached after the elapsed time following the receipt of the write command, and in cases where (2) a write command exists after the elapsed time following the receipt of the write command has reached the mandatory response start time, the controller 4 switches the write destination of the user data. In case (1), the writing of the corresponding user data to the NAND partition 51 begins before the mandatory response start time is reached after the elapsed time following the receipt of the write command, so the controller 4 can respond to the write command within the time expected by the host 2. In addition, in case (2), by writing the corresponding user data to the shared write buffer 52, the controller 4 can respond to the write command within the time expected by the host 2.

[0197] Therefore, in storage system 3, write commands can be responded to within the time expected by host 2, while effectively utilizing the storage area of ​​NAND flash memory 5.

[0198] Furthermore, the operations in the aforementioned storage system 3 are not limited to the case of managing data stored in the NAND flash memory 5 by partition, but can also be applied to the case of managing data stored in the NAND flash memory 5 by LBA. In this case, the operations of the partition management unit 124 (e.g., the transition of a partition to a closed state, or the notification of a partition state change to the host 2) are not performed.

[0199] In this configuration, controller 4 manages at least one storage region and at least one shared write buffer 52 within the NAND flash memory 5. The at least one storage region is a logically partitioned storage region of the NAND flash memory 5. Each of the at least one storage region corresponds to at least one LBA.

[0200] Next, refer to Figures 14 to 20 The flowchart illustrates the steps of the processing performed in storage system 3 and host 2.

[0201] (The process for setting up a forced response in storage system 3)

[0202] Figure 14This is a flowchart illustrating an example of the setup process steps performed by CPU 12. CPU 12 begins setup processing upon receiving a setup command from host 2. Setup processing is used to set the time from when CPU 12 accepts a write command until it forcibly begins processing corresponding to that write command.

[0203] First, CPU12 obtains the namespace ID specified by the setting command (step S101). Then, CPU12 obtains the value m of forced_completion_time specified by the setting command (step S102). m is, for example, an integer greater than or equal to 0.

[0204] Next, CPU 12 determines whether the obtained value m of forced_completion_time is 0 (step S103). If the value m of forced_completion_time is 0 (step S103: Yes), CPU 12 determines whether there is an entry in the NS response management table 23 corresponding to the obtained namespace ID (step S104). If there is an entry in the NS response management table 23 corresponding to the obtained namespace ID (step S104: Yes), CPU 12 deletes the entry corresponding to the obtained namespace ID from the NS response management table 23 (step S105) and ends the setting process. Thus, CPU 12 performs the setting in a way that does not forcibly start the processing and response of write commands that use the namespace associated with the obtained namespace ID as the object.

[0205] If no entry corresponding to the acquired namespace ID exists in the NS response management table 23 (step S104: No), the CPU 12 ends the configuration process. That is, the CPU 12 has been configured not to forcibly start the processing and response of write commands that use the namespace associated with the acquired namespace ID as the object, so the configuration process ends.

[0206] Furthermore, if the value of forced_completion_time m is not 0 (step S106: No), that is, if it is 1 or more, CPU 12 calculates m × 100 milliseconds as the forced response completion time (step S106). Then, CPU 12 obtains the value of process_time n (step S107). CPU 12 calculates (mn) × 100 milliseconds as the forced response start time (step S108).

[0207] CPU12 determines whether the calculated forced response completion time and forced response start time are valid values ​​(step S109). If at least one of the calculated forced response completion time and forced response start time is invalid (step S109: No), CPU12 notifies host 2 of the error (step S110) and ends the setting process.

[0208] If the calculated forced response completion time and forced response start time are valid values ​​(step S109: Yes), CPU 12 determines whether there is an entry in NS response management table 23 corresponding to the obtained namespace ID (step S111). If there is an entry in NS response management table 23 corresponding to the obtained namespace ID (step S111: Yes), CPU 12 updates the entry using the calculated forced response completion time and forced response start time (step S112) and ends the setting process. Thus, CPU 12 can change the forced response completion time and forced response start time associated with the specified namespace according to the setting command.

[0209] On the other hand, if there is no entry in the NS response management table 23 corresponding to the acquired namespace ID (step S111: No), the CPU 12 appends an entry including the acquired namespace ID, the calculated forced response completion time, and the forced response start time to the NS response management table 23 (step S113) and ends the setting process. Thus, the CPU 12 can set the forced response completion time and forced response start time associated with the specified namespace according to the setting command.

[0210] Through the above configuration process, CPU12 can set (change) whether to initiate a forced response when a write command targeting a specified namespace is accepted, according to the configuration command. Furthermore, CPU12 can set the time from accepting a write command to forcibly starting the processing corresponding to that write command, according to the configuration command.

[0211] (The process for initiating a forced response in storage system 3)

[0212] Figure 15 This is a flowchart illustrating an example of the confirmation process performed by CPU 12. CPU 12 begins the confirmation process upon receiving a confirmation command from host 2. The confirmation process provides host 2 with information related to the timing of the forced response start for the namespace setting.

[0213] First, CPU 12 obtains the namespace ID specified by the setting command (step S201). CPU 12 determines the entry corresponding to the obtained namespace ID in the NS response management table 23 (step S202). CPU 12 obtains the forced response completion time from the determined entry (step S203). Then, CPU 12 sends the obtained forced response completion time to host 2 (step S204). Furthermore, CPU 12 may also send information associated with the forced response completion time to host 2. The information associated with the forced response completion time is, for example, the value m of forced_completion_time converted to a value in 100 milliseconds (= forced response completion time / 100).

[0214] Alternatively, CPU12 can retrieve the forced response start time from the determined entries and send it to host 2. Or, CPU12 can send information associated with the forced response start time to host 2. This information might include, for example, the forced response start time converted to a value in 100 milliseconds, i.e., the difference mn between the value m of forced_completion_time and the value n of process_time.

[0215] Through the above confirmation process, CPU12 can provide host 2 with information related to at least one of the forced response completion time and forced response start time set for the namespace, based on the confirmation command.

[0216] (Processing in host 2 for writing user data to storage system 3)

[0217] Figure 16 This is a flowchart illustrating an example of the steps involved in a write request processing performed on host 2. Write request processing is the process used by host 2 to request the writing of user data to storage system 3. Write request processing is performed, for example, by an executable program set up on the processor of host 2.

[0218] Host 2 stores the user data that should be written to the NAND flash memory 5 of storage system 3 in data buffer 403 (step S301). Then, host 2 writes a write command to the position in the commit queue 401 indicated by the SQ tail pointer (step S302). This write command is a write command requesting the writing of the stored user data.

[0219] Next, host 2 increments the SQ tail pointer by 1 (step S303). Furthermore, if the value obtained by incrementing the SQ tail pointer by 1 reaches the number of slots in the submission queue 401, host 2 sets the SQ tail pointer to 0. Then, host 2 writes the updated SQ tail pointer value to the SQ tail pointer register in storage system 3 (step S304).

[0220] Through the above write request processing, host 2 can request storage system 3 to write user data stored in data buffer 403. Host 2 issues a write command to storage system 3 via submit queue 401, thereby requesting storage system 3 to write user data.

[0221] Figure 17 This is a flowchart illustrating an example of the steps involved in response reception processing performed in host 2. Response reception processing is the process by which host 2 receives a response to a write command from storage system 3. Response reception processing is performed, for example, by an execution program configured on the processor of host 2. Host 2 begins execution of response reception processing upon receiving an interrupt issued by storage system 3.

[0222] First, host 2 retrieves a completion notification from the position in the completion queue 402 indicated by the CQ header pointer (step S401). This completion notification is a response indicating that the writing of user data to the NAND flash memory 5 according to the write command issued by host 2 has been completed.

[0223] Next, host 2 increments the CQ head pointer by 1 (step S402). Furthermore, if the value obtained by incrementing the CQ head pointer reaches the number of slots in the completion queue 402, host 2 sets the CQ head pointer to 0. Host 2 writes the updated CQ head pointer value to the CQ Head pointer register of storage system 3 (step S403). Then, host 2 clears the interrupt received from storage system 3 (step S404).

[0224] Next, based on the acquired completion notification, host 2 releases the area in data buffer 403 that stores the user data that has been written (step S405).

[0225] Through the above response receiving process, host 2 can release the area in data buffer 403 that stores the user data after the writing of the user data corresponding to the issued write command has been completed.

[0226] Furthermore, host 2 can also receive a notification from storage system 3 indicating that a partition has transitioned to a closed state during response reception processing. More specifically, host 2 may receive a notification indicating that a partition where user data was originally written has transitioned to a closed state, in the case where user data corresponding to a published write command has been written based on the initiation of a forced response. Based on this notification, host 2 may, for example, stop issuing write commands requesting the writing of user data to that partition.

[0227] (Processing for writing user data in storage system 3)

[0228] Figure 18 This is a flowchart illustrating an example of the steps of write control processing performed by CPU 12. Write control processing is the process by which CPU 12 receives write commands issued by host 2 and controls the writing of user data corresponding to the accepted write commands. Here, for ease of understanding, an example is shown where CPU 12 receives only write commands from host 2's submission queue 401.

[0229] First, CPU12 determines whether the SQ head pointer is equal to the SQ tail pointer (step S501). That is, CPU12 uses the SQ head pointer and SQ tail pointer to determine whether there is a write command that should be retrieved in the submission queue 401.

[0230] If the SQ head pointer and SQ tail pointer are different (step S501: No), a write command that should be retrieved exists in the commit queue 401, so CPU 12 executes command acceptance processing (step S502). Command acceptance processing is the process by which CPU 12 accepts write commands and obtains information managing the accepted write commands. More specifically, in command acceptance processing, the write management table 26 is updated according to the accepted write command. The write management table 26 manages, for example, information related to the accepted write command by partition where corresponding user data should be written. See later. Figure 19 The flowchart illustrates the specific steps involved in accepting and processing the command.

[0231] Next, CPU 12 determines whether user data for a write unit of a partition is stored in the data buffer 403 of host 2 (step S503). If user data for a write unit of a partition is stored in the data buffer 403 (step S503: Yes), CPU 12 transfers the user data for the write unit from the data buffer 403 to the DRAM 6 of storage system 3 (step S504). Hereinafter, the partition where the user data for the write unit should be written is referred to as the first target partition. In addition, the NAND partition 51 corresponding to the first target partition is also referred to as the first target NAND partition 51. CPU 12 transfers the received user data to the NAND flash memory 5 and writes it to the first target NAND partition 51 (step S505). Alternatively, CPU 12 may transfer the user data for the write unit from the data buffer 403 to the NAND flash memory 5 without caching it in DRAM 6.

[0232] Next, CPU 12 determines whether there is a write command that enables the reading of the corresponding user data (step S506). If there is no write command that enables the reading of the corresponding user data (step S506: No), CPU 12 returns to step S506. That is, since it is not yet possible to notify host 2 that the writing of the user data corresponding to the write command has been completed, CPU 12 returns to step S506.

[0233] If a write command exists that enables the reading of the corresponding user data (step S506: Yes), CPU 12 executes response processing (step S507). Response processing is used to notify host 2 that the writing of the user data corresponding to the write command has been completed and to update the information managing the write command. See below for further details. Figure 20 The flowchart illustrates the specific steps of response processing.

[0234] Then, CPU12 determines whether all write commands corresponding to the user data of the write unit written in step S505 have been responded to (step S508). If at least one of the write commands corresponding to the user data of the write unit has not been responded to (step S508: No), the processing of CPU12 returns to step S506.

[0235] On the other hand, after responding to all write commands corresponding to the user data of the write unit (step S508: Yes), the processing of CPU 12 proceeds to step S501. That is, CPU 12 continues to perform processing for accepting new write commands from host 2 and controlling the writing of user data corresponding to the accepted write commands.

[0236] Additionally, if no user data for a write unit to a partition is stored in the data buffer 403 of host 2 (step S503: No), CPU 12 updates the command response management table 24 using the write command accepted in step S502 (step S509), and the processing of CPU 12 proceeds to step S510. Specifically, CPU 12 obtains the forced response start time from NS response management table 23 using the namespace ID specified by the write command accepted in step S502. Moreover, CPU 12 appends an entry including the command ID specified by the write command and the obtained forced response start time to the command response management table 24. The forced response start time in the appended entry is used as the initial value of the time until the forced start of the processing corresponding to the write command (i.e., the time until start). CPU 12 reduces the time until start contained in each entry of the command response management table 24, for example, according to the elapsed time measured by timer 16.

[0237] In addition, if the SQ head pointer and the SQ tail pointer are equal (step S501: Yes), the CPU12 process also proceeds to step S510.

[0238] Next, the CPU 12 determines whether there is a write command whose elapsed time after acceptance has reached the mandatory response start time (step S510). Specifically, for example, if the command response management table 24 includes an entry indicating that the time up to the start time has become 0, the CPU 12 determines that there is a write command whose elapsed time after acceptance has reached the mandatory response start time.

[0239] If there is no write command whose time has elapsed since acceptance has reached the mandatory response start time (step S510: No), the processing of CPU12 proceeds to step S501.

[0240] If a write command is received and the elapsed time reaches the mandatory response start time (step S510: Yes), CPU 12 determines the partition (hereinafter referred to as the second object partition) where user data corresponding to the write command should be written (step S511). CPU 12 determines the second object partition, for example, using write management table 26. Then, CPU 12 transfers the user data to be written to the second object partition from the data buffer 403 of host 2 to DRAM 6 of storage system 3 (step S512). More specifically, CPU 12 determines, for example, at least one piece of user data to be written to the second object partition using write management table 26. The at least one piece of user data corresponds to at least one write command. CPU 12 transfers the determined at least one piece of user data from data buffer 403 to DRAM 6. The size of the transferred user data is smaller than the write unit corresponding to NAND flash memory 5.

[0241] Next, CPU 12 writes the received user data to shared write buffer 52 with padding (step S513). That is, CPU 12 writes the data to the shared write buffer 52 by adding padding data to the user data. The shared write buffer 52, where user data is written, is associated with the NAND partition 51 corresponding to the second object partition. Furthermore, CPU 12 can also transfer user data from data buffer 403 to NAND flash memory 5 without caching it in DRAM 6.

[0242] Next, CPU12 determines whether there is a write command that enables the reading of the corresponding user data (step S514). If there is no write command that enables the reading of the corresponding user data (step S514: No), the processing of CPU12 returns to step S514.

[0243] If a write command exists that enables the reading of the corresponding user data (step S514: Yes), CPU 12 performs response processing (step S515). That is, CPU 12 notifies host 2 that the writing of the user data corresponding to the write command has been completed, and updates the information managing the write command.

[0244] Then, CPU 12 determines whether all write commands corresponding to the user data written in step S513 have been responded to (step S516). If at least one of the write commands corresponding to the written user data has not been responded to (step S516: No), the processing of CPU 12 returns to step S514.

[0245] On the other hand, after responding to all write commands corresponding to the written user data (step S516: Yes), CPU 12 changes the second object partition to a closed state (step S517). Then, CPU 12 notifies host 2 of the change in the state of the second object partition (step S518), and the processing of CPU 12 proceeds to step S501.

[0246] Alternatively, CPU 12 may not bring the second object partition to a closed state, but instead bring it to a full state. For example, in step S513, CPU 12 writes the transmitted user data and padding data to the shared write buffer 52 in a state where data has been written to the entire second object partition (full state). In this case, after responding to all write commands corresponding to the written user data, CPU 12 notifies host 2, for example, that the second object partition has become full. Then, CPU 12's processing proceeds to step S501.

[0247] Through the above write control processing, CPU12 can accept write commands from host 2 and control the writing of user data corresponding to the accepted write commands.

[0248] Specifically, when the data buffer 403 stores user data for a write unit that should be written to the first object partition, the CPU 12 writes the user data for that write unit to the first object NAND partition 51. Furthermore, the CPU 12 returns a completion notification to the host 2 for the write command corresponding to the completed write data.

[0249] Furthermore, in the case of a write command where the elapsed time after acceptance reaches the mandatory response start time, CPU 12 determines that the corresponding user data should be written to the second object partition. CPU 12 writes the user data stored in data buffer 403 that should be written to the second object partition to the shared write buffer 52, without writing to the NAND partition 51. Furthermore, CPU 12 returns a completion notification to host 2 for the write command corresponding to the completed user data.

[0250] Thus, the storage system 3 can respond to write commands within the time expected by the host 2, while effectively utilizing the storage area of ​​the NAND flash memory 5.

[0251] Figure 19 This is a flowchart illustrating an example of the command acceptance and processing steps performed by CPU12. Command acceptance and processing is used to accept write commands and obtain information managing the accepted write commands. Command acceptance and processing is equivalent to the steps outlined above. Figure 18 The write control processing step S502.

[0252] First, CPU 12 retrieves a write command from the position in the commit queue 401 indicated by the SQ header pointer (step S601). CPU 12 increments the SQ header pointer by 1 (step S602). Furthermore, if the number of times the SQ header pointer is incremented by 1 reaches the number of slots in the commit queue 401, CPU 12 sets the SQ header pointer to 0.

[0253] Next, CPU 12 obtains the command ID, LBA, data length, and data buffer information from the acquired write command (step S603). CPU 12 determines the partition that includes the acquired LBA (step S604). That is, CPU 12 determines the partition that has been allocated an LBA range including the acquired LBA.

[0254] Then, CPU12 updates the write management table 26 (step S605) and ends the command acceptance process. Specifically, CPU12 appends the entry representing the obtained command ID, LBA, data length, data buffer information, and the determined partition to the write management table 26.

[0255] Through the above command processing, CPU 12 can accept write commands from host 2 and obtain information for managing the accepted write commands. CPU 12 uses the information for managing the obtained write commands to update write management table 26. CPU 12 can use write management table 26 to manage user data that should be written to NAND flash memory 5 according to each write command.

[0256] Figure 20 This is a flowchart illustrating an example of the response processing steps performed by CPU 12. Response processing is used to notify host 2 that the writing of user data corresponding to the write command has been completed and to update the information managing the write command. Response processing is equivalent to the steps outlined above. Figure 18 The write control processing steps S507 and S515 are described above.

[0257] First, CPU12 writes a completion notification of the object write command to the position in the completion queue 402 indicated by the CQ tail pointer (step S701). The object write command is a write command indicating that the writing of corresponding user data to the NAND flash memory 5 has been completed.

[0258] Next, CPU 12 increments the CQ tail pointer by 1 (step S702). Furthermore, if the number of times the CQ tail pointer is incremented reaches the number of slots in the completion queue 402, CPU 12 sets the CQ tail pointer to 0. Then, CPU 12 issues an interrupt to host 2 (step S703). CPU 12 notifies host 2 of the existence of a new completion notification that should be processed in the completion queue 402 by issuing the interrupt.

[0259] CPU 12 updates the write management table 26 (step S704). Specifically, CPU 12 deletes the entry corresponding to the object write command from the write management table 26. Then, CPU 12 updates the command response management table 24 (step S705) and ends the response processing. Specifically, CPU 12 deletes the entry corresponding to the object write command from the command response management table 24. Furthermore, if there is no entry corresponding to the object write command in the command response management table 24, CPU 12 skips step S705 and ends the response processing. For example, if it is determined that the CPU 12 has accepted the object write command and that the write user data for a region is stored in the data buffer 403, the entry corresponding to the object write command is not appended to the command response management table 24. In this case, CPU 12 skips step S705.

[0260] Through the above response processing, CPU12 can notify host 2 that the writing of user data corresponding to the write command has been completed, and update the information managing the write command.

[0261] As described above, according to this embodiment, the storage system 3 can respond to write requests within the time expected by the host 2. The controller 4 receives a first write request from the host 2, which is associated with first data having a size smaller than a first data unit that is a write unit to the NAND flash memory 5. The controller 4 begins writing a second data unit containing at least the first data to the NAND flash memory 5 based on the first time elapsed since the acceptance of the first write request. Upon completion of the write process, the controller 4 sends a first response to the first write request to the host 2. The first time is the time obtained by subtracting a third time from a second time, and the second time is specified by the host 2 as a time limit from the acceptance of the first write request to the sending of the first response.

[0262] Thus, the controller 4 forcibly begins writing the second data, which contains at least the first data associated with the first write request, to the NAND flash memory 5 based on the first time elapsed since the first write request was received, so that it can respond to the first write request within the time expected by the host 2.

[0263] Each of the various functions described in this embodiment can also be implemented by a circuit (processing circuit). Examples of processing circuits include a programmed processor such as a central processing unit (CPU). This processor executes the various functions described in this embodiment by executing a computer program (instruction set) stored in memory. The processor can also be a microprocessor that includes circuitry. Examples of processing circuits also include digital signal processors (DSPs), application-specific integrated circuits (ASICs), microcontrollers, controllers, and other circuit components. Other components besides the CPU described in this embodiment can also be implemented by the processing circuit.

[0264] Several embodiments of the present invention have been described, but these embodiments are provided by way of example and are not intended to limit the scope of the invention. These new embodiments can be implemented in a wide variety of other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and / or variations thereof are included within the scope and / or spirit of the invention, and are included within the scope of the invention described in the technical solution and its equivalents.

Claims

1. A storage system comprising: Non-volatile memory; as well as The controller is configured as follows: The host accepts a first write request associated with first data having a size smaller than the first data unit, the first data unit being a write unit to the non-volatile memory; If the host does not issue a subsequent write request after issuing the first write request, the write process of the first data to the non-volatile memory will not begin. Based on the fact that a first time has elapsed since the acceptance of the first write request, a write process for second data, which contains at least the first data, to the non-volatile memory begins, wherein the second data has the size of the first data unit; Based on the completion of the write process, a first response to the first write request is sent to the host. The first time is obtained by subtracting the third time from the second time. The second time, as the time limit from acceptance of the first write request to the sending of the first response, is specified by the host. The third time corresponds to the time from the start of the write process of the second data to the non-volatile memory until the second data becomes readable from the non-volatile memory.

2. The storage system according to claim 1, The second data includes the first data and the padding data.

3. The storage system according to claim 1, The controller retrieves the first data from the host at the start of the write process of the second data.

4. The storage system according to claim 1, The controller further initiates a write process for a fourth data unit, comprising the first data and the third data, to the non-volatile memory based on a second write request associated with the third data received before the first time elapses from the acceptance of the first write request. The fourth data unit has the size of the first data unit.

5. The storage system according to claim 4, The controller further sends a first response to the first write request and a second response to the second write request to the host based on the completion of the write process for the fourth data.

6. The storage system according to claim 4, The controller further, The management system logically divides the logical address space provided by the storage system to the host into multiple partitions, including at least a first partition. The writing process for the fourth data begins when both the first write request and the second write request target the first partition.

7. The storage system according to claim 6, The controller further, Manage at least one first storage region corresponding to the plurality of partitions, wherein the at least one first storage region is a local storage region obtained by logically dividing the storage region of the non-volatile memory. The fourth data is written to the first storage area corresponding to the first partition.

8. The storage system according to claim 6, The plurality of partitions also includes a second partition. The controller further, Manage multiple second storage regions corresponding one-to-one with each of the multiple partitions, wherein the multiple second storage regions are local storage regions obtained by logically dividing the storage regions of the non-volatile memory; According to a third write request received from the host, which is associated with fifth data of the size of the first data unit and is directed to the second partition, the fifth data is written to the third storage area of ​​the plurality of second storage areas corresponding to the second partition.

9. The storage system according to claim 6, The controller further causes the state of the first partition to change from a first state where data writing is enabled to a second state where data writing is interrupted.

10. The storage system according to claim 6, The controller further, The management system divides the logical address space provided by the storage system to the host into at least one namespace, and the at least one namespace includes the plurality of partitions; For each of the plurality of partitions included in the at least one namespace, the second time specified by the host for the at least one namespace is jointly managed.

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