SAR payload on-board processing evaluation system and method based on CGRA chip

Abstract

The application provides a SAR load on-board processing evaluation system and method based on a CGRA chip, relates to the technical field of data processing chips and SAR load on-board processing evaluation, and introduces CGRA chip reconfigurable computing technology into a SAR load on-board processing simulation system, so that the operation performance of the on-board processing simulation system is greatly improved. The CGRA chip reconfigurable computing technology is adopted to realize control over signal acquisition and reception, to ensure real-time performance in the high-speed operation process, to provide support for a digital signal processing algorithm of the on-board processing simulation system; for operation of a complex algorithm with high operation complexity and time complexity, parallelism of CGRA chip reconfigurable computing is utilized to greatly improve operation speed, reduce data transmission paths, and improve calculation density. Due to the dynamic reconfigurability of the CGRA chip, the application can switch different operations at any time according to needs, and improve flexibility of algorithm implementation.

Description

Technical Field

[0001] This invention relates to the field of data processing chips and on-board processing and evaluation technology for SAR payloads, specifically to an on-board processing and evaluation system and method for SAR payloads based on a CGRA chip. Background Technology

[0002] Data processing chips, as core components of satellite payload processing systems, are widely used in communication, remote sensing, reconnaissance, navigation, and resource satellites, holding an irreplaceable and crucial position. With advancements in satellite application technologies, data processing chip technology also needs continuous development. On the one hand, data-driven applications such as remote sensing are increasingly demanding on-orbit data processing capabilities; on the other hand, emerging concepts such as software-defined satellites are gaining momentum, placing higher demands on the flexibility of satellite data processing platforms. To support these evolving application needs, future on-orbit data processing chips must simultaneously meet requirements such as high computing power, high caching capacity, low power consumption, and dynamic reconfigurability, and must possess versatility to support satellite application upgrades. This presents a significant challenge to the hardware architecture design of these chips.

[0003] As the brain of artificial satellites, data processing chips need to cope with the extreme temperature environment and ubiquitous back radiation when working in space, which places extremely strict requirements on circuit design and packaging.

[0004] In practical applications, a heterogeneous combination of multiple chip types is often used, which seems to compensate for the shortcomings of a single type of device. However, the inherent problems of each type of chip still exist. This approach is also unlikely to meet future demanding requirements.

[0005] Traditional onboard SAR payload processing and evaluation systems are inadequate for meeting the demands of rapid information acquisition, intelligence generation, and information services. There is an urgent need to develop onboard SAR payload information processing systems that can directly perform data processing, information extraction, and information transmission through real-time onboard processing equipment. Furthermore, this would enable autonomous onboard mission planning, significantly improving the real-time performance of space missions, directly supporting effective information acquisition, and alleviating the dependence of traditional space remote sensing on satellite-to-ground links and ground systems.

[0006] Currently, research on on-board information processing systems for SAR payloads in my country is fragmented, lacking unified specifications and universal standards. Most system designs are coupled with single-function, dedicated systems, making it difficult to be compatible with different processing algorithms. This results in a long-standing problem of insufficient hardware system functional versatility and task adaptability, severely hindering the productization, standardization, and diversification of on-board information processing systems. To address these issues, research on evaluation technologies for on-board SAR payload processing and evaluation systems is urgently needed.

[0007] Coarse-Grained Reconfigurable Array (CGRA) is a popular research area in chip architecture in recent years. CGRA is a dynamically reconfigurable architecture composed of processing units, memory access units, and monitoring units. It offers greater flexibility compared to ASIC (Application-Specific Integrated Circuit) architectures and higher energy efficiency compared to Field-Programmable Gate Array (FPGA) architectures. It is a heterogeneous processing acceleration architecture designed for high-performance, high-efficiency, and low-power applications. Compared to FPGAs, CGRA employs a coarse-grained reconfiguration approach, optimizing chip architecture reconfiguration time by reconfiguring the computing unit array structure, while retaining the characteristics of array operations such as pipelined processing and parallel processing, effectively reducing chip architecture power consumption and area.

[0008] The CGRA processing chip combines high performance and flexibility, making it particularly suitable for computationally intensive applications with high parallelism and large data volumes, such as SAR payload radar signal processing.

[0009] On-board processing of SAR payloads based on CGRA chips has numerous application scenarios, and the processing algorithms are also complex and diverse. Based on typical on-board processing application scenarios, the processing algorithms can be simply categorized as follows:

[0010] (1) SAR Imaging Algorithms: On-orbit real-time SAR imaging features multiple modes, high resolution, large swath width, high satellite orbital altitude, and long target synthetic aperture time. Simultaneously, the massive data processing and multi-mode collaborative guidance place high demands on the timeliness of real-time processing and present significant technical challenges. On-orbit real-time processors need to establish unified and precise processing flows and methods. Currently, SAR imaging algorithms mainly include time-domain processing algorithms, range-frequency-azimuth time-domain processing algorithms, range-Doppler domain processing algorithms, multi-transform frequency-domain algorithms, two-dimensional frequency-domain algorithms, and polar coordinate domain algorithms. SAR imaging algorithms are constantly being updated and improved based on the on-orbit SAR imaging modes, operating systems, and performance indicators, and are also continuously iterating and updating. With the continuous development of on-orbit SAR technology, new or improved imaging algorithms will inevitably emerge.

[0011] (2) Real-time target detection and recognition algorithm: Real-time target detection and recognition algorithm for satellite remote sensing images can accurately detect and classify important targets, such as ships, aircraft, and vehicles. At the same time, it can accurately delineate the outline of the coastline and the boundary of the airport. The algorithm usually defines the target detection and recognition task as a regression task, and then predicts the spatially separated bounding boxes and related class probabilities. Typical algorithms include VGG16, SSD, and YOLO series algorithms. These algorithms achieve a significant improvement in detection speed by sacrificing a little detection accuracy.

[0012] Currently, with the improvement of computing power in processing system hardware, on-board processing algorithms are also constantly iterating, developing towards higher real-time performance, higher reliability, and higher performance. Optimizing the computational and memory access performance of algorithms based on the processing system architecture is also a major development trend. It is necessary to accurately evaluate and select on-board processing algorithms that both meet system performance indicators and have strong adaptability to processing hardware. Summary of the Invention

[0013] To address the aforementioned technical problems, this invention provides an on-board SAR payload processing evaluation system and method based on a CGRA chip. The system tests and evaluates the hardware and software architecture and typical algorithms of the on-board processing evaluation system, and provides relevant optimization suggestions to improve on-board processing capabilities and optimize the on-board processing architecture.

[0014] To achieve the above objectives, the present invention adopts the following technical solution:

[0015] A SAR payload on-board processing and evaluation system based on a CGRA chip includes an RF preprocessing unit, an ADC acquisition unit, a data processing unit, a data transmission unit, and a DDR storage unit. The RF preprocessing unit preprocesses, amplifies, and filters RF signals to extract analog signals. The data processing unit includes a CGRA functional unit, a GPU computing unit, an NPU computing unit, and a DSP computing unit. The CGRA functional unit performs AD data decoding, high-speed data exchange, and external RF component control, while also handling data reconstruction and loading to implement the SAR payload on-board processing algorithm. The GPU computing unit, NPU computing unit, and DSP computing unit implement the SAR payload on-board processing algorithm. The DDR storage unit caches data during the SAR payload on-board processing algorithm. The data transmission unit transmits data externally.

[0016] This invention also provides a processing and evaluation method for an on-board SAR payload processing and evaluation system based on a CGRA chip, comprising the following steps:

[0017] Step 1: Analyze the radar signal processing process, identify the data-intensive and computationally-intensive operations and their main components, including FFT, convolution, and matrix transpose. Extract the key algorithms in the radar signal processing of the SAR payload, including pulse compression, FFT butterfly operation, and matrix transpose. The data-intensive and computationally-intensive operations include digital down-conversion, pulse compression, moving target detection, fixed clutter cancellation, and space-time two-dimensional adaptive processing.

[0018] Step 2: Analyze the key algorithm, and based on the hardware structure of the CGRA chip and the characteristics of the SAR radar real-time imaging algorithm, design and implement the structure of the processing and evaluation method; the characteristics of the SAR radar real-time imaging algorithm refer to its inclusion of FFT operation, matrix transpose operation and two-dimensional matrix interpolation operation.

[0019] Step 3: Conduct a processing evaluation to obtain evaluation indicators.

[0020] Beneficial effects:

[0021] 1. This invention introduces CGRA chip reconfigurable computing technology into the SAR payload on-board processing simulation system, which can greatly improve the operational performance of the on-board simulation system. Using CGRA chip reconfigurable computing technology to control signal acquisition and reception ensures real-time performance during high-speed operation, providing support for the digital signal processing algorithms of the SAR payload on-board processing simulation system. For complex algorithms with high computational and time complexity, the parallelism of CGRA chip reconfigurable computing can significantly improve operating speed, reduce data transmission paths, and increase computational density. Due to the dynamic reconfigurability of the CGRA chip, different operations can be switched at any time as needed, improving the flexibility of algorithm implementation.

[0022] 2. This invention replaces the on-board verification process with ground-based testing and verification, and provides evaluation conclusions on the algorithm, chip, and system, which can shorten the on-orbit application cycle of the on-board processing algorithm.

[0023] 3. The evaluation conclusions of this invention can propose a SAR payload processor hardware and software solution with high computing power, high cache, and high bandwidth, breaking through the limitations of traditional chips such as low energy efficiency, limited capacity, and high usage threshold.

[0024] 4. This invention can overcome the problems of traditional on-board processing and evaluation systems, such as limited processing functions, long development cycles, and poor flexibility.

[0025] 5. This invention can provide a processing architecture with strong versatility, strong algorithm adaptability, strong reconfigurability, high computing power, high caching, and high bandwidth to support the increasing on-board processing needs.

[0026] 6. This invention can accurately assess the processing capabilities of existing processing chips, and then propose effective suggestions for improving the processing chip capabilities based on the assessment results. Attached Figure Description

[0027] Figure 1 This is a schematic block diagram of the on-board processing and evaluation method for SAR payloads based on the CGRA chip of the present invention.

[0028] Figure 2This is a diagram of the on-board processing and evaluation system architecture for SAR payloads based on the CGRA chip of the present invention.

[0029] Figure 3 This is a schematic diagram of a SAR payload evaluation platform based on the CGRA chip. Detailed Implementation

[0030] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention. Furthermore, the technical features involved in the various embodiments of this invention described below can be combined with each other as long as they do not conflict with each other.

[0031] The on-board processing and evaluation method for SAR payloads based on CGRA chips of the present invention is as follows: Figure 1 As shown.

[0032] CGRA chips are a prime example of dynamically reconfigurable processors. The on-chip architecture of a CGRA chip typically consists of a data cache unit, a configuration information cache unit, a processing unit (PE) array, and interconnects of configurable computing units. A key characteristic that distinguishes CGRA chips from other hardware is that the system undergoes reconfiguration before computation. Reconfiguration involves loading configuration information from memory into the reconfigurable array, changing the functionality of the PEs and the interconnection methods of related computing resources within the array, thereby completing the specified task.

[0033] The operation of a typical CGRA chip is divided into four stages: configuration, read-out, arithmetic, and data storage. The on-chip configuration process is controlled by a main controller. A PE (Programmer) typically consists of a configurable ALU (Arithmetic Logic Unit) and input / output registers. Based on the configuration information, the ALU in each PE can be configured to perform common logical operations, such as arithmetic operations, AND, OR, NOT, and shift operations. These operations can be added or removed according to the application requirements. Due to the common structure of CGRA chips, the number of PEs is typically between 10^10. 2 The number of chips is on the order of magnitude and is usually arranged in a regular one-dimensional or two-dimensional form. The wiring cost of the computing path is greatly reduced. The CGRA chip can be quickly configured with configuration information of relatively small volume. This configuration information is stored in the on-chip configuration information cache and called by the main controller to achieve dynamic reconfiguration.

[0034] As a hardware architecture that combines software flexibility and hardware efficiency, the CGRA chip is suitable for performing signal processing operations in SAR payload radar that involve large amounts of data, computational intensity, and diverse algorithms.

[0035] This paper proposes an on-board processing and evaluation method for SAR payloads based on the CGRA chip. First, it analyzes the radar signal processing process, identifying the computationally intensive steps and key operations involved. It then extracts the key algorithms and their operational characteristics from the radar signal processing of the SAR payload. Next, it analyzes these key algorithms, and considering the hardware structure of the CGRA chip and the operational characteristics of the core SAR payload radar algorithms, designs the basic structure of the processing process. Finally, it selects the most suitable implementation scheme for the CGRA chip from various algorithm implementation options.

[0036] The processing of radar signals by SAR payloads involves several common components: digital down-conversion, pulse compression, moving target detection, fixed clutter cancellation, and space-time two-dimensional adaptive processing. These steps are data-intensive and computationally intensive. Analysis reveals that the sub-algorithms included in SAR payload radar signal processing primarily include FFT (Fast Fourier Transform), FIR (Finite Impulse Response Filter), and matrix transpose. These data- and computationally intensive sub-algorithms account for the majority of the computational load in radar signal processing. These algorithms are characterized by a large number of points and high order. For example, analyzing the radix-2 FFT operation reveals the following characteristics: 1. High parallelism, as it can be broken down into multiple independent sub-operations; 2. Simple operation type, with each sub-operation consisting of basic two-point dish-shaped computational units. This computationally intensive, highly parallel, and simple operation type makes it highly suitable for implementation in CGRAS chips with abundant parallel resources.

[0037] In the processing and computation of radar signals for common SAR payloads, the main computational types include multiplication, addition and subtraction, comparison, shifting, and bitwise logic operations. For example, in the neural network operations of common target detection and recognition algorithms, the main computational types include the following:

[0038] (1) Multiplication: Used for calculations such as convolution window multiplication, regularized scaling, and scaling factor;

[0039] (2) Addition and subtraction: used for calculations such as convolution window accumulation, channel accumulation, and regularization offset;

[0040] (3) Comparison: Used for calculations such as pooling sampling and activation layers;

[0041] (4) Displacement: including arithmetic left and right shifts, which can replace the multiplication of 2 times;

[0042] (5) Bitwise logic operations: including bitwise AND, bitwise OR, bitwise XOR, and bitwise NOT, providing bit-level logic extensions;

[0043] (6) Truncation: Used to handle overflow truncation;

[0044] (7) Pass-through: Used in conjunction with the selection of cache registers for temporary data storage.

[0045] This approach allows for the solidification of relatively uniform parts of computational tasks, thereby reducing the overall complexity of system configuration. By pre-compiling fine-grained units into the required coarse-grained basic processing units, and then further compiling these coarse-grained processing units, compilation time is significantly shortened. The coarse-grained reconfigurable structure (CGRA) is adopted, and the system structure is realized through a regular two-dimensional processing unit array and programmable interconnects.

[0046] The evaluation of the on-board processing algorithm based on the CGRA chip in this invention includes the following aspects:

[0047] (1) Processing results: Processing results are one of the most important indicators for evaluating algorithms. The processing results vary in different on-board processing scenarios. For example, the processing result in a SAR imaging scenario is a SAR image, while the processing result in a target detection and recognition scenario is the feature information of the detected and recognized target. These processing results correspond to different performance indicators: for SAR images, the main concern is the image signal-to-noise ratio under various imaging modes, including strip mode, spotting mode, sliding spotting mode, mosaic mode, and TOPS mode; for detection and recognition, the main concern is the detection rate and false alarm rate of the detection results, the accuracy of the recognition results, the size of the target, and other feature information.

[0048] (2) Computational complexity: The computational complexity of a processing algorithm is often contradictory to the quality of the processing result. Computational complexity often directly affects the timeliness of the processing system. Timeliness is an extremely critical indicator for on-board processing. Therefore, accurately assessing the computational complexity of a processing algorithm is of great significance for selecting on-board processing algorithms.

[0049] (3) Amount of computational data: The amount of computational data of the processing algorithm is a key factor affecting the design of the processing system. The amount of computational data means the algorithm’s requirements for system memory capacity and transmission bandwidth. If the amount of computational data of the algorithm is large, it needs to be matched with high cache and high bandwidth processing hardware. If the amount of computational data of the algorithm is small, the requirements for memory and transmission can be appropriately relaxed. Accurately assessing the amount of computational data of the processing algorithm is of great significance to the design of the processing system architecture.

[0050] The above three indicators can comprehensively summarize the overall capabilities of processing algorithms in the on-board processing evaluation system, and the evaluation of on-board processing algorithms is based on this. By accurately and comprehensively evaluating the capabilities of algorithms in the on-board processing evaluation system based on these three types of indicators, processing algorithms with excellent processing results, low computational complexity, and small data volume can be selected.

[0051] The SAR payload on-board processing evaluation system and method based on CGRA chip utilizes programs (high-level language programming) and integrated development tools to constrain and evaluate the chip hardware architecture, configuration system, memory, configuration management, control unit, computing architecture, memory and arithmetic unit array of the on-board processing system to be evaluated.

[0052] The present invention also discloses an on-board processing and evaluation system for SAR payloads based on a CGRA chip, the architecture of which is as follows: Figure 2 As shown. The SAR payload on-board processing and evaluation system includes a radio frequency preprocessing unit, an ADC acquisition unit, a data processing unit, a data transmission unit, and a DDR storage unit. After the radio frequency signal is input from the antenna end, it is transmitted through the feed line to the radio frequency preprocessing unit, where the radio frequency signal is preprocessed, amplified, and filtered to extract the useful analog signal, which is then sent to the ADC acquisition unit. The ADC acquisition unit converts the analog signal into a digital signal and transmits it to the CGRA function unit of the data processing unit.

[0053] The data processing unit mainly comprises a CGRA functional unit, a GPU computing unit, an NPU computing unit, and a DSP computing unit. The CGRA functional unit primarily handles AD data decoding, high-speed data exchange, and external RF component control; it is also responsible for data reconstruction and loading, and implementing on-board SAR payload processing algorithms. The GPU, NPU, and DSP computing units implement the on-board SAR payload processing algorithms. The DDR storage unit performs data caching during algorithm processing. The data transmission unit handles external data transmission.

[0054] The CGRA functional unit consists of several dynamic and static areas. The static area contains fixed basic resources, including I / O interfaces, clock configuration, reset logic, etc. During reconstruction, the static area program remains unchanged, while the functional program is dynamically loaded and reconstructed in the dynamic area. Different functional programs are loaded according to the requirements of the SAR payload processing task. When a function version is switched in a certain dynamic area, it does not affect the normal operation of the functions in other dynamic areas. This ensures the continuity and real-time performance of the system during reconstruction.

[0055] The SAR payload on-board processing evaluation method based on the CGRA chip of this invention evaluates the aforementioned SAR payload on-board processing evaluation system based on the CGRA chip. It includes evaluations of both the system hardware architecture and the processing algorithm. Based on these two aspects, key evaluation indicators for assessing the merits of the SAR payload on-board processing evaluation system are derived. These evaluation indicators include:

[0056] (1) Physical parameters: Based on the processing algorithm and the capabilities of the processing chip, and corresponding to the actual needs of the on-board processing evaluation system, evaluate the size, weight and power consumption of the processing system; these physical parameters are the prerequisites for designing the on-board processing evaluation system.

[0057] (2) Processing timeliness: Processing timeliness is one of the key technical indicators of the processing system. On-board processing evaluation systems often have high requirements for real-time processing. Ideally, the data processing time should be in a 1:1 relationship with the data acquisition time so that the system can achieve fully real-time processing. Accurately evaluating processing timeliness is of guiding significance for optimizing the design of the on-board processing evaluation system.

[0058] (3) Processing result indicators: These include SAR image signal-to-noise ratio, integral sidelobe ratio, peak sidelobe ratio, imaging mode, and maximum number of imaging points. The processing result indicators are determined based on the on-board processing application. Evaluating the processing result indicators requires the development of application datasets and algorithm sets for testing and verification.

[0059] The above three indicators can comprehensively summarize the overall capabilities of the CGRA chip-based SAR payload on-board processing evaluation system, and the evaluation of the CGRA chip-based SAR payload on-board processing evaluation system should also be based on this. By accurately and comprehensively evaluating the capabilities of the CGRA chip-based SAR payload on-board processing evaluation system based on these three types of indicators, processing systems that meet the physical requirements and demonstrate excellent processing timeliness and results can be selected.

[0060] Example

[0061] First, a SAR payload evaluation platform based on the CGRA chip is built, such as... Figure 3 As shown, the evaluation platform consists of three parts: a payload data simulator, a CGRA chip on-board processing simulation system, and a data recording and analysis unit. The payload data simulator primarily handles the timing of simulated payload data transmission, the standardization of payload data formats, and data format conversion. The CGRA chip on-board processing evaluation system's simulation component handles the hardware and software coordination of the on-board processing evaluation system. The data recording and analysis unit performs high-speed data collection and processing, as well as SAR image quality analysis.

[0062] When evaluating on-board processing algorithms, the payload data simulator, the CGRA chip on-board processing simulation system, and the data recording and analysis unit are connected in series. The algorithm to be evaluated is loaded into the CGRA chip on-board processing simulation system. The powerful heterogeneous computing resources of the CGRA chip on-board processing simulation system can be used to perform prototype verification and performance evaluation of various typical algorithms related to different projects.

[0063] The payload data simulator generates the stimulus required by the algorithm. First, a corresponding dataset is loaded based on the algorithm's application scope. This dataset generates the payload data needed for the on-board processing algorithm. Then, the payload data is converted to a standard format, and the timing of payload transmission is simulated. The data is then sent to the on-board SAR payload processing simulation subsystem as the stimulus required by the algorithm. Simultaneously, the payload data simulator generates a synchronization trigger signal to ensure time synchronization between the payload data simulator, the CGRA chip on-board processing simulation system, and the data recording and analysis unit for calculating processing delays.

[0064] After receiving the stimulus data, the CGRA chip processing simulation system uses the on-board processing algorithm to be evaluated to process the data. After the calculation is completed, the processing result is sent to the data recording and analysis unit. Here, the on-board processing algorithm to be evaluated needs to be ported to the CGRA chip on-board processing simulation system in advance (because the system has abundant heterogeneous computing resources and software development kits, developers can quickly port the algorithm to be evaluated into the on-board processing simulation subsystem).

[0065] After receiving the processing results, the data logging and analysis unit records the results, analyzes and evaluates the algorithm's performance indicators, calculates the processing latency of the entire process, and provides an evaluation conclusion. Users can then determine whether the algorithm's performance and processing latency meet the requirements based on the evaluation conclusion and formulate the next optimization plan.

[0066] Those skilled in the art will readily understand that the above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A SAR payload on-board processing and evaluation system based on a CGRA chip, characterized in that, The system includes an RF preprocessing unit, an ADC acquisition unit, a data processing unit, a data transmission unit, and a DDR storage unit. The RF preprocessing unit preprocesses, amplifies, and filters RF signals to extract analog signals. The data processing unit includes a CGRA functional unit, a GPU computing unit, an NPU computing unit, and a DSP computing unit. The CGRA functional unit performs AD data decoding, high-speed data exchange, and external RF component control, while also handling data reconstruction and loading to implement the SAR payload on-board processing algorithm. The GPU computing unit, NPU computing unit, and DSP computing unit implement the SAR payload on-board processing algorithm. The DDR storage unit caches data during the SAR payload on-board processing algorithm. The data transmission unit transmits data externally. This paper analyzes the radar signal processing process, identifies the data-intensive and computationally-intensive operations involved, including FFT, convolution, and matrix transpose. It also extracts key algorithms from the radar signal processing of SAR payloads, such as pulse compression, FFT butterfly operations, and matrix transpose. The data-intensive and computationally-intensive operations include digital down-conversion, pulse compression, moving target detection, fixed clutter cancellation, and two-dimensional space-time adaptive processing. The key algorithm is analyzed, and combined with the hardware structure of the CGRA chip, the structure of the processing and evaluation method is designed and implemented according to the characteristics of the SAR radar real-time imaging algorithm. The characteristics of the SAR radar real-time imaging algorithm include FFT operation, matrix transpose operation and two-dimensional matrix interpolation operation. Conduct a processing assessment to obtain assessment indicators.

2. The on-board processing and evaluation system for SAR payloads based on a CGRA chip according to claim 1, characterized in that, After the radio frequency signal is input from the antenna end, it is transmitted through the feeder and enters the radio frequency preprocessing unit to be converted into an analog signal. The analog signal is then sent to the ADC acquisition unit. The ADC acquisition unit converts the analog signal into a digital signal and transmits it to the CGRA functional unit.

3. The on-board processing and evaluation system for SAR payloads based on a CGRA chip according to claim 1, characterized in that, The CGRA functional unit consists of several dynamic and static areas. The static area includes IO interfaces, clock configuration, and reset logic. During reconstruction, the program in the static area remains unchanged, while the functional program is dynamically loaded and reconstructed in the dynamic area. Different functional programs are loaded according to the needs of the SAR payload onboard processing tasks. Furthermore, when a functional program is switched in a certain dynamic area, it does not affect the normal operation of other functional programs in that dynamic area.

4. A method for on-board processing and evaluation of SAR payloads based on a CGRA chip, characterized in that, The system implements an on-board SAR payload processing and evaluation system based on the CGRA chip. This system includes a radio frequency (RF) preprocessing unit, an ADC acquisition unit, a data processing unit, a data transmission unit, and a DDR storage unit. The RF preprocessing unit preprocesses, amplifies, and filters RF signals to extract analog signals. The data processing unit includes a CGRA functional unit, a GPU computing unit, an NPU computing unit, and a DSP computing unit. The CGRA functional unit performs AD data decoding, high-speed data exchange, and external RF component control, while also handling data reconstruction and loading to implement the on-board SAR payload processing algorithm. The GPU computing unit, NPU computing unit, and DSP computing unit implement the on-board SAR payload processing algorithm. The DDR storage unit caches data during the on-board SAR payload processing algorithm. The data transmission unit transmits data externally. The method includes the following steps: Step 1: Analyze the radar signal processing process, identify the data-intensive and computationally-intensive operations and their main components, including FFT, convolution, and matrix transpose. Extract the key algorithms in the radar signal processing of the SAR payload, including pulse compression, FFT butterfly operation, and matrix transpose. The data-intensive and computationally-intensive operations include digital down-conversion, pulse compression, moving target detection, fixed clutter cancellation, and space-time two-dimensional adaptive processing. Step 2: Analyze the key algorithm, and based on the hardware structure of the CGRA chip and the characteristics of the SAR radar real-time imaging algorithm, design and implement the structure of the processing and evaluation method; the characteristics of the SAR radar real-time imaging algorithm refer to its inclusion of FFT operation, matrix transpose operation and two-dimensional matrix interpolation operation. Step 3: Conduct a processing evaluation to obtain evaluation indicators.

5. The processing and evaluation method according to claim 4, characterized in that, The hardware structure of the CGRA chip in step 2 consists of a data cache, a configuration information cache, an array of processing units, and interconnected configurable computing units. Each processing unit consists of a configurable computing logic unit and input and output registers. According to the configuration information, the computing logic unit in each processing unit is configured to perform logical operations. Logical operations can be added or removed according to the needs of the application scenario. The number of processing units is between 10 and 100, and they are arranged in one-dimensional or two-dimensional form.

6. The processing and evaluation method according to claim 5, characterized in that, The evaluation indicators in step 3 include: (1) Physical specifications, including the volume, weight and power consumption of the onboard processing system for the SAR payload; (2) Processing timeliness indicators, including data processing time and data acquisition time, with the data processing time and data acquisition time maintaining a 1:1 relationship; (3) Processing result indicators, including SAR image signal-to-noise ratio, integral sidelobe ratio, peak sidelobe ratio, imaging mode, and maximum number of imaging points.

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