电路噪声参数获取方法、装置与电子设备
By automatically calculating the capacitance and logic state of signal lines in integrated circuits and obtaining noise parameters, the problem of low efficiency in signal line capacitance analysis is solved, thereby improving the efficiency and accuracy of integrated circuit development.
CN117272885BActive Publication Date: 2026-07-17CHANGXIN MEMORY TECH INC
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- CHANGXIN MEMORY TECH INC
- Filing Date
- 2022-06-14
- Publication Date
- 2026-07-17
AI Technical Summary
Technical Problem
In integrated circuit design, the analysis of parasitic capacitance and coupling capacitance between signal lines is inefficient, especially after layout redesign, which requires re-analysis, leading to low development efficiency.
Method used
By automatically acquiring the capacitance between the signal lines under test, the logic state of each signal line under test is determined under each circuit operating state combination. Noise parameters, including external and internal noise parameters, are calculated using post-simulation results and logic state polarity differences.
Benefits of technology
This greatly improves the efficiency of noise parameter acquisition, enhances integrated circuit development efficiency, and ensures the accuracy and speed of analysis.
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Figure CN117272885B_ABST
Abstract
本公开提供一种电路噪声参数获取方法、装置与电子设备。方法包括：确定多个待测电路，每个待测电路均包括一或多条待测信号线，每个待测电路具有至少一种工作状态；获取每一待测信号线与所有其他待测信号线之间的寄生电容，以及确定每个工作状态下每个待测电路中每条待测信号线的逻辑状态；确定多个待测电路的多个工作状态组合，并在多个工作状态组合中确定一个目标工作状态组合；在目标工作状态组合下，根据每条待测信号线的逻辑状态和寄生电容确定每条待测信号线的噪声参数，噪声参数包含其他待测电路造成的外部噪声参数和待测信号线对应的待测电路自身的内部噪声参数。本公开实施例可以迅速得到电路多个工作状态下每条待测信号线的噪声参数。
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