A method for extracting parasitic capacitance of a MOS transistor in an integrated circuit chip

Abstract

The application discloses a method for extracting MOS tube parasitic capacitance in an integrated circuit chip, comprising the following steps: determining a target MOS tube in the integrated circuit chip; obtaining structural physical parameters of the target MOS tube; obtaining V GS ‑I DS1 and V DS ‑I DS1 of the target MOS tube; modeling the target MOS tube by using TCAD simulation software according to the structural physical parameters to obtain a simulation model, and obtaining V GS ‑I DS2 and V DS ‑I DS2 of the target MOS tube according to the simulation model; comparing V GS ‑I DS1 and V GS ‑I DS2 , V DS ‑I DS1 and V DS ‑I DS2 respectively, correcting and determining a final simulation model according to a comparison result; and obtaining C gg ‑V GS curves, C gd ‑V GS curves and C gs ‑V GS curves according to the final simulation model. The application can achieve the purpose of extracting MOS tube overlapping parasitic capacitance in the integrated circuit chip.

Description

Technical Field

[0001] This invention belongs to the field of capacitance parameter extraction and simulation analysis technology, specifically relating to a method for extracting the parasitic capacitance of a single MOS transistor in an integrated circuit chip. Background Technology

[0002] Currently, silicon-based integrated circuits widely used in various fields are mostly manufactured using bipolar, CMOS (Complementary Metal Oxide Semiconductor), and BiCMOS (Bipolar CMOS) processes. MOS (Metal-Oxide-Semiconductor Field-Effect Transistor) devices are a major component of CMOS and BiCMOS processes. During the active region ion implantation and thermal annealing processes in forming MOS devices, parasitic capacitances such as gate-drain overlap capacitance and gate-source overlap capacitance are inevitably introduced. With the rapid development of integrated circuits, integration density is increasing, and feature sizes are shrinking, these parasitic capacitances have a significant impact on the dynamic characteristics of MOS devices. Especially for high-speed integrated circuit chips, parasitic capacitance is a major factor affecting chip speed.

[0003] Traditional methods for extracting parasitic capacitance assume that the actual geometry of an integrated circuit chip is highly consistent with the geometry of its layout design. Therefore, parasitic capacitance extraction typically employs a parasitic capacitance extraction engine to directly extract capacitance based on integrated circuit process parameters and layout design data, thus forming a parasitic capacitance netlist. The capacitance of metal interconnects is then calculated from this netlist. Alternatively, high-frequency CV methods can also be used to measure and extract parasitic capacitance, primarily employing techniques in the high-frequency range (10⁻⁶ Ω·cm). 5 Hz ~10 8 The capacitance in a device (Hz) is affected by the frequency response, resulting in impedance changes. By measuring the frequency-impedance change relationship, the values ​​of various capacitances in the device can be analyzed.

[0004] However, as circuit dimensions gradually decrease and manufacturing processes vary, the actual circuit pattern differs significantly from the layout data. Traditional methods using parasitic capacitance netlists can only provide a rough estimate of gate-drain and gate-source overlap parasitic capacitances, lacking practical physical significance. Furthermore, parasitic capacitance measured using the high-frequency CV method is the result of multiple capacitors coupling together, making data separation difficult. This method also has stringent testing requirements and is easily affected by noise, leading to significant errors in the test results. Summary of the Invention

[0005] To address the aforementioned problems in the prior art, this invention provides a method for extracting the parasitic capacitance of a single MOS transistor in an integrated circuit chip. The technical problem to be solved by this invention is achieved through the following technical solution: This invention provides a method for extracting the parasitic capacitance of a single MOS transistor in an integrated circuit chip, comprising: Identify the target MOSFET in the integrated circuit chip; Obtain the structural physical parameters of the target MOS transistor; The actual transfer characteristic curve V of the target MOS transistor was obtained by using micro-nano probe testing. GS -I DS1 and the actual output characteristic curve V DS -I DS1 ; Based on the structural physical parameters, a simulation model of the target MOSFET is obtained by modeling the MOSFET using TCAD simulation software (Technology Computer Aided Design). The simulation transfer characteristic curve V of the target MOSFET is then obtained based on the simulation model. GS -I DS2 and simulation output characteristic curve V DS -I DS2 ; Compare the actual transfer characteristic curves V respectively GS -I DS1 and the simulated transfer characteristic curve V GS -I DS2 and the actual output characteristic curve V DS -I DS1 and the simulation output characteristic curve V DS -I DS2 The final simulation model is then revised and determined based on the comparison results. The gate capacitance C of the target MOS transistor is obtained by simulation based on the final simulation model. gg -V GS The curve, and the gate-drain parasitic capacitance C gd -V GS Curve, gate-source parasitic capacitance C gs -V GS curve.

[0006] In one embodiment of the present invention, the structural physical parameters of the target MOS transistor include: the location, size, material, doping type and distribution parameters of the substrate, source region, drain region, electrode and oxide layer of the target MOS transistor, as well as the dielectric constant, band structure, intrinsic carrier mobility and recombination rate parameters of each material.

[0007] In one embodiment of the present invention, a simulation model is obtained by modeling the target MOS transistor based on the structural physical parameters and using TCAD simulation software, including: Using the device structure construction tool in TCAD simulation software, a two-dimensional simulation structure of the target MOS transistor is formed based on the physical parameters of the structure. Using the device characteristic calculation tool in TCAD simulation software, a physical model for simulating the basic electrical characteristics of the MOS transistor is set based on the two-dimensional simulation structure of the target MOS transistor, and the voltage bias conditions for simulating the basic electrical characteristics of the MOS transistor are set. The output characteristic curve and transfer characteristic curve of the target MOS transistor are simulated according to the physical model and the voltage bias conditions to obtain the simulation model.

[0008] In one embodiment of the present invention, the final simulation model is corrected and determined based on the comparison results, including: If the comparison result does not meet the preset control conditions, the structural physical parameters used in the simulation model are corrected, and the target MOS transistor is remodeled using TCAD simulation software based on the corrected structural physical parameters until the preset control conditions are met. If the comparison result meets the preset control conditions, then the current corrected simulation model is determined to be the final simulation model.

[0009] In one embodiment of the present invention, it further includes: The final simulation model is modified to be unaffected by parasitic capacitance, and the intrinsic gate capacitance C' of the target MOS transistor is obtained by simulation based on the modified simulation model. gg -V GS curve.

[0010] In one embodiment of the present invention, the process of modifying the final simulation model to make the final simulation model unaffected by parasitic capacitance includes: Obtain the coordinates of the source, drain, and gate regions of the target MOS transistor in the final simulation model; Determine whether there is any overlap between the coordinates of the source region, the drain region, and the gate region; When overlap exists, the overlapping portions of the source region, drain region, and gate region are shifted left and right respectively to ensure that the final simulation model is not affected by parasitic capacitance.

[0011] In one embodiment of the present invention, the target MOS transistor is integrated and packaged within the integrated circuit chip.

[0012] In one embodiment of the present invention, the target MOS transistor is exposed and integrated on the integrated circuit chip.

[0013] The beneficial effects of this invention are: The method for extracting parasitic capacitance of MOSFETs in integrated circuit chips proposed in this invention is a practically meaningful and widely applicable method for extracting the parasitic capacitance of a single MOSFET device in an integrated circuit chip. The implementation process includes: identifying the target MOSFET in the integrated circuit chip; obtaining the structural physical parameters of the target MOSFET; and using micro / nano probes to test and obtain the actual transfer characteristic curve V of the target MOSFET. GS -I DS1 and the actual output characteristic curve V DS -I DS1 Based on the structural physical parameters, a simulation model of the target MOSFET is obtained by modeling the MOSFET using TCAD simulation software. The simulated transfer characteristic curve V of the target MOSFET is then obtained based on the simulation model. GS -I DS2 and simulation output characteristic curve V DS -I DS2 Compare the actual transfer characteristic curves V respectively. GS -I DS1 and the simulated transfer characteristic curve V GS -I DS2 and the actual output characteristic curve V DS -I DS1 and simulation output characteristic curve V DS -I DS2 The final simulation model is then revised and determined based on the comparison results; the gate capacitance C of the target MOS transistor is then simulated based on the final simulation model. gg -V GS The curve, and the gate-drain parasitic capacitance C gd -V GS Curve, gate-source parasitic capacitance C gs -V GS The curve. It can be seen that the method proposed in this invention has strong practical physical significance, employing a combination of actual measurement and simulation, and utilizing easily measurable transfer characteristic curves (actual transfer characteristic curve V). GS -I DS1 ) and output characteristic curve (actual output characteristic curve V) DS -I DS1 ), and the simulated transfer characteristic curve (simulated transfer characteristic curve V). GS -I DS2 ) and output characteristic curve (simulated output characteristic curve V) DS -I DS2 By comparing the simulation model with that of the target MOS transistor, which was modeled using TCAD simulation software based on the structural physical parameters of the MOS transistor, the simulation model was calibrated. Then, the simulation model was used to calculate the CV curve, which is difficult to measure in practice, especially the gate-drain parasitic capacitance C. gd -VGS Curve, gate-source parasitic capacitance C gs -V GS The curve, and the gate-drain parasitic capacitance C gd -V GS Curve, gate-source parasitic capacitance C gs -V GS The curves can be used to reflect the gate-drain parasitic capacitance C. gd Gate-source parasitic capacitance C gs The proposed method achieves the purpose of extracting overlapping parasitic capacitance by obtaining the capacitance value. It has wide applicability and can be applied to devices of various sizes, down to the nanometer level, for extracting overlapping parasitic capacitance of nanoscale devices. Compared to methods that roughly estimate overlapping parasitic capacitance using parasitic capacitance netlists, the proposed method can obtain a CV curve, which is difficult to measure in practice, through simulation. The CV curve provides a more accurate capacitance value for overlapping parasitic capacitance. Compared to high-frequency CV methods, it is more tolerant of testing conditions during the extraction of overlapping parasitic capacitance, and the test results are less susceptible to noise interference, exhibiting strong robustness.

[0014] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0015] Figure 1 This is a flowchart illustrating a method for extracting parasitic capacitance of a MOS transistor in an integrated circuit chip, provided by an embodiment of the present invention. Figure 2 (a)~ Figure 2 (b) is the actual transfer characteristic curve V of the target MOS transistor under overlapping conditions provided in the embodiment of the present invention. GS -I DS1 and the actual output characteristic curve V DS -I DS1 and the simulated transfer characteristic curve V GS -I DS2 and simulation output characteristic curve V DS -I DS2 Schematic diagram; Figure 3 This is a schematic diagram of the two-dimensional simulation structure of the target MOS transistor under overlapping conditions provided in the embodiments of the present invention; Figure 4 (a)~ Figure 4 (c) is a schematic diagram of the simulated capacitance of the target MOS transistor under overlapping conditions provided in the embodiment of the present invention; Figure 5 This is a flowchart illustrating another method for extracting the parasitic capacitance of a MOS transistor in an integrated circuit chip, provided by an embodiment of the present invention. Figure 6This is a schematic diagram of the two-dimensional simulation structure of the target MOS transistor under non-overlapping conditions provided in an embodiment of the present invention; Figure 7 This is the intrinsic gate capacitance C' of the target MOS transistor under non-overlapping conditions provided in the embodiments of the present invention. gg -V GS Schematic diagram of the curve. Detailed Implementation

[0016] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.

[0017] Please see Figure 1 This invention provides a method for extracting the parasitic capacitance of a MOS transistor in an integrated circuit chip, comprising the following steps: S10. Identify the target MOS transistor in the integrated circuit chip.

[0018] In one embodiment of the present invention, the target MOSFET can be integrated and packaged within an integrated circuit chip. For integrated circuit chips with this package structure, before extracting the parasitic capacitance of the MOSFET, the integrated circuit chip is first decapsulated. A gas laser in the infrared band is used to release laser cutting of the package shell of the integrated circuit chip, obtaining an exposed bare chip containing the target MOSFET, thereby identifying the target MOSFET within the integrated circuit chip.

[0019] It should be noted that the opening process can also be achieved using acid corrosion or chemical reaction methods.

[0020] In one embodiment of the present invention, the target MOSFET can also be integrated bare on the integrated circuit chip. For integrated circuit chips with this bare structure, the capping process is omitted, and the target MOSFET inside the integrated circuit chip can be directly identified.

[0021] S20. Obtain the structural physical parameters of the target MOSFET.

[0022] In one embodiment of the present invention, the structural physical parameters of the target MOS transistor include: the location, size, material, doping type and distribution parameters of the substrate, source region, drain region, electrode and oxide layer of the target MOS transistor, as well as the dielectric constant, band structure, intrinsic carrier mobility and recombination rate parameters of each material.

[0023] The structural physical parameters will vary for different types of target MOSFETs. The specific parameters can be flexibly obtained according to the actual design needs, and there are no restrictions on the method of obtaining them, as long as the required structural physical parameters can be obtained.

[0024] S30. Obtain the actual transfer characteristic curve V of the target MOSFET using micro / nano probe testing. GS -IDS1 and the actual output characteristic curve V DS -I DS1 .

[0025] The transfer and output characteristic curves of the target MOSFET obtained by S10 are measured using existing methods, such as using micro / nano probes to pre-test and obtain the actual transfer characteristic curve of the target MOSFET, denoted as V. GS -I DS1 And the actual output characteristic curve, denoted as V DS -I DS1 ,like Figure 2 (a)~ Figure 2 (b) shows the line marked "Test Value", where, Figure 2 In (a), the line marked "test value" is a schematic diagram of the actual transfer characteristic curve of the target MOSFET under overlapping conditions. Figure 2 (b) The line marked "Test Value" is a schematic diagram of the actual output characteristic curve of the target MOSFET under overlapping conditions. It can be seen that, in one embodiment of the present invention, the parameters of the testing process include: Actual transfer characteristic curve V GS -I DS1 Gate source voltage V GS The range is 0V~4.0V, and the source-drain voltage V DS The actual output characteristic curve V is 1.0V. DS -I DS1 Source drain voltage V DS The range is 0V~6.0V, the step frequency is 0.5V, and the gate-source voltage V GS The range is 1.0V~5.0V.

[0026] It should be noted here that for different types of target MOS devices, their corresponding... Figure 2 (a)~ Figure 2 In (b), the parameters of the line marked "test value" are different; this is only to illustrate the actual transfer characteristic curve V of the target MOSFET obtained by using a micro / nano probe. GS -I DS1 and the actual output characteristic curve V DS -I DS1 The output of .

[0027] S40. Based on the structural physical parameters, and using TCAD simulation software to model the target MOSFET to obtain a simulation model, the simulation transfer characteristic curve V of the target MOSFET is obtained based on the simulation model. GS -I DS2 and simulation output characteristic curve V DS -I DS2 .

[0028] In one embodiment of the present invention, a simulation model is obtained by modeling the target MOS transistor based on structural physical parameters and using TCAD simulation software, including: Using the device structure construction tool in TCAD simulation software, a two-dimensional simulation structure of the target MOS transistor is formed based on the structural physical parameters. Specifically, using the device structure construction tool in TCAD simulation software, based on the structural physical parameters obtained from S20, the location, size, material, doping type, and distribution parameters of the device substrate, source region, drain region, electrodes, and oxide layer are defined in TCAD simulation software. The dielectric constant, band structure, intrinsic carrier mobility, and recombination rate parameters of each material are also defined to form the two-dimensional simulation structure of the target MOS transistor, such as... Figure 3 As shown.

[0029] Using the device characteristic calculation tool in TCAD simulation software, a physical model for simulating the basic electrical characteristics of a MOSFET was set up based on its two-dimensional simulation structure. The voltage bias conditions for this simulation were also set. Based on the physical model and voltage bias conditions, the output characteristic curves and transfer characteristic curves of the target MOSFET were simulated to obtain the simulation model. The physical model included carrier mobility and recombination models, carrier transport models, and band structure models.

[0030] It should be noted that TCAD simulation software includes, but is not limited to, Sentaurus TCAD and Silvaco TCAD simulation software.

[0031] Furthermore, the simulated transfer characteristic curve of the target MOSFET is obtained based on the simulation model, denoted as V. GS -I DS2 And the simulation output characteristic curve, denoted as V DS -I DS2 ,like Figure 2 (a)~ Figure 2 (b) shows the line marked "Simulation Values", where, Figure 2 In (a), the line marked "simulation value" is a schematic diagram of the simulated transfer characteristic curve of the target MOSFET under overlapping conditions. Figure 2 (b) The line marked "Simulation Value" is a schematic diagram of the simulated output characteristic curve of the target MOSFET under overlapping conditions. Similar to the testing process, the parameters of the simulation process include: Simulation transfer characteristic curve V GS -I DS2 Gate source voltage V GS The range is 0V~4.0V, and the source-drain voltage V DS The voltage is 1.0V; the simulated output characteristic curve V DS -I DS2Source drain voltage V DS The range is 0V~6.0V, the step frequency is 0.5V, and the gate-source voltage V GS The range is 1.0V~5.0V.

[0032] S50. Compare the actual transfer characteristic curves V respectively. GS -I DS1 and the simulated transfer characteristic curve V GS -I DS2 and the actual output characteristic curve V DS -I DS1 and simulation output characteristic curve V DS -I DS2 The final simulation model is then revised and determined based on the comparison results.

[0033] In one embodiment of the present invention, the modeling process involves comparisons such as... Figure 2 (a)~ Figure 2 The actual transfer characteristic curve V shown in (b) GS -I DS1 and the simulated transfer characteristic curve V GS -I DS2 and the actual output characteristic curve V DS -I DS1 and simulation output characteristic curve V DS -I DS2 To correct and calibrate the simulation model. Specifically, based on the comparison results, the final simulation model is corrected and determined, including: If the comparison result does not meet the preset control conditions, the structural physical parameters used in the simulation model, such as S20, are corrected. Based on the corrected structural physical parameters, the target MOS transistor is remodeled using TCAD simulation software until the preset control conditions are met. If the comparison result meets the preset control conditions, the current corrected simulation model is determined as the final simulation model.

[0034] The preset control conditions in this embodiment of the invention include a judgment coefficient R. 2 Threshold voltage V in the transfer characteristic curve TH A comprehensive consideration of the saturation voltage point in the output characteristic curve.

[0035] For example, when the actual transfer characteristic curve V GS -I DS1 and the simulated transfer characteristic curve V GS -I DS2 Actual output characteristic curve V DS -I DS1 and simulation output characteristic curve V DS -I DS2 The determination coefficient R 2All values ​​are controlled to be greater than 0.9, and the actual transfer characteristic curve V is judged. GS -I DS1 and the simulated transfer characteristic curve V GS -I DS2 Threshold voltage V TH The error at the point is controlled within 0.05V, and the actual output characteristic curve V DS -I DS1 and simulation output characteristic curve V DS -I DS2 If the error of the saturation current point should be controlled within 0.1mA, then the correction behavior is stopped, and it is assumed that the simulation results output by the simulation model are as consistent as possible with the measured results in step S20. The simulation model corrected at this time is taken as the final simulation model.

[0036] Here, the judgment coefficient R 2 This involves calculating the correlation coefficient between the two sets of data, which can be done using existing techniques and will not be elaborated upon here.

[0037] S60. Based on the final simulation model, the gate capacitance C of the target MOSFET is obtained through simulation. gg -V GS The curve, and the gate-drain parasitic capacitance C gd -V GS Curve, gate-source parasitic capacitance C gs -V GS curve.

[0038] In one embodiment of the present invention, the gate capacitance C of the target MOS transistor is simulated based on the final simulation model determined in S50. gg -V GS The curve, and the gate-drain parasitic capacitance C gd -V GS Curve, gate-source parasitic capacitance C gs -V GS Curves, such as Figure 4 (a)~ Figure 4 As shown in (c), where, Figure 4 (a) is the gate capacitance Cgg-V of the target MOSFET under overlapping conditions. GS Curve diagram, Figure 4 (b) is the gate-drain parasitic capacitance C of the target MOSFET under overlapping conditions. gd -V GS Curve diagram, Figure 4 (c) is the gate-source parasitic capacitance C of the target MOSFET under overlapping conditions. gs -V GS Schematic diagram of the curve. It can be seen that, in one embodiment of the present invention, the gate capacitance C is extracted. gg Gate-drain parasitic capacitance C gd Gate-source parasitic capacitance Cgs At that time, the simulation parameters of the final simulation model include: Gate-source voltage V GS The voltage range is -5.0V to 5.0V, and the sweep frequency is 100kHz.

[0039] It should be noted here that, same Figure 2 (a)~ Figure 2 (b) For different types of target MOS transistors, the corresponding simulation parameters and simulation results are different. This is just an illustration of one embodiment.

[0040] final, Figure 4 (a)~ Figure 4 (c) The gate capacitance C gg -V GS The curve, and the gate-drain parasitic capacitance C gd -V GS Curve, gate-source parasitic capacitance C gs -V GS The curves can be used to reflect the gate capacitance C. gg Gate-drain parasitic capacitance C gd Gate-source parasitic capacitance C gs The capacitance value is used to achieve the purpose of extracting overlapping parasitic capacitance.

[0041] In one embodiment of the present invention, please refer to Figure 5 The method for extracting parasitic capacitance of MOS transistors in integrated circuit chips proposed in this embodiment of the invention further includes: S70. Modify the final simulation model to make it unaffected by parasitic capacitance, and simulate the intrinsic gate capacitance C' of the target MOSFET based on the modified simulation model. gg -V GS curve.

[0042] In addition to extracting the gate capacitance C through S60, the embodiments of the present invention also include... gg Gate-drain parasitic capacitance C gd Gate-source parasitic capacitance C gs It can also extract the intrinsic gate capacitance C' gg -V GS In one embodiment of the present invention, the gate-drain parasitic capacitance C extracted in S10~S60 above... gd Gate-source parasitic capacitance C gs It is an overlapping capacitance, therefore, when extracting the intrinsic gate capacitance C' gg -V GS At this time, coordinate transformation is required to modify the final simulation model so that the final simulation model is not affected by the gate-drain parasitic capacitance C. gd Gate-source parasitic capacitance C gs Due to the overlapping effects, the two-dimensional simulation structure of the target MOSFET is as follows: Figure 6 As shown. The specific process of modifying the final simulation model to make it unaffected by parasitic capacitance includes: Obtain the coordinates of the source, drain, and gate regions of the target MOS transistor in the final simulation model; determine whether there is overlap between the coordinates of the source, drain, and gate regions; when there is overlap, shift the overlapping parts of the source, drain, and gate regions left and right respectively so that the final simulation model is not affected by the overlap of parasitic capacitance.

[0043] Furthermore, the intrinsic gate capacitance C' of the target MOSFET was obtained through simulation based on the modified simulation model. gg -V GS Curves, such as Figure 7 As shown, in one embodiment of the present invention, the intrinsic gate capacitance C' is extracted. gg At that time, similar to Figure 4 (a)~ Figure 4 (c) The simulation parameters of the final simulation model include: Gate-source voltage V GS The voltage range is -5.0V to 5.0V, and the sweep frequency is 100kHz.

[0044] final, Figure 7 The intrinsic gate capacitance C' shown gg -V GS The curve can be used to reflect the state of the unaffected gate-drain parasitic capacitance C. gd and gate-source parasitic capacitance C gs The intrinsic gate capacitance C' of the target MOS device affected by overlapping effects gg The capacitance value is such that the intrinsic gate capacitance C' can be extracted. gg The purpose.

[0045] In summary, the method for extracting parasitic capacitance of MOSFETs in integrated circuit chips proposed in this invention is a method with practical physical significance and wide applicability for extracting the parasitic capacitance of a single MOSFET device in an integrated circuit chip. The implementation process of this method includes: identifying the target MOSFET in the integrated circuit chip; obtaining the structural physical parameters of the target MOSFET; and using micro / nano probes to test and obtain the actual transfer characteristic curve V of the target MOSFET. GS -I DS1 and the actual output characteristic curve V DS -I DS1 Based on the structural physical parameters, a simulation model of the target MOSFET is obtained by modeling the MOSFET using TCAD simulation software. The simulated transfer characteristic curve V of the target MOSFET is then obtained based on the simulation model. GS -I DS2 and simulation output characteristic curve V DS -I DS2Compare the actual transfer characteristic curves V respectively. GS -I DS1 and the simulated transfer characteristic curve V GS -I DS2 and the actual output characteristic curve V DS -I DS1 and simulation output characteristic curve V DS -I DS2 The final simulation model is then revised and determined based on the comparison results; the gate capacitance C of the target MOS transistor is then simulated based on the final simulation model. gg -V GS The curve, and the gate-drain parasitic capacitance C gd -V GS Curve, gate-source parasitic capacitance C gs -V GS The curve. It can be seen that the method proposed in this embodiment of the invention has strong practical physical significance. It employs a combination of actual measurement and simulation, using easily measurable transfer characteristic curves (actual transfer characteristic curve V). GS -I DS1 ) and output characteristic curve (actual output characteristic curve V) DS -I DS1 ), and the simulated transfer characteristic curve (simulated transfer characteristic curve V). GS -I DS2 ) and output characteristic curve (simulated output characteristic curve V) DS -I DS2 By comparing the simulation model with that of the target MOS transistor, which was modeled using TCAD simulation software based on the structural physical parameters of the MOS transistor, the simulation model was calibrated. Then, the simulation model was used to calculate the CV curve, which is difficult to measure in practice, especially the gate-drain parasitic capacitance C. gd -V GS Curve, gate-source parasitic capacitance C gs -V GS The curve, and the gate-drain parasitic capacitance C gd -V GS Curve, gate-source parasitic capacitance C gs -V GS The curves can be used to reflect the gate-drain parasitic capacitance C. gd Gate-source parasitic capacitance C gsThe proposed method achieves the purpose of extracting overlapping parasitic capacitance by obtaining the capacitance value. The method is widely applicable and can be applied to devices of various sizes, down to the nanometer level, for extracting overlapping parasitic capacitance of nanometer-scale devices. Compared to methods that roughly estimate overlapping parasitic capacitance using parasitic capacitance netlists, the proposed method can obtain a CV curve that is difficult to measure in practice through simulation models. The CV curve provides a more accurate capacitance value for overlapping parasitic capacitance. Compared to high-frequency CV methods, the proposed method is more tolerant of testing conditions during the extraction of overlapping parasitic capacitance, and the test results are less susceptible to noise interference, exhibiting strong robustness.

[0046] Meanwhile, the method proposed in this embodiment of the invention can calculate the gate-drain parasitic capacitance C without being affected by the simulation model. gd Gate-source parasitic capacitance C gs Influence of intrinsic gate capacitance C' gg -V GS The curve represents the intrinsic gate capacitance C'. gg -V GS The curve can be used to reflect the intrinsic gate capacitance C' of the target MOS device. gg The capacitance value is such that the intrinsic gate capacitance C' can be extracted. gg The purpose.

[0047] In addition, the method for extracting the parasitic capacitance of a single MOS transistor in an integrated circuit chip provided in this embodiment of the invention can also be applied to JFET (Junction Field Effect Transistor). The method for extracting the parasitic capacitance of a JFET transistor can be implemented using the same approach as for extracting the parasitic capacitance of a MOS transistor, which will not be elaborated here.

[0048] In the description of this invention, it should be understood that the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0049] Although the invention has been described herein in conjunction with various embodiments, those skilled in the art, by reviewing the specification and accompanying drawings, will understand and implement other variations of the disclosed embodiments in carrying out the claimed invention. In the specification, the word "comprising" does not exclude other components or steps, and "a" or "an" does not exclude a plurality. While certain measures are described in different embodiments, this does not mean that these measures cannot be combined to produce good results.

[0050] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A method for extracting the parasitic capacitance of a MOS transistor in an integrated circuit chip, characterized in that, include: Identify the target MOSFET in the integrated circuit chip; Obtain the structural physical parameters of the target MOS transistor; The actual transfer characteristic curve V of the target MOS transistor was obtained by using micro-nano probe testing. GS -I DS1 and the actual output characteristic curve V DS -I DS1 ; Based on the structural physical parameters, a simulation model of the target MOSFET is obtained using TCAD simulation software. The simulation transfer characteristic curve V of the target MOSFET is then obtained based on the simulation model. GS -I DS2 and simulation output characteristic curve V DS -I DS2 ; Compare the actual transfer characteristic curves V respectively GS -I DS1 and the simulated transfer characteristic curve V GS -I DS2 and the actual output characteristic curve V DS -I DS1 and the simulation output characteristic curve V DS -I DS2 The simulation model is then corrected and determined based on the comparison results. This process includes: if the comparison results do not meet preset control conditions, the structural physical parameters used in the simulation model are corrected, and the target MOS transistor is remodeled using TCAD simulation software based on the corrected structural physical parameters until the preset control conditions are met; if the comparison results meet the preset control conditions, the current corrected simulation model is determined as the final simulation model. The preset control conditions include the actual transfer characteristic curve V. GS -I DS1 and the simulated transfer characteristic curve V GS -I DS2 Actual output characteristic curve V DS -I DS1 and simulation output characteristic curve V DS -I DS2 The determination coefficient R 2 All values ​​are controlled to be greater than 0.9, while the actual transfer characteristic curve V GS -I DS1 and the simulated transfer characteristic curve V GS -I DS2 The error at the threshold voltage point is controlled within 0.05V, and the actual output characteristic curve V... DS -I DS1 and simulation output characteristic curve V DS -I DS2 The error at the saturation current point is controlled within 0.1mA; The gate capacitance C of the target MOS transistor is obtained by simulation based on the final simulation model. gg -V GS The curve, and the gate-drain parasitic capacitance C gd -V GS Curve, gate-source parasitic capacitance C gs -V GS curve; The final simulation model was modified to be unaffected by parasitic capacitance, and the intrinsic gate capacitance C' of the target MOSFET was obtained through simulation based on the modified model. gg -V GS The process of modifying the final simulation model to make it unaffected by parasitic capacitance includes: obtaining the coordinates of the source, drain, and gate regions of the target MOS transistor in the final simulation model; determining whether there is overlap between the coordinates of the source, drain, and gate regions; and when there is overlap, shifting the overlapping portions of the source, drain, and gate regions left and right to make the final simulation model unaffected by parasitic capacitance.

2. The method for extracting parasitic capacitance of a MOS transistor in an integrated circuit chip according to claim 1, characterized in that, The structural physical parameters of the target MOS transistor include: the location, size, material, doping type and distribution parameters of the substrate, source region, drain region, electrode and oxide layer of the target MOS transistor, as well as the dielectric constant, band structure, intrinsic carrier mobility and recombination rate parameters of each material.

3. The method for extracting parasitic capacitance of a MOS transistor in an integrated circuit chip according to claim 1, characterized in that, Based on the structural physical parameters, and using TCAD simulation software to model the target MOS transistor, a simulation model is obtained, including: Using the device structure construction tool in TCAD simulation software, a two-dimensional simulation structure of the target MOS transistor is formed based on the physical parameters of the structure. Using the device characteristic calculation tool in TCAD simulation software, a physical model for simulating the basic electrical characteristics of the MOS transistor is set based on the two-dimensional simulation structure of the target MOS transistor, and the voltage bias conditions for simulating the basic electrical characteristics of the MOS transistor are set. The output characteristic curve and transfer characteristic curve of the target MOS transistor are simulated according to the physical model and the voltage bias conditions to obtain the simulation model.

4. The method for extracting the parasitic capacitance of a MOS transistor in an integrated circuit chip according to claim 1, characterized in that, The target MOS transistor is integrated and packaged within the integrated circuit chip.

5. The method for extracting the parasitic capacitance of a MOS transistor in an integrated circuit chip according to claim 1, characterized in that, The target MOS transistor is exposed and integrated on the integrated circuit chip.

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