A method, apparatus, device and medium for processing a gated clock
By identifying and modifying the gated clock in the FPGA prototype circuit, and combining timing analysis and simulation checks, the problem of non-standard gated clock processing in the prior art was solved, realizing efficient and fully automated circuit function checks, improving work efficiency and reducing costs.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SHANDONG YUNHAI GUOCHUANG CLOUD COMPUTING EQUIP IND INNOVATION CENT CO LTD
- Filing Date
- 2023-09-22
- Publication Date
- 2026-07-21
AI Technical Summary
In FPGA prototyping, the lack of standardized gating clock processing methods in existing technologies leads to incomplete circuit function checks, which can easily cause potential problems after modification. Moreover, the modification process is time-consuming and inefficient.
By identifying the gated clock in the FPGA prototype circuit, searching for related circuits, obtaining timing analysis reports, determining critical clock paths, modifying the gated clock, and checking the correctness of the output signal through simulation, the process continues until all related circuits function correctly.
It enables efficient and comprehensive inspection of the circuit function after the gated clock is modified, predicts potential problems in advance, reduces the workload of R&D personnel, improves processing efficiency, and reduces R&D costs.
Smart Images
Figure CN117272887B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of integrated circuit design, and more particularly to a gated clock processing method, apparatus, device, and medium. Background Technology
[0002] FPGA prototyping is essential in chip design and verification. Before chip manufacturing, significant effort is spent verifying the RTL code; additionally, software development needs to begin before the chip is ready for production. Both of these tasks rely on FPGA prototyping as a verification platform to simulate chip behavior, helping hardware and software developers improve efficiency. However, as a substitute for a chip, FPGA prototyping also has limitations, such as size, speed, power consumption, and structural constraints. The physical structures of chips and FPGAs differ; chips are based on standard cell libraries, while FPGAs are based on manufacturer-provided macrocell modules (lookup tables and flip-flops). This necessitates code conversion for FPGA prototyping verification. This conversion is only at the code level; it replaces parts of the chip code with methods feasible for FPGA implementation, without altering the original functionality.
[0003] In chip design, numerous gated clocks are incorporated into the circuitry to conserve power during operation. Clock gating is one of the simplest and most common methods for reducing dynamic power consumption. When a circuit within the chip is in use, its clock is enabled via a gated clock, activating its function; conversely, when a circuit is not in use, its clock is disabled via the same gated clock, putting the corresponding circuit into a sleep state, thus reducing power consumption. However, FPGAs do not have such power-saving gated clock circuits. Introducing gated clocks from the chip design into FPGA prototyping can severely impact the FPGA's timing performance, leading to timing convergence issues in the synthesized and implemented engineering versions. It can also cause various functional anomalies. Therefore, appropriate handling of gated clocks is essential during FPGA prototype porting.
[0004] Currently, the handling of gated clocks in existing FPGA prototypes relies entirely on the developer's experience and the actual impact of modifications on circuit timing, lacking standardized practices. Furthermore, in existing solutions, functional checks of the FPGA prototype after gated clock modifications are only performed during online debugging after the engineering version has been synthesized and implemented. This approach has the following problems: First, the lack of a functional check mechanism for modified gated clocks in the FPGA prototype makes it prone to potential issues. Second, after modifying the gated clock, an engineering version needs to be synthesized and implemented beforehand, and then checked during online debugging. If functional problems are found after the gated clock modification, the RTL code of that circuit needs to be investigated, the cause of the anomaly located, and the RTL code modified, followed by resynthesis and reimplementation of the engineering version. This process involves repeated iterations, is time-consuming, inefficient, and severely impacts work efficiency. Therefore, there is an urgent need to improve the existing gated clock handling methods. Summary of the Invention
[0005] In view of this, it is necessary to provide a gated clock processing method, device, equipment and medium to address the above technical problems.
[0006] According to a first aspect of the present invention, a gated clock processing method is provided, the method comprising:
[0007] Identify all gated clocks in the FPGA prototype circuit;
[0008] For each identified gated clock, a drive circuit search is performed to obtain all associated circuits related to the drive circuit corresponding to each gated clock.
[0009] Perform engineering version synthesis on the FPGA prototype circuit before the gated clock is modified, and obtain the timing analysis report output after synthesis;
[0010] Based on the timing analysis report, the key clock paths affecting timing convergence are obtained, and when it is necessary to modify the gated clock, the gated clock modification method is determined based on the key clock paths.
[0011] Perform a synthesis simulation of the modified gated clock separately, and check the output signal of each associated circuit corresponding to the modified gated clock based on the simulation results;
[0012] If the output signal of a certain associated circuit is incorrect, the RTL code of that associated circuit is modified.
[0013] Return to the step of performing a separate synthesis simulation on the modified gated clock and checking whether the output signal of each associated circuit corresponding to the modified gated clock is correct based on the simulation results, until the output signals of all associated circuits corresponding to the modified gated clock are correct.
[0014] In some embodiments, the step of identifying all gated clocks in the FPGA prototype circuit includes:
[0015] Find all circuits in the FPGA prototype circuit that have one clock input, one clock enable, and one clock output.
[0016] Iterate through the logic operation mode of each circuit found, and obtain all circuits that generate clock output by performing any one of the following operations: logical AND, logical OR, or logical NOT between the clock input and clock enable terminals, in order to obtain all gated clocks.
[0017] In some embodiments, the step of determining the gating clock modification method based on the critical clock path when it is necessary to modify the gating clock includes:
[0018] Determine whether the gated clock that needs to be modified belongs to the critical clock path;
[0019] If the gated clock needs to be modified and belongs to the critical clock path, then the method for modifying the gated clock is to replace the gated clock with the global clock module with clock enable in the FPGA prototype.
[0020] In some embodiments, the step of determining the gated clock modification method based on the critical clock path when it is necessary to modify the gated clock further includes:
[0021] In response to the need to modify the gated clock, which is not part of the critical clock path, it is confirmed that the modification method for the gated clock is to remove the clock enable terminal and directly connect the clock input terminal and the clock output terminal in the circuit corresponding to the gated clock that needs to be modified to perform a connection process.
[0022] In some embodiments, multiple gated clocks need to be modified. The step of determining the gated clock modification method based on the critical clock path when gated clock modification is required further includes:
[0023] Iterate through each gated clock that needs to be modified to obtain the corresponding gated clock modification method for each gated clock;
[0024] Apply the corresponding gated clock modification method to each gated clock that needs modification to perform the modification operation.
[0025] In some embodiments, the step of modifying the RTL code of a certain associated circuit in response to an incorrect output signal of that associated circuit includes:
[0026] Acquire all signals where the output signal contains errors;
[0027] For each erroneous output signal, locate the target associated circuit it belongs to, and obtain the target RTL code corresponding to the target associated circuit;
[0028] Investigate the target RTL code to locate the cause of the error, and modify the target RTL code based on the cause of the error.
[0029] In some embodiments, the method further includes:
[0030] If the output signals of all associated circuits corresponding to the modified gated clock are correct, then the engineering version is synthesized and released again.
[0031] According to a second aspect of the present invention, a gated clock processing apparatus is provided, the apparatus comprising:
[0032] The identification module is configured to identify all gated clocks in the FPGA prototype circuit.
[0033] The search module is configured to perform a drive circuit search for each identified gated clock to obtain all associated circuits related to the drive circuit corresponding to each gated clock.
[0034] The acquisition module is configured to perform engineering version synthesis on the FPGA prototype circuit before the gated clock is modified, and acquire the timing analysis report output after synthesis.
[0035] The determination module is configured to obtain the critical clock path affecting timing convergence based on the timing analysis report, and determine the gated clock modification method based on the critical clock path when it is necessary to modify the gated clock.
[0036] The inspection module is configured to perform a synthesis simulation of the modified gated clock separately, and check whether the output signal of each associated circuit corresponding to the modified gated clock is correct based on the simulation results.
[0037] A modification module is configured to modify the RTL code of a certain associated circuit in response to an incorrect output signal of that associated circuit.
[0038] The return module is configured to return the simulation after synthesizing the modified gated clock separately, and check whether the output signal of each associated circuit corresponding to the modified gated clock is correct based on the simulation results, until the output signals of all associated circuits corresponding to the modified gated clock are correct.
[0039] According to a third aspect of the present invention, an electronic device is also provided, the electronic device comprising:
[0040] At least one processor; and
[0041] The memory stores computer programs that can run on the processor, which executes the aforementioned gated clock processing method when executing the program.
[0042] According to a fourth aspect of the present invention, a computer-readable storage medium is also provided, which stores a computer program that, when executed by a processor, performs the aforementioned gated clock processing method.
[0043] The above-mentioned gated clock processing method can perform efficient and comprehensive consistency checks on the circuit functions in the FPGA prototype after the gated clock is modified, predict problems and hidden dangers in the circuit driven by the gated clock in advance, improve the efficiency of gated clock processing in the RTL code investigation stage, realize fully automated gated clock processing and checking, reduce the workload of R&D personnel, and reduce R&D costs.
[0044] In addition, the present invention also provides a gated clock processing device, an electronic device, and a computer-readable storage medium, which can achieve the above-mentioned technical effects, and will not be described in detail here. Attached Figure Description
[0045] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other embodiments can be obtained based on these drawings without creative effort.
[0046] Figure 1 A flowchart illustrating a gated clock processing method according to an embodiment of the present invention;
[0047] Figure 2 A flowchart illustrating another gated clock processing method provided in another embodiment of the present invention;
[0048] Figure 3 A schematic diagram of a gated clock processing device provided in another embodiment of the present invention;
[0049] Figure 4 This is an internal structure diagram of an electronic device according to another embodiment of the present invention;
[0050] Figure 5 This is a structural diagram of a computer-readable storage medium in another embodiment of the present invention. Detailed Implementation
[0051] To make the objectives, technical solutions, and advantages of the present invention clearer, the embodiments of the present invention will be further described in detail below with reference to specific examples and the accompanying drawings.
[0052] It should be noted that all uses of "first" and "second" in the embodiments of the present invention are for the purpose of distinguishing two entities or parameters with the same name but different names. It is clear that "first" and "second" are only for the convenience of expression and should not be construed as limiting the embodiments of the present invention. Subsequent embodiments will not explain this in detail.
[0053] For ease of understanding, the technology used in the examples of this invention will be described as follows:
[0054] FPGA: Field Programmable Gate Array, is a product of further development based on traditional programmable devices. It emerged as a semi-custom circuit in the field of application-specific integrated circuits (chips), solving the shortcomings of custom circuits and overcoming the limitation of the limited number of gate circuits in traditional programmable devices.
[0055] FPGA prototype verification: This is a chip verification method based on FPGA. It is generally performed after the front-end RTL design and RTL simulation stages are completed and before the chip is fabricated. It verifies as many functions of the chip as possible on an FPGA prototype.
[0056] RTL: Register Transfer Level, in integrated circuit design, is an abstract description of the operation of synchronous digital circuits.
[0057] Clock gating: This is a technique in chip design to disable the clock on certain unused circuits. The "circuit" here can be a single register, module, subsystem, or even the entire chip.
[0058] Synthesis: Synthesis is a crucial step in front-end design. It involves transforming the high-level abstraction of the user-designed digital circuit into a logic gate-level netlist through Boolean function simplification and optimization. Its purpose is to determine the circuit's gate-level architecture, achieve a balance between timing and area, and between power consumption and timing, thereby enhancing the circuit's testability.
[0059] In one embodiment, please refer to Figure 1 As shown, the present invention provides a gated clock processing method 100, specifically, the method includes the following steps:
[0060] Step 101: Identify all gated clocks in the FPGA prototype circuit;
[0061] Step 102: Perform a drive circuit search for each identified gated clock to obtain all associated circuits related to the drive circuit corresponding to each gated clock.
[0062] Step 103: Perform engineering version synthesis on the FPGA prototype circuit before the gated clock modification, and obtain the timing analysis report output after synthesis;
[0063] Step 104: Based on the timing analysis report, obtain the key clock path that affects timing convergence, and determine the gated clock modification method based on the key clock path when it is necessary to modify the gated clock.
[0064] Step 105: Perform a synthesis simulation on the modified gated clock separately, and check the output signal of each associated circuit corresponding to the modified gated clock based on the simulation results.
[0065] Step 106: In response to an incorrect output signal of a certain associated circuit, the RTL code of the associated circuit is modified.
[0066] Step 107: Return to step 105 to perform a synthesis simulation of the modified gated clock separately, and check whether the output signal of each associated circuit corresponding to the modified gated clock is correct based on the simulation results, until the output signals of all associated circuits corresponding to the modified gated clock are correct.
[0067] The above-mentioned gated clock processing method can perform efficient and comprehensive consistency checks on the circuit functions in the FPGA prototype after the gated clock is modified, predict problems and hidden dangers in the circuit driven by the gated clock in advance, improve the efficiency of gated clock processing in the RTL code investigation stage, realize fully automated gated clock processing and checking, reduce the workload of R&D personnel, and reduce R&D costs.
[0068] In some embodiments, step 101 above, identifying all gated clocks in the FPGA prototype circuit, includes:
[0069] Find all circuits in the FPGA prototype circuit that have one clock input, one clock enable, and one clock output.
[0070] Iterate through the logic operation mode of each circuit found, and obtain all circuits that generate clock output by performing any one of the following operations: logical AND, logical OR, or logical NOT between the clock input and clock enable terminals, in order to obtain all gated clocks.
[0071] This embodiment of a gated clock processing method actively searches and identifies all circuits, utilizing the circuit characteristics of gated clocks, namely the number of input ports, output ports, and enable ports, as well as the logic operation method, to find all gated clock circuits in the FPGA prototype circuit. This avoids manual identification, significantly reducing the workload of R&D personnel. Furthermore, this identification method has high accuracy, avoiding the occurrence of omissions in identification.
[0072] In some embodiments, step 104 above, determining the gated clock modification method based on the critical clock path when the gated clock needs to be modified, includes:
[0073] Determine whether the gated clock that needs to be modified belongs to the critical clock path;
[0074] If the gated clock needs to be modified and belongs to the critical clock path, then the method for modifying the gated clock is to replace the gated clock with the global clock module with clock enable in the FPGA prototype.
[0075] In some embodiments, step 104 above, determining the gated clock modification method based on the critical clock path when the gated clock needs to be modified, further includes:
[0076] In response to the need to modify the gated clock, which is not part of the critical clock path, it is confirmed that the modification method for the gated clock is to remove the clock enable terminal and directly connect the clock input terminal and the clock output terminal in the circuit corresponding to the gated clock that needs to be modified to perform a connection process.
[0077] This embodiment of a gated clock processing method combines the path where the gated clock is located, uses the critical clock path to measure the importance of the gated clock, and defines two different modification methods based on the importance of its path, thereby achieving standardization and unification of gated clock modification processing and having excellent versatility.
[0078] In some embodiments, multiple gated clocks need to be modified. Step 104 above, which involves determining the gated clock modification method based on the critical clock path when a gated clock modification is needed, further includes:
[0079] Iterate through each gated clock that needs to be modified to obtain the corresponding gated clock modification method for each gated clock;
[0080] Apply the corresponding gated clock modification method to each gated clock that needs modification to perform the modification operation.
[0081] This embodiment of a gated clock processing method addresses the scenario of modifying multiple gated clocks in a single operation. By traversing the circuits, it matches the corresponding modification method to each gated clock circuit. Since the modifications to each gated clock circuit are independent of each other, the parallel matching method significantly improves the efficiency of gated clock modification, reduces the workload of R&D personnel, and saves R&D costs.
[0082] In some embodiments, step 106, in response to an incorrect output signal of a certain associated circuit, modifies the RTL code of the associated circuit, including:
[0083] Acquire all signals where the output signal contains errors;
[0084] For each erroneous output signal, locate the target associated circuit it belongs to, and obtain the target RTL code corresponding to the target associated circuit;
[0085] Investigate the target RTL code to locate the cause of the error, and modify the target RTL code based on the cause of the error.
[0086] This embodiment of a gated clock processing method uses an erroneous output signal to locate the associated circuit that needs to be investigated and its corresponding RTL code. By locating the cause of the error and modifying the RTL code in conjunction with the cause of the error, ineffective investigation is avoided.
[0087] In some embodiments, the method further includes:
[0088] If the output signals of all associated circuits corresponding to the modified gated clock are correct, then the engineering version is synthesized and released again.
[0089] In yet another embodiment, for ease of understanding the present invention, please refer to... Figure 2 As shown, this example provides another method for gated clock processing, the implementation principle of which is as follows:
[0090] A consistency check engine was designed, comprising the following functions: gated clock identification, driver circuit search, gated clock modification, and driver circuit output check. This consistency check engine can proactively identify gated clocks present in the FPGA prototype and actively search for all associated circuits driven by those gated clocks. Based on the timing report after synthesis of the engineering version, it extracts and determines whether the clock path containing the gated clock is a critical path, deciding whether to modify the gated clock by either pulling or replacing it. The circuit driven by the gated clock after pulling or replacing is then simulated after synthesis to check the correctness of the output signal. If correct, the circuit after modifying the gated clock is considered functionally equivalent, and the engineering version is implemented accordingly; if incorrect, the RTL code of the circuit is investigated based on the error signal to locate the cause of the error and modify the RTL code. After completing the checks of all gated clock driver circuits, the engineering version is synthesized and implemented. In this way, before creating the engineering version, it can be ensured that the circuit in the FPGA prototype is functionally equivalent to the circuit in the chip design after modifying the gated clock.
[0091] The implementation process of the method of this invention will be explained in detail below, combining the functions of each part of the consistency check engine:
[0092] The first step is gated clock identification. Based on the circuit characteristics of gated clocks, all gated clocks present in the FPGA prototype circuit are actively identified. The circuit characteristics of a gated clock are that it has one clock input, one clock enable, and one clock output. The logic AND / OR / NOT operation between the clock input and the clock enable produces the clock output.
[0093] The second step is to search the drive circuit. Based on the circuit path through which the gated clock passes, the system actively searches for all associated circuits driven by the gated clock.
[0094] The third step is to perform an engineering version synthesis on the FPGA prototype circuit with the gated clock unchanged.
[0095] The fourth step involves extracting and identifying which gated clock paths are critical paths affecting timing convergence based on the timing analysis report output after synthesis in the engineering version. Gated clocks on critical paths are replaced with global clock modules with enable pins from the FPGA prototype; while gated clocks on non-critical paths have their enable pins removed, and their inputs and outputs are directly connected for continuity processing.
[0096] The fifth step involves performing a post-synthesis simulation on each circuit driven by either a switched-on or replaced gated clock, checking the correctness of the output signal. If correct, the circuit with the modified gated clock is considered functionally equivalent, and an engineering version is implemented based on this. If incorrect, the RTL code of the circuit is investigated based on the erroneous signal to pinpoint the cause of the error, and the RTL code is modified. After modification, step five is executed again, and a post-synthesis simulation is performed to check the correctness of the output signal.
[0097] The sixth step, after checking all the gated clock drive circuits and ensuring that all circuits function correctly, is to synthesize and implement the engineering version. This way, before the engineering version is completed, it can be ensured that the circuits in the FPGA prototype are functionally equivalent to those in the chip design after modifying the gated clock.
[0098] This embodiment of a gated clock processing method has at least the following beneficial technical effects: On the one hand, it moves the circuit function check of the FPGA prototype after the gated clock is modified from the online debugging stage of the engineering version to the synthesis stage of the engineering version, predicting problems and hidden dangers of the circuit driven by the gated clock in advance, and advancing the RTL code investigation stage, thereby improving the efficiency of FPGA prototype verification. On the other hand, for the circuit function check of the FPGA prototype after the gated clock is modified, each circuit driven by the modified gated clock is simulated separately after synthesis to check whether the output signal is correct. These circuit simulation checks can be performed in parallel, accelerating the circuit checking efficiency in the FPGA prototype, avoiding repeated synthesis and implementation of the engineering version, saving a lot of debugging time; significantly improving the efficiency of gated clock processing and reducing R&D costs.
[0099] In some embodiments, please refer to Figure 3 As shown, the present invention also provides a gated clock processing device 200, the device comprising:
[0100] Identification module 201, configured to identify all gated clocks in the FPGA prototype circuit;
[0101] Search module 202 is configured to perform a drive circuit search for each identified gated clock to obtain all associated circuits related to the drive circuit corresponding to each gated clock.
[0102] The acquisition module 203 is configured to perform engineering version synthesis on the FPGA prototype circuit before the gated clock is modified, and acquire the timing analysis report output after synthesis.
[0103] The determination module 204 is configured to obtain the critical clock path affecting timing convergence based on the timing analysis report, and determine the gated clock modification method based on the critical clock path when it is necessary to modify the gated clock.
[0104] The inspection module 205 is configured to perform a synthesis simulation of the modified gated clock separately, and check whether the output signal of each associated circuit corresponding to the modified gated clock is correct based on the simulation results.
[0105] Modification module 206 is configured to modify the RTL code of a certain associated circuit in response to an incorrect output signal of that associated circuit.
[0106] Return module 207 is configured to return the simulation after synthesizing the modified gated clock separately, and check whether the output signal of each associated circuit corresponding to the modified gated clock is correct based on the simulation results, until the output signals of all associated circuits corresponding to the modified gated clock are correct.
[0107] The aforementioned gated clock processing device can perform efficient and comprehensive consistency checks on the circuit functions in the FPGA prototype after the gated clock is modified, predict problems and potential risks in the circuit driven by the gated clock in advance, improve the efficiency of gated clock processing in the RTL code investigation stage, realize fully automated gated clock processing and checking, reduce the workload of R&D personnel, and lower R&D costs.
[0108] It should be noted that the specific limitations of the gated clock processing device can be found in the limitations of the gated clock processing method above, and will not be repeated here. Each module in the aforementioned gated clock processing device can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in the processor of the electronic device in hardware form or independently of it, or stored in the memory of the electronic device in software form, so that the processor can call and execute the operations corresponding to each module.
[0109] According to another aspect of the present invention, an electronic device is provided, which may be a server, and its internal structure diagram is shown below. Figure 4As shown. The electronic device includes a processor, memory, network interface, and database connected via a system bus. The processor provides computing and control capabilities. The memory includes a non-volatile storage medium and internal memory. The non-volatile storage medium stores an operating system, computer programs, and a database. The internal memory provides an environment for the operation of the operating system and computer programs in the non-volatile storage medium. The database stores data. The network interface communicates with external terminals via a network connection. When the computer program is executed by the processor, it implements the gated clock processing method described above. Specifically, the method includes the following steps:
[0110] Identify all gated clocks in the FPGA prototype circuit;
[0111] For each identified gated clock, a drive circuit search is performed to obtain all associated circuits related to the drive circuit corresponding to each gated clock.
[0112] Perform engineering version synthesis on the FPGA prototype circuit before the gated clock is modified, and obtain the timing analysis report output after synthesis;
[0113] Based on the timing analysis report, the key clock paths affecting timing convergence are obtained, and when it is necessary to modify the gated clock, the gated clock modification method is determined based on the key clock paths.
[0114] Perform a synthesis simulation of the modified gated clock separately, and check the output signal of each associated circuit corresponding to the modified gated clock based on the simulation results;
[0115] If the output signal of a certain associated circuit is incorrect, the RTL code of that associated circuit is modified.
[0116] Return to the step of performing a separate synthesis simulation on the modified gated clock and checking whether the output signal of each associated circuit corresponding to the modified gated clock is correct based on the simulation results, until the output signals of all associated circuits corresponding to the modified gated clock are correct.
[0117] According to another aspect of the present invention, a computer-readable storage medium is provided, please refer to Figure 5 As shown, a computer program is stored on it. When the computer program is executed by the processor, it implements the gated clock processing method described above. Specifically, it includes the following steps:
[0118] Identify all gated clocks in the FPGA prototype circuit;
[0119] For each identified gated clock, a drive circuit search is performed to obtain all associated circuits related to the drive circuit corresponding to each gated clock.
[0120] Perform engineering version synthesis on the FPGA prototype circuit before the gated clock is modified, and obtain the timing analysis report output after synthesis;
[0121] Based on the timing analysis report, the key clock paths affecting timing convergence are obtained, and when it is necessary to modify the gated clock, the gated clock modification method is determined based on the key clock paths.
[0122] Perform a synthesis simulation of the modified gated clock separately, and check the output signal of each associated circuit corresponding to the modified gated clock based on the simulation results;
[0123] If the output signal of a certain associated circuit is incorrect, the RTL code of that associated circuit is modified.
[0124] Return to the step of performing a separate synthesis simulation on the modified gated clock and checking whether the output signal of each associated circuit corresponding to the modified gated clock is correct based on the simulation results, until the output signals of all associated circuits corresponding to the modified gated clock are correct.
[0125] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. Any references to memory, storage, databases, or other media used in the embodiments provided in this application can include non-volatile and / or volatile memory. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memory can include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in various forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), dual data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), Rambus direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM), etc.
[0126] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0127] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.
Claims
1. A gated clock processing method, characterized in that, The method includes: Identify all gated clocks in the FPGA prototype circuit; For each identified gated clock, a drive circuit search is performed to obtain all associated circuits related to the drive circuit corresponding to each gated clock. Perform engineering version synthesis on the FPGA prototype circuit before the gated clock is modified, and obtain the timing analysis report output after synthesis; Based on the timing analysis report, the key clock paths affecting timing convergence are obtained, and when it is necessary to modify the gated clock, the gated clock modification method is determined based on the key clock paths. Perform a synthesis simulation of the modified gated clock separately, and check the output signal of each associated circuit corresponding to the modified gated clock based on the simulation results; If the output signal of a certain associated circuit is incorrect, the RTL code of that associated circuit is modified. Return to the step of performing a separate synthesis simulation on the modified gated clock and checking whether the output signal of each associated circuit corresponding to the modified gated clock is correct based on the simulation results, until the output signals of all associated circuits corresponding to the modified gated clock are correct.
2. The gated clock processing method according to claim 1, characterized in that, The steps for identifying all gated clocks in the FPGA prototype circuit include: Find all circuits in the FPGA prototype circuit that have one clock input, one clock enable, and one clock output. Iterate through the logic operation mode of each circuit found, and obtain all circuits that generate clock output by performing any one of the following operations: logical AND, logical OR, or logical NOT between the clock input and clock enable terminals, in order to obtain all gated clocks.
3. The gated clock processing method according to claim 1, characterized in that, The step of determining the gated clock modification method based on the critical clock path when it is necessary to modify the gated clock includes: Determine whether the gated clock that needs to be modified belongs to the critical clock path; If the gated clock needs to be modified and belongs to the critical clock path, then the method for modifying the gated clock is to replace the gated clock with the global clock module with clock enable in the FPGA prototype.
4. The gated clock processing method according to claim 3, characterized in that, The step of determining the gated clock modification method based on the critical clock path when it is necessary to modify the gated clock further includes: In response to the need to modify the gated clock, which is not part of the critical clock path, it is confirmed that the modification method for the gated clock is to remove the clock enable terminal and directly connect the clock input terminal and the clock output terminal in the circuit corresponding to the gated clock that needs to be modified to perform a connection process.
5. The gated clock processing method according to claim 4, characterized in that, If multiple gated clocks need to be modified, the step of determining the gated clock modification method based on the critical clock path when gated clocks need to be modified further includes: Iterate through each gated clock that needs to be modified to obtain the corresponding gated clock modification method for each gated clock; Apply the corresponding gated clock modification method to each gated clock that needs modification to perform the modification operation.
6. The gated clock processing method according to claim 1, characterized in that, The step of modifying the RTL code of a certain associated circuit in response to an incorrect output signal of that associated circuit includes: Acquire all signals where the output signal contains errors; For each erroneous output signal, locate the target associated circuit it belongs to, and obtain the target RTL code corresponding to the target associated circuit; Investigate the target RTL code to locate the cause of the error, and modify the target RTL code based on the cause of the error.
7. The gated clock processing method according to claim 1, characterized in that, The method further includes: If the output signals of all associated circuits corresponding to the modified gated clock are correct, then the engineering version is synthesized and released again.
8. A gated clock processing device, characterized in that, The device includes: The identification module is configured to identify all gated clocks in the FPGA prototype circuit. The search module is configured to perform a drive circuit search for each identified gated clock to obtain all associated circuits related to the drive circuit corresponding to each gated clock. The acquisition module is configured to perform engineering version synthesis on the FPGA prototype circuit before the gated clock is modified, and acquire the timing analysis report output after synthesis. The determination module is configured to obtain the critical clock path affecting timing convergence based on the timing analysis report, and determine the gated clock modification method based on the critical clock path when it is necessary to modify the gated clock. The inspection module is configured to perform a synthesis simulation of the modified gated clock separately, and check whether the output signal of each associated circuit corresponding to the modified gated clock is correct based on the simulation results. A modification module is configured to modify the RTL code of a certain associated circuit in response to an incorrect output signal of that associated circuit. The return module is configured to return the simulation after synthesizing the modified gated clock separately, and check whether the output signal of each associated circuit corresponding to the modified gated clock is correct based on the simulation results, until the output signals of all associated circuits corresponding to the modified gated clock are correct.
9. An electronic device, characterized in that, include: At least one processor; as well as A memory storing a computer program executable in the processor, wherein the processor executes the program to perform the method according to any one of claims 1-7.
10. A computer-readable storage medium storing a computer program, characterized in that, When the computer program is executed by a processor, it performs the method described in any one of claims 1-7.