Method, device, equipment and storage medium for updating photolithography mask

Abstract

Embodiments of the present application provide a photolithography mask updating method, device, equipment and storage medium, and relate to the chip technical field. The method comprises: acquiring a parameter index of a mask graph corresponding to a target chip layout, the parameter index being used to indicate imaging quality and complexity of the mask graph; determining a correction edge placement error loss function according to a correction edge placement error of the target chip layout and the parameter index; wherein the correction edge placement error is used to correct a wafer imaging pattern generated based on the mask graph; determining a loss function used for updating the mask graph according to the correction edge placement error loss function; and updating the mask graph according to the loss function. The present application can generate a mask graph with high quality and low complexity, and can significantly shorten the optimization time compared with the OPC algorithm.

Description

Technical Field

[0001] This application relates to the field of chip technology, and in particular to a method, apparatus, device, and storage medium for updating a photomask. Background Technology

[0002] In the chip manufacturing process, it is necessary to obtain the mask images corresponding to each chip layout in order to perform photolithography exposure.

[0003] In related technologies, a photomask updating method based on Optical Proximity Correction (OPC) is provided. The OPC algorithm uses computational methods to correct the pattern on the mask, so that the pattern projected onto the photoresist conforms as closely as possible to the design requirements, which is a photolithography resolution enhancement technique.

[0004] However, as chip layout features become smaller and more complex, traditional rule-based or model-based OPC algorithms produce masks of low quality and are computationally expensive. Summary of the Invention

[0005] This application provides a method, apparatus, device, and storage medium for updating photolithographic masks, which can improve the generation quality of photolithographic masks and reduce computational time costs. The technical solution is as follows:

[0006] According to one aspect of the embodiments of this application, a method for updating a photolithographic mask is provided, the method comprising:

[0007] Obtain the parameter indicators of the mask image corresponding to the target chip layout, wherein the parameter indicators are used to indicate the imaging quality and complexity of the mask image;

[0008] Based on the corrected edge placement error of the target chip layout and the parameter index, a corrected edge placement error loss function is determined; wherein, the corrected edge placement error is used to correct the wafer imaging pattern generated based on the mask image;

[0009] Based on the corrected edge placement error loss function, a loss function for updating the mask image is determined;

[0010] The mask image is updated according to the loss function.

[0011] According to one aspect of the embodiments of this application, a photomask updating apparatus is provided, the apparatus comprising:

[0012] The indicator acquisition module is used to acquire the parameter indicators of the mask image corresponding to the target chip layout. The parameter indicators are used to indicate the imaging quality and complexity of the mask image.

[0013] An error determination module is used to determine a correction edge placement error loss function based on the correction edge placement error of the target chip layout and the parameter index; wherein the correction edge placement error is used to correct the wafer imaging pattern generated based on the mask image;

[0014] The loss determination module is used to determine a loss function for updating the mask image based on the corrected edge placement error loss function.

[0015] The mask update module is used to update the mask image according to the loss function.

[0016] According to one aspect of the embodiments of this application, a computer device is provided, the computer device including a processor and a memory, the memory storing a computer program, the computer program being loaded and executed by the processor to implement the above-described method for updating a photolithographic mask.

[0017] According to one aspect of the embodiments of this application, a computer-readable storage medium is provided, wherein a computer program is stored in the computer-readable storage medium, the computer program being loaded and executed by a processor to implement the above-described method for updating a photomask.

[0018] According to one aspect of the embodiments of this application, a computer program product is provided, the computer program product including a computer program stored in a computer-readable storage medium. A processor of a computer device reads the computer program from the computer-readable storage medium, and the processor executes the computer program, causing the computer device to perform the above-described photomask updating method.

[0019] The technical solutions provided in this application embodiment may have the following beneficial effects:

[0020] By obtaining the parameter indices of the mask image corresponding to the target chip layout, which indicate the imaging quality and complexity of the mask image, a loss function for updating the mask image is determined based on these parameters. When updating the mask image based on this loss function, the optimization objectives are to improve the imaging quality and reduce the complexity of the mask image, thereby generating a high-quality, low-complexity mask image. Furthermore, updating and optimizing the mask image based on the loss function significantly shortens the optimization time compared to the OPC algorithm.

[0021] In addition, when calculating the loss function used to update the mask, a corrected edge placement error loss function is considered. This corrected edge placement error loss function is determined based on the corrected edge placement error of the target chip layout and the parameter indicators of the mask. The corrected edge placement error is used to correct the wafer imaging pattern generated based on the mask. In this way, the corrected edge placement error loss function can be used to provide constraints during the mask update and optimization process, so that the wafer imaging pattern generated based on the mask is as close as possible to the target chip layout, thereby improving the efficiency and accuracy of optimization.

[0022] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and do not limit this application. Attached Figure Description

[0023] Figure 1 This is a flowchart of a photomask updating method provided in one embodiment of this application;

[0024] Figure 2 This is a flowchart of a photomask updating method provided in another embodiment of this application;

[0025] Figure 3 This is a schematic diagram of a target chip layout and its corresponding correction for edge placement error provided in one embodiment of this application;

[0026] Figure 4 This is a schematic diagram of a target chip layout provided in one embodiment of this application;

[0027] Figure 5 This is a schematic diagram illustrating the correction of edge placement error provided in one embodiment of this application;

[0028] Figure 6 This is a flowchart of a photomask updating method provided in another embodiment of this application;

[0029] Figure 7 This is a block diagram of a photomask updating apparatus provided in one embodiment of this application;

[0030] Figure 8 This is a block diagram of a photomask updating apparatus provided in another embodiment of this application;

[0031] Figure 9 This is a structural block diagram of a computer device provided in one embodiment of this application. Detailed Implementation

[0032] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of methods consistent with some aspects of this application as detailed in the appended claims.

[0033] First, let me introduce some of the terms used in this application.

[0034] Chip layout: Also known as integrated circuit layout, it is a planar geometric description of the actual physical state of an integrated circuit. The integrated circuit layout is the result of the physical design, the lowest-level step in integrated circuit design. Physical design uses placement and routing techniques to convert the results of logic synthesis into a layout file. This file contains the shape, area, and location information of each hardware unit on the chip.

[0035] Optical Proximity Correction (OPC) is a photolithography resolution enhancement technique that uses computational methods to correct the pattern on a photomask so that the pattern projected onto the photoresist closely matches the design requirements. In photolithography, the pattern on the mask is projected onto the photoresist through an exposure system. Due to imperfections in the optical system and diffraction effects, the pattern on the photoresist and the pattern on the mask are not perfectly identical. If these distortions are not corrected, they can significantly alter the electrical performance of the manufactured circuits. Optical Proximity Correction adjusts the topology of the transparent areas on the photomask or adds small sub-resolution auxiliary patterns to the mask to make the image in the photoresist as close as possible to the mask pattern. OPC also compensates for the degradation in image quality of the photolithography system by changing the amplitude of the transmitted light from the mask. OPC is primarily used in the manufacturing process of semiconductor devices.

[0036] Photolithography mask: A photolithography mask is a light-masking film, similar in function to photography. Through a photolithography mask, a portion of the photoresist "underneath" the mask becomes photosensitive (and insoluble in organic chemicals), while another portion remains photosensitive (and readily soluble in organic chemicals), thus creating the desired pattern. In the manufacturing process of planar transistors and integrated circuits, multiple photolithography steps are required. Therefore, a set of photolithography masks with specific geometric patterns must be prepared. Photolithography mask preparation involves creating mask patterns of the required size and precision according to the geometric patterns required by the transistor and integrated circuit parameters, following a selected method. These patterns are then repeatedly arranged on a mask substrate at specific intervals and layouts, allowing for the mass production of photolithography masks for use in photolithography processes.

[0037] Artificial intelligence (AI) is the theory, methods, technology, and application systems that use digital computers or machines controlled by digital computers to simulate, extend, and expand human intelligence, perceive the environment, acquire knowledge, and use that knowledge to achieve optimal results. In other words, AI is a comprehensive technology within computer science that attempts to understand the essence of intelligence and produce a new kind of intelligent machine that can react in a way similar to human intelligence. AI studies the design principles and implementation methods of various intelligent machines, enabling them to possess the functions of perception, reasoning, and decision-making.

[0038] Artificial intelligence (AI) is a comprehensive discipline encompassing a wide range of fields, including both hardware and software technologies. Fundamental AI technologies generally include sensors, dedicated AI chips, cloud computing, distributed storage, big data processing, operating / interactive systems, and mechatronics. AI software technologies primarily include computer vision, speech processing, natural language processing, and machine learning / deep learning.

[0039] In this embodiment of the application, the idea of ​​calculating gradients based on loss functions in machine learning is adopted when updating and optimizing the mask image. By calculating the loss function used to update the mask image, and then continuously updating and optimizing the mask image with the goal of minimizing the value of the loss function, the updated mask image is obtained when the stopping optimization condition is met.

[0040] The method provided in this application can also be extended to other stages of integrated circuit design, such as chip logic circuit simulation, chip thermal transport simulation, chip performance testing, chip defect detection, light source-mask co-optimization, and other EDA (Electronic Design Automation) fields. For example, when integrated into an EDA computing platform or combined with mainstream computational lithography software, chip manufacturers can input chip layouts and obtain high-quality and low-complexity lithography masks through the technical solution of this application, thereby providing masks for subsequent chip lithography processes and significantly reducing the time and cost for chip manufacturers to generate lithography masks.

[0041] This application Figure 1 A method for updating a photolithographic mask is provided, which may include the following steps:

[0042] S11. Determine the loss function;

[0043] First, define the loss function for mask optimization. Then, minimize this loss function as the objective to optimize and update the mask.

[0044] In this embodiment, the loss function design considers a corrected edge placement error loss function, which is determined based on the corrected edge placement error of the target chip layout and the parameter indices of the mask image corresponding to the target chip layout. The parameter indices indicate the imaging quality and complexity of the mask image, while the corrected edge placement error is used to correct the wafer imaging pattern generated based on the mask image. Therefore, the corrected edge placement error loss function provides constraints for mask image update optimization, ensuring that the mask image is as close as possible to the target chip layout, thereby improving the efficiency and accuracy of optimization.

[0045] For details on how the loss function is calculated, please refer to the description in the examples below.

[0046] S12. Initialize the mask pattern corresponding to the target chip layout;

[0047] This step generates an initialized mask image corresponding to the target chip layout. In some embodiments, the target chip layout can be directly used as the initialized mask image. In some embodiments, the target chip layout can also be preprocessed to obtain the initialized mask image. This preprocessing can speed up the mask update efficiency and simplify the mask update process.

[0048] S13. Determine the optimization direction of the mask image based on the loss function;

[0049] For example, the optimization direction of the mask image can be determined by gradient descent algorithms such as steepest descent or conjugate gradient.

[0050] S14. Update the mask image according to the optimization direction;

[0051] The pixel values ​​of each pixel in the mask image are updated based on the calculated optimization direction (i.e., gradient).

[0052] S15. Repeat S13 and S14 until the maximum number of iterations or the gradient is reduced to the desired value;

[0053] S16. Perform binarization on the updated mask image and output the binarized mask image.

[0054] In the updated mask image, the pixel values ​​of each pixel are continuously distributed, for example, they can be continuous values ​​between [0,1]. The purpose of binarization is to binarize the pixel values ​​of each pixel into 0 and 1, so that the pixel values ​​of each pixel become 0 or 1, and finally obtain the binarized mask image.

[0055] The method provided in this application can be executed by a computer device. A computer device refers to any electronic device with data computing, processing and storage capabilities, such as a PC (Personal Computer), tablet computer, smartphone, wearable device, intelligent robot, intelligent voice interaction device, smart home appliance, vehicle terminal, aircraft, medical device and other terminal devices, or a server. This application does not limit the scope of the application to this.

[0056] Please refer to Figure 2 The diagram illustrates a flowchart of a photomask updating method according to another embodiment of this application. This method may include the following steps (201-204):

[0057] Step 201: Obtain the parameter index of the mask image corresponding to the target chip layout. The parameter index is used to indicate the imaging quality and complexity of the mask image.

[0058] The target chip layout refers to the graphical representation of the target chip. The target chip layout can be the layout of a specific functional layer of the target chip, such as a connectivity layer, metalline layer, or other functional layers. Furthermore, in this application embodiment, the type of target chip is not limited, and includes, but is not limited to, quantum chips, home appliance chips, mobile phone chips, computer chips, wearable device chips, industrial robot chips, etc.

[0059] The mask image corresponding to the target chip layout is an image used to distinguish between the areas in the target chip layout where components need to be placed and the areas where components do not need to be placed.

[0060] The parameters of a mask image can be obtained by analyzing the mask image, such as by analyzing the pixel values ​​of each pixel in the mask image. In the embodiments of this application, the parameters of the mask image can reflect both the imaging quality (or imaging accuracy) and the complexity of the mask image. Subsequent updates and optimizations of the mask image aim to improve its imaging quality, making the image as close as possible to the target chip layout, and to reduce its complexity, thereby improving its manufacturability.

[0061] Step 202: Determine the edge placement error correction loss function based on the corrected edge placement error and parameter index of the target chip layout; wherein, the edge placement error correction is used to correct the wafer imaging pattern generated based on the mask image.

[0062] Corrected edge placement error of the target chip layout is used to correct the wafer imaging pattern generated based on the mask image, so that the wafer imaging pattern generated based on the mask image is as close as possible to the target chip layout.

[0063] For example, such as Figure 3 As shown, it illustrates the target chip layout and its corresponding corrected edge placement error schematic. For clarity, Figure 3 It can be further broken down into Figure 4 and Figure 5 Two pictures, one of which Figure 4 A schematic diagram of the target chip layout is shown. Figure 5 A schematic diagram illustrating the correction of edge placement errors is shown. (Refer to reference.) Figure 3 and Figure 4 Frame 31 represents the area in the target chip layout where components need to be placed, while the area outside frame 31 represents the area in the target chip layout where components do not need to be placed. For example... Figure 3 As shown, several sampling points 32 can be taken on the wireframe 31, and straight line segments 33 perpendicular to the wireframe 31 are drawn through the sampling points 32. These straight line segments 33 constitute a schematic diagram for correcting edge placement errors, as shown. Figure 5 As shown. The aforementioned straight line segment 33 can also be called an error line. The correction of edge placement error is related to the length of the straight line segment 33 and the distance between adjacent straight line segments 33. The purpose of correcting edge placement error is to correct the wafer imaging pattern generated based on the mask image, so that the wafer imaging pattern generated based on the mask image is as close as possible to the target chip layout.

[0064] In this embodiment, a correction edge placement error loss function is determined by combining the corrected edge placement error of the target chip layout and the parameter indices of the mask image corresponding to the target chip layout. This correction edge placement error loss function can be understood as the result of adjusting the correction edge placement error based on the parameter indices; this result is referred to as the correction edge placement error loss function in this application. The correction edge placement error loss function reflects the dependency between the correction edge placement error and the parameter indices. It provides constraints to ensure that the mask image is as close as possible to the target chip layout, thereby improving the efficiency and accuracy of the optimization.

[0065] Step 203: Determine the loss function used to update the mask image based on the corrected edge placement error loss function.

[0066] After determining the loss function for correcting edge placement error, a loss function for updating the mask image is further determined based on this loss function.

[0067] In some embodiments, the corrected edge placement error loss function can be directly used as the loss function for updating the mask image.

[0068] In some embodiments, a loss function for updating the mask image can be determined based on the corrected edge placement error loss function and the parameter index. For example, a weighted sum of the corrected edge placement error loss function and the parameter index can be used to obtain the loss function for updating the mask image.

[0069] Step 204: Update the mask image according to the loss function.

[0070] After calculating the loss function, the pixel values ​​of each pixel in the mask image are continuously adjusted through multiple iterations with the goal of minimizing the value of the loss function, so as to obtain the updated mask image.

[0071] The technical solution provided in this application obtains the parameter indicators of the mask image corresponding to the target chip layout. Since these parameter indicators are used to indicate the imaging quality and complexity of the mask image, after determining the loss function for updating the mask image based on these parameter indicators, updating the mask image based on this loss function can aim to improve the imaging quality and reduce the complexity of the mask image, thereby generating a high-quality, low-complexity mask image. Moreover, updating and optimizing the mask image based on the loss function can significantly shorten the optimization time compared to the OPC algorithm.

[0072] In addition, when calculating the loss function used to update the mask image, a corrected edge placement error loss function is considered. This corrected edge placement error loss function is determined based on the corrected edge placement error of the target chip layout and the parameter indicators of the mask image corresponding to the target chip layout. The corrected edge placement error is used to correct the wafer imaging pattern generated based on the mask image. In this way, the corrected edge placement error loss function can be used to provide constraints during the mask image update and optimization process, so that the imaging of the mask image is as close as possible to the target chip layout, thereby improving the efficiency and accuracy of optimization.

[0073] Please refer to Figure 6 This illustrates a flowchart of a photomask updating method according to another embodiment of this application. The method may include the following steps (601-605):

[0074] Step 601: Obtain the parameter indices of the mask image corresponding to the target chip layout. The parameter indices include: imaging error, discrete regularization term, and total variational regularization term.

[0075] Imaging error measures the difference between the wafer image pattern generated from the mask and the target chip layout. A smaller imaging error indicates a smaller difference between the generated wafer image pattern and the target chip layout, meaning a higher quality mask. Conversely, a larger imaging error indicates a greater difference between the generated wafer image pattern and the target chip layout, meaning a lower quality mask.

[0076] In some embodiments, for each pair of pixels at corresponding positions in the wafer imaging pattern and the target chip layout, the difference between the two pixel values ​​in the pixel pair is calculated; and the imaging error is determined based on the difference between the two pixel values ​​in each pair in the wafer imaging pattern and the target chip layout.

[0077] For example, the imaging error L Aerial The calculation formula is as follows:

[0078]

[0079] Where Z represents the wafer imaging pattern, Z t This represents the target chip layout, where Z(x,y) represents the pixel value of the pixel at coordinate (x,y) in the wafer imaging pattern Z. t (x,y) represents the target chip layout Z. t The pixel value at coordinate (x, y). γ is an adjustable parameter; for example, γ = 2. L represents the sum of the perimeters of the areas in the target chip layout where components need to be placed, for example... Figure 3 and Figure 4 The sum of the perimeters of all wireframes 31 in the equation. N represents the maximum values ​​of the x-coordinate and y-coordinate. From the above formula, it can be seen that after introducing the parameter L, the imaging error L... Aerial The dimension of is a unit of length, consistent with the dimension of chip node size. Chip node size refers to the size of the transistor gate circuitry on the chip surface, such as 14nm (nanometer), 10nm, 7nm, 5nm, etc.

[0080] The discrete regularization term measures the difference between continuously distributed pixel values ​​and binary discrete values ​​in the mask image. During the mask image update and optimization process, the pixel values ​​of each pixel in the mask image are values ​​between [0,1]. Ultimately, a binarized mask image needs to be generated, meaning each pixel's value is either 0 or 1. Therefore, the discrete regularization term is needed to characterize the difference between continuously distributed pixel values ​​and binary discrete values ​​(i.e., 0 and 1) in the mask image, and this difference should not be too large during the mask image update and optimization process. Optionally, a larger discrete regularization term indicates a greater difference between continuously distributed pixel values ​​and binary discrete values ​​in the mask image; conversely, a smaller discrete regularization term indicates a smaller difference between continuously distributed pixel values ​​and binary discrete values ​​in the mask image.

[0081] In some embodiments, for each pixel in the mask image, the difference value corresponding to the pixel is determined based on the difference between the pixel value and the binary discrete value; and the discrete regularization term is determined based on the difference value corresponding to each pixel in the mask image.

[0082] For example, the discrete regularization term R D The calculation formula is as follows:

[0083]

[0084] Where M represents the mask image, and M(x,y) represents the pixel value of the pixel at coordinate (x,y) in mask M. L represents the sum of the perimeters of the areas in the target chip layout where components need to be placed. N represents the maximum values ​​of the x-coordinate and y-coordinate.

[0085] The total variational regularization term is used to measure the complexity of the mask image. Optionally, a larger value of the total variational regularization term indicates a higher complexity of the mask image; conversely, a smaller value indicates a lower complexity. During the update and optimization of the mask image, its complexity should be reduced as much as possible, eliminating small complex structures (such as islands, hollow areas, jagged edges, and protrusions) to improve the manufacturability of the final generated mask image.

[0086] In some embodiments, a difference matrix is ​​obtained based on the difference between the pixel values ​​at corresponding positions in the mask image and the target chip layout; and a total variational regularization term is determined based on the difference matrix and a set matrix.

[0087] For example, the total variational regularization term R TV The calculation formula is as follows:

[0088]

[0089] Where M represents the mask image, Z tLet f represent the target chip layout, D represent the difference matrix, D represent the setting matrix (or fixed matrix), for example, the setting matrix D can be the first derivative of the matrix, T represent the matrix transpose, and ||.|1 represents the norm of 1. Represents matrix product. L represents the sum of the perimeters of the areas in the target chip layout where components need to be placed.

[0090] Step 602: Determine the edge placement error correction loss function based on the corrected edge placement error and parameter index of the target chip layout; wherein, the edge placement error correction is used to correct the wafer imaging pattern generated based on the mask image.

[0091] Since the parameters include imaging error, discrete regularization term, and total variational regularization term, the corrected edge placement error loss function can be determined based on the corrected edge placement error of the target chip layout, as well as the imaging error, discrete regularization term, and total variational regularization term.

[0092] In some embodiments, a first intermediate variable is calculated based on the corrected edge placement error and the imaging error; a second intermediate variable is calculated based on the corrected edge placement error and the discrete regularization term; a third intermediate variable is calculated based on the corrected edge placement error and the total variational regularization term; and a corrected edge placement error loss function is calculated based on the first intermediate variable, the second intermediate variable, and the third intermediate variable.

[0093] The aforementioned first intermediate variable can be referred to as the imaging edge placement error. For example, the first intermediate variable (or imaging edge placement error) L... Aerial-MEPE The calculation formula is as follows:

[0094]

[0095] The aforementioned second intermediate variable can be referred to as the edge placement error discrete regularization term. For example, the second intermediate variable (or edge placement error discrete regularization term) R... D-MEPE The calculation formula is as follows:

[0096]

[0097] The aforementioned third intermediate variable can be referred to as the total variational regularization term of the edge placement error. For example, the third intermediate variable (or the total variational regularization term of the edge placement error) R... TV-MEPE The calculation formula is as follows:

[0098]

[0099] MEPE (Modified Edge Placement Error) represents the correction of edge placement error, such as... Figure 3 and Figure 5The matrix is ​​composed of 3x3 straight line segments. ⊙ represents element-wise multiplication of the matrix. From the calculation formulas of imaging error, discrete regularization term, and total variational regularization term, it can be seen that the calculation results of these parameters have lost information related to the target chip layout. In this embodiment, by using MEPE to incorporate the relevant information of the target chip layout in the imaging edge placement error, edge placement error discrete regularization term, and edge placement error total variational regularization term, since MEPE carries the relevant information of the target chip layout, this corrected edge placement error loss function can provide constraints during the mask update and optimization process, making the mask image as close as possible to the target chip layout, thereby improving the efficiency and accuracy of optimization.

[0100] In some embodiments, a weighted summation of the first, second, and third intermediate variables is performed to obtain the corrected edge placement error loss function. For example, the corrected edge placement error loss function L... MEPE The calculation formula is as follows:

[0101] L MEPE =L Aerial-MEPE +αR D-MEPE +κR TV-MEPE

[0102] Where α and κ are adjustable coefficients used to balance L Aerial-MEPE R D-MEPE and R TV-MEPE The relative sizes of each item.

[0103] Step 603: Determine the loss function used to update the mask image based on the edge placement error correction loss function and parameter indices.

[0104] In some embodiments, a loss function for updating the mask image is determined based on a corrected edge placement error loss function, as well as imaging error, discrete regularization term, and total variational regularization term. Exemplarily, the corrected edge placement error loss function, imaging error, discrete regularization term, and total variational regularization term are weighted and summed to obtain the loss function for updating the mask image.

[0105] For example, the loss function L used to update the mask image total The calculation formula is as follows:

[0106] L total =L Aerial +αR D +κR TV +βL MEPE

[0107] Where α, κ, and β represent adjustable coefficients used to balance L Aerial RD R TV and L MEPE The relative magnitudes of each term. For example, α, κ, and β are 0.025, 0.06, and 2, respectively.

[0108] Step 604: Update the mask image according to the loss function.

[0109] In some embodiments, the optimization direction of the mask image is determined based on the loss function, and the mask image is updated according to the optimization direction.

[0110] In some embodiments, the steepest descent method is used to calculate the optimization direction of the mask image, including: calculating the gradient of the loss function with respect to the mask image, and determining the optimization direction of the mask image based on the gradient. That is, the optimization direction is the total loss function L... total About mask images gradient

[0111] In some embodiments, the conjugate gradient method is used to calculate the optimization direction of the mask, including: using the gradient of the loss function relative to the mask image as the initial optimization direction; and in each iteration of optimization, determining the optimization direction of the current iteration based on the gradient and the optimization direction of the previous iteration. That is, the initial optimization direction is... Subsequent optimization directions all retain the optimization direction of the previous step, while automatically adjusting the conjugate gradient factor η. k To avoid optimization stagnation.

[0112] For example, the gradient of the total loss function is defined as follows:

[0113]

[0114] in θ M and M th For example, θ is a preset constant. M and M th The values ​​are 4 and 0.225, respectively.

[0115] The gradient of the imaging error is defined as follows:

[0116]

[0117] Where, θ M and θ Z For example, θ is a preset constant. M and θ Z Take 4 and 50 respectively, H * It is the complex conjugate of the kernel function H of the lithography system, H fliP It was obtained by flipping H by 180°. This represents matrix convolution operation.

[0118] The gradient of the discrete regularization term is defined as follows:

[0119]

[0120] The gradient of the total variational regularization term is defined as follows:

[0121]

[0122] Where sign represents the sign function, i.e., sign(x) = 0, x = 0; sign(x) = 1, x > 0; sign(x) = -1, x < 0.

[0123] The gradient of the imaging edge placement error is defined as follows:

[0124]

[0125] The gradient of the discrete regularization term of the edge placement error is defined as follows:

[0126]

[0127] The gradient of the total variational regularization term of the edge placement error is defined as follows:

[0128]

[0129] Furthermore, after determining the optimization direction of the mask image based on the loss function, the mask image is updated according to this optimization direction. Optionally, the optimization step size adopts... The step size factor ε is set to a small value, such as 0.1. Additionally, the updated mask pixel values ​​may exceed 1 or be less than 0; therefore, the sigmoid function is used to fix the mask pixel values ​​between 0 and 1.

[0130] Step 605: Perform binarization on the updated mask to obtain the binarized mask corresponding to the target chip layout.

[0131] In some embodiments, for each pixel value in the updated mask, if the pixel value is greater than or equal to 0.5, the pixel value is set to 1; otherwise, if the pixel value is less than 0.5, the pixel value is set to 0, thereby obtaining a binarized mask.

[0132] If the loss function is constructed purely based on parameters such as imaging error, discrete regularization term, and total variational regularization term, the information of the target chip layout is lost in these parameters. In this embodiment, by calculating the imaging edge placement error, the discrete regularization term of the edge placement error, and the total variational regularization term of the edge placement error, a corrected edge placement error loss function is constructed based on the above. This allows the information of the target chip layout to be reintroduced by correcting the edge placement error. In this way, during the mask update and optimization process, the corrected edge placement error loss function can be used to provide constraints, making the mask image as close as possible to the target chip layout, thereby improving the efficiency and accuracy of optimization.

[0133] Moreover, experimental results show that the loss function constructed based on the corrected edge placement error loss function, as well as the loss function constructed based on the imaging error, discrete regularization term, and total variational regularization term, has higher imaging quality and accuracy than the loss function constructed based solely on the imaging error, discrete regularization term, and total variational regularization term.

[0134] In some embodiments, the initialized mask is obtained by: modifying the target chip layout to obtain a modified chip layout; and converting the discretely distributed pixel values ​​in the modified chip layout into continuously distributed pixel values ​​to obtain the initialized mask.

[0135] In some embodiments, correcting the target chip layout to obtain a corrected chip layout includes: multiplying each pixel value in the target chip layout by a first value, and then adding the result to a second value to obtain the corrected chip layout. Optionally, the corrected chip layout... Here, Zt represents the target chip layout, and w1 and w2 are the first and second values ​​mentioned above, respectively. For example, using 0.98 and 0.1 for w1 and w2 respectively ensures that the calculated gradient is not too small, which is beneficial for subsequent gradient descent. The reason is that the pixel values ​​of each pixel in the target chip layout are either 0 or 1. If the target chip layout is directly used as the initial mask, the gradient will be very small during gradient optimization, which is detrimental to optimization efficiency. By modifying the target chip layout using the above formula, since the pixel values ​​of each pixel in the modified chip layout are no longer 0 or 1, using this modified chip layout as the initial mask, or generating an initial mask based on the modified chip layout, ensures that the calculated gradient is not too small, which helps to accelerate gradient descent and improve optimization efficiency.

[0136] In some embodiments, converting the discretely distributed pixel values ​​in the corrected chip layout into continuously distributed pixel values ​​to obtain the initialized mask image includes: mapping each pixel value in the corrected chip layout to the interval [0,1] using the sigmoid function to obtain the initialized mask image. Considering that discontinuous optimization of binary masks is very difficult, this application uses the sigmoid function to transform the discrete mask optimization problem into a continuous optimization problem, i.e. Where θ M and M th For example, θ is a preset constant. M and M th The values ​​are 4 and 0.225 respectively. Here, the sigmoid function can also act as a filter, filtering out small complex structures (such as islands, hollows, jagged edges, and protrusions) in the generated mask, thus increasing the manufacturability of the mask.

[0137] In some embodiments, wafer imaging patterns are obtained in the following manner:

[0138] Using a photolithography physical model, the light intensity distribution of the target chip layout on the wafer is calculated based on the mask pattern corresponding to the target chip layout; the wafer imaging pattern is then calculated based on the light intensity distribution.

[0139] The wafer imaging pattern Z is calculated using a photolithography physical model. This model obtains the light intensity distribution I imaged on the wafer, which is obtained by convolving the mask M with the photolithography system kernel function h. The kernel function can be obtained by singular value decomposition of the cross-transfer coefficients of the photolithography system (such as a 193 nm ring light source). The photolithography physical model is defined as follows:

[0140]

[0141] Among them, h k and ω k These are the k-th kernel function and its corresponding weight coefficient after singular value decomposition. This application uses the first 24 kernel functions and their corresponding weight coefficients after singular value decomposition, i.e., K = 24.

[0142] The wafer imaging pattern is obtained by transforming the light intensity distribution I using the sigmoid function, as defined below:

[0143]

[0144] Where θ Z and I th These are preset constants, for example, 50 and 0.225 respectively.

[0145] Optionally, during the calculation of light intensity distribution, matrix operations can be accelerated using a GPU (Graphics Processing Unit). Compared to using a CPU (Central Processing Unit) with a for loop to perform addition, subtraction, multiplication, and division operations between matrices, using a GPU to perform these operations fully leverages the GPU's computational performance advantages for matrices (or images), thus speeding up the calculation process.

[0146] The lithography physical models introduced above are mathematical and physical simulation models based on optical principles, such as the Hopkins diffraction lithography physical model for partially coherent imaging systems. Optionally, the code for the above lithography physical models can be implemented using open-source mathematical libraries (such as ptorch, tensorflow, etc.). This allows for easy acceleration of matrix operations using GPUs when calculating light intensity distribution using these lithography physical models.

[0147] In some embodiments, the influence of different process parameters on the mask pattern can also be considered. Multiple mask patterns corresponding to the target chip layout are generated using various different process parameters. Then, for each of these multiple mask patterns, the corresponding loss function is calculated using the method described in the above embodiments. After averaging the loss functions corresponding to the multiple mask patterns, an average loss function is obtained. The mask pattern is then optimized based on this average loss function to obtain a mask pattern with stronger process robustness.

[0148] The following are embodiments of the apparatus described in this application, which can be used to execute the embodiments of the method described in this application. For details not disclosed in the apparatus embodiments of this application, please refer to the embodiments of the method described in this application.

[0149] Please refer to Figure 7 This diagram illustrates a block diagram of a photomask updating apparatus according to an embodiment of this application. The apparatus has the functionality to implement the above-described photomask updating method example; this functionality can be implemented in hardware or by hardware executing corresponding software. The apparatus 700 can be the computer device described above, or it can be installed within a computer device. The apparatus 700 may include: an index acquisition module 710, an error determination module 720, a loss determination module 730, and a mask updating module 740.

[0150] The indicator acquisition module 710 is used to acquire the parameter indicators of the mask image corresponding to the target chip layout. The parameter indicators are used to indicate the imaging quality and complexity of the mask image.

[0151] The error determination module 720 is used to determine the edge placement error correction loss function based on the edge placement error correction of the target chip layout and the parameter index; wherein the edge placement error correction is used to correct the wafer imaging pattern generated based on the mask image.

[0152] The loss determination module 730 is used to determine a loss function for updating the mask image based on the corrected edge placement error loss function.

[0153] The mask update module 740 is used to update the mask image according to the loss function.

[0154] In some embodiments, the parameter indices include: imaging error, discrete regularization term, and total variational regularization term;

[0155] The imaging error is used to measure the difference between the wafer imaging pattern and the target chip layout;

[0156] The discrete regularization term is used to measure the difference between pixel values ​​that are continuously distributed in the mask image and binary discrete values;

[0157] The total variational regularization term is used to measure the complexity of the mask image.

[0158] In some embodiments, the error determination module 720 is configured to calculate a first intermediate variable based on the corrected edge placement error and the imaging error; calculate a second intermediate variable based on the corrected edge placement error and the discrete regularization term; calculate a third intermediate variable based on the corrected edge placement error and the total variational regularization term; and calculate the corrected edge placement error loss function based on the first intermediate variable, the second intermediate variable, and the third intermediate variable.

[0159] In some embodiments, the error determination module 720 is used to perform a weighted summation of the first intermediate variable, the second intermediate variable, and the third intermediate variable to obtain the corrected edge placement error loss function.

[0160] In some embodiments, the index acquisition module 710 is used to calculate the difference between two pixel values ​​in each corresponding pixel pair in the wafer imaging pattern and the target chip layout; and to determine the imaging error based on the difference between two pixel values ​​in each pixel pair in the wafer imaging pattern and the target chip layout.

[0161] In some embodiments, the index acquisition module 710 is configured to, for each pixel in the mask image, determine the difference value corresponding to the pixel based on the difference between the pixel value of the pixel and the binary discrete value; and determine the discrete regularization term based on the difference value corresponding to each pixel in the mask image.

[0162] In some embodiments, the index acquisition module 710 is used to obtain a difference matrix based on the difference between the pixel values ​​at corresponding positions in the mask image and the target chip layout; and to determine the total variational regularization term based on the difference matrix and a set matrix.

[0163] In some embodiments, the loss determination module 730 is configured to determine the loss function for updating the mask image based on the corrected edge placement error loss function and the parameter index.

[0164] In some embodiments, the mask update module 740 is configured to determine the optimization direction of the mask image based on the loss function, and update the mask image according to the optimization direction.

[0165] In some embodiments, the mask update module 740 is configured to calculate the gradient of the loss function relative to the mask image, and determine the optimization direction of the mask image based on the gradient; or, use the gradient of the loss function relative to the mask image as the initial optimization direction, and determine the optimization direction of the current iteration process in each iteration optimization process based on the gradient and the optimization direction of the previous iteration optimization process.

[0166] In some embodiments, such as Figure 8 As shown, the device 700 further includes: a mask initialization module 750, used to perform correction processing on the target chip layout to obtain a corrected chip layout; and to convert the discretely distributed pixel values ​​in the corrected chip layout into continuously distributed pixel values ​​to obtain the initialized mask image.

[0167] In some embodiments, the mask initialization module 750 is used to multiply each pixel value in the target chip layout by a first value and then add it to a second value to obtain the corrected chip layout.

[0168] In some embodiments, the mask initialization module 750 is used to map each pixel value in the corrected chip layout to the interval [0,1] using the sigmoid function to obtain the initialized mask image.

[0169] In some embodiments, such as Figure 8As shown, the device 700 further includes: a wafer imaging module 760, used to calculate the light intensity distribution of the target chip layout on the wafer based on the mask image using a photolithography physical model; wherein, the calculation of the light intensity distribution is accelerated by matrix operations through a GPU; and the wafer imaging pattern is calculated based on the light intensity distribution.

[0170] In some embodiments, such as Figure 8 As shown, the device 700 further includes a binary processing module 770, used to perform binarization processing on the updated mask image to obtain a binary mask image corresponding to the target chip layout.

[0171] It should be noted that the apparatus provided in the above embodiments is only illustrated by the division of the above functional modules when implementing its functions. In actual applications, the above functions can be assigned to different functional modules as needed, that is, the internal structure of the device can be divided into different functional modules to complete all or part of the functions described above. In addition, the apparatus and method embodiments provided in the above embodiments belong to the same concept, and the specific implementation process can be found in the method embodiments, which will not be repeated here.

[0172] Please refer to Figure 9 This diagram illustrates a structural block diagram of a computer device according to an embodiment of this application. The computer device is used to implement the photomask updating method provided in the above embodiments. Specifically:

[0173] The computer device 900 includes a CPU (Central Processing Unit) 901, a system memory 904 including RAM (Random Access Memory) 902 and ROM (Read-Only Memory) 903, and a system bus 905 connecting the system memory 904 and the central processing unit 901. The computer device 900 also includes a basic I / O (Input / Output) system 906 that facilitates information transfer between various components within the computer, and a mass storage device 907 for storing the operating system 913, application programs 914, and other program modules 915.

[0174] The basic input / output system 906 includes a display 908 for displaying information and an input device 909 for user input, such as a mouse or keyboard. Both the display 908 and the input device 909 are connected to the central processing unit 901 via an input / output controller 910 connected to the system bus 905. The basic input / output system 906 may also include the input / output controller 910 for receiving and processing input from multiple other devices such as a keyboard, mouse, or electronic stylus. Similarly, the input / output controller 910 also provides output to a display screen, printer, or other types of output devices.

[0175] The mass storage device 907 is connected to the central processing unit 901 via a mass storage controller (not shown) connected to the system bus 905. The mass storage device 907 and its associated computer-readable media provide non-volatile storage for the computer device 900. That is, the mass storage device 907 may include computer-readable media (not shown) such as a hard disk or a CD-ROM (Compact Disc Read-Only Memory) drive.

[0176] Without loss of generality, the computer-readable medium may include computer storage media and communication media. Computer storage media include volatile and non-volatile, removable and non-removable media implemented using any method or technology for storing information such as computer-readable instructions, data structures, program modules, or other data. Computer storage media include RAM, ROM, EPROM (Erasable Programmable Read Only Memory), EEPROM (Electrically Erasable Programmable Read Only Memory), flash memory or other solid-state storage, CD-ROM, DVD (Digital Video Disc) or other optical storage, magnetic tape cassettes, magnetic tape, disk storage, or other magnetic storage devices. Of course, those skilled in the art will recognize that the computer storage media are not limited to the above-mentioned types. The system memory 904 and mass storage device 907 described above can be collectively referred to as memory.

[0177] According to various embodiments of this application, the computer device 900 can also be connected to a remote computer on a network, such as the Internet. That is, the computer device 900 can be connected to a network 912 via a network interface unit 911 connected to the system bus 905, or the network interface unit 911 can be used to connect to other types of networks or remote computer systems (not shown).

[0178] In an exemplary embodiment, a computer-readable storage medium is also provided, wherein a computer program is stored therein, which, when executed by a processor, implements the above-described method for updating the photomask.

[0179] Optionally, the computer-readable storage medium may include: ROM (Read-Only Memory), RAM (Random-Access Memory), SSD (Solid State Drives), or optical disc, etc. The random access memory may include ReRAM (Resistance Random Access Memory) and DRAM (Dynamic Random Access Memory).

[0180] In an exemplary embodiment, a computer program product is also provided, comprising a computer program stored in a computer-readable storage medium. A processor of a computer device reads the computer program from the computer-readable storage medium and executes the computer instructions, causing the computer device to perform the aforementioned photomask updating method.

[0181] It should be understood that "multiple" as used in this article refers to two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone. The character " / " generally indicates that the preceding and following related objects have an "or" relationship.

[0182] The above description is merely an exemplary embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A method for updating a photolithographic mask, characterized in that, The method includes: Obtain the parameter indicators of the mask image corresponding to the target chip layout, wherein the parameter indicators are used to indicate the imaging quality and complexity of the mask image; Based on the corrected edge placement error of the target chip layout and the parameter index, a corrected edge placement error loss function is determined; wherein, the corrected edge placement error is used to correct the wafer imaging pattern generated based on the mask image; Based on the corrected edge placement error loss function, a loss function for updating the mask image is determined; The mask image is updated according to the loss function; The correction of edge placement error is a matrix that carries information related to the target chip layout. It is formed by taking a number of sampling points on the boundary of the area where components need to be placed in the target chip layout, and then constructing error line segments perpendicular to the boundary through the sampling points. The parameter index loses relevant information about the target chip layout during calculation, while the corrected edge placement error carries relevant information about the target chip layout. By incorporating the relevant information about the target chip layout into the corrected edge placement error loss function, constraints are provided during the mask update and optimization process.

2. The method according to claim 1, characterized in that, The parameters include: imaging error, discrete regularization term, and total variational regularization term; The imaging error is used to measure the difference between the wafer imaging pattern and the target chip layout; The discrete regularization term is used to measure the difference between pixel values ​​that are continuously distributed in the mask image and binary discrete values; The total variational regularization term is used to measure the complexity of the mask image.

3. The method according to claim 2, characterized in that, The step of determining the edge placement error correction loss function based on the corrected edge placement error of the target chip layout and the parameter indicators includes: The first intermediate variable is calculated based on the corrected edge placement error and the imaging error; The second intermediate variable is calculated based on the corrected edge placement error and the discrete regularization term; The third intermediate variable is calculated based on the corrected edge placement error and the total variational regularization term; The corrected edge placement error loss function is calculated based on the first intermediate variable, the second intermediate variable, and the third intermediate variable.

4. The method according to claim 3, characterized in that, The step of calculating the corrected edge placement error loss function based on the first intermediate variable, the second intermediate variable, and the third intermediate variable includes: The first intermediate variable, the second intermediate variable, and the third intermediate variable are weighted and summed to obtain the corrected edge placement error loss function.

5. The method according to claim 2, characterized in that, The parameters for obtaining the mask image corresponding to the target chip layout include: For each pair of pixels at corresponding positions in the wafer imaging pattern and the target chip layout, calculate the difference between the two pixel values ​​in the pixel pair; The imaging error is determined based on the difference between the two pixel values ​​in each pixel pair in the wafer imaging pattern and the target chip layout.

6. The method according to claim 2, characterized in that, The parameters for obtaining the mask image corresponding to the target chip layout include: For each pixel in the mask image, the difference value corresponding to the pixel is determined based on the difference between the pixel value and the binary discrete value. The discrete regularization term is determined based on the difference value corresponding to each pixel in the mask image.

7. The method according to claim 2, characterized in that, The parameters for obtaining the mask image corresponding to the target chip layout include: The difference matrix is ​​obtained by comparing the pixel values ​​at corresponding positions in the mask image and the target chip layout. The total variation regularization term is determined based on the difference matrix and the set matrix.

8. The method according to claim 1, characterized in that, The step of determining the loss function for updating the mask image based on the corrected edge placement error loss function includes: The loss function used to update the mask image is determined based on the corrected edge placement error loss function and the parameter index.

9. The method according to claim 1, characterized in that, The step of updating the mask image according to the loss function includes: The optimization direction of the mask image is determined based on the loss function; The mask image is updated according to the optimization direction.

10. The method according to claim 9, characterized in that, Determining the optimization direction of the mask image based on the loss function includes: Calculate the gradient of the loss function with respect to the mask image; determine the optimization direction of the mask image based on the gradient; or, The gradient of the loss function relative to the mask image is used as the initial optimization direction; in each iteration of optimization, the optimization direction of the current iteration is determined based on the gradient and the optimization direction of the previous iteration.

11. The method according to claim 1, characterized in that, The method further includes: The target chip layout is corrected to obtain the corrected chip layout. The discrete pixel values ​​in the corrected chip layout are converted into continuously distributed pixel values ​​to obtain the initialized mask image.

12. The method according to claim 11, characterized in that, The step of correcting the target chip layout to obtain the corrected chip layout includes: The corrected chip layout is obtained by multiplying each pixel value in the target chip layout by a first value and then adding the second value.

13. The method according to claim 11, characterized in that, The step of converting the discretely distributed pixel values ​​in the corrected chip layout into continuously distributed pixel values ​​to obtain the initialized mask image includes: The sigmoid function is used to map each pixel value in the corrected chip layout to the interval [0,1] to obtain the initialized mask image.

14. The method according to claim 1, characterized in that, The method further includes: The photolithography physical model is used to calculate the light intensity distribution of the target chip layout on the wafer based on the mask image; wherein, the calculation of the light intensity distribution is accelerated by matrix operations using a graphics processing unit (GPU). The wafer imaging pattern is calculated based on the light intensity distribution.

15. The method according to claim 1, characterized in that, After updating the mask image according to the loss function, the process further includes: The updated mask image is binarized to obtain the binarized mask image corresponding to the target chip layout.

16. A photomask renewal device, characterized in that, The device includes: The indicator acquisition module is used to acquire the parameter indicators of the mask image corresponding to the target chip layout. The parameter indicators are used to indicate the imaging quality and complexity of the mask image. An error determination module is used to determine a correction edge placement error loss function based on the correction edge placement error of the target chip layout and the parameter index; wherein the correction edge placement error is used to correct the wafer imaging pattern generated based on the mask image; The loss determination module is used to determine a loss function for updating the mask image based on the corrected edge placement error loss function. A mask update module is used to update the mask image according to the loss function; The correction of edge placement error is a matrix that carries information related to the target chip layout. It is formed by taking a number of sampling points on the boundary of the area where components need to be placed in the target chip layout, and then constructing error line segments perpendicular to the boundary through the sampling points. The parameter index loses relevant information about the target chip layout during calculation, while the corrected edge placement error carries relevant information about the target chip layout. By incorporating the relevant information about the target chip layout into the corrected edge placement error loss function, constraints are provided during the mask update and optimization process.

17. The apparatus according to claim 16, characterized in that, The parameters include: imaging error, discrete regularization term, and total variational regularization term; The imaging error is used to measure the difference between the wafer imaging pattern and the target chip layout; The discrete regularization term is used to measure the difference between pixel values ​​that are continuously distributed in the mask image and binary discrete values; The total variational regularization term is used to measure the complexity of the mask image.

18. The apparatus according to claim 17, characterized in that, The error determination module is used for: The first intermediate variable is calculated based on the corrected edge placement error and the imaging error; The second intermediate variable is calculated based on the corrected edge placement error and the discrete regularization term; The third intermediate variable is calculated based on the corrected edge placement error and the total variational regularization term; The corrected edge placement error loss function is calculated based on the first intermediate variable, the second intermediate variable, and the third intermediate variable.

19. The apparatus according to claim 18, characterized in that, The error determination module is used for: The first intermediate variable, the second intermediate variable, and the third intermediate variable are weighted and summed to obtain the corrected edge placement error loss function.

20. The apparatus according to claim 17, characterized in that, The indicator acquisition module is used for: For each pair of pixels at corresponding positions in the wafer imaging pattern and the target chip layout, calculate the difference between the two pixel values ​​in the pixel pair; The imaging error is determined based on the difference between the two pixel values ​​in each pixel pair in the wafer imaging pattern and the target chip layout.

21. The apparatus according to claim 17, characterized in that, The indicator acquisition module is used for: For each pixel in the mask image, the difference value corresponding to the pixel is determined based on the difference between the pixel value and the binary discrete value. The discrete regularization term is determined based on the difference value corresponding to each pixel in the mask image.

22. The apparatus according to claim 17, characterized in that, The indicator acquisition module is used for: The difference matrix is ​​obtained by comparing the pixel values ​​at corresponding positions in the mask image and the target chip layout. The total variation regularization term is determined based on the difference matrix and the set matrix.

23. The apparatus according to claim 16, characterized in that, The loss determination module is used for: The loss function used to update the mask image is determined based on the corrected edge placement error loss function and the parameter index.

24. The apparatus according to claim 16, characterized in that, The mask update module is used for: The optimization direction of the mask image is determined based on the loss function; The mask image is updated according to the optimization direction.

25. The apparatus according to claim 24, characterized in that, The mask update module is used for: Calculate the gradient of the loss function with respect to the mask image; determine the optimization direction of the mask image based on the gradient; or, The gradient of the loss function relative to the mask image is used as the initial optimization direction; in each iteration of optimization, the optimization direction of the current iteration is determined based on the gradient and the optimization direction of the previous iteration.

26. The apparatus according to claim 16, characterized in that, The device further includes a mask initialization module for: The target chip layout is corrected to obtain the corrected chip layout. The discrete pixel values ​​in the corrected chip layout are converted into continuously distributed pixel values ​​to obtain the initialized mask image.

27. The apparatus according to claim 26, characterized in that, The mask initialization module is used for: The corrected chip layout is obtained by multiplying each pixel value in the target chip layout by a first value and then adding the second value.

28. The apparatus according to claim 26, characterized in that, The mask initialization module is used for: The sigmoid function is used to map each pixel value in the corrected chip layout to the interval [0,1] to obtain the initialized mask image.

29. The apparatus according to claim 16, characterized in that, The device also includes a wafer imaging module for: The photolithography physical model is used to calculate the light intensity distribution of the target chip layout on the wafer based on the mask image; wherein, the calculation of the light intensity distribution is accelerated by matrix operations using a graphics processing unit (GPU). The wafer imaging pattern is calculated based on the light intensity distribution.

30. The apparatus according to claim 16, characterized in that, The device also includes a binary processing module: The updated mask image is binarized to obtain the binarized mask image corresponding to the target chip layout.

31. A computer device, characterized in that, The computer device includes a processor and a memory, the memory storing a computer program that is loaded and executed by the processor to implement the photomask updating method as described in any one of claims 1 to 15.

32. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program, which is loaded and executed by a processor to implement the photomask updating method as described in any one of claims 1 to 15.

33. A computer program product, characterized in that, The computer program product includes a computer program stored in a computer-readable storage medium, which a processor reads from and executes to implement the photomask updating method as described in any one of claims 1 to 15.

Images