Method of designing integrated circuits

Abstract

A method of designing an integrated circuit is provided. The method includes performing a synthesis operation using at least one processor to generate a netlist from input data regarding the integrated circuit, placing and routing standard cells using at least one processor to generate layout data and wiring data, the standard cells defining the integrated circuit using the netlist, extracting parasitic components from the layout data using at least one processor, and performing a timing analysis of the integrated circuit based on the layout data and the wiring data according to timing constraints using at least one processor.

Description

[0001] This invention is a divisional application of the invention patent application filed on February 27, 2018, with application number 201810160711.3 and title "Method and System for Designing Integrated Circuits". Technical Field

[0002] The present invention relates to an integrated circuit, and more specifically, to a method and system for designing integrated circuits using timing delays. Background Technology

[0003] Integrated circuits can be designed based on standard cells. Specifically, the layout of the integrated circuit is generated by placing standard cells to define the integrated circuit and routing those standard cells. The routing data is then used to fabricate the integrated circuit. Summary of the Invention

[0004] According to one aspect of an exemplary embodiment, a method for designing an integrated circuit is provided. The method includes: performing a synthesis operation using at least one processor to generate a netlist from input data relating to the integrated circuit; placing and routing standard cells using at least one processor to generate layout data and wiring data, the standard cells using the netlist to define the integrated circuit; extracting parasitic components from the layout data using at least one processor; and performing timing analysis of the integrated circuit using at least one processor based on the layout data and wiring data, according to timing constraints.

[0005] According to another aspect of an exemplary embodiment, a method for designing an integrated circuit is provided, the method comprising: generating wiring data from placement and routing data of standard cells using at least one processor, the standard cells defining the integrated circuit, the wiring data including layer information of at least one wiring and physical information of at least one wiring, the layer information of at least one wiring corresponding to a network included in the integrated circuit; and performing timing analysis on timing paths including the network using at least one processor to generate timing analysis data based on the wiring data, wherein the physical information of at least one wiring includes process variations of at least one wiring.

[0006] According to another aspect of an exemplary embodiment, a method for designing an integrated circuit is provided, the method comprising: generating wiring data from placement and routing data of standard cells using at least one processor, the standard cells defining the integrated circuit, the wiring data including layer information of at least one wiring and physical information of at least one wiring, the layer information of at least one wiring corresponding to a network included in the integrated circuit; extracting parasitic components from the placement and routing data using at least one processor; and performing timing analysis using at least one processor, using the physical information of at least one wiring included in the wiring data, and using the extracted parasitic components to generate timing analysis data, wherein the physical information of at least one wiring includes process variations of at least one wiring. Attached Figure Description

[0007] The exemplary embodiments will be more clearly understood by reading the following detailed description in conjunction with the accompanying drawings, in which:

[0008] Figure 1 This is a flowchart illustrating an integrated circuit design method according to an exemplary embodiment.

[0009] Figure 2 An integrated circuit according to an exemplary embodiment is shown.

[0010] Figure 3A and Figure 3B Show Figure 2 An example of an implementation of a clock tree contained in an integrated circuit is shown.

[0011] Figure 4 This is a flowchart illustrating an integrated circuit design method according to an exemplary embodiment.

[0012] Figure 5 This is a block diagram illustrating an integrated circuit design system for designing integrated circuits according to exemplary embodiments.

[0013] Figure 6 To explain in more detail Figure 5 The block diagram of the integrated circuit design system is shown.

[0014] Figure 7 The example shown is based on an exemplary embodiment. Figure 6 The wiring data generated by the integrated circuit design system shown.

[0015] Figure 8 The example shown is based on an exemplary embodiment of the relationship between Figure 7 The metal layer corresponding to the network of the wiring data shown.

[0016] Figure 9 This describes the method for using, according to an exemplary embodiment, to... Figure 6The table shows the parameters for calculating wire delay skew in the timing analyzer of the integrated circuit design system.

[0017] Figure 10 This is a graph illustrating the resistance and capacitance of the m-th metal layer according to an exemplary embodiment.

[0018] Figure 11 This is a flowchart illustrating a timing analysis method according to an exemplary embodiment.

[0019] Figure 12 This describes the implementation of an exemplary model. Figure 6 The flowchart illustrates the operation between the placement and routing (P&R) module and the static timing analysis (STA) module in the integrated circuit design system.

[0020] Figure 13 This is a flowchart illustrating an integrated circuit timing analysis method according to an exemplary embodiment.

[0021] Figure 14 This is a block diagram illustrating an integrated circuit design system according to an exemplary embodiment.

[0022] Figure 15 An integrated circuit according to an exemplary embodiment is shown.

[0023] Figure 16 Show Figure 15 The wiring data for the integrated circuit shown is shown.

[0024] Figures 17A to 17C Showing about according to exemplary embodiments Figure 15 The timing analysis results of the integrated circuit shown.

[0025] Figure 18 This is a flowchart illustrating an integrated circuit design method according to an exemplary embodiment.

[0026] Figure 19 This is a flowchart illustrating a method for manufacturing a semiconductor device according to an exemplary embodiment.

[0027] Figure 20 A computer-readable storage medium according to an exemplary embodiment is shown.

[0028] Explanation of icon numbers

[0029] 100, 100a, 100b, 400: Integrated Circuits

[0030] 110, 410: Unit 1

[0031] 120, 420: Unit 2

[0032] 130, 430: Unit 3

[0033] 140, 440: Unit 4

[0034] 150, 450: Unit 5

[0035] 160, 460: Unit Six

[0036] 200: Integrated Circuit Design System

[0037] 210: Processor

[0038] 230: Memory

[0039] 231, 331: Placement and routing modules

[0040] 233, 333: Parasitic Extraction Module

[0041] 235, 335: Static timing analysis module

[0042] 250: Input / Output Device

[0043] 270, 350: Storage devices

[0044] 271, 351: Unit database

[0045] 273, 353: Database layout

[0046] 275, 355: Technical Document Database

[0047] 290: Bus

[0048] 300: Integrated Circuit Design System / Computing System

[0049] 310: User Equipment

[0050] 311: Processor

[0051] 313: User Interface

[0052] 330: Integrated Circuit Design Platform

[0053] 1000: Storage medium / computer-readable storage medium

[0054] 1100: Placement and Routing Program

[0055] 1200: Static Timing Analysis Program

[0056] 1300: Layout Data

[0057] 1400: Wiring data

[0058] C, D, L: Delay

[0059] CCP, CCPa, CCPb: Capture clock path

[0060] c cell,0 d cell,0 d cell,1 d cell,2 d cell,3 l cell,0 Delay / Unit Delay

[0061] c net,0 d net,0 d net,1 d net,2 d net,3 l net,0 Latency / Network Latency

[0062] CN: Corner value

[0063] D1: Metal layer / First metal layer

[0064] D2: Second metal layer

[0065] D10, D10', D10a, D10b: Wiring data

[0066] D20: Netlist

[0067] D30: Wiring Model - Hardware-Related Specifications

[0068] D40: Proportional factor for resistance-capacitance change

[0069] DP: Data path

[0070] EV: Added Value

[0071] LCP, LCPa, LCPb: Transmit clock path

[0072] M1: First metal layer

[0073] M2: Second metal layer

[0074] M3: Third Metal Layer

[0075] M4: Fourth Metal Layer

[0076] M5: Fifth Metal Layer

[0077] Ma, Ma, Mb, Mc, Md, Me, Mf: Layer information

[0078] N1: Network / First Network

[0079] N2: Network / Second Network

[0080] N3: Network / Third Network

[0081] N4: Network / Fourth Network

[0082] N5: Network / Fifth Network

[0083] N6, N7, N1a, N1b, N2a, N2b: Network

[0084] PLC: Placement Device

[0085] RT: Router

[0086] S110, S120, S130, S140, S210, S220, S310, S320, S330, S340, S350, S360, S410, S420, S430, S440, S450, S460, S470, S480, S490, S510, S520, S530, S540, S550, S560, S570, S610, S620, S630, S710, S720, S730, S740, S750, S760: Operation

[0087] TA: Timing Analyzer

[0088] TC1: First time constant

[0089] TC2: Second time constant

[0090] T HOLD : Maintain time margin

[0091] λ1, λ2, λ3, λ4, λ5, λ 3a , λ 3b , λ 4a , λ 4b :length

[0092] λ 1,2 , λ 2,3 , λ 3,4 , λ 4,3 , λ 5,5 , λ 6,4 , λ 7,2 Metal route length

[0093] δ total Total wiring length

[0094] δ1, δ1: First wiring delay

[0095] δ1', δ2': Second wiring delay

[0096] λ m Length / Metallic Wiring Length

[0097] τ1: First unit delay information

[0098] τ2: Second unit delay information

[0099] σ1: The proportional factor of the first resistance-capacitance change

[0100] σ2: The proportional factor for the second resistance-capacitance change Detailed Implementation

[0101] As semiconductor devices are minimized, the size of patterns included in the layout may gradually decrease, and therefore, even small differences between the size of the designed pattern and the size of the pattern implemented in hardware can lead to a decrease in integrated circuit yield. Specifically, due to process variations of one or more metal layers corresponding to the back-end-of-line (BEOL) process, delays in timing paths including wiring implemented by said one or more metal layers can increase, and therefore, timing constraint violations may occur in the timing paths.

[0102] In the following sections, exemplary embodiments will be described in detail with reference to the accompanying drawings.

[0103] Figure 1 This is a flowchart illustrating an integrated circuit design method according to an exemplary embodiment.

[0104] Reference Figure 1 As an operation for designing the layout of integrated circuits, an integrated circuit design method can be executed using tools for designing integrated circuits. In this case, the tools for designing integrated circuits can be programs comprising multiple instructions executed by a processor. The processor can be a microprocessor or a central processing unit (CPU), and one or more processors can be used. Therefore, the integrated circuit design method can be referred to as a computer-implemented method for designing integrated circuits.

[0105] In operation S110, a synthesis operation is performed. The synthesis operation processes the abstract form of the circuit into a hardware implementation. For example, a synthesis tool can be used to execute operation S110 via a processor. The synthesis tool can generate a netlist by converting input data about the integrated circuit into hardware types including logic gates. Therefore, "synthesis" can be referred to as "logic synthesis." The "input data" can be an abstract form describing the behavior of the integrated circuit, such as data defined in register transfer level (RTL) code. The "netlist" can be generated from the register transfer level code using a standard cell library, and the "netlist" can be a gate-level netlist. In some exemplary embodiments, register transfer level code can be provided to the synthesis tool as an input file, and a netlist can be output from the netlist tool as an output file.

[0106] In operation S120, placement and routing can be performed. That is, placement and routing (P&R) are performed on the standard cells that define the integrated circuit. For example, an enhanced placement and routing (P&R) tool can be used to perform operation S120 via a processor. Specifically, a layout of the integrated circuit can be generated by placing the standard cells used to define the integrated circuit according to a netlist and routing the nets contained in the placed standard cells. For example, the layout data can be data in graphic design system (GDS) II format. In some exemplary embodiments, a netlist can be provided as an input file to the enhanced placement and routing (EP&R) tool, and layout data can be output as an output file from the placement and routing tool.

[0107] According to some exemplary embodiments, in operation S120, wiring data D10 may be further generated. Wiring data D10 includes layer information and physical information of the wiring corresponding to a net included in the layout of the integrated circuit. Here, "net" may refer to an equipotential in the equivalent circuit diagram of the integrated circuit and may correspond to an interconnect in the layout of the integrated circuit. Layer information may represent one or more layers of the wiring pattern used to implement the net, i.e., the layer of the back-end process (BEOL). Physical information may represent the layout size (e.g., line length, line width, line area, etc.) of the wiring pattern used to implement the net, i.e., the layout size of the back-end process. In this case, the output file of the placement and routing tool may be layout data and wiring data D10. In other words, the layout data and wiring data D10 may be output as separate output files from the placement and routing tool. However, the inventive concept is not limited thereto, and according to some exemplary embodiments, in operation S120, the layout data regarding the integrated circuit may include wiring data. In this case, the output file of the placement and routing tool may be layout data.

[0108] As described above, the concept of a "mesh" can represent equipotentiality in the equivalent circuit diagram of an integrated circuit and can correspond to interconnections in the layout of an integrated circuit. An interconnection can correspond to a wiring structure including at least one via and at least one metal layer electrically connected to each other. In conventional layout methods, wiring data is generated for each metal layer. However, there is no concept of how to interconnect wiring together to form various meshes in the layout. Therefore, the "wiring corresponding to a mesh" described herein can include multiple vias and multiple metal layers actually used to implement the mesh. In other words, for example, a wiring corresponding to a mesh can include a wiring that travels from a logic gate on a first layer, through the first layer and then through a via to a second layer, through the second layer and then through another via back to the first layer to connect to another logic gate on the first layer. (See the explanation below.) Figure 3A and Figure 3B (Another example in the text). It should be noted that in some cases, a mesh may include wiring that runs through a single metal layer to connect logic components. In this case, a mesh may be considered synonymous with wiring. In this document, "wiring" may correspond to a downstream process in the production line and will be used as a concept that includes both metal layers and vias. Therefore, wiring data D10 may be metal layer data and may be via data.

[0109] In some exemplary embodiments, wiring data D10 may include layer information and physical information of a metal layer corresponding to a mesh included in the layout of an integrated circuit. For example, the physical information of the metal layer may include length information, width information, spatial information, or shielding information of the metal layer. The length information of the metal layer may be the size of a first direction of the metal layer pattern used to implement the mesh. The width information of the metal layer may be the size of a second direction of the metal layer pattern used to implement the mesh, and the first and second directions may be perpendicular to each other. The spatial information of the metal layer may be the distance between adjacent metal layer patterns of the same layer as the metal layer pattern used to implement the mesh. The shielding information of the metal layer may indicate whether there is a shielding pattern adjacent to the metal layer pattern used to implement the mesh. For example, as an adjacent metal layer of the same layer as the metal layer, the shielding pattern may be a pattern to which a first voltage (e.g., a ground voltage) is applied.

[0110] In some exemplary embodiments, wiring data D10 may include layer information and physical information of vias corresponding to meshes included in the layout of an integrated circuit. For example, the physical information of a via may include the type or number of vias. The type of via may be various types, such as dual vias, single vias, or bar vias used in the process. The number of vias may represent the number of vias placed in different metal layers. As another example, the physical information of a via may include the length, perimeter, or width information of the via.

[0111] In operation S130, parasitic components are extracted. Parasitic components can be extracted from layout data. For example, operation S130 can be performed by a processor using an enhanced parasitic extraction (PEX) tool. Specifically, parasitic components such as parasitic resistance and capacitance of the net contained in the layout data can be extracted, and an enhanced standard parasitic extraction format (SPEF) file can be generated. The enhanced standard parasitic extraction format file can be a modified form of the standard parasitic extraction format (SPEF) file. For example, the standard parasitic extraction format file can include the resistance and capacitance of each of the multiple metal layers used in the net. For example, the standard parasitic extraction format file can include the resistance and capacitance of each of the multiple vias used in the net. In other words, as an example, the parasitic resistance and capacitance of the net can include the parasitic resistance and capacitance of each of the following: wiring passing through the first layer, vias from the first layer to the second layer, wiring passing through the second layer, and vias returning from the second layer to the first layer. According to this exemplary embodiment, layout data can be provided to the parasitic extraction tool as an input file, and a standard parasitic extraction format file can be output from the placement and routing tool as an output file.

[0112] In operation S140, timing analysis is performed. Timing analysis of the integrated circuit can be performed. For example, the processor can use an enhanced static timing analysis (STA) tool to perform operation S140. "Timing analysis" refers to the operation of determining whether the timing paths contained in the layout of the integrated circuit meet timing constraints and selecting the timing critical path of the integrated circuit. For example, a timing critical path can be a timing path in which, according to the determination result, the total timing delay from input (i.e., start point) to output (i.e., end point) exceeds the timing requirements in the timing path. Timing constraints may include setup timing constraints and holdtime constraints.

[0113] According to this exemplary embodiment, in operation S140, timing analysis data reflecting process changes in wiring can be generated by performing timing analysis on the timing paths contained in the layout data based on wiring data. According to some exemplary embodiments, layout data including wiring data can be provided as an input file to a static timing analysis tool, and timing analysis data can be output as an output file from the static timing analysis tool. Alternatively, in other exemplary embodiments, each of the layout data and wiring data (as separate files) can be provided to the static timing analysis tool, and timing analysis data can be output as an output file from the static timing analysis tool.

[0114] In some exemplary embodiments, the design method may further include performing engineering change orders (ECO) operations based on timing analysis data. In some exemplary embodiments, the design method may further include performing clock tree synthesis (CTS) operations using timing analysis data. In some exemplary embodiments, the design method may further include performing placement and routing operation optimization operations using timing analysis data. In some exemplary embodiments, the design method may further include modifying metal routing included in placement and routing operations using timing analysis data. For example, based on timing analysis data, the length of one or more wirings may be modified and / or the metal layer of the wiring may be changed to another metal layer to improve the timing of the network corresponding to the wiring.

[0115] Figure 2 An integrated circuit 100 according to an exemplary embodiment is shown.

[0116] Reference Figure 2Integrated circuit 100 may include a first unit 110, a second unit 120, a third unit 130, a fourth unit 140, a fifth unit 150, and a sixth unit 160. For example, the second unit 120 may correspond to a launch flip-flop, and the third unit 130 may correspond to a capture flip-flop. For example, in... Figure 1 In operation S140, timing analysis can be performed on the timing paths contained in integrated circuit 100. The operating speed of integrated circuit 100 can be determined based on the delays in the timing paths. The setup timing path or hold timing path includes the data path DP, the transmit clock path LCP, and the capture clock path CCP, as shown below. Figure 2 As shown.

[0117] The data path DP can be defined as the timing path from the clock pin of the second unit 120 corresponding to the emit bistable flip-flop to the data input pin of the third unit 130 corresponding to the capture bistable flip-flop. The delay D in the data path DP can be expressed by the following Equation 1.

[0118] Formula 1

[0119]

[0120] In this paper, "n" represents the number of units contained in the data path DP. For example, the data path DP may include the second unit 120, the fourth unit 140, the fifth unit 150, and the sixth unit 160, and therefore, in this case, "n" is 4. cell "This represents the total unit delay of the data path DP, and may correspond, for example, to the delay d of the second unit 120." cell,0 The delay d of Unit 4, 140 cell,1 The delay d of Unit 5, 150 cell,2 and the delay d of Unit 6, 160 cell,3 The sum of. "D" net "This represents the total net delay of the data path DP, and may, for example, correspond to the delay d of network N3 connecting the second unit 120 and the fourth unit 140." net,0 The delay d of network N4 connecting unit 140 and unit 150 net,1 The delay d of network N5 connecting unit 5 (150) and unit 6 (160) net,2 and the delay d of network N6 connecting sixth unit 160 and third unit 130 net,3The sum of these two factors. Generally speaking, since the data path DP includes a relatively large number of units, the data path DP is less sensitive to total network delay (i.e., wiring delay) than the transmit clock path LCP and the capture clock path CCP.

[0121] The transmit clock path LCP can be defined as the timing path from the common clock pin of the clock tree to the clock input pin of the second unit 120 corresponding to the transmit bistable flip-flop. The delay L in the transmit clock path LCP can be expressed by the following formula 2.

[0122] Formula 2

[0123]

[0124] In this document, "j" represents the number of cells contained in the transmit clock path LCP. For example, the transmit clock path LCP may include a first cell 110, and therefore in this case, "j" is 1. cell "This represents the total unit delay of the transmit clock path LCP, and may correspond, for example, to the delay of the first unit 110." cell,0 "L" net "This represents the total network delay of the transmit clock path LCP, and may correspond, for example, to the delay l of network N1 connecting the first unit 110 and the second unit 120." net,0 Generally speaking, because the transmit clock path (LCP) consists of a relatively small number of cells, the transmit clock path (LCP) is more sensitive to overall network delay (i.e., wiring delay) than the data path (DP).

[0125] The capture clock path CCP can be defined as the timing path from the common clock pin of the clock tree to the clock input pin of the third unit 130 corresponding to the capture bistable flip-flop. The delay C in the capture clock path CCP can be expressed by the following formula 3.

[0126] Formula 3

[0127]

[0128] In this document, "k" represents the number of units contained in the capture clock path CCP. For example, the capture clock path CCP may include a first unit 110, and therefore in this case, "k" is 1. cell "This indicates the total unit delay of the captured clock path CCP, and may correspond, for example, to the delay of the first unit 110." cell0 "C" net "This represents the total network delay of the capture clock path CCP, and may correspond, for example, to the delay c of network N2 connecting the first unit 110 and the third unit 130." net,0Generally speaking, because the capture clock path CCP includes a relatively small number of units, the capture clock path CCP is more sensitive to total network delay (i.e., wiring delay) than the data path DP.

[0129] Using formulas 1 to 3, the hold time slack T can be expressed by the following formula 4. HOLD .

[0130] Formula 4

[0131] T HOLD =L+D-C+α

[0132] =(L cell +L wire )+(D cell +D wire )-(C cell +C wire )+α

[0133] =(L cell +D cell -C cell )+(L wire +D wire -C wire )+α

[0134] =S cell +S wire +α

[0135] In this paper, "α" is a constant and represents the sum of other timing parameters such as clock uncertainty and bistable flip-flop hold margin. In this paper, "S" cell "S" indicates the hold slack difference caused by cell delay, and "S" represents the hold slack difference. wire "L" indicates the retention margin difference caused by wiring delay. In Formula 4, "L" wire “D” wire “C” wire "This can correspond to "L" in Formula 2 respectively. net ", Formula 1's "D" net " and Formula 3's "C net ".

[0136] For example, it can be implemented using only metal layer D1. Figure 2 In the case of the integrated circuit shown, when the resistance of the metal layer D1 used to implement the integrated circuit 100 is manufactured to be 20% larger than the target value of the model, in Equation 4, the constant "α" and the retention margin difference "S" caused by the cell delay are... cell "No change, and only the retention margin difference caused by wiring delay"S wire"A change occurs. In this case, the hold time slack difference ΔT can be expressed by the following formula 5." HOLD .

[0137] Formula 5

[0138] ΔT HOLD =T HOLD,D1@20％ -T HOLD

[0139] =(S cell +S wireD1@20％ +α)-(S cell +S wire +α)

[0140] =S wireD1@20％ -S wire =ΔS wire

[0141] Use the retention margin difference "S" caused by wiring delay wire This section analyzes the model-to-hardware correlation (MHC) problem. "Model-to-hardware correlation" refers to the consistency between the model upon which the design is based and the actual hardware implemented in silicon. When the electrical characteristics of the model differ from those measured in silicon, the expected chip performance during the design phase may not be achieved.

[0142] Specifically, "wire MHC mismatch" represents the difference between the modeled resistance / capacitance values ​​of a wiring and the actual resistance / capacitance values ​​of the implemented wiring. For example, wire MHC mismatch can be caused by process variations in downstream processes such as changes in metal layer resistance, metal layer capacitance, or vias. For instance, when the actual resistance of a metal layer is greater than the modeled target resistance, delays in timing paths including the metal layer can increase, and therefore, as a result of timing analysis of the timing path, hold violations may occur.

[0143] According to traditional design methodologies, during the timing analysis phase, the physical information about the nets contained in the timing path may not be known. That is, during the timing analysis phase, it may not be known which metal layers or layers actually implement the nets. Therefore, timing analysis data reflecting process variations in wiring may not be generated during the timing analysis phase. However, according to an exemplary embodiment, in the operations of generating layout data or extracting parasitic components, the accuracy of timing analysis can be improved by generating wiring data and performing timing analysis using the generated wiring data, which includes layer information and physical information about the wiring corresponding to the nets contained in the layout of the integrated circuit. Therefore, by discovering and resolving design flaws, improved mass production can be ensured. (Refer to...) Figures 6 to 12 This section will elaborate on the timing analysis process.

[0144] Figure 3A and Figure 3B Show Figure 2 Examples of implementations of the clock tree included in the integrated circuit shown (100a and 100b).

[0145] Reference Figure 3A Integrated circuit 100a is an example of an implementation with a robust clock tree. The network N1a included in the transmit clock path LCPa can be implemented by the first metal layer D1 and the second metal layer D2, and the network N2a included in the capture clock path CCPA can also be implemented by the first metal layer D1 and the second metal layer D2. For example, the variation can occur only in the first metal layer D1 of the first metal layer D1 and the second metal layer D2, and therefore, the resistance of the first metal layer D1 can be increased compared to the target value. In this case, since both the wiring delay in the transmit clock path LCPa and the wiring delay in the capture clock path CCPA increase simultaneously in Equation 4, the hold time margin difference between LCPa and CCPA is 0 in Equation 5, and a hold violation does not occur. In other words, since the transmit clock path LCPa and the capture clock path CCPA include similar wiring on similar layers, no hold time margin difference occurs.

[0146] Reference Figure 3BIntegrated circuit 100b is an example implementation of a clock tree that is susceptible to variations in wiring process. The network N1b included in the transmit clock path LCPb can be implemented by a first metal layer D1 and a second metal layer D2, and the network N2b included in the capture clock path CCPb can be implemented by a second metal layer D2. For example, a change can be made only in the first metal layer D1 of the first metal layer D1 and the second metal layer D2, and therefore, the resistance of the first metal layer D1 can increase compared to the target value. In this case, since the wiring delay in the transmit clock path LCPb increases while the wiring delay in the capture clock path CCPb does not increase, the hold time margin difference in Equation 5 can have a value greater than 0, and a hold violation can occur.

[0147] Therefore, when the clock tree lacks a robust structure, maintenance violations may occur due to wiring model-hardware dependent (MHC) mismatches, such as changes in resistance and / or capacitance of the metal layers corresponding to the wiring (e.g., D1 becomes faster or D2 becomes slower), and / or changes in vias corresponding to the mesh. Therefore, this invention proposes a novel timing analysis method that analyzes the metal routing structure to remove timing violations caused by wiring model-hardware dependent timing and uses wiring resistance-capacitance variation specifications to predict timing margins.

[0148] Figure 4 This is a flowchart illustrating an integrated circuit design method according to an exemplary embodiment.

[0149] Reference Figure 4 As a method for performing timing analysis of integrated circuits while taking into account wiring variations, the integrated circuit design method according to an exemplary embodiment can correspond to... Figure 1 The illustrated implementation example. In operation S210, layout data and wiring data are generated by placing and routing standard cells. For example, layout data of the integrated circuit and wiring data D10 corresponding to the nets included in the layout of the integrated circuit are generated by placing and routing standard cells that define the integrated circuit. Wiring data D10 may include layer information of at least one wiring corresponding to the nets included in the integrated circuit and physical information of said at least one wiring. For example, wiring data D10 may include wiring length information. According to some exemplary embodiments, an operation of extracting parasitic components from the layout data may be further included between operation S210 and operation S220. For example, the operation of extracting parasitic components may correspond to... Figure 1 Operation S130 is shown.

[0150] In operation S220, timing analysis data is generated by performing timing analysis based on wiring data to take into account changes in the wiring. For example, timing analysis data reflecting the process changes of the at least one wiring is generated by performing timing analysis on a timing path including the network based on wiring data D10. In some exemplary embodiments, timing analysis can be performed on the timing path based on unit delay information representing the delay per unit length of the at least one wiring and the physical information of the at least one wiring. In some exemplary embodiments, the wire delay skew of the timing path can be calculated based on a time constant scaling factor, which is based on the process changes of the at least one wiring, the unit delay information representing the delay per unit length of the at least one wiring, and the physical information of the at least one wiring. (Refer to...) Figures 9 to 12 To elaborate on the timing analysis in more detail. In some exemplary embodiments, the design method may further include performing an Engineering Change Order (ECO) based on the timing analysis data.

[0151] Figure 5 This is a block diagram illustrating an integrated circuit design system 200 that designs integrated circuits according to an exemplary embodiment.

[0152] Reference Figure 5 The integrated circuit design system 200 can be a computing system used for designing integrated circuits. The integrated circuit design system may include a processor 210, a memory 230, input / output (I / O) devices 250, a storage device 270, and a bus 290. The integrated circuit design system 200 can perform integrated circuit design operations, including... Figure 1 Operations S110 to S140 shown or Figure 4 Operations S210 and S220 are shown. In... Figure 4 In the exemplary embodiment shown, the integrated circuit design system 200 can be implemented as an integrated device, and therefore, the integrated circuit design system 200 can also be referred to as an integrated circuit design apparatus. The integrated circuit design system 200 can be configured as a dedicated device for designing integrated circuits for semiconductor devices, or it can be a computer for driving various simulation tools or design tools.

[0153] Processor 210 may include one or more microprocessors and may be configured to execute instructions to perform at least one of various operations for designing an integrated circuit. Processor 210 may communicate with memory 230, input / output device 250, and storage device 270 via bus 290. Processor 210 may perform integrated circuit design operations by driving placement and routing module 231, parasitic extraction module 233, and static timing analysis module 235 loaded in memory 230.

[0154] The memory 230 may store the placement and routing module 231, the parasitic extraction module 233, and the static timing analysis module 235. Additionally, the memory 230 may further store the synthesis module. The placement and routing module 231, the parasitic extraction module 233, and the static timing analysis module 235 may be loaded from the storage device 270 into the memory 230. The memory 230 may include, for example, volatile memory, such as static random access memory (SRAM) or dynamic random access memory (DRAM); or non-volatile memory, such as phase change random access memory (PRAM), magnetic random access memory (MRAM), resistive random access memory (ReRAM), ferroelectric random access memory (FRAM), or NOR flash memory.

[0155] The placement and routing module 231 may include, for example, a method for determining the placement and routing based on the location of the object. Figure 1 Operation S120 shown or Figure 4 The illustrated operation S210 is a program that executes multiple instructions for enhanced placement and routing operations. The parasitic extraction module 233 may, for example, include instructions for... Figure 1 The illustrated operation S130 is a program that executes multiple instructions for an enhanced parasitic extraction operation. The static timing analysis module 235 may, for example, include instructions for... Figure 1 Operation S140 shown or Figure 4 The illustrated operation S220 is a program that executes multiple instructions for enhanced timing analysis. Note that the placement and routing module 231, parasitic extraction module 233, and static timing analysis module 235 are located within... Figure 5 The components are shown as separate entities. However, this is merely an example, and the placement and routing module 231, the parasitic extraction module 233, and the static timing analysis module 235 can be combined into one module or into two modules. In other words, the modules do not need to be configured as separate modules.

[0156] Input / output device 250 can control user input and output from one or more user interface devices. For example, input / output device 250 may include input devices (e.g., keyboard, mouse, and / or touchpad) to receive input data defining the integrated circuit. In some exemplary embodiments, input / output device 250 may receive various user inputs, such as metal resistance-capacitance scaling factors. For example, input / output device 250 may include display devices (e.g., display and / or speaker) to display placement results, routing results, and / or timing analysis results. In some exemplary embodiments, for wiring corresponding to a network included in the integrated circuit, input / output device 250 may display a first wiring delay based on a target value, a second wiring delay based on process variations, and wiring delays resulting from the first and second wiring delays.

[0157] Storage device 270 can store various data related to placement and routing module 231, parasitic extraction module 233, and static timing analysis module 235. Storage device 270 may include, for example, memory cards (e.g., multimedia card (MMC), embedded MMC (eMMC), secure digital card (SD), micro-secure digital card (MicroSD)), solid-state drives, and / or hard disk drives.

[0158] Figure 6 To explain in more detail Figure 5 The block diagram of the integrated circuit design system is shown.

[0159] Reference Figure 5 and Figure 6 The program stored in memory 230 may include multiple processes, and a process may represent a series of instructions for performing a specific task. A process may also be referred to as a function, routine, subroutine, or subroutine. Figure 6 In the exemplary embodiment shown, the process may include a placer PLC, a router RT, and a timing analyzer TA. Specifically, the placement and routing module 231 may include the placer PLC and the router RT, and the static timing analysis module 235 may include the timing analyzer TA. Additionally, the process may further include a parasitic extractor, which may be included, for example, in the parasitic extraction module 233. In this document, the process may be described by... Figure 5 The processor 210 shown executes operations by processes (placers, routers, or timing analyzers), which is represented as operations performed by processes (placers, routers, or timing analyzers).

[0160] Storage device 270 may include a cell library database (DB) 271, a layout database 273, and a technology (tech) document database 275. Cell library database 271 may store information about standard cells used to generate layouts for integrated circuits and may be referred to as a standard cell library database. Layout database 273 may store information about layouts generated during the process, such as physical information about the layout. Technology document database 275 may store technical documents used to store materials and rules used in the integrated circuit manufacturing process. Technology (tech) document database 275 may store, for example, layer definitions, device definitions, and / or design tools. Figure 6 In the exemplary embodiment shown, the tech document database 275 can store the memory cell latency corresponding to a plurality of metal layers respectively.

[0161] The placement PLC can place standard cells according to the netlist D20, and specifically, the placement PLC can perform the placement operation by accessing the cell library database 271 of the storage device 270. The router RT can generate layout data by routing the standard cells placed by the placement PLC. The generated layout data can be stored in the layout database 273 of the storage device 270. In addition, the router RT can generate wiring data D10, which includes layer information and physical information of at least one wiring corresponding to each of the plurality of nets contained in the integrated circuit. Referring to the following... Figure 7 and Figure 8 The wiring data D10 is described in more detail.

[0162] Figure 7 Showing according to an exemplary embodiment Figure 6 The wiring data shown is D10.

[0163] Reference Figure 7 Wiring data D10 may include, for example, data related to... Figure 2 The integrated circuit 100 shown includes layer information (Ma to Mf) for at least one wiring corresponding to each of the nets N1 to N7, as well as length information of the metal layer of the at least one wiring. For example, wiring data D10 can be... Figure 4 This is generated in the operation S210 shown. For example, the metal layers corresponding to mesh N4 can be the second metal layer M2, the third metal layer M3, the fourth metal layer M4, and the fifth metal layer M5, and the lengths of the second metal layer M2 to the fifth metal layer M5 used to implement mesh N4 can be λ2 to λ5, respectively.

[0164] Figure 8 The example shown is based on an exemplary embodiment of the relationship between Figure 7 The metal layer corresponding to mesh N4 shown.

[0165] Reference Figure 7 and Figure 8 Mesh N4 can be implemented using the second metal layer M2 to the fifth metal layer M5. The total wiring length λ corresponding to mesh N4 is... total This corresponds to the sum of the corresponding lengths λ2 to λ5 of the wiring of the mesh implemented in the second metal layer M2 to the fifth metal layer M5, respectively. Therefore, it can be expressed by the following formula 6. Figure 7 and Figure 8 The total wiring length λ corresponding to network N4 shown is... total .

[0166] Formula 6

[0167] λ t o tal =λ2+λ3+λ4+λ5=(λ 1,2 +λ 7,2 )+(λ 2,3 +λ 4,3 )+(λ 3,4 +λ 6,4 )+λ 5,5

[0168] In the following text, λ i,m "i" represents the length of the metal route, "i" represents the order of the metal routes, and "m" represents the number of metal layers.

[0169] Figure 9 This describes the method for using, according to an exemplary embodiment, to... Figure 6 The timing analyzer TA shown calculates the wiring delay skew Δ. m The table of parameters.

[0170] Reference Figure 6 and Figure 9 The timing analyzer TA can perform timing analysis on the integrated circuit to search for timing critical paths, generate a cell list of standard cells contained in the timing critical paths, and transmit the generated cell list to the placement and routing module 231. The placement and routing module 231 can discover networks connected to the standard cells contained in the cell list and transmit wiring data D10 for the discovered networks to the static timing analysis module 235 (i.e., the timing analyzer TA). For example, the wiring data D10 may include the metal wiring length λ of the m-th metal wiring. m .

[0171] Next, the timing analyzer (TA) can calculate the wiring delay skew Δ based on the wiring data D10, the wiring model-hardware dependent (MHC) specification D30, and the resistance-capacitance (RC) scaling factor D40. mSpecifically, the timing analyzer TA can receive, from the technical document database 275 contained in the storage device 270, the unit delay τ of the m-th metal wiring. m Wiring model - hardware-related specification D30. For example, the unit delay τ of the m-th metal wiring can be generated by a silicon monitoring circuit. m Additionally, the timing analyzer TA can receive user input from the input / output device 250, including a scaling factor σ representing the change in the resistance-capacitance time constant of the m-th metal layer. m (That is, D40). The following will refer to... Figure 10 Explain the proportional factor σ of the resistance-capacitance change. m .

[0172] The timing analyzer TA can calculate the wiring delay δ of one or more wirings in a specific metal layer based on the following. total λ is the length of the metal wiring of one or more conductors in the m-th metal layer. m The unit delay τ of the m-th metal layer, including one or more wirings. m And the resistance-capacitance ratio σ of the m-th metal layer, which includes one or more wirings. m The wiring delay δ of one or more wirings in a specific metal layer. total This can be included in the timing analysis data output from the timing analyzer (TA). The timing analyzer (TA) can be based on the wiring delay δ. total Calculate wiring delay skew Δ m Wiring delay skew can be included in the timing analysis data output from the timing analyzer (TA).

[0173] Figure 10 This is a graph illustrating the resistance and capacitance of the m-th metal layer according to an exemplary embodiment.

[0174] Reference Figure 10 The horizontal axis represents the resistance of the m-th metal layer, and the vertical axis represents the capacitance of the m-th metal layer. Figure 10 In the diagram shown, the boxes represented by dashed lines indicate the allowable range of the modeled RC values ​​for the m-th metal layer. These boxes can be experimentally set based on measured resistance and capacitance values ​​of the metal layers. The RC time constant can be set as a first time constant TC1 based on the corner value CN of the m-th metal layer. When the RC of the m-th metal layer has an extra value EV that exceeds the allowable range due to process variations in the m-th metal layer, the RC time constant can be set as a second time constant TC2. In this case, the ratio of the second time constant TC2 to the first time constant TC1 can be defined as the RC variation scaling factor σ. m .

[0175] Figure 11 This is a flowchart illustrating a timing analysis method according to an exemplary embodiment.

[0176] Reference Figure 11 , Figure 11 The timing analysis method shown in the exemplary embodiment can correspond to Figure 4 An example of an implementation of operation S220 is shown. For example, Figure 11 The timing analysis method shown in the exemplary embodiment can be derived from... Figure 5 The integrated circuit design system 200 shown is executed sequentially. In the following text, reference will be made to... Figure 11 Describe the time series analysis method.

[0177] In operation S310, a timing-critical path is searched. For example, the static timing analysis module 235 can determine the timing-critical path by performing timing analysis on the timing paths contained in the integrated circuit. For example, a timing-critical path may be a path where a hold violation occurs. See, for example... Figure 3A and Figure 3B And the related discussion above. The static timing analysis module 235 can determine the timing critical path. However, the concept of the invention is not limited thereto, and in some exemplary embodiments, operation S310 can be performed by the placement and routing module 231.

[0178] In operation S320, the cell delay and network delay of each determined timing critical path are collected. For example, the cell delay and network delay of one path selected from the determined timing critical paths can be collected. For example, the static timing analysis module 235 can obtain the delay in the selected path by collecting the cell delay of multiple cells contained in the selected path and the network delay of multiple networks contained in the selected path. However, the concept of the present invention is not limited to this, and in some exemplary embodiments, operation S320 can be performed by the placement and routing module 231.

[0179] For example, re-referencing Figure 2 And with the associated explanation, when the selected path includes a data path, the unit delay d of the n units contained in the data path can be collected according to Formula 1 above. cell,0 to d cell,n-1 And the network latency d of the n networks contained in the data path. net,0 to d net,n-1 When the selected path includes a transmission path, the cell delay l of the j cells contained in the transmission path can be collected according to Formula 2 above. cell,0 To l cell,j-1 and the network delay l of the j networks included in the transmission path. net,0 To l net,j-1When the selected path includes a capture path, the cell delay c of the k cells contained in the capture path can be collected according to Formula 3 above. cell,0 To c cell,k-1 And the network delay c of the k networks contained in the capture path. net,0 To c net,k-1 .

[0180] In operation S330, physical information about at least one wiring corresponding to at least one network is collected for each network. For example, physical information about at least one wiring corresponding to at least one network included in a selected path is collected. In some exemplary embodiments, the selected path may include multiple networks, and physical information about at least one wiring corresponding to each network may be collected. In some exemplary embodiments, the selected path may include a single network, and physical information about at least one wiring corresponding to that single network may be collected. In some exemplary embodiments, the at least one wiring may include multiple portions of the at least one wiring located on multiple metal layers, and the physical information may include length information of the portion of the at least one wiring located on each metal layer. See, for example... Figure 7 In the following text, during operation S330, the length information of each of the multiple metal layers corresponding to the mesh contained in the selected path will be mainly described.

[0181] In some exemplary embodiments, the placement and routing module 231 may collect length information of multiple metal layers corresponding to the meshes included in the selected path. In some exemplary embodiments, the parasitic extraction module 233 may collect length information of multiple metal layers corresponding to the meshes included in the selected path. In some exemplary embodiments, the static timing analysis module 235 may receive length information of multiple metal layers corresponding to the meshes included in the selected path from the placement and routing module 231 or the parasitic extraction module 233. In some exemplary embodiments, operation S330 may be performed on all meshes included in the selected path. However, the inventive concept is not limited thereto, and in some exemplary embodiments, operation S330 may be performed on only a portion of the meshes included in the selected path.

[0182] In operation S340, wiring delay is calculated based on physical information. For example, for at least one wiring corresponding to a network, the wiring delay is calculated based on the physical information of at least one wiring. In some exemplary embodiments, the wiring delay can be calculated based on the length information of a portion of the wiring located in a metal layer and the unit delay information of the metal layer. For example, the static timing analysis module 235 can calculate the wiring delay of a portion of the wiring located in the m-th metal layer based on the length information of the m-th metal layer. However, the concept of the invention is not limited to this, and in some exemplary embodiments, operation S340 can be performed by the placement and routing module 231.

[0183] In operation S350, the wiring delay is updated based on the process changes of the wiring. For example, for at least one wiring corresponding to a network, the wiring delay is updated based on the process changes of at least one wiring. In some exemplary embodiments, the wiring delay may be updated based on the RC ratio factor of the metal layer including said portion of the wiring, which varies with the process. For example, the static timing analysis module 235 may update the wiring delay of a portion of the wiring located in the m-th metal layer based on the RC ratio factor of the m-th metal layer that varies with the process. However, the inventive concept is not limited thereto, and in some exemplary embodiments, operation S350 may be performed by the placement and routing module 231.

[0184] In operation S360, the updated wiring delay is used to calculate timing margins. In some exemplary embodiments, for each of a plurality of metal layers, a wiring delay skew that varies according to the difference between the wiring delay of the metal layer and the updated wiring delay can be calculated, and the wiring delay skews of the plurality of metal layers can be used to calculate timing margins. For example, timing margins can be hold margins or build-up margins. For example, static timing analysis module 235 can calculate the wiring delay skew of the portion of the wiring located on the m-th metal layer and use the wiring delay skews of the portions of the wiring located on all metal layers corresponding to the network to calculate timing margins. However, the concept of the invention is not limited thereto, and in some exemplary embodiments, operation S360 can be performed by placement and routing module 231. After operation S360, operation S320 can be performed on the next path in the determined timing critical path.

[0185] Figure 12 This describes the implementation of an exemplary model. Figure 6 The flowchart shows the operation between the placement and routing module 231 and the static timing analysis module 235.

[0186] Reference Figure 12 For example, it can be derived from Figure 6The static timing analysis module 235 shown executes operations S310 to S330 and operations S370 to S390 sequentially, and can be, for example, by... Figure 6 The placement and routing module 231 is shown to execute operations S340 to S360 sequentially. Further reference will be made below. Figures 6 to 11 This will illustrate the timing analysis operation.

[0187] In operation S410, the static timing analysis module 235 determines the timing critical path. The static timing analysis module 235 determines the timing critical path by performing timing analysis on the timing paths contained in the integrated circuit. In operation S420, the static timing analysis module 235 selects a path from the timing critical path and generates a cell list including standard cells associated with the selected path. In operation S430, the static timing analysis module 235 transmits the cell list to the placement and routing module 231.

[0188] In operation S440, the placement and routing module 231 can discover networks connected to standard cells included in the cell list. In operation S450, the placement and routing module 231 can generate wiring data, which includes layer information of at least one wiring corresponding to each network and physical information of the at least one wiring. In some exemplary embodiments, the placement and routing module 231 can generate wiring data representing the layer of the wiring corresponding to each of the plurality of networks (i.e., the type of wiring in the layout data generation operation), and generate wiring data corresponding to a specific network by measuring the length of the wiring corresponding to the specific network according to the request of the static timing analysis module 235 in operation S450. In some exemplary embodiments, in operation S450, the placement and routing module 231 can generate total wiring data in the layout data generation operation, including the type of wiring corresponding to each of the plurality of networks and the length information of the wiring, and extract wiring data corresponding to a specific network from the total wiring data according to the request of the static timing analysis module 235. In operation S460, the placement and routing module 231 can transmit the generated wiring data to the static timing analysis module 235.

[0189] In operation S470, the static timing analysis module 235 can calculate wiring delay skew and hold-up margin based on wiring data, wiring model-hardware dependent (MHC) specification D30, and resistor-capacitor variation scaling factor D40. (Refer to...) Figure 13Operation S470 is described in more detail. In operation S480, the static timing analysis module 235 can generate a timing report. For example, the timing report may include the wiring model - hardware-related margins, worst-case metal layer, wiring delay skew for each metal layer, resistor-capacitor ratio factor for each metal layer, and hold-up margin difference for each metal layer. In operation S490, the static timing analysis module 235 can determine whether the path selected in operation S420 is the last path in the timing critical paths determined in operation S410. As a result of the determination, if the path is not the last path, operation S420 is executed, and if the path is the last path, the timing analysis operation ends.

[0190] Figure 13 This is a flowchart illustrating an integrated circuit timing analysis method according to an exemplary embodiment.

[0191] Reference Figure 13 , Figure 13 The timing analysis method shown in the exemplary embodiment can correspond to Figure 4 An example of an implementation of operation S220 is shown. For example, Figure 13 The timing analysis method shown in the exemplary embodiment can be derived from... Figure 6 The static timing analysis module 235 shown is executed sequentially. In the following text, reference will be made to... Figures 6 to 13 This section describes the operation of calculating the wiring delay corresponding to network N4 using the timing analyzer TA.

[0192] In operation S510, a first wiring delay is calculated based on the target value of the wiring. In some exemplary embodiments, a net may correspond to multiple wirings, and operation S510 may be performed on each of the multiple wirings. For example, the first wiring delay δ on the m-th metal layer may be assumed. m The length λ of the wiring on the m-th metal layer m and the unit delay τ of the m-th metal layer m Proportional. Therefore, the first wiring delay δ on the m-th metal layer can be expressed by the following formula 7. m .

[0193] Formula 7

[0194] δ m =β×τ m ×λ m

[0195] For example, it can be said that, with network N4 ( Figure 7 The corresponding first total distribution delay δ (as shown) total The sum of the delays δ2 to δ5 of the first wiring corresponding to the portion of the wiring located on the second metal layer M2 to the fifth metal layer M5 (i.e., δ total=δ2+δ3+δ4+δ5). Therefore, the first total distribution delay δ corresponding to network N4 can be expressed by the following formula 8. total .

[0196] Formula 8

[0197] δ total =β×(τ2×λ2+τ3×λ3+τ4×λ4+τ5×λ5)

[0198] β in Formula 8 can be represented by the following Formula 9.

[0199] Formula 9

[0200]

[0201] Based on formulas 8 and 9, the first wiring delay δ on the m-th metal layer can be expressed by the following formula 10. m .

[0202] Formula 10

[0203]

[0204] In operation S520, a second wiring delay is calculated based on the process variations of the wiring. In some exemplary embodiments, a net may correspond to multiple wirings, and operation S520 may be performed on each of the multiple wirings. Specifically, various equations may be used to perform the operation of calculating the second wiring delay. In some exemplary embodiments, the second wiring delay δ' of a portion of the wiring located on the m-th metal layer may be represented by the following formula 11. m .

[0205] Formula 11

[0206]

[0207] In this paper, σ m This is the proportional factor for the metal resistance-capacitance variation of the m-th metal layer and can be set by the user. Furthermore, in some exemplary embodiments, Formula 11 can be modified by further considering the physical information of the vias corresponding to the mesh (e.g., the number or type of vias), and the modified Formula 11 can be used to calculate the second wiring delay δ'. m Furthermore, in some exemplary embodiments, Formula 11 can be modified by further considering the resistance-capacitance variation of the vias corresponding to the mesh, and the modified Formula 11 can be used to calculate the second wiring delay δ'. m .

[0208] In some exemplary embodiments, the second wiring delay δ' of the wiring located on the m-th metal layer can be represented by the following formula 12.m .

[0209] Formula 12

[0210]

[0211] Furthermore, in some exemplary embodiments, Formula 12 can be modified by further considering the physical information of the vias corresponding to the mesh (e.g., a scaling factor that varies with the type or number of vias), and the modified Formula 12 can be used to calculate the second wiring delay δ'. m Furthermore, in some exemplary embodiments, Formula 12 can be modified by further considering the resistance-capacitance variation of the vias corresponding to the mesh, and the modified Formula 12 can be used to calculate the second wiring delay δ'. m .

[0212] In operation S530, the wiring delay skew is calculated based on the first wiring delay and the second wiring delay. In some exemplary embodiments, a network may correspond to multiple wirings, and operation S530 may be performed on each of the multiple wirings. For example, when calculating the second wiring delay δ' according to Formula 11... m At that time, it can be based on the first wiring delay δ m and the second wiring delay δ' m The wiring portion located on the m-th metal layer is delayed and skewed by Δ. m It is represented by the following formula 13.

[0213] Formula 13

[0214]

[0215] For example, when calculating the second wiring delay δ' according to Formula 12 m At that time, it can be based on the first wiring delay δ m and the second wiring delay δ' m The wiring portion located on the m-th metal layer is delayed and skewed by Δ. m It is represented by the following formula 14.

[0216] Formula 14

[0217]

[0218] For example, when a process change occurs only in the m-th metal layer and not in the other metal layers, the total wiring delay skew can be equal to the wiring delay skew Δ of the portion of the wiring located on the m-th metal layer. m .

[0219] In operation S540, timing margin is calculated. For example, the timing margin of the network can be calculated based on the wiring delay skew corresponding to multiple wirings corresponding to the network. In some exemplary embodiments, the timing margin can be calculated by applying the root sum square (RSS) method to the wiring delay skew. For example, the timing margin can be calculated according to the following formula 15.

[0220] Formula 15

[0221]

[0222] In operation S550, a timing violation is determined based on the timing margin. In some exemplary embodiments, as a result of the determination, if a timing violation occurs, measures can be taken to remove the timing violation (S560). For example, in some exemplary embodiments, an Engineering Change Order (ECO) can be performed to remove the timing violation. In some exemplary embodiments, when a timing violation occurs, the timing margin of the timing path can be further ensured by using a timing engine such as Clock Tree Synthesis (CTS). In some exemplary embodiments, when a timing violation occurs, the timing margin of the timing path can be further ensured by utilizing optimizations in placement and routing tools. In some exemplary embodiments, when a timing violation occurs, the metal routing can be modified. For example, the length of the metal layer can be modified, or a portion of the wiring located in one metal layer can be moved to another metal layer. As a result of the determination, if no timing violation occurs, the timing analysis operation can be terminated (S570).

[0223] Figure 14 This is a block diagram illustrating a computing system 300 for designing integrated circuits according to an exemplary embodiment.

[0224] Reference Figure 14 The integrated circuit design system 300 may include a user device 310, an integrated circuit design platform 330, and a storage device 350. For example, the integrated circuit design system 300 may perform integrated circuit design operations, including... Figure 1 Operations S110 to S140 shown or Figure 4 Operations S210 and S220 are shown. In... Figure 14 In the exemplary embodiments shown, at least one of the user device 310, the integrated circuit design platform 330, and the storage device 350 may be a separate device, and the user device 310, the integrated circuit design platform 330, and the storage device 350 may be connected via wireless / wired communication or a network. In some exemplary embodiments, at least one of the user device 310, the integrated circuit design platform 330, and the storage device 350 may be spaced apart from each other.

[0225] User device 310 may include processor 311 and user interface (UI) 313. Processor 311 may include one or more microprocessors or central processing units (CPUs) and may drive integrated circuit design platform 330 based on user input received through user interface 313. Integrated circuit design platform 330 may include placement and routing module 331, parasitic extraction module 333, and static timing analysis module 335 as a set of computer-readable instructions for designing integrated circuits. Placement and routing module 331, parasitic extraction module 333, and static timing analysis module 335 may respectively correspond to... Figure 5 The diagram shows a placement and routing module 231, a parasitic extraction module 233, and a static timing analysis module 235. The storage device 350 may include a cell library database 351, a layout database 353, and a technical document database 355. The cell library database 351, layout database 353, and technical document database 355 may respectively correspond to… Figure 6 The shown databases are: Unit Library Database 271, Layout Database 273, and Technical (tech) Document Database 276.

[0226] Figure 15 An integrated circuit 400 according to an exemplary embodiment is shown.

[0227] Reference Figure 15 Integrated circuit 400 may include a first unit 410, a second unit 420, a third unit 430, a fourth unit 440, a fifth unit 450, and a sixth unit 460, as well as a first network N1, a second network N2, a third network N3, a fourth network N4, and a fifth network N5. The first network N1 includes wiring located on a first metal layer M1 and wiring located on a second metal layer M2. The second network N2 includes wiring located on a third metal layer M3. The third network N3 includes wiring located on a third metal layer M3, and the fourth network N4 and the fifth network N5 each include wiring located on a fourth metal layer M4. The capture clock path CCP may include the first unit 410 and the second unit 420, as well as the first network N1 and the second network N2. For example, in the capture clock path CCP, the unit delay may be 3 ps, the network delay may be 3 ps, and the total delay may be 6 ps. The transmit clock path LCP may include the third unit 430 and the third network N3. For example, in the transmit clock path LCP, the cell delay can be 1 ps, the network delay can be 1 ps, and the total delay can be 2 ps. The data path DP can include fourth cell 440 and fifth cell 450, as well as fourth network N4 and fifth network N5. For example, in the data path DP, the cell delay can be 2 ps, the network delay can be 2 ps, and the total delay can be 4 ps. In the following text, reference will be made to... Figures 14 to 17C This section will describe the timing analysis operations performed on integrated circuit 400.

[0228] Figure 16 Show Figure 15 The wiring data D10' of the integrated circuit 400 shown is shown.

[0229] Reference Figure 16 The first mesh N1 can correspond to the first metal layer M1 and the second metal layer M2. The length of the wiring on the first metal layer M1 used to implement the first mesh N1 can be λ1, and the length of the wiring on the second metal layer M2 used to implement the first mesh N1 can be λ2. The second mesh N2 and the third mesh N3 can correspond to the third metal layer M3. The length of the wiring on the third metal layer M3 used to implement the second mesh N2 can be λ1. 3a The length of the wiring located on the third metal layer M3 used to implement the third network N3 can be λ. 3b The fourth mesh N4 and the fifth mesh N5 can correspond to the fourth metal layer M4, and the length of the wiring on the fourth metal layer M4 used to implement the fourth mesh N4 can be λ. 4a The length of the wiring located on the fourth metal layer M4 used to implement the fourth network N4 can be λ. 4b .

[0230] Figures 17A to 17C The example shown illustrates the pair according to an exemplary embodiment. Figure 15 An example of timing analysis of the integrated circuit 400 is shown. For instance, process changes may occur only in the first metal layer M1 and the second metal layer M2 of the first metal layers M1 to the fourth metal layers M4 corresponding to the first network N1 to the fifth network N5 included in the integrated circuit 400, while no process changes may occur in the third metal layer M3 and the fourth metal layer M4. In this case, wiring delay may vary only in the first network N1 implemented by the first metal layer M1 and the second metal layer M2. For example, the resistance of each of the first metal layer M1 and the second metal layer M2 may be increased by 15% compared to the modeled target value. In the following, reference will be made to... Figure 6 and Figures 15 to 17C Explain the time series analysis operation.

[0231] Figure 17AThis describes the operation of calculating the first wiring delay corresponding to the first network N1. The static timing analysis module 235 can receive wiring data D10' from the placement and routing module 231. Wiring data D10' includes the length λ1 of the wiring on the first metal layer M1 and the length λ2 of the wiring on the second metal layer M2. For example, λ1 can be 40 μm and λ2 can be 60 μm. Additionally, the static timing analysis module 235 can receive first unit delay information τ1 and second unit delay information τ2 contained in the technical documentation. The first unit delay information τ1 represents the delay per unit length of the first metal layer M1, and the second unit delay information τ2 represents the delay per unit length of the second metal layer M2. For example, τ1 can be 19.3 fs / μm and τ2 can be 3.3 fs / μm.

[0232] like Figure 15 As shown, when the delay of the first network N1 is 1ps, the first wiring delay δ1 of the first metal layer M1 can be calculated as 795.9fs (=1000*19.3*40 / (19.3*40+3.3*60)) using Formula 10 above, and the first wiring delay δ2 of the second metal layer M2 can be calculated as 204.1fs (=1000*3.3*60 / (19.3*40+3.3*60)) using Formula 10 above.

[0233] Figure 17B This describes the operation of calculating the second wiring delay corresponding to the first network N1. The static timing analysis module 235 can receive a first resistance-capacitance variation scaling factor σ1 and a second resistance-capacitance variation scaling factor σ2 as user input. When the resistance of each of the first metal layer M1 and the second metal layer M2 increases by 15% compared to the modeled target value, both the first resistance-capacitance variation scaling factor σ1 and the second resistance-capacitance variation scaling factor σ2 can be 1.15. For example, the second wiring delay δ1' of the wiring in the first metal layer M1 can be calculated using formula 11 or 12 above. In this case, the second wiring delay δ1' of the wiring in the first metal layer M1 can be calculated as 915.3 fs, and the second wiring delay δ2' of the wiring in the second metal layer M2 can be calculated as 234.7 fs. However, the concept of the present invention is not limited to this, and the formula used to calculate the second wiring delay can vary with various exemplary embodiments.

[0234] Figure 17C This section explains the operation for calculating the wiring delay skew corresponding to the first network N1. (Refer to...) Figure 17C The wiring delay skew Δ1 corresponding to the first metal layer M1 is -119.4 fs, and the wiring delay skew Δ2 corresponding to the second metal layer M2 is -30.6 fs. For example, the retention margin of the first mesh N1 can be calculated using Formula 15 above. Therefore, the retention margin can be calculated as follows:

[0235] Figure 18 This is a flowchart illustrating an integrated circuit design method according to an exemplary embodiment.

[0236] Reference Figure 18 As a method for performing timing analysis of integrated circuits while taking into account wiring variations, the integrated circuit design method can correspond to Figure 1 Examples of implementation methods are shown. Figure 18 The exemplary embodiments shown may correspond to Figure 4 A modified exemplary embodiment of the method shown. Therefore, the above references Figures 4 to 17C The explanations provided can also be applied to Figure 18 The exemplary embodiments shown are presented below, and for the sake of brevity, they will not be described in detail hereafter.

[0237] In operation S610, layout data for the integrated circuit is generated by placing and routing standard cells used to define the integrated circuit. In some exemplary embodiments, in operation S610, wiring data D10a corresponding to the nets included in the integrated circuit may be further generated. The wiring data D10a may include layer information of at least one wiring corresponding to the nets included in the layout of the integrated circuit and physical information of said at least one wiring. For example, the wiring data may include wiring length information.

[0238] In operation S620, parasitic components are extracted from the layout data. In some exemplary embodiments, in operation S620, wiring data D10b corresponding to a network included in the integrated circuit may be further generated. The wiring data D10b may include layer information of at least one wiring corresponding to a network included in the layout of the integrated circuit and physical information of said at least one wiring. For example, the wiring data may include wiring length information.

[0239] The wiring data D10a generated in operation S610 and the wiring data D10b generated in operation S620 may be substantially equal to each other. Therefore, in some exemplary embodiments, when wiring data D10a is generated in operation S610, wiring data D10b may not be generated in operation S620. Furthermore, in some exemplary embodiments, when wiring data D10b is generated in operation S620, wiring data D10a may not be generated in operation S610. In this way, wiring data D10a and wiring data D10b can be generated selectively.

[0240] In operation S630, timing analysis data reflecting process variations in the wiring is generated by performing timing analysis based on the physical information of the wiring. In some exemplary embodiments, the wiring data D10a generated in operation S610 may contain physical information about the wiring. Therefore, physical information can be obtained from the wiring data D10a in operation S630. In some exemplary embodiments, the wiring data D10b generated in operation S620 may contain physical information about the wiring. Therefore, physical information can be obtained from the wiring data D10b in operation S630. In some exemplary embodiments, the wiring delay skew of the timing path can be calculated based on a time constant scaling factor, said time constant scaling factor being based on process variations in the wiring, unit delay information representing the delay per unit length of the wiring, and the physical information of the wiring. In some exemplary embodiments, the integrated circuit design method may further include performing an Engineering Change Order (ECO) operation based on the timing analysis data. In some exemplary embodiments, in the design method, clock tree synthesis or optimization in placement and routing tools may be performed again based on the timing analysis data.

[0241] Figure 19 This is a flowchart illustrating a method for manufacturing a semiconductor device according to an exemplary embodiment.

[0242] Reference Figure 19 The semiconductor device manufacturing method can be divided into an integrated circuit design process and an integrated circuit manufacturing process. The integrated circuit design process may include operations S710 to S740, and the integrated circuit manufacturing process may include operations S750 and S760. The integrated circuit manufacturing process can be executed in a semiconductor process module as an operation based on layout data and according to the integrated circuit manufacturing of a semiconductor device. Figure 19 The semiconductor device manufacturing method shown in the exemplary embodiment can be referenced. Figures 1 to 18 The above-described integrated circuit design method is used to manufacture a semiconductor device. Specifically, operations S710 to S740 can respectively correspond to... Figure 1 Operations S110 to S140 are shown, and for the sake of simplicity, they will not be described in detail.

[0243] In operation S750, a mask is generated. The mask can be generated based on layout data. Specifically, optical proximity correction (OPC) can first be performed based on the layout data; OPC refers to a process of modifying the layout by reflecting errors based on optical proximity effects. Then, a mask can be manufactured based on the layout that has been modified according to the results of the OPC. In this case, a layout reflecting the OPC (e.g., a graphic data system (GDS) II reflecting the OPC) can be used to manufacture the mask.

[0244] In operation S760, a semiconductor device including an integrated circuit is manufactured. Masks can be used to manufacture the semiconductor device. Specifically, a semiconductor device including an integrated circuit is formed by performing various semiconductor processes on a semiconductor substrate, such as a wafer, using multiple masks. For example, the process using masks can represent a patterning process based on lithography. Through the patterning process, a desired pattern can be formed on a semiconductor substrate or material layer. Semiconductor processes can include deposition processes, etching processes, ionization processes, and cleaning processes. Additionally, semiconductor processes can include packaging processes that mount the semiconductor device on a printed circuit board (PCB) and seal the semiconductor device using a sealant, and can include test processes that test the semiconductor device or package.

[0245] Figure 20 A computer-readable storage medium 1000 is shown according to an exemplary embodiment.

[0246] Reference Figure 20The storage medium 1000 may store placement and routing program 1100, static timing analysis program 1200, layout data 1300, and wiring data 1400. The storage medium 1000 may be a computer-readable storage medium, and may include a storage medium that can be read by a computer and is used to provide instructions and / or data to a computer. For example, the computer-readable storage medium 1000 may include: magnetic or optical media, such as magnetic disks, magnetic tapes, compact disc read-only memory (CD-ROM), digital video disc read-only memory (DVD-ROM), compact disc-recordable (CD-R), compact disc-rewritable (CD-RW), digital video disc-recordable (DVD-R), or digital video disc-rewritable (DVD-RW); volatile or non-volatile memory, such as random access memory (RAM), read-only memory (ROM), or flash memory, non-volatile memory accessible via a universal serial bus interface, and microelectromechanical systems (MEMS). Computer-readable storage media can be inserted into a computer, integrated into a computer, or connected to a computer via communication media such as a network and / or wireless link.

[0247] The placement and routing program 1100 may include multiple instructions to perform a method for generating layout data of an integrated circuit using a standard cell library according to the exemplary embodiments described above. For example, the placement and routing program 1100 may be used to execute... Figure 1 Operation S120 shown Figure 4 Operation S210 shown Figure 12 Operations S440 to S460 are shown. Figure 18 The operation shown is S610 or Figure 19 The operation shown is S720.

[0248] The static timing analysis program 1200 may include multiple instructions to execute the timing analysis method according to the exemplary embodiments described above. For example, the static timing analysis program 1200 may be used to execute... Figure 1 Operation S140 shown Figure 4 Operation S220 shown Figure 12Operations S410 to S430 and operations S470 to S490 are shown. Figure 11 Operations S310, S320, and S340 to S360 are shown. Figure 13 Operations S510 to S540 are shown. Figure 18 The operation shown is S630 or Figure 19 The operation shown is S740.

[0249] Layout data 1300 may include physical information about the layout generated by placement and routing operations. For example, layout data 1300 may include spatial and width values ​​of conductive patterns constituting a signal network. Wiring data 1400 may include layer information and physical information of at least one wiring corresponding to each network included in the integrated circuit. Additionally, wiring data 1400 may include layer information and physical information of at least one via corresponding to each network included in the integrated circuit. For example, wiring data 1400 may be generated by placement and routing procedure 1100. However, the inventive concept is not limited to this, and wiring data 1400 may also be generated by parasitic extraction procedure. Although Figure 20 Layout data 1300 and wiring data 1400 are shown separately, but the concept of the invention is not limited thereto. In some exemplary embodiments, layout data 1300 may include wiring data 1400.

[0250] Exemplary embodiments of the present invention have been described above with reference to the accompanying drawings. Although specific terms are used herein to describe exemplary embodiments, these terms are for illustrating the technical concept of the invention and are not intended to limit the scope of the invention as set forth in the foregoing claims. Therefore, those skilled in the art will understand that various modifications and other equivalent embodiments can be derived therefrom. Consequently, the spirit and scope of the present invention should be defined by the appended claims.

[0251] Although the concept of the invention has been specifically shown and described with reference to exemplary embodiments thereof, it should be understood that various changes in form and detail may be made herein without departing from the spirit and scope of the foregoing claims.

Claims

1. A method for designing integrated circuits, characterized in that, include: At least one processor is used to perform synthesis operations to generate a netlist from input data about the integrated circuit; The at least one processor is used to place and route standard cells to generate layout data and wiring data, wherein the standard cells use the netlist to define the integrated circuit; The parasitic components are extracted from the layout data using the at least one processor; as well as The at least one processor performs timing analysis of the integrated circuit based on the layout data and the wiring data, and according to timing constraints.

2. The method according to claim 1, characterized in that, For wiring included in at least one network, the wiring data includes the metal layer of the wiring and the wiring length of the wiring.

3. The method according to claim 1, characterized in that, The wiring data includes: Layers of wiring patterns; The layout and size of the wiring pattern; At least one through hole; At least one metal layer; and Layer information of at least one metal layer.

4. The method according to claim 3, characterized in that, The wiring data also includes physical information about the at least one metal layer. The physical information includes at least one length information of the at least one metal layer, the width information of the at least one metal layer, the spatial information of the at least one metal layer, or the shielding information of the at least one metal layer.

5. The method according to claim 4, characterized in that, The physical information of the at least one metal layer also includes information related to process changes of the at least one metal layer.

6. The method according to claim 1, characterized in that, Performing the timing analysis of the integrated circuit includes: The wiring delay skew of each of the plurality of metal layers used to construct the integrated circuit is calculated based on a time constant scaling factor, which is set according to the process variation of at least one wiring included in the wiring data, unit delay information representing the delay per unit length of the at least one wiring, and physical information of the at least one wiring.

7. The method according to claim 1, characterized in that, The parasitic components include the parasitic resistance and parasitic capacitance of each of the multiple metal layers contained in the integrated circuit.

8. The method according to claim 1, characterized in that, Performing the timing analysis of the integrated circuit includes: Select a timing path from a plurality of timing paths in the integrated circuit as a timing critical path: the total timing delay from the start point of the timing path to the end point of the timing path is greater than or equal to a threshold delay.

9. A method for designing integrated circuits, characterized in that, include: Wiring data is generated from placement and routing data of standard cells defining the integrated circuit using at least one processor. The wiring data includes layer information for at least one wiring and physical information for the at least one wiring, the layer information corresponding to a network included in the integrated circuit. Using the at least one processor, timing analysis is performed on the timing path including the network to generate timing analysis data based on the wiring data. The physical information of the at least one wiring includes process variations of the at least one wiring.

10. The method according to claim 9, characterized in that, The physical information of the at least one wiring includes physical information corresponding to at least one metal layer of the mesh, and The process variation includes the scaling factor of the resistance / capacitance constant of the at least one metal layer.

11. The method according to claim 9, characterized in that, The physical information of the at least one wiring also includes physical information corresponding to at least two metal layers of the network, and The process variation includes the scaling factor of the resistance / capacitance constant of each of the at least two metal layers.

12. The method according to claim 10, characterized in that, The physical information of the at least one wiring also includes physical information corresponding to at least one via of the mesh, and The process variation includes the scaling factor of the resistance / capacitance constant of the at least one via.

13. The method according to claim 9, characterized in that, The physical information of the at least one wiring also includes the length information of the at least one wiring.

14. The method according to claim 9, characterized in that, The generation of the time series analysis data includes: The timing delay of the at least one wiring is calculated using the physical information of the at least one wiring; and The calculated timing delay is used to determine the time margin of the network.

15. A method for designing integrated circuits, characterized in that, include: At least one processor is used to generate wiring data from placement and routing data of standard cells, which define the integrated circuit. The wiring data includes layer information of at least one wiring and physical information of the at least one wiring, the layer information of the at least one wiring corresponding to a network contained in the integrated circuit. Using the at least one processor, parasitic components are extracted from the placement and routing data; as well as Timing analysis is performed using the at least one processor, the physical information of the at least one wiring included in the wiring data, and the extracted parasitic components to generate timing analysis data. The physical information of the at least one wiring includes process variations of the at least one wiring.

16. The method according to claim 15, characterized in that, The parasitic components include the parasitic resistance and parasitic capacitance of each of the multiple metal layers contained in the wiring data.

17. The method according to claim 15, characterized in that, The wiring data also includes at least one of the following: Layers of wiring patterns; The layout and size of the wiring pattern; At least one through hole; At least one metal layer; and Layer information of at least one metal layer.

18. The method according to claim 15, characterized in that, The physical information of the at least one wiring also includes the length information of the at least one wiring.

19. The method according to claim 15, characterized in that, The generation of the time series analysis data includes: The wiring delay skew of each of the plurality of metal layers used to construct the integrated circuit is calculated based on a time constant scaling factor, which is set according to the process variation of at least one wiring included in the wiring data, unit delay information representing the delay per unit length of the at least one wiring, and physical information of the at least one wiring.

20. The method according to claim 15, characterized in that, Performing the timing analysis includes: Select a timing path from a plurality of timing paths in the integrated circuit as a timing critical path: the total timing delay from the start point of the timing path to the end point of the timing path is greater than or equal to a threshold delay.

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