Data processing method, data processing circuit, electronic device, and storage medium

Abstract

The application discloses a data processing method, a data processing circuit, an electronic device and a storage medium, and belongs to the technical field of data processing. The data processing method comprises the following steps: acquiring target information from a target memory segment of a master chip based on an image processing chip and a first address in the image processing chip, wherein the first address is a mapping address of a second address, the second address is an address of the master chip used for reading and writing the target memory segment, and the target information comprises initial image data; and processing the initial image data based on the image processing chip to obtain target image data.

Description

Technical Field

[0001] This application relates to the field of data processing technology, specifically to a data processing method, a data processing circuit, an electronic device, and a storage medium. Background Technology

[0002] With the development of image processing technology, people have increasingly higher requirements for the images displayed by electronic devices. To ensure that electronic devices can output high-quality images that meet user needs, some electronic devices have introduced external chip solutions, that is, attaching a dedicated image processing chip to the application processor (AP) platform of the electronic device. As the image processing capabilities of image processing chips continue to improve, a large amount of static random-access memory (SRAM) is usually required in the image processing chip to meet the memory requirements of the image processing chip during image processing. However, SRAM requires a large wafer area during chip manufacturing, and the extensive use of SRAM will greatly increase the area of ​​the image processing chip, thereby increasing the chip manufacturing cost. Therefore, related technologies have the problem of excessively large image processing chip area due to the need to configure large amounts of SRAM in the image processing chip. When using dynamic range memory (DRAM) to store data during image processing, the image processing chip needs to frequently access the DDR device during operation. Therefore, the process of accessing the DDR device generates a lot of power consumption, which limits its application in power-sensitive terminal devices. Summary of the Invention

[0003] This application provides a data processing method, a data processing circuit, an electronic device, and a storage medium that can reduce the area of ​​an image processing chip.

[0004] In a first aspect, embodiments of this application provide a data processing method, including: Based on the image processing chip, target information is obtained from the target memory segment of the main control chip through the first address in the image processing chip, wherein the first address is a mapping address of the second address, the second address is the address in the main control chip used to read and write the target memory segment, and the target information includes initial image data; The initial image data is processed using the image processing chip to obtain the target image data.

[0005] Secondly, embodiments of this application provide a data processing circuit, including a main control chip and an image processing chip, wherein the main control chip is connected to the image processing chip; The image processing chip is used to obtain target information from the target memory segment of the main control chip through a first address in the image processing chip, wherein the first address is a mapping address of a second address, the second address is an address in the main control chip used to read and write the target memory segment, and the target information includes initial image data; The image processing chip is also used to process the initial image data to obtain target image data.

[0006] Thirdly, embodiments of this application provide an electronic device, including a processor and a memory, wherein the memory stores a program or instructions executable on the processor, and the program or instructions, when executed by the processor, implement the steps of the data processing method as described in the first aspect.

[0007] Fourthly, embodiments of this application provide a readable storage medium, characterized in that a program or instructions are stored on the readable storage medium, and when the program or instructions are executed by a processor, they implement the steps of the data processing method as described in the first aspect.

[0008] Fifthly, embodiments of this application provide a chip, the chip including a processor and a communication interface, the communication interface being coupled to the processor, the processor being used to run programs or instructions to implement the steps of the data processing method as described in the first aspect.

[0009] In a sixth aspect, embodiments of this application provide a computer program product stored in a storage medium, which is executed by at least one processor to implement the steps of the data processing method as described in the first aspect.

[0010] In this embodiment, since the first address is a mapped address of the second address, the image processing chip can read and write to the target memory segment in the main control chip through the first address. This allows the target information during image processing to be stored in the target memory segment of the main control chip, and the target information can be retrieved from the target memory segment for image processing. Because the data during image processing can be stored in the target memory segment of the main control chip, the SRAM in the image processing chip can be eliminated, thus reducing the chip's area. Furthermore, compared to using DDR to store data during image processing, frequent access to DDR devices is unnecessary, reducing power consumption during image processing and making it suitable for various terminal devices. Attached Figure Description

[0011] Figure 1This is a flowchart illustrating the data processing method provided in an embodiment of this application; Figure 2 This is one of the structural schematic diagrams of a data processing circuit provided in the embodiments of this application; Figure 3 This is a second schematic diagram of the structure of a data processing circuit provided in an embodiment of this application; Figure 4 This is a schematic diagram of the structure of another electronic device provided in an embodiment of this application; Figure 5 This is a schematic diagram of the hardware structure of the electronic device provided in the embodiments of this application. Detailed Implementation

[0012] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0013] The terms "first," "second," etc., used in the specification and claims of this application are used to distinguish similar objects and not to describe a specific order or sequence. It should be understood that such use of data can be interchanged where appropriate so that embodiments of this application can be implemented in orders other than those illustrated or described herein, and the objects distinguished by "first," "second," etc., are generally of the same class and the number of objects is not limited; for example, a first object can be one or more. Furthermore, in the specification and claims, "and / or" indicates at least one of the connected objects, and the character " / " generally indicates that the preceding and following objects are in an "or" relationship.

[0014] The following description, in conjunction with the accompanying drawings, details a data processing method, data processing circuit, electronic device, and storage medium provided in this application through specific embodiments and application scenarios.

[0015] Please see Figure 1 , Figure 1 This is a flowchart illustrating a data processing method provided in an embodiment of this application. The data processing method includes the following steps: Step 101: Based on the image processing chip, obtain target information from the target memory segment of the main control chip through the first address in the image processing chip, wherein the first address is a mapping address of the second address, the second address is the address in the main control chip used to read and write the target memory segment, and the target information includes initial image data; Step 102: Process the initial image data based on the image processing chip to obtain the target image data.

[0016] The above data processing method can be applied to various electronic devices with shooting functions, as well as various monitoring systems, such as access control monitoring systems.

[0017] The aforementioned main control chip can be an application processor (AP) or a system-on-chip (SOC). The aforementioned image processing chip can be various types of image processing chips, such as an image signal processing (ISP) chip, a video processing unit (VPU), a graphics processing unit (GPU), a neural network processing unit (NPU), etc.

[0018] In one embodiment of this application, the aforementioned main control chip can be connected to multiple image processing chips simultaneously via PCIe, and each image processing chip can include a first address. The first address in each image processing chip is a mapping address to a second address in the main control chip. Thus, each image processing chip can read and write to a target memory segment in the main control chip through its own first address, thereby enabling multiple image processing chips to share the target memory segment in the main control chip. The multiple image processing chips can be different chips, such as VPU, GPU, NPU, and ISP chips.

[0019] In one embodiment of this application, a mapping relationship between the first address and the second address can be pre-established, so that both the first address and the second address can read and write to the target memory segment. It is understood that the specific address contents of the first address and the second address can be the same or different. When establishing the mapping relationship between the first address and the second address, the first address can be mapped to the second address, or the second address can be mapped to the first address.

[0020] The aforementioned first address serves as a mapped address. While there is no actual memory space within the image processing chip, since this first address is a mapped address to the second address, the image processing chip directly reads and writes data in the target memory segment through this first address. In this process, the image processing chip is essentially reading and writing to its local memory. Please refer to [link to relevant documentation]. Figure 2The target memory segment is equivalent to forming a virtual mapped memory in the image processing chip. This mapped memory is no different from the local memory of the image processing chip, but does not need to occupy the actual area of ​​the image processing chip.

[0021] It is understood that the aforementioned target memory segment is the actual memory space within the main control chip. The aforementioned second address serves as the actual read / write address for the target memory segment of the main control chip, and the main control chip can also directly read and write data in the target memory segment through the second address.

[0022] In this embodiment, since the first address is a mapped address of the second address, the image processing chip can read and write to the target memory segment in the main control chip through the first address. This allows the target information during image processing to be stored in the target memory segment of the main control chip, and the target information can be retrieved from the target memory segment for image processing. Because the data during image processing can be stored in the target memory segment of the main control chip, the SRAM in the image processing chip can be eliminated, thus reducing the chip's area. Furthermore, compared to using DDR to store data during image processing, the power consumption of the image processing chip can be reduced because frequent access to DDR devices is unnecessary, and it is applicable to various terminal devices.

[0023] Optionally, the target information further includes processing parameters, the initial image data is initial tensor data, and the processing of the image data based on the image processing chip to obtain the target image data includes: The image processing chip processes the initial tensor data using the processing parameters to obtain target tensor data, wherein the target image data includes the target tensor data.

[0024] The initial tensor data mentioned above can be image data from various scenarios. For example, the initial tensor data can be image data or video data from a shooting scenario, or video data from a video viewing scenario. Correspondingly, processing the initial tensor data using the processing parameters based on the image processing chip can refer to performing image enhancement processing on the initial tensor data using the processing parameters based on the image processing chip. The image enhancement method can be various types of image enhancement methods, such as noise reduction, white balance adjustment, and contrast enhancement. It is understood that the target tensor data obtained after processing refers to the image data obtained after processing.

[0025] Since the processing parameters of the image processing chip typically differ for image data in different scenarios, the processing parameters for each scenario can be pre-stored in the target memory segment of the main control chip. Thus, when the image processing chip acquires the target information, it can first obtain the initial tensor data, and then, based on the scenario to which the initial tensor data belongs, obtain the processing parameters corresponding to the initial tensor data.

[0026] In this embodiment, since the image processing chip can also store the processing parameters during image processing in the target memory segment of the main control chip, the image processing chip does not need to have an SRAM for storing the processing parameters, which helps to further reduce the area of ​​the image processing chip. Furthermore, compared to storing the processing parameters in DDR, the storage method of this embodiment reduces the power consumption of the image processing chip during image processing because it does not require frequent access to the DDR device.

[0027] Optionally, before the image processing chip obtains the target information from the target memory segment of the main control chip via the first address in the image processing chip, the method further includes: The image processing chip is connected to the main control chip via a high-speed serial computer expansion bus (Peripheral Component Interconnect Express, PCIE). The first address is mapped to the second address through the base address register (BAR). The target memory segment is a memory segment in the main control chip's dynamic memory (Double Data Rate RAM, DDR).

[0028] Please see Figure 2 In one embodiment of this application, the main control chip includes a PCIe root complex (RC) interface, and the image processing chip includes a PCIe endpoint (EP) interface. The PCIe RC interface of the main control chip and the PCIe EP interface of the image processing chip are connected via PCIe. The aforementioned BAR refers to the PCIe BAR in the image processing chip. When mapping the first address, the image processing chip can first write the first address into the BAR of the image processing chip, for example, it can write the first address into BAR1 or BAR2. Then, the first address located in the BAR is mapped to the second address of the main control chip through the PCIe connection, thereby establishing a mapping relationship between the first address and the second address.

[0029] Specifically, the main control chip acts as the RC (Responsive Controller) terminal, and the image processing chip acts as the EP (Electronic Execution Terminal) terminal. The first address is specifically the PCIe memory address in the image processing chip, and the second address is the PCIe memory address in the main control chip. The EP terminal includes multiple BARs (Block Arrangements), and each BAR can be allocated one PCIe memory address. The PCIe memory addresses of the RC terminal and the PCIe memory addresses of the EP terminal can be mapped to each other. After mapping, each BAR contains two PCIe memory addresses, thus establishing the mapping relationship between the first address and the second address.

[0030] In this embodiment, the image processing chip uses a PCIe connection and a BAR to map the first address to the second address, thereby establishing the mapping relationship between the first address and the second address.

[0031] Optionally, the image processing chip includes a neural network processing module, and the neural network processing module is pre-configured with an image processing model. The processing parameters include target weight parameters of the image processing model. The step of processing the initial tensor data using the processing parameters based on the image processing chip to obtain target tensor data includes: The image processing chip updates the weight parameters of the neural network model in the neural network processing module using the target weight parameters. The initial tensor data is processed by the neural network processing module to perform image enhancement processing, thereby obtaining the target tensor data.

[0032] Please see Figure 2 The aforementioned neural network processing module can be a neural network processing unit (NPU) in the image processing chip. The NPU, for different application scenarios (e.g., night scene noise reduction, video frame interpolation, video super-resolution), needs to switch different neural network weights (NN weights) to achieve different image processing effects. Therefore, the aforementioned processing parameters can include the NN weights, and the target weight parameter is the NN weight. Please see further... Figure 2 The image processing chip also includes a PCIe controller, which serves as a component of the PCIe EP end for configuring and controlling the PCIe interface.

[0033] Please see Figure 3 In one specific embodiment of this application, the NPU serves as the aforementioned image processing chip, and the target memory segment is a mapped DDR section within the entire DDR (Whole DDR) of the main control chip AP. The NPU may include a large number of operators, such as multiply matrix operators, accumulator (ACC) operators, activation operators, etc., and all of these operators in the NPU can directly read and write the virtual mapped memory to ensure that the NPU can perform image processing based on the target information stored in the mapped DDR section. Furthermore, please refer to... Figure 3 The NPU may also include a Direct Memory Access Engine (DMA Engine), wherein the DMA Engine is a hardware DMA engine integrated into PCIe, which is typically configured to move data to memory.

[0034] It is understood that the aforementioned neural network model can be a pre-trained neural network model, and the neural network processing module can perform various types of image enhancement processing on the received image data based on the neural network model, such as noise reduction processing, frame interpolation processing, contrast enhancement processing, etc.

[0035] The above-mentioned image enhancement processing of the initial tensor data based on the neural network processing module to obtain the target tensor data specifically refers to: performing image enhancement processing on the initial tensor data based on the neural network processing module after parameter update to obtain the target tensor data.

[0036] In this embodiment, the weight parameters of the neural network model in the neural network processing module are updated based on the target weight parameters using the image processing chip; and the target tensor data is obtained by performing image enhancement processing on the initial tensor data based on the neural network processing module, thereby realizing the process of processing the initial tensor data using the neural network model based on the target weight parameters.

[0037] Optionally, after processing the initial tensor data using the processing parameters based on the image processing chip to obtain the target tensor data, the method further includes: Based on the image processing chip, the target tensor data is written into the target memory segment via the first address.

[0038] Specifically, since the image processing chip can directly read and write the target memory segment based on the first address, after processing the initial tensor data to obtain the target tensor data, the target tensor data can be written into the target memory segment based on the first address.

[0039] In this embodiment, the target tensor data is written to the target memory segment based on the first address, thereby realizing the process of sending the processed target tensor data back to the main control chip. Subsequently, the main control chip can read the target tensor data based on the second address so that the main control chip can perform subsequent processing on the target tensor data.

[0040] Optionally, the step of obtaining target information from the target memory segment of the main control chip through a first address in the image processing chip includes: When the image processing chip receives a first interrupt notification sent by the main control chip, the image processing chip obtains target information from the target memory segment of the main control chip based on the first address in the image processing chip. The first interrupt notification is used to notify the image processing chip to process the initial tensor data. After the image processing chip writes the target tensor data into the target memory segment via the first address, the method further includes: The image processing chip sends a second interrupt notification to the main control chip, wherein the second interrupt notification is used to notify the main control chip that the processing of the initial tensor data has been completed.

[0041] The first and second interrupt notifications mentioned above can be generated using various common interrupt mechanisms. For example, please refer to [link to relevant documentation]. Figure 2 It can be an interrupt notification generated using the Extended Message-Signalled Interrupt (MSI-X) mechanism.

[0042] When the aforementioned main control chip obtains the initial tensor data to be processed by the image processing chip, it can write the initial tensor data into the target memory segment via the second address. Then, it sends a first interrupt notification to the image processing chip to instruct the image processing chip to retrieve the initial tensor data and corresponding processing parameters from the target memory segment for processing. Correspondingly, after the image processing chip completes the processing of the initial tensor data and writes the resulting target tensor data into the target memory segment, it can send a second interrupt notification to the main control chip. Upon receiving the second interrupt notification, the main control chip can read the target tensor data from the target memory segment via the second address and perform subsequent processing on the target tensor data.

[0043] In this embodiment, the data read and write operations of the main control chip and the image processing chip are triggered by using a first interrupt notification and a second interrupt notification. This ensures that the image processing chip can process the initial tensor data to be processed in a timely manner. At the same time, it ensures that after the image processing chip completes the processing of the initial tensor data, the main control chip can perform subsequent processing on the target tensor data in a timely manner, thereby improving the efficiency of image processing.

[0044] Please see Figure 2 and Figure 3 This is a schematic diagram of a data processing circuit provided in an embodiment of the present application. The data processing circuit includes a main control chip and an image processing chip, and the main control chip is connected to the image processing chip. The image processing chip is used to obtain target information from the target memory segment of the main control chip through a first address in the image processing chip, wherein the first address is a mapping address of a second address, the second address is an address in the main control chip used to read and write the target memory segment, and the target information includes initial image data; The image processing chip is also used to process the initial image data to obtain target image data.

[0045] Optionally, the target information further includes processing parameters, and the initial image data is initial tensor data; The image processing chip is specifically used to process the initial tensor data using the processing parameters to obtain target tensor data, wherein the target image data includes the target tensor data.

[0046] Optionally, the main control chip and the image processing chip are connected via PCIe; The image processing chip is used to map the first address to the second address via BAR based on the PCIe connection, wherein the target memory segment is a memory segment in the DDR of the main control chip.

[0047] Optionally, the image processing chip includes a neural network processing module, and the neural network processing module is pre-configured with an image processing model, the processing parameters including the target weight parameters of the image processing model; The image processing chip is used to update the weight parameters of the neural network model in the neural network processing module using the target weight parameters; The image processing chip is also used to perform image enhancement processing on the initial tensor data based on the neural network processing module to obtain the target tensor data.

[0048] Optionally, the image processing chip is further configured to write the target tensor data into the target memory segment via the first address.

[0049] Optionally, the image processing chip is specifically used to obtain target information from the target memory segment of the main control chip based on the first address in the image processing chip when it receives a first interrupt notification sent by the main control chip, wherein the first interrupt notification is used to notify the image processing chip to process the initial tensor data; The image processing chip is also used to send a second interrupt notification to the main control chip, wherein the second interrupt notification is used to notify the main control chip that the processing of the initial tensor data has been completed.

[0050] It is understood that the data processing circuit provided in the embodiments of this application can implement each process of the data processing method described in the above embodiments and has the same beneficial effects. To avoid repetition, it will not be described again here.

[0051] In this embodiment, since the first address is a mapped address of the second address, the image processing chip can read and write to the target memory segment in the main control chip through the first address. This allows the target information during image processing to be stored in the target memory segment of the main control chip, and the target information can be retrieved from the target memory segment for image processing. Because the data during image processing can be stored in the target memory segment of the main control chip, the SRAM in the image processing chip can be eliminated, thus reducing the area of ​​the image processing chip.

[0052] Optionally, such as Figure 4As shown, this application embodiment also provides another electronic device 400, including a processor 401, a memory 402, and a program or instructions stored in the memory 402 and executable on the processor 401. When the program or instructions are executed by the processor 401, they implement the various processes of the above-described data processing method embodiment and achieve the same technical effect. To avoid repetition, they will not be described again here.

[0053] It should be noted that the electronic devices in the embodiments of this application include the mobile electronic devices and non-mobile electronic devices described above.

[0054] Figure 5 A schematic diagram of the hardware structure of an electronic device to implement an embodiment of this application.

[0055] The electronic device 500 includes, but is not limited to, components such as: radio frequency unit 501, network module 502, audio output unit 503, input unit 504, sensor 505, display unit 506, user input unit 507, interface unit 508, memory 509, and processor 510.

[0056] The processor 510 is used to obtain target information from a target memory segment of the main control chip based on the image processing chip through a first address in the image processing chip, wherein the first address is a mapping address of a second address, the second address is an address in the main control chip used for reading and writing the target memory segment, and the target information includes initial image data. The processor 510 is also used to process the initial image data based on the image processing chip to obtain target image data.

[0057] Optionally, the target information further includes processing parameters, the initial image data is initial tensor data, and the processor 510 is further configured to process the initial tensor data using the processing parameters based on the image processing chip to obtain target tensor data, wherein the target image data includes the target tensor data.

[0058] Optionally, the processor 510 is used for the image processing chip to map the first address to the second address through the base address register BAR based on the high-speed serial computer expansion bus PCIE connection between the main control chip and the image processing chip, wherein the target memory segment is a memory segment in the dynamic memory DDR of the main control chip.

[0059] Optionally, the processor 510 is configured to update the weight parameters of the neural network model in the neural network processing module based on the target weight parameters of the image processing chip; The processor 510 is used to perform image enhancement processing on the initial tensor data based on the neural network processing module to obtain the target tensor data.

[0060] Optionally, the processor 510 is configured to write the target tensor data into the target memory segment based on the image processing chip via the first address.

[0061] Optionally, the processor 510 is configured to, upon receiving a first interrupt notification from the main control chip, obtain target information from the target memory segment of the main control chip based on a first address in the image processing chip, wherein the first interrupt notification is used to notify the image processing chip to process the initial tensor data. The processor 510 is used to send a second interrupt notification to the main control chip based on the image processing chip, wherein the second interrupt notification is used to notify the main control chip that the processing of the initial tensor data has been completed.

[0062] Those skilled in the art will understand that the electronic device 500 may also include a power supply (such as a battery) for supplying power to various components. The power supply may be logically connected to the processor 510 through a power management system, thereby enabling functions such as managing charging, discharging, and power consumption through the power management system. Figure 5 The electronic device structure shown does not constitute a limitation on the electronic device. The electronic device may include more or fewer components than shown, or combine certain components, or have different component arrangements, which will not be elaborated here.

[0063] It should be understood that, in this embodiment, the input unit 504 may include a graphics processing unit (GPU) 5041 and a microphone 5042. The GPU 5041 processes image data of still images or videos obtained by an image capture device (such as a camera) in video capture mode or image capture mode. The display unit 506 may include a display panel 5061, which may be configured in the form of a liquid crystal display, an organic light-emitting diode, etc. The user input unit 507 includes a touch panel 5071 and other input devices 5072. The touch panel 5071 is also called a touch screen. The touch panel 5071 may include a touch detection device and a touch controller. Other input devices 5072 may include, but are not limited to, physical keyboards, function keys (such as volume control buttons, power buttons, etc.), trackballs, mice, joysticks, etc., which will not be described in detail here. The memory 509 can be used to store software programs and various data, including but not limited to applications and operating systems. The processor 510 may integrate an application processor and a modem processor, wherein the application processor mainly handles the operating system, user interface, and applications, and the modem processor mainly handles wireless communication. It is understandable that the aforementioned modem processor may not be integrated into processor 510.

[0064] This application also provides a readable storage medium storing a program or instructions. When the program or instructions are executed by a processor, they implement the various processes of the above-described data processing method embodiments and achieve the same technical effects. To avoid repetition, they will not be described again here.

[0065] The processor is the processor in the electronic device described in the above embodiments. The readable storage medium includes computer-readable storage media, such as computer read-only memory (ROM), random access memory (RAM), magnetic disk, or optical disk.

[0066] This application embodiment also provides a chip, which includes a processor and a communication interface. The communication interface is coupled to the processor. The processor is used to run programs or instructions to implement the various processes of the above data processing method embodiments and can achieve the same technical effect. To avoid repetition, it will not be described again here.

[0067] It should be understood that the chip mentioned in the embodiments of this application may also be referred to as a system-on-a-chip, system chip, chip system, or system-on-a-chip, etc.

[0068] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element. Furthermore, it should be noted that the scope of the methods and apparatuses in the embodiments of this application is not limited to performing functions in the order shown or discussed, but may also include performing functions substantially simultaneously or in the reverse order, depending on the functions involved. For example, the described methods may be performed in a different order than described, and various steps may be added, omitted, or combined. Additionally, features described with reference to certain examples may be combined in other examples.

[0069] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods of the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) and includes several instructions to cause a terminal (which may be a mobile phone, computer, server, air conditioner, or network device, etc.) to execute the methods described in the various embodiments of this application.

[0070] The embodiments of this application have been described above with reference to the accompanying drawings. However, this application is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of this application without departing from the spirit and scope of the claims, and all of these forms are within the protection scope of this application.

Claims

1. A data processing method, characterized in that, include: Based on the image processing chip, target information is obtained from the target memory segment of the main control chip through the first address in the image processing chip, wherein the first address is a mapping address of the second address, the second address is the address in the main control chip used to read and write the target memory segment, and the target information includes initial image data; The initial image data is processed using the image processing chip to obtain the target image data.

2. The method according to claim 1, characterized in that, The target information also includes processing parameters. The initial image data is initial tensor data. The process of processing the initial image data based on the image processing chip to obtain the target image data includes: The image processing chip processes the initial tensor data using the processing parameters to obtain target tensor data, wherein the target image data includes the target tensor data.

3. The method according to claim 1, characterized in that, Before the image processing chip obtains target information from the target memory segment of the main control chip via a first address in the image processing chip, the method further includes: The image processing chip is connected to the main control chip via a high-speed serial computer expansion bus (PCIE). The first address is mapped to the second address through the base address register (BAR). The target memory segment is a memory segment in the dynamic memory (DDR) of the main control chip.

4. The method according to claim 2, characterized in that, The image processing chip includes a neural network processing module, and the neural network processing module is pre-configured with an image processing model. The processing parameters include the target weight parameters of the image processing model. The step of processing the initial tensor data using the processing parameters based on the image processing chip to obtain target tensor data includes: Based on the image processing chip, the weight parameters of the neural network model in the neural network processing module are updated using the target weight parameters; The initial tensor data is processed by the neural network processing module to perform image enhancement processing, thereby obtaining the target tensor data.

5. The method according to claim 2, characterized in that, After processing the initial tensor data using the processing parameters based on the image processing chip to obtain the target tensor data, the method further includes: Based on the image processing chip, the target tensor data is written into the target memory segment via the first address.

6. The method according to claim 5, characterized in that, The step of obtaining target information from the target memory segment of the main control chip through a first address in the image processing chip includes: When the image processing chip receives a first interrupt notification sent by the main control chip, the image processing chip obtains target information from the target memory segment of the main control chip based on the first address in the image processing chip. The first interrupt notification is used to notify the image processing chip to process the initial tensor data. After the image processing chip writes the target tensor data into the target memory segment via the first address, the method further includes: The image processing chip sends a second interrupt notification to the main control chip, wherein the second interrupt notification is used to notify the main control chip that the processing of the initial tensor data has been completed.

7. A data processing circuit, characterized in that, It includes a main control chip and an image processing chip, wherein the main control chip is connected to the image processing chip; The image processing chip is used to obtain target information from the target memory segment of the main control chip through a first address in the image processing chip, wherein the first address is a mapping address of a second address, the second address is an address in the main control chip used to read and write the target memory segment, and the target information includes initial image data; The image processing chip is also used to process the initial image data to obtain target image data.

8. The data processing circuit according to claim 7, characterized in that, The target information also includes processing parameters, and the initial image data is initial tensor data; The image processing chip is specifically used to process the initial tensor data using the processing parameters to obtain target tensor data, wherein the target image data includes the target tensor data.

9. The data processing circuit according to claim 7, characterized in that, The main control chip and the image processing chip are connected via PCIe; The image processing chip is used to map the first address to the second address via BAR based on the PCIe connection, wherein the target memory segment is a memory segment in the DDR of the main control chip.

10. The data processing circuit according to claim 8, characterized in that, The image processing chip includes a neural network processing module, and the neural network processing module is pre-configured with an image processing model. The processing parameters include the target weight parameters of the image processing model. The image processing chip is used to update the weight parameters of the neural network model in the neural network processing module using the target weight parameters; The image processing chip is also used to perform image enhancement processing on the initial tensor data based on the neural network processing module to obtain the target tensor data.

11. The data processing circuit according to claim 8, characterized in that, The image processing chip is also used to write the target tensor data into the target memory segment via the first address.

12. The data processing circuit according to claim 11, characterized in that, Specifically, the image processing chip is used to obtain target information from the target memory segment of the main control chip based on the first address in the image processing chip when it receives a first interrupt notification sent by the main control chip. The first interrupt notification is used to notify the image processing chip to process the initial tensor data. The image processing chip is also used to send a second interrupt notification to the main control chip, wherein the second interrupt notification is used to notify the main control chip that the processing of the initial tensor data has been completed.

13. An electronic device, characterized in that, It includes a processor and a memory, the memory storing a program or instructions that can run on the processor, the program or instructions being executed by the processor to implement the steps of the data processing method as described in any one of claims 1 to 6.

14. A readable storage medium, characterized in that, The readable storage medium stores a program or instructions that, when executed by a processor, implement the steps of the data processing method as described in any one of claims 1 to 6.

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