Display device

Abstract

A display device includes a pixel circuit on a substrate; a data line configured to transmit a data signal for the pixel circuit on the substrate; a power supply line; and an additional voltage supply line different from the power supply line and the data line; wherein the pixel circuit includes a drive transistor configured to control an amount of current supplied to a light emitting element; a storage capacitor disposed between a gate terminal of the drive transistor and the power supply line; a first switching transistor disposed between the power supply line and the drive transistor; a second switching transistor disposed between a source terminal of the drive transistor and the data line; and a third switching transistor disposed between the source terminal of the drive transistor and the additional voltage supply line.

Description

[0001] This application is a divisional application of application number 202010303623.1, filed on April 17, 2020, entitled "Display Device and Method for Controlling the Display Device". Technical Field

[0002] This disclosure relates to a display device and a method for controlling the display device. Background Technology

[0003] Flat panel display devices, such as liquid crystal displays (LCDs) and organic light-emitting diode (OLEDs), are used in a wide variety of fields. For example, they are used in computer monitors, home televisions, and mobile terminals such as smartphones and tablets, and even in automobiles and machine tools.

[0004] This expansion of applications for flat panel displays (FPS) devices is placing them in more demanding environments, such as high-temperature, high-humidity, and mechanically vibrating conditions. For this reason, increasingly higher demands are being placed on the reliability and fault tolerance of FPS devices. Summary of the Invention

[0005] The aforementioned flat panel display device typically has a pixel circuit array on a substrate and data lines for transmitting data signals to the pixel circuit array. These data lines are electrically connected to a data driver via chip-on-glass (COG) or thin-film-on-glass (FOG) technology.

[0006] Data signals are used to determine the brightness of pixels. Data signal transmission failures can severely impact display quality. As mentioned above, flat panel display devices are used in various environments, which increases the likelihood of data signal transmission failures. Therefore, a technology is needed to improve tolerance to data signal transmission failures.

[0007] One aspect of this disclosure is a display device comprising: a pixel circuit on a substrate; a data line configured to transmit a data signal for the pixel circuit on the substrate; a power line; and an additional voltage supply line different from the power line and the data line; wherein the pixel circuit includes: a driving transistor configured to control the amount of current supplied to a light-emitting element; a storage capacitor disposed between a gate terminal of the driving transistor and the power line; a first switching transistor disposed between the power line and the driving transistor; a second switching transistor disposed between a source terminal of the driving transistor and the data line; and a third switching transistor disposed between a source terminal of the driving transistor and the additional voltage supply line, wherein the third switching transistor provides a signal voltage different from the data signal from the additional voltage supply line to the driving transistor.

[0008] One aspect of this disclosure is to increase the tolerance for data signal transmission failures in display devices. It will be understood that the foregoing general description and the following detailed description are exemplary and explanatory, and not intended to limit this disclosure. Attached Figure Description

[0009] Figure 1 An example configuration of an OLED display device is illustrated schematically;

[0010] Figure 2 An example of the circuit configuration used in Embodiment 1 for monitoring and resolving data signal transmission failures is shown;

[0011] Figure 3 An example configuration of the internal controls of the driver IC for monitoring data signal transmission and resolving failures (if any) is shown;

[0012] Figure 4 An example configuration of a multiplexer (DeMUX) is shown;

[0013] Figure 5 A thumbnail of the configuration example in Embodiment 2 is shown schematically;

[0014] Figure 6 An example of the configuration of the backplane of the OLED display device in Embodiment 2 is illustrated schematically;

[0015] Figure 7 An example configuration of a pixel circuit with monitoring functionality is shown;

[0016] Figure 8 It is used for control (driving). Figure 7 Timing diagram of the signals of the pixel circuit in a frame period;

[0017] Figure 9 An example of a data signal transmission failure caused by an interruption (error) in the data line between the driver IC and the select transistor is shown;

[0018] Figure 10 The signal waveforms of the selection line during one frame period under normal operation and the signal waveforms of the selection line during one frame period after a data signal transmission failure is detected are shown.

[0019] Figure 11 An example configuration of the monitoring line control circuit in the driver IC is shown;

[0020] Figure 12 This shows another example of a monitoring cycle;

[0021] Figure 13AThis illustrates the operation of the monitoring line control circuit when no failure occurs (under normal operation);

[0022] Figure 13B The operation of the monitoring line control circuit associated with the failed data line and the operation of the monitoring line control circuit associated with the normal data line are shown.

[0023] Figure 14 An example configuration of a multiplexer (DeMUX) is shown;

[0024] Figure 15 An example configuration of a pixel circuit with monitoring functionality is shown;

[0025] Figure 16 Another configuration example of a pixel circuit with monitoring capabilities is shown;

[0026] Figure 17 Another example configuration of a pixel circuit with monitoring capabilities is shown;

[0027] Figure 18 Another example configuration of a pixel circuit with monitoring capabilities is shown;

[0028] Figure 19 Another example configuration of a pixel circuit with monitoring capabilities is shown;

[0029] Figure 20 Another example configuration of a pixel circuit with monitoring capabilities is shown;

[0030] Figure 21 Another example configuration of a pixel circuit with monitoring capabilities is shown;

[0031] Figure 22 Another example configuration of a pixel circuit with monitoring capabilities is shown;

[0032] Figure 23 Another example configuration of a pixel circuit with monitoring capabilities is shown;

[0033] Figure 24 An example configuration showing multiple monitoring lines connected to a single monitoring pad is shown;

[0034] Figure 25 An example configuration is shown where a multiplexer on a substrate sequentially selects multiple monitoring lines connected to a monitoring pad; and

[0035] Figure 26 An example configuration is shown where a multiplexer included in a driver IC sequentially selects multiple monitoring lines, each connected to a monitoring pad. Detailed Implementation

[0036] Hereinafter, embodiments are described in detail with reference to the accompanying drawings. Common elements in the drawings are indicated by the same reference numerals, and for clarity of understanding, some elements in the drawings are exaggerated in size and shape.

[0037] This disclosure discloses a technique for improving the reliability and fault tolerance of display devices such as liquid crystal display (LCD) devices or organic light-emitting diode (OLED) display devices. The technique in this disclosure is suitable for display devices intended for use in harsh operating environments, such as automotive display devices.

[0038] Display devices used in harsh environments with high temperature, high humidity, and mechanical vibration, such as automotive displays, have experienced line defects caused by data signal transmission failures. In particular, line defects caused by connection failures in COG- or FOG- mounting sections are frequently observed. COG data drivers have small bump pitches and narrow widths for each bump; therefore, aging of the bumps connecting the data driver (driver IC) to the substrate can cause initially undetected disconnections.

[0039] Specifically, in OLED display devices utilizing various pixel circuit configurations, data signal transmission failure manifests as a brightness defect rather than a black defect. Furthermore, in OLED display devices utilizing special pixel circuit configurations, data signal transmission failure manifests as a brightness line defect emitting high-brightness light. For example, there are known pixel circuits that apply a reset voltage to the gate of the driving thin-film transistor (TFT) during a cycle before detecting the gate threshold voltage Vth. If the correct data signal is not provided to the pixel after the voltage of the driving TFT's gate (marked as GND) is reset, the pixel circuit enters a light-emitting cycle in the reset state. Because the difference between the reset voltage and the supply voltage provided to the source of the driving transistor, i.e., the gate voltage Vgs, is very large, the light-emitting element emits high-brightness light.

[0040] The configuration examples described below detect data signal transmission failures and eliminate or mitigate display defects caused by these failures during the operation of the display device. As a result, the fault tolerance of the display device is improved, and user convenience is further enhanced.

[0041] Example 1

[0042] Figure 1An exemplary configuration example of an OLED display device 10 is shown. The OLED display device 10 includes a thin-film transistor (TFT) substrate 100 on which OLED elements (light-emitting elements) are formed, an encapsulation substrate 200 for encapsulating the OLED elements, and a bonding member (glass fused seal) 300 for bonding the TFT substrate 100 to the encapsulation substrate 200. The space between the TFT substrate 100 and the encapsulation substrate 200 is filled with an inert gas such as dry nitrogen and sealed by the bonding member 300.

[0043] Around the cathode formation region 114, which is located further outward than the display region 125 of the TFT substrate 100, scan circuits 131 and 132, a driver IC 134, and a multiplexer 136 are provided. The driver IC 134 is connected to an external device via a flexible printed circuit (FPC) 135. The scan circuits 131 and 132 drive scan lines on the TFT substrate 100.

[0044] The driver IC 134 is mounted, for example, with an anisotropic conductive film (ACF). The driver IC 134 provides power and timing signals (control signals) to the scan circuits 131 and 132, and also provides data signals to the multiplexer 136.

[0045] Multiplexer 136 continuously outputs the output of one pin of driver IC 134 to d (d is an integer greater than 1) data lines. Multiplexer 136 changes the output data lines of the data signal from driver IC 134 d times per scan cycle, driving the same number of data lines as the output pins of driver IC 134 d times.

[0046] Display area 125 includes multiple OLED elements (pixels) and multiple pixel circuits for controlling the light emission of the multiple pixels. In the example of a color OLED display device, each OLED element emits light of one color among red, yellow, and blue. The multiple pixel circuits constitute a pixel circuit array. As described later, each pixel circuit includes a driving TFT (driving transistor). Data signals transmitted via data lines determine the gate voltage (Vgs) of the driving TFT. The data signals analogously change the conductance of the driving TFT to provide a pre-bias current to the OLED element corresponding to the light emission level.

[0047] Figure 2 An example of a circuit configuration for monitoring and resolving data signal transmission failures is shown in this embodiment. Figure 2An example of a connection failure 121 between the bumps of the driver IC 134 on the TFT substrate 100 and the data pad 102 is shown. The TFT substrate 100 includes a pixel circuit array 150, data lines 105, and data pads 102 formed thereon. The data lines 105 transmit data signals to the pixel circuit array 150. The data pads 102 interconnect the data lines 105 with the bumps of the driver IC 134. A plurality of data pads 102 constitute a data pad set.

[0048] The TFT substrate 100 also includes a monitoring line 111 and a monitoring pad 101 formed thereon. The monitoring pad 101 interconnects the monitoring line 111 with bumps of the driver IC 134. Multiple monitoring pads 101 constitute a monitoring pad set. Each monitoring line 111 is deployed so as not to overlap with the data pad 102 and connects to the data line 105 at a specific point (referred to as the monitoring point). Figure 2 In the middle, the monitoring point is located at the point between the data pad 102 and the pixel circuit array 150 on the data line 105.

[0049] The driver IC 134 transmits data signals to each pixel circuit connected to the data line 105 via the data pad 102 and the data line 105. The driver IC 134 includes data signal supply circuitry (not shown) for generating and supplying the data signals. The driver IC 134 monitors the data signal (data signal voltage) of the data line 105 (and the data pad 102) by monitoring the voltage of the monitoring line 111 (and the monitoring pad 101) associated with the data line 105.

[0050] Driver IC 134 can detect data signal transmission failure due to voltage from monitoring line 111. When a data signal transmission failure is detected on a data line 105, driver IC 134 provides a correction signal (correction signal voltage) to the data line 105 via monitoring line 111 connected to the data line 105, replacing the data signal. The data line 105 then transmits this correction signal to the pixel circuitry. Providing this correction signal prevents display defects from occurring.

[0051] For example, when a connection failure occurs at data pad 102A, the voltage of the associated data line 105A becomes inconsistent with the data signal from driver IC 134, but remains constant. Driver IC 134 uses monitoring line 111A and monitoring pad 101A to monitor the voltage of data line 105A to detect data signal transmission failure caused by the connection failure at data pad 102A. Driver IC 134 provides a correction signal to data line 105A via monitoring line 111A and monitoring pad 101A. This correction signal is provided to the pixel circuitry via data line 105A.

[0052] The driver IC 134 can be configured to notify a control circuit (not shown) upon detecting a data signal transmission failure. The control circuit (not shown) can be configured to issue a visual or auditory warning to the user requesting partial replacement. As a result, further failures can be avoided.

[0053] Figure 3 An example configuration of the internal controls for the driver IC used to monitor data signal transmission and resolve failures (if any) is shown. Figure 3 A monitoring line control circuit 340 for a pair of data lines 105 and a monitoring line 111 is shown. The driver IC 134 includes monitoring circuitry, which includes multiple monitoring line control circuits 340. Figure 3 In the configuration example, each monitoring line control circuit 340 is associated with a pair of data lines 105 and monitoring lines 111. The monitoring line control circuit 340 includes a DA converter (DAC) 341; buffer amplifiers 342 and 345; a first switch 343; a second switch 344; a comparator 346; and a NOT gate 347.

[0054] When the inputs to comparator 346 are equal, the output φ is 0. When the inputs to comparator 346 are different, the output φ is 1. Each switch 343 and 344 is OFF when its input control signal is 0 and ON when its input control signal is 1. The control signal for the first switch 343 is the inverted signal of the output φ of comparator 346. Conversely, the control signal for the second switch 344 is the output φ of comparator 346.

[0055] Under normal operation, the DA converter 341 converts digital video data from an external source into an analog data signal. The buffer amplifier 342 receives the data signal from the DA converter 341 and outputs it to the data pad 102. This data signal is then transmitted to the pixel circuit via data line 105 connected to the data pad 102.

[0056] Under normal operation, the first switch 343 is on and the second switch 344 is off. The data signal (voltage) from the buffer amplifier 342 is input to the comparator 346. In addition, since the first switch is on, the data signal (voltage) from the data line 105 is input to the comparator 346 via the monitoring line 111 and the monitoring pad 101.

[0057] Since the two inputs of comparator 346 are equal (or the data signal voltage), the output φ of comparator 346 is 0. The output φ of comparator 346 is inverted by NOT gate 347 and input as a control signal to the first switch 343. In addition, the output φ of comparator 346 is input as a control signal to the second switch 344.

[0058] Next, the operation in the event of a data signal transmission failure is described. When a connection failure (connection anomaly) occurs between the data pad 102 and the driver IC 134, the values ​​of the two inputs to comparator 346 become different. One input to comparator 346 is the output of buffer amplifier 342 preceding the data pad 102, while the other input is the voltage on data line 105. The output of buffer amplifier 342 varies with the video data, while the voltage on data line 105 remains constant.

[0059] When the input values ​​of comparator 346 are different, its output φ is 1. As a result, the first switch 343 changes from on to off, and the second switch 344 changes from off to on. The data signal from the DA converter 341 enters the monitoring pad 101 via the buffer amplifier 342 and the second switch 344. The monitoring line 111 transmits the data signal from the monitoring pad 101 to the data line 105.

[0060] As described above, the monitoring line control circuit 340 uses monitoring line 111 to monitor the voltage of data line 105 to detect data signal transmission failure. In response to detecting a failure, the monitoring line control circuit 340 uses the data signal from the DA converter 341 as a correction signal and provides it to data line 105 via monitoring pad 101 and monitoring line 111. This data signal is transmitted through data line 105 to be provided to the pixel circuit. This configuration allows the data signal to be provided as a correction signal to the pixel circuit when a connection failure occurs at data pad 102.

[0061] Figure 4 An example configuration of the multiplexer (DeMUX) 136 is shown. In this embodiment, the driver IC 134 has terminals for monitoring data signal transmission in addition to terminals for outputting data signals. The multiplexer 136 enables a reduction in the number of terminals of the driver IC 134 and the number of pads on the substrate.

[0062] Multiplexer 136 includes a switching transistor 361 controlled by clock signal CKA and a switching transistor 362 controlled by clock signal CKB. The switching transistors are controlled to be on or off. Clock signals CKA and CKB are provided by driver IC 134. Each data pad 102 is connected to a pair of switching transistors 361 and 362.

[0063] Switching transistor 361 is connected to data line 105A, which is connected to pixel circuit array 150. Switching transistor 362 is connected to data line 105B, which is connected to pixel circuit array 150. Data lines 105A and 105B are connected to different pixel circuit sets. Data line 105C connects switching transistors 361 and 362 to data pad 102. Data line 105C transmits the data signal transmitted by both data lines 105A and 105B.

[0064] Switching transistors 361 and 362 are turned on in different cycles according to clock signals CKA and CKB. When switching transistor 361 is on, the data signal from data pad 102 is provided to the pixel circuit assembly via data line 105C, switching transistor 361, and data line 105A. When switching transistor 362 is on, the data signal from data pad 102 is provided to another pixel circuit assembly via data line 105C, switching transistor 362, and data line 105B.

[0065] Figure 4 An example configuration is such that a data pad 102 is connected to two data lines to transmit data signals to different sets of pixel circuits; however, a data pad 102 may be connected to three or more signal lines to transmit data signals to different sets of pixel circuits.

[0066] Example 2

[0067] The configuration example in Example 1 monitors the voltage of the data line at a monitoring point located between the pixel circuit array and the data pad, and provides a correction signal to the pixel circuit via the data line in response to detecting a voltage error. The configuration example described below has a monitoring point inside the pixel array, uses a monitoring line extending in the pixel circuit to monitor the voltage at that monitoring point, and provides a correction signal via the monitoring line.

[0068] Figure 5 A thumbnail diagram of a configuration example of this embodiment is shown as an example. This configuration example includes a pixel circuit 500 with monitoring functionality and a monitoring line 111 extending within a pixel circuit array 150. The voltage monitoring point, monitored using the monitoring line 111, is located within the pixel circuit array 150. This configuration example monitors the voltage of the monitoring line 111 to detect data signal transmission failure. Figure 5 In this configuration, a data signal transmission failure caused by a connection failure 121 at the data pad 102 is detected via monitoring line 111. Furthermore, in this configuration example, a correction signal is provided to the pixel circuit 500 via the monitoring line 111 in response to the detected failure.

[0069] Figure 6An exemplary configuration of the backplane of the OLED display device in this embodiment is shown. Pixel circuits 500 are deployed in a matrix constituting the pixel circuit array 150. Each pixel circuit 500 controls the emission of light from the OLED element. Figure 6 In the diagram, a group of pixel circuits 500 arranged vertically in a line is called a pixel circuit column, and a group of pixel circuits 500 arranged horizontally in a line is called a pixel circuit row.

[0070] Multiple data lines 105 and multiple monitoring lines 111 from driver IC 134 extend within pixel circuit array 150. The data lines 105 and monitoring lines 111 extend in the column direction. Each pair of data lines 105 and monitoring lines 111 is connected to a pixel circuit in a pixel circuit column.

[0071] Multiple thin-film-on-glass (FOG) pads 104 are disposed on the TFT substrate 100. An FPC (Flexible Printed Circuit) is connected to external devices. Figure 6 (Not shown) is connected to certain FOG pads 104. Some other FOG pads 104 are connected to the terminals of driver IC 134. Figure 6 The control lines from driver IC 134 to scan circuits 131 and 132 are omitted.

[0072] Another FOG pad 104 is connected to the anode power line PVDD. The anode power line PVDD supplies the anode power voltage from an external device (not shown) to the pixel circuit 500. Multiple anode power lines PVDD are deployed inside the pixel circuit array 150 and are all connected. Figure 6 In this example, multiple anode power lines PVDD comprise multiple anode power lines PVDD, each extending along a pixel circuit column. These anode power lines PVDD provide the power supply voltage to the anode of the OLED element (light-emitting element).

[0073] Another FPG pad 104 is connected to a reset power line Vrst. These reset power lines Vrst supply reset power voltage from an external device (not shown) to the pixel circuitry 500. Multiple reset power lines Vrst are deployed inside the pixel circuitry array 150 and they are all connected.

[0074] exist Figure 6 In this example, the multiple reset power lines Vrst comprise multiple reset power lines Vrst, each extending along a pixel circuit row. These reset power lines Vrst provide a sufficiently low reset voltage to the anode of the OLED element (light-emitting element) and the gate of the driving transistor.

[0075] Figure 7An example configuration of a pixel circuit 500 with monitoring function is shown. The pixel circuit 500 with monitoring function includes seven transistors (TFTs) M1-M7. The pixel circuit 500 with monitoring function controls the light emission of the OLED element 501 and also monitors the data signal transmission of the pixel circuit 500 with monitoring function. In this example, transistors M1-M7 are p-type.

[0076] Transistor M3 is a drive transistor used to control the amount of current supplied to OLED element 501. Drive transistor M3 controls the amount of current supplied to OLED element 501 from the anode power line PVDD based on the voltage held by storage capacitor Cst. The cathode of OLED element 501 is connected to the cathode power line VEE. Storage capacitor Cst holds the voltage between the gate and source of transistor M3 (also simply referred to as the gate voltage).

[0077] Transistors M1 and M6 control whether OLED element 501 emits light. Transistor M1 switches on / off (ON / OFF) the current supplied from the anode power line PVDD to the driving transistor M3. Transistor M6 switches on / off (ON / OFF) the current supplied from the driving transistor M3 to the OLED element 501. Transistor M6 also functions to provide a reset voltage to the gate of the driving transistor M3. Transistors M1 and M6 are controlled by light emission control lines Em1 and Em2 extending from scanning circuits 131 or 132, respectively.

[0078] Transistor M5 controls whether a reset voltage is provided to the anode of OLED element 501 and the gate of driving transistor M3. When transistor M5 is switched ON by the select line S1 extending from scan circuit 131 or 132, transistor M5 provides a reset voltage from the reset power supply line Vrst to the anode of OLED 501, and provides the reset voltage to the gate of driving transistor M3 via transistors M6 and M4.

[0079] Transistor M2 is a selection transistor used to select the pixel circuit 500 to which data signals will be provided. The gate voltage of transistor M2 is controlled by the selection line S2 extending from scan circuit 131 or 132. When selection transistor M2 is ON, it provides the data signal from data line 105 to the gate (storage capacitor Cst) of drive transistor M3.

[0080] In this example, the selection transistor M2 (its source and drain) is connected between the data line 105 and the source of the driving transistor M3. Additionally, the transistor M4 (its source and drain) is connected between the drain and gate of the driving transistor M3.

[0081] Transistor M4 functions to compensate for changes in the threshold voltage of the driving transistor M3. When transistor M4 is on, the driving transistor M3 becomes a diode-connected transistor. The data signal from data line 105 is supplied to the storage capacitor Cst via the on select transistor M2, driving transistor M3, and transistor M4. The storage capacitor Cst maintains the voltage obtained by applying the threshold voltage Vth of the driving transistor M3 to the data signal. Transistor M4 also functions to provide a reset voltage to the gate of the driving transistor M3. The reset voltage is provided to the gate of the driving transistor M3 during the cycles when transistors M4, M5, and M6 are on.

[0082] Transistor M7 is a monitoring transistor used to monitor data signal transmission. The gate voltage of monitoring transistor M7 is controlled by select line S3 extending from scan circuit 131 or 132. Monitoring transistor M7 is a switching transistor whose on / off state is adjusted by the control signal from select line S3. The source / drain of monitoring transistor M7 is connected to monitoring point PB between driving transistor M3 and transistor M6, and the remaining source / drain is connected to monitoring line 111. Driver IC 134 uses monitoring transistor M7 and monitoring line 111 to monitor the voltage at monitoring point PB.

[0083] Figure 8 It is used for control (driving). Figure 7 The timing diagram of the signal of the pixel circuit 500 in one frame period is shown. Figure 8 This is a timing diagram used to select the Nth row and write the data signal Vdata(N) to the pixel circuit 500. During the period from time T2 to time T3, the data signal Vdata(N) is written to the storage capacitor Cst of the pixel circuit 500.

[0084] At time T1, prior to time T2, the light emission control line Em1 changes from low to high, and the selection line S1 changes from high to low. At time T1, the light emission control line Em2 is low, and the selection lines S2 and S3 are high.

[0085] According to the control signals described above, at time T1, transistor M1 is off, while transistor M6 is on. Transistors M4 and M5 are on. Transistors M2 and M7 are off. The states of these transistors remain unchanged throughout the period from time T1 to time T2.

[0086] During the period from time T1 to time T2, transistors M4, M5, and M6 are on. The reset voltage of the reset power line Vrst is supplied to the anode of OLED element 501 via transistor M5. The reset voltage of the reset power line Vrst is also supplied to the gate of driving transistor M3 via transistors M5, M6, and M4.

[0087] At time T2, the light-emitting control line Em2 changes from low to high, while the selection line S2 changes from high to low. At time T2, the light-emitting line Em1 is high, the selection line S1 is low, and the selection line S3 is high. Based on these control signals, at time T2, transistors M1 and M6 are off. Transistors M4 and M5 are on. The selection transistor M2 is on. Transistor M7 is off. These transistor states remain unchanged throughout the period from time T2 to time T3.

[0088] During the period from time T2 to time T3, transistor M6 is off; the supply of reset voltage to the gate of driving transistor M3 is also off. Since transistor M4 is on, driving transistor M3 is in diode connection. Since transistor M2 is on, the data signal Vdata(N) from data line 105 is transmitted via transistors M2, M3, and M4 and written to storage capacitor Cst. The voltage to be written to storage capacitor Cst is either the threshold voltage Vth of driving transistor M3 compensated for, or the threshold voltage Vth and the data signal Vdata(N).

[0089] During the period from time T3 to time T4, all lines are high. At time T4, the selection line S3 changes from high to low. The other lines remain high. During the period from time T4 to time T5, the selection line S3 is low, and the other lines are high. Because the selection line S3 is low, transistor M7 is on.

[0090] The voltage at monitoring point PB on the drain side of driving transistor M3 is read by driver IC 134 through transistor M7 and monitoring line 111. The period from time T4 to time T5 is the monitoring period (voltage measurement period) for monitoring the data signal transmission of pixel circuit 500. When the data signal is being transmitted normally, driver IC 134 reads the voltage corresponding to the data signal Vdata.

[0091] At time T5, selection line S3 changes from low to high. During the period from time T5 to time T6, all lines are high. At time T6, the light-emitting control lines Em1 and EM2 change from high to low, thus turning transistors M1 and M6 from off to on. Since the other lines are high, transistors M2, M4, M5, and M7 remain off. The driving transistor M3 controls the driving current to be supplied to OLED element 501 based on the data signal Vdata(N).

[0092] Figure 9An example of data signal transmission failure caused by an interrupt (error) 122 in the data line between driver IC 134 and select transistor M2 is shown. The storage capacitor Cst is not supplied with a data signal. Driver IC 134 monitors (measures) the voltage at monitoring point PB using monitoring line 111 during the monitoring cycle (from time T4 to time T5). If the voltage at monitoring point PB differs from the voltage corresponding to the transmitted data signal, driver IC 134 provides a correction signal to storage capacitor Cst via monitoring line 111, transistor M7, and transistor M4.

[0093] The correction signal can be a value (voltage) determined based on the video data or a predetermined constant value (constant voltage) corresponding to the black level. When providing a black level voltage to a pixel circuit, the driver IC 134 can also provide a correction signal corresponding to the black level to pixel circuits used for other pixel colors associated with the same video data pixel. The correction signal reduces display quality degradation caused by data signal transmission failures.

[0094] Figure 10 The diagram shows the signal waveforms of selection lines S2 and S3 during one frame period under normal operation, and the signal waveforms of selection lines S2 and S3 during one frame period after a data signal transmission failure is detected. The signal waveforms of selection lines S2 and S3 under normal operation are combined. Figure 8 To describe.

[0095] As described above, when a data signal transmission failure is detected, a correction signal is provided via monitoring line 111 and transistor M7 instead of the data signal provided via data line 105. Figure 10 In the example, the signal waveform used to control the selection line S3 of transistor M7 and the combination Figure 8 The signal waveform of the selection line S2 is the same as described. That is, the selection line S3 is low during the period from time T4 to time T5, thus turning on transistor M7. During the period from time T4 to T5, the correction signal is provided to the storage capacitor Cst via monitoring line 111, transistor M7, and transistor M4.

[0096] exist Figure 10 In the example, transistor M7 is connected to the node between driving transistors M3 and M6. Transistor M6 is off during the period when the correction signal is provided. Therefore, the correction signal from transistor M7 can be provided to the storage capacitor Cst (the gate of driving transistor M3) instead of to the OLED element 501. Typically, the period for providing the data signal is shorter than the period from time T2 to T3 during which the selection line S2 is low, for example, in the latter half of the period from time T2 to time T3. Therefore, the selection line S3 can only be low for a portion of the period from time T2 to T3.

[0097] Figure 11 An example configuration of the monitoring line control circuit 400 in the driver IC 134 is shown. Each monitoring pad 101 is provided with a monitoring line control circuit 400; each monitoring line control circuit monitors the voltage through the associated monitoring pad 101 and additionally outputs a correction signal. The monitoring line control circuit 400 monitors the voltage of the monitoring line 111 in monitoring mode, and enters a correction mode when a data signal transmission failure is detected. In correction mode, the monitoring line control circuit 400 provides a correction signal to the storage capacitor Cst of the pixel circuit 500 as a substitute for the data signal.

[0098] In the mode of monitoring the voltage of monitoring line 111, the flag (signal) FLG output from the failure determination circuit 408 is 0 (low). The flag FLG and the flag FLG inverted by the NOT circuit 407 are input to switches 402 and 401, respectively. Each switch 401 and 402 is made of a pair of p-type transistors and n-type transistors connected in parallel.

[0099] In monitoring mode, switch 401 is on and switch 402 is off. The voltage of monitoring line 111 is input to the analog-to-digital converter (ADC) 405 via switch 401 and buffer amplifier (sensing amplifier) ​​403. Failure determination circuit 408 determines whether a data signal transmission failure has occurred based on the output of ADC 405.

[0100] In one example, the failure determination circuit 408 determines whether a failure has occurred based on whether the output from the ADC 405 changes. If a data signal transmission failure occurs, the voltage at the monitoring point remains substantially constant. If the voltage variation is within a predetermined range over a predetermined number of frame periods, the failure determination circuit 408 determines that a data signal transmission failure has occurred.

[0101] In another example, the failure determination circuit 408 determines whether a failure has occurred based on the data signal output to data line 105 and the output from ADC 405. Under normal operation, the failure determination circuit 408 obtains information about the provided data signal and the voltage measured at the monitoring point, and identifies the relationship between the data signal and the voltage monitored at the monitoring point. If the difference between the voltage measured at the monitoring point and the value obtained from the provided data signal using the aforementioned relationship is greater than a threshold, the failure determination circuit 408 determines that a data signal transmission failure has occurred.

[0102] The relationship between the data signal and the monitored voltage can be preset to the driver IC 134. Corresponding to the data signal, the monitored voltage changes positively as the display's scale value (brightness) increases. When an interrupt occurs, a large current flows, causing the voltage to be observed to deviate significantly from the voltage monitored at the highest scale value under normal operation. The failure determination circuit 408 detects this deviation.

[0103] Upon determining that a data signal transmission failure has occurred, the failure determination circuit 408 switches the monitoring line control circuit 400 to correction mode. The failure determination circuit 408 inverts the flag FLG. The flag FLG changes from 0 (low) to 1 (high). Switch 401 is switched from on to off, while switch 402 is switched from off to on.

[0104] Data correction circuit 409 in combination Figure 9 and Figure 10 During normal operation, the data signal is written to the output correction data in the cycle. DAC 406 converts the correction data into an analog correction signal and outputs it to switch 402 via buffer amplifier 404. Since switch 402 is on, the correction signal is output to monitoring line 111.

[0105] The data correction circuit 409 generates correction data based on the video data and correction data from the failure determination circuit 408. For example... Figure 9 As shown, the correction signal is provided to the storage capacitor Cst without passing through the driving transistor M3. Therefore, the threshold voltage Vth of the driving transistor M3 is not compensated when the correction signal is provided.

[0106] The failure determination circuit 408 determines a threshold voltage, for example, during the monitoring cycle using the relationship between the data signal and the monitored voltage, and provides this value to the data correction circuit 409. The data correction circuit 409 applies this threshold voltage to the data signal determined by the video data before outputting. In another example, the driver IC 134 may have the function of measuring the threshold voltage of the driving transistor M3. The data correction circuit 409 or the failure determination circuit 408 obtains the threshold voltage measured by this function before a failure occurs. Methods for measuring the threshold voltage of the driving transistor by controlling the transistor in the pixel circuit are known and will not be explained here.

[0107] Regardless of the video data, the correction signal can be constant. For example, the correction signal will turn off the drive transistor M3. This simple control eliminates luminance line defects. While providing a correction signal to turn off the drive transistor in a pixel circuit, the driver IC 134 can also provide correction signals to pixel circuits used for other pixel colors corresponding to the same video data pixels.

[0108] In the example above, the voltage at monitoring point PB was measured before the OLED element 501 started emitting light. Figure 12Another example of a monitoring cycle is shown. In this example, the voltage at monitoring point PB is monitored during the period when the OLED element 501 emits light. Specifically, selection line S3 is low during a predetermined period between time T6 and time T1 of the next frame, and high during other periods. When the data signal is being transmitted normally, driver IC 134 reads the voltage based on the data signal Vdata.

[0109] When a data signal transmission failure is detected, the driver IC 134 changes the control timing used to select line S3 so that transistor M7 will be on during the data write cycle under normal operation.

[0110] Select line S3 controls transistor M7 in pixel circuits 500 within a row. For this reason, turning transistor M7 on during the data signal write cycle to provide a correction signal to one pixel circuit 500 (the failed pixel circuit) causes all transistors M7 in the other pixel circuits 500 (the normal pixel circuits) in the same row to also turn on. Therefore, it is important to properly control the monitoring line control circuit for the normal pixel circuits (to which data signals are normally transmitted) when a failure occurs.

[0111] Figure 13A The operation of the monitoring line control circuit 400 is shown when no failure occurs (under normal operation). The flag FLG from the failure determination circuit 408 is 0. Monitoring line 111 is connected to the sense amplifier 403. During the data signal write cycle (from time T2 to time T3), select line S2 is low and select line S3 is high. Monitoring transistor M7 is off; therefore, no signal comes from monitoring line 111.

[0112] During the voltage monitoring cycle (measurement cycle) from time T4 to time T5 using monitoring line 111, selection line S2 is high and selection line S3 is low. Monitoring transistor M7 is on; therefore, the monitoring signal from monitoring line 111 enters sensing amplifier 403.

[0113] Figure 13B The operation of the monitoring line control circuit 400 associated with the failed data line and the operation of the monitoring line control circuit 400 associated with the normal data line 105 are shown. Figure 13B The diagram illustrates the operation during a cycle in which a correction signal or a data signal is written to the storage capacitor Cst. During this cycle, select lines S2 and S3 are low, while transistors M2 and M7 are on. A correction signal is provided to the failed pixel circuit (first pixel circuit), and a data signal is provided to the normal pixel circuit (second pixel circuit).

[0114] In the monitoring line control circuit 400 for the failed data line, FLG is marked as 1. Monitoring line 111 is connected to the output buffer amplifier 404; a correction signal from the DAC 406 is output to monitoring line (first monitoring line) 111. The correction signal is provided to the storage capacitor Cst via transistors M7 and M4.

[0115] In the monitoring line control circuit 400 used for the normal data line (normal pixel circuit), FLG is marked as 0. Monitoring line 111 is connected to the sensing amplifier 403. The data signal is provided to the normal pixel circuit via data line 105. The data signal is provided to the storage capacitor Cst via transistors M2, M3, and M4. In the normal pixel circuit, transistor M7 is on. Therefore, the data signal from data line 105 is input to the sensing amplifier 403 via transistor M7.

[0116] The monitoring line control circuit 400 for the normal pixel circuit (second pixel circuit) stops supplying power voltage to the sensing amplifier 403. This brings the monitoring line (second monitoring line) 111 into a high-impedance state, which reduces the impact on the data signal to be supplied to the pixel circuit and also prevents the sensing amplifier 403 from being damaged by the data signal.

[0117] Figure 14 An example configuration of the multiplexer (DeMUX) 136 is shown. The description is consistent with that in Embodiment 1. Figure 4 The difference between the configuration examples and... Figure 4 Unlike the configuration example in the example, monitoring line 111 extends into pixel circuit array 150 via multiplexer 136. As described above, each monitoring line 111 is connected to transistor M7 of pixel circuit 500. Multiplexer 136 enables a reduction in the number of data pads 102.

[0118] Example 3

[0119] The following describes some configuration examples of pixel circuits with monitoring functions. As will be described below, the techniques for monitoring data signal transmission and correcting data signal transmission failures in this disclosure are applicable to display devices with various pixel circuit configurations.

[0120] Figure 15 An example configuration of a pixel circuit 500 with monitoring functionality is shown. The main description is related to... Figure 7 and Figure 9 The difference in the illustrated configuration example is that the source / drain of the monitoring transistor M7 is connected to data line 105. In other words, the monitoring point PC is located on the data line. The driver IC 134 directly monitors the voltage of the data line to detect data signal transmission failure. In one example, the driver IC 134 monitors (measures) the voltage during the period when the data signal is transmitted on data line 105.

[0121] The driver IC 134 provides a correction signal to the pixel circuit via data line 105, just like a data signal. Since the correction signal is provided to the storage capacitor Cst (the gate of the driver transistor M3) via the driver transistors M3 and M4, the correction signal can compensate for the threshold voltage.

[0122] Figure 16 Another configuration example of a pixel circuit 500 with monitoring capabilities is shown. The main description is related to... Figure 7 and Figure 9 The differences in the illustrated configuration examples are as follows: The source / drain of monitoring transistor M7 is connected to the node between transistor M4 and storage capacitor Cst. In other words, the monitoring point PC is the gate node of driving transistor M3 and is located between transistor M4 and storage capacitor Cst. Driver IC 134 monitors the gate voltage of driving transistor M3 to detect data signal transmission failure. In one example, driver IC 134 monitors (measures) the voltage during the light emission cycle of OLED element 501.

[0123] The correction signal is provided to the gate node (storage capacitor Cst) of the driving transistor M3 via transistor M7. In one example, driver IC134 provides a correction signal that compensates for a threshold voltage Vth determined based on the monitored voltage, or a correction signal for a black level.

[0124] Figure 17 Another configuration example of a pixel circuit 500 with monitoring functionality is shown. The main description is related to... Figure 7 and Figure 9 The difference in the illustrated configuration example is that the source / drain of monitoring transistor M7 is connected to the node between transistor M1 and driving transistor M3. In other words, the monitoring point PC is located between transistor M1 and driving transistor M3.

[0125] Driver IC 134 monitors the voltage at the source / drain of driver transistor M3 to detect data signal transmission failure. In one example, driver IC 134 monitors (measures) the voltage during the light emission cycle of OLED element 501. A correction signal is provided to storage capacitor Cst (the gate of driver transistor M3) via driver transistors M3 and M4, just like the data signal. Therefore, the correction signal compensates for the threshold voltage.

[0126] Figure 18 Another configuration example of a pixel circuit 500 with monitoring functionality is shown. The main description is related to... Figure 7 and Figure 9The difference in the illustrated configuration example is the addition of another transistor M8. The gate of transistor M8 is connected to the select line S1; its source / drain is connected to the reset power line Vrst; and the remaining source / drain is connected to the node between the storage capacitor Cst and transistor M4. The gates of transistors M4 and M5 are connected to the select line S2. Voltage monitoring and correction signals using monitoring transistor M7 are provided in the same manner as in Example 2.

[0127] Figure 19 Another configuration example of a pixel circuit 500 with monitoring functionality is shown. Transistor M2 provides a data signal from data line 105 to the gate of driving transistor M3 via coupling capacitor C1. Transistor M2 is switched on / off by select line S1. The voltage at the gate of driving transistor M3 is determined by two capacitors C1 and C2, the data signal, and the threshold voltage Vth of driving transistor M3. Capacitors C1 and C2 constitute a storage capacitor.

[0128] Transistor M6, located between driving transistor M3 and OLED element 501, controls the light emission of OLED element 501. Transistor M6 is switched on / off by the light emission control line Em. Transistor M4 compensates for the threshold voltage Vth of driving transistor M3. Transistor M4 is switched on / off by the selection line S2. When transistor M4 is on, driving transistor M3 is in a diode connection.

[0129] The monitoring transistor M7 is switched on / off by the select line S3. The source / drain of the monitoring transistor M7 is connected to the monitoring line 111, and the remaining source / drain is connected to the node between the driving transistors M3 and M6. The monitoring point PB is located between the driving transistors M3 and M6. In one example, the driver IC 134 monitors (measures) the anode voltage of the OLED element 501 during the emission cycle.

[0130] The correction signal is provided to the gate of the driving transistor M3 via transistors M7 and M4. Since the threshold voltage Vth is not automatically compensated, the monitoring line control circuit in the driver IC 134 can be configured to generate a correction signal in which the threshold voltage Vth is compensated or a black level correction signal, as described in Example 2.

[0131] Figure 20 Another example configuration of a pixel circuit 500 with monitoring functionality is shown. The transistors (TFTs) in this circuit are n-type. Transistor M2 provides the data signal from data line 105 to the storage capacitor Cst (the gate of the driving transistor M3). Transistor M2 is switched on / off by the select line S1.

[0132] Transistor M5 connects the anode of OLED element 501 to the reset power line Vrst. Transistor M5 is switched on / off by select line S2. Transistor M5 provides a reset voltage to the anode of OLED element 501 to reset the voltage at the anode before OLED element 501 emits light.

[0133] The monitoring transistor M7 is switched on / off by the select line S3. The source / drain of the monitoring transistor M7 is connected to monitoring line 111, and the remaining source / drain is connected to the gate of the driving transistor M3. The monitoring point PC is the gate node of the driving transistor M3 located between the gate of the driving transistor M3 and the storage capacitor Cst. In one example, the driver IC 134 monitors (measures) the voltage at the gate of the driving transistor M3 during the light emission cycle. A correction signal is provided to the gate node of the driving transistor M3 via transistor M7.

[0134] Figure 21 Another configuration example of a pixel circuit 500 with monitoring functionality is shown. (Compared to...) Figure 20 Compared to the configuration example in the previous example, the connection node position of the monitoring transistor M7 is different. Monitoring transistor M7 connects monitoring line 111 to data line 105. The monitoring point PC is located on data line 105. Driver IC 134 measures the voltage of data line 105 during the data write cycle to detect failure. A correction signal is provided to the gate of driver transistor M3 via monitoring line 111 and data line 105.

[0135] Figure 22 Another configuration example of a pixel circuit 500 with monitoring functionality is shown. Transistor M1 is connected between the anode power line PVDD and the driving transistor M3 to control whether the OLED element 501 emits light. Transistor M1 is switched on / off by the light emission control line Em. Transistor M2 provides the data signal from the data line 105 to the storage capacitor Cst via transistor M10. Transistor M2 is switched on / off by the selection line S1.

[0136] Transistors M9 and M10 operate to set the threshold voltage of the driving transistor M3 to the storage capacitor Cst. Transistor M9 is connected between the reference power line Vref and the storage capacitor Cst, and its on / off state is adjusted by the select line S1. Transistor M10 is connected between the storage capacitor Cst and the gate of the driving transistor M3, and its on / off state is adjusted by the light-emitting control line Em. The node between the storage capacitor Cst and transistors M9 and M10, and the node between transistor M1 and the driving transistor M3, are connected.

[0137] The monitoring transistor M7 is connected to monitoring line 111 and data line 105. The monitoring point PC is located on data line 105. The driver IC134 measures the voltage of data line 105 during the data write cycle to detect failure. A correction signal is provided to the storage capacitor Cst via monitoring line 111 and data line 105.

[0138] Figure 23 Another configuration example of a pixel circuit 500 with monitoring functionality is shown. (Compared to...) Figure 22 Compared to the configuration example in the example, another transistor M5 is added. Transistor M5 is connected to the anode of OLED element 501 and the reset power line Vrst. Transistor M5 is switched on / off by the select line S1. Transistor M5 provides a reset voltage to the anode of OLED element 501 to reset the voltage at the anode before OLED element 501 emits light.

[0139] Example 4

[0140] The following describes a configuration example for reducing the monitoring pad (the monitoring terminal of driver IC 134) and the monitoring line control circuit in driver IC 134. Figure 24 An example configuration is shown where multiple monitoring lines are connected to a single monitoring pad. Figure 24 In this example, the number of monitoring line control circuits 326 in the driver IC 134 is equal to the number of monitoring pads 101; each monitoring line control circuit 326 monitors the voltage and additionally sends a correction signal through the associated monitoring pad 101.

[0141] exist Figure 24 In this example, data lines 105R, 105G, and 105B are connected to different data pads 102. Data lines 105R, 105G, and 105B transmit data signals used to display the same pixel in video data. A monitoring pad 101 is connected to three monitoring lines 111R, 111G, and 111B. Monitoring lines 111R, 111G, and 111B are monitoring lines used to monitor the transmission of data signals through data lines 105R, 105G, and 105B, respectively.

[0142] When the monitoring line control circuit 326 detects a failure in any of the monitoring lines 111R, 111G, and 111B, it provides a black-level correction signal through all monitoring lines 111R, 111G, and 111B. This configuration generates black lines regardless of the image to be displayed. This configuration example reduces the number of monitoring pads 101 and the number of monitoring line control circuits 326 to one-third.

[0143] Figure 25 An example configuration is shown where a multiplexer on a substrate sequentially selects multiple monitoring lines connected to a monitoring pad. The following description primarily focuses on... Figure 24difference from the configuration example in . The multiplexer 137 is disposed between the monitoring pad 101 on the substrate 100 and the pixel circuit array 150 ( Figure 25 not shown). The multiplexer 137 includes a plurality of switches. Each switch turns on / off the electrical connection between the monitoring line and the monitoring pad.

[0144] The driver IC 134 includes a selection control circuit 327. The selection control circuit 327 controls the multiplexer 137. The selection control circuit 327 sequentially turns on selected monitoring lines from among the plurality of monitoring lines connected to each monitoring pad. In Figure 25 this example, the selection control circuit 327 is connected to selection control lines 116R, 116G and 116B via selection pads 103R, 103G and 103B, respectively.

[0145] The selection control lines 116R, 116G and 116B control the switches of the monitoring lines 111R, 111G and 111B connected to each monitoring pad in the multiplexer 137. In Figure 25 this example, the selection control line 116R is connected to all switches for the monitoring line 111R; the selection control line 116G is connected to all switches for the monitoring line 111G; and the selection control line 116B is connected to all switches for the monitoring line 111B.

[0146] The selection control circuit 327 sequentially selects the selection control lines 116R, 116G and 116B, and outputs a signal for turning on the associated switch to the selected selection control line, so as to sequentially connect the monitoring lines 111R, 111G and 111B of each monitoring pad (all monitoring pads) 101 to their corresponding monitoring line control circuits 326. Each monitoring line control circuit 326 controls three monitoring lines in a time-division manner.

[0147] This configuration example achieves a reduction in the number of monitoring pads and the number of monitoring control circuits, and additionally allows individual control of the monitoring lines. The number of monitoring lines 111 connected to one monitoring pad 101 may be 2 or more than 3.

[0148] Figure 26 there is shown a configuration example in which the multiplexer included in the driver IC 134 sequentially selects a plurality of monitoring lines each connected to one monitoring pad. The difference from the configuration example in Figure 25 is that the multiplexer 328 for selecting monitoring lines is integrated in the driver IC 134. Each monitoring pad 101 is connected to only one monitoring line. The selection control lines and selection pads on the substrate 100 shown in Figure 25 are omitted.

[0149] Multiplexer 328 changes the connection between the monitoring line control circuit and the monitoring pads. In this example, each monitoring line control circuit 326 is connected to three monitoring pads 101 and multiplexer 328. Each switch of multiplexer 328 toggles the connection / disconnection of each pair of monitoring pads and monitoring lines with the monitoring line control circuit 326.

[0150] The selection control circuit 327 sequentially selects three monitoring pads connected to each of the monitoring line control circuits 326. This configuration example reduces the number of monitoring line control circuits and also allows for individual control of the monitoring lines. The number of monitoring lines 111 connected to a monitoring pad 101 can be two or more than three.

[0151] As described above, embodiments of the present disclosure have been presented; however, the present disclosure is not limited to the foregoing embodiments. Those skilled in the art can readily modify, add to, or transform each element in the foregoing embodiments within the scope of this disclosure. A portion of the configuration of one embodiment may be replaced by the configuration of another embodiment, or the configuration of one embodiment may be incorporated into the configuration of another embodiment.

Claims

1. A display device, comprising: Pixel circuitry on a substrate; The data line is configured to transmit data signals for pixel circuitry on the substrate; Power cord; as well as An additional voltage supply line, different from the power line and the data line; The pixel circuit includes: The driving transistor is configured to control the amount of current supplied to the light-emitting element; A storage capacitor is deployed between the gate terminal of the driving transistor and the power line; A first switching transistor is deployed between the power line and the driving transistor; A second switching transistor is disposed between the source terminal of the driving transistor and the data line; and A third switching transistor is deployed between the source terminal of the driving transistor and the additional voltage supply line, and Wherein, after the period in which the data signal is provided in the frame, the third switching transistor provides the driving transistor from the additional voltage supply line a signal voltage that is different from the data signal, determined based on the video data provided to the display device, or as a constant voltage corresponding to the black level.

2. The display device according to claim 1, The pixel circuitry further includes a fourth switching transistor disposed between the gate terminal and the drain terminal of the driving transistor, and The third switching transistor provides a signal voltage via a driving transistor and the fourth switching transistor.

3. The display device according to claim 1, The pixel circuitry further includes a fifth switching transistor deployed between the drain terminal of the driving transistor and the light-emitting element.

4. The display device of claim 3, wherein the pixel circuit further comprises a sixth switching transistor disposed between the node of the second power line and the fifth switching transistor and the light-emitting element.

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