Pixel circuit, driving method of pixel circuit, and display panel

Abstract

The pixel circuit, the driving method of the pixel circuit and the display panel provided by the embodiments of the present application relate to the technical field of display. A second reset module is added in the pixel circuit, and the second reset module is configured to apply a third reset signal provided by a third reset signal line to a first end of the light-emitting module when all working levels of a second scan signal for controlling the first reset module are located in a display light-emitting area in a reset stage. In this way, the reset voltage of the first end of the light-emitting module can be stabilized, the reset voltage of the light-emitting module caused by the load difference of the second reset signal line in different time periods can be improved, and in turn, the multi-split display defect of the display panel can be improved, and the display quality of the display panel can be improved.

Description

Technical Field

[0001] This application relates to the field of display technology, and more specifically, to a pixel circuit, a driving method for the pixel circuit, and a display panel. Background Technology

[0002] In AMOLED (Active-Matrix Organic Light-Emitting Diode) display technology, pixels are driven and lit by pixel circuits. At low frequencies, the display panel suffers from multi-screen display defects, which seriously affects the user experience. Summary of the Invention

[0003] In order to overcome the technical problems mentioned in the above technical background, this application provides a pixel circuit, a pixel circuit driving method, and a display panel.

[0004] In a first aspect, this application provides a pixel circuit, the pixel circuit comprising: an initialization module, a data writing module, a storage module, a driving module, a threshold compensation module, a light emission control module, a light emission module, a first reset module, and a second reset module; The storage module is connected between the control terminal of the drive module and the first power signal line; The initialization module and the storage module are connected in series between the first reset signal line and the first power signal line; The threshold compensation module is connected between the control terminal of the drive module and the first terminal of the drive module. The data writing module is connected to the second end of the driving module, and the light-emitting module, the light-emitting control module and the driving module are connected in series between the first power signal line and the second power signal line; The first reset module is connected between the second reset signal line and the first end of the light-emitting module, and the second reset module is connected between the third reset signal line and the first end of the light-emitting module; The second reset module is configured to apply a third reset signal provided by the third reset signal line to the first end of the light-emitting module when the operating level of the second scan signal controlling the first reset module is all in the display light-emitting area during the reset phase. The third reset signal provided by the third reset signal line is the same as the second reset signal provided by the second reset signal line.

[0005] The pixel circuit described above is configured such that, during the reset phase, when the operating level of the second scan signal controlling the first reset module is all located in the display light-emitting area, the third reset signal provided by the third reset signal line is applied to the first end of the light-emitting module. This can stabilize the reset voltage of the first end of the light-emitting module, improve the difference in reset voltage of the light-emitting module caused by the load difference of the second reset signal line in different time periods, thereby improving the multi-screen display defects of the display panel and improving the display quality of the display panel.

[0006] In one possible embodiment of this application, the first reset module is further connected to the fourth reset signal line and the first or second end of the drive module; The frequency of the second scan signal used to control the first reset module is an integer multiple of the frequency of the first scan signal used to control the data writing module.

[0007] In one possible embodiment of this application, the second reset module includes a ninth transistor; The first terminal of the ninth transistor is connected to the first terminal of the light-emitting module, the second terminal of the ninth transistor is connected to the third reset signal line, and the control terminal of the ninth transistor is connected to the third signal scan line. The third signal scan line is configured to synchronize the third scan signal provided by the third signal scan line with the second scan signal when the working level of the second scan signal of the first reset module is entirely in the display light-emitting area, and to be in a non-working level state when the working level of the second scan signal is in the blanking area.

[0008] In one possible embodiment of this application, the threshold compensation module includes a third transistor; The second terminal of the third transistor is connected to the first terminal of the driving module, the first terminal of the third transistor is connected to the control terminal of the driving module, and the control terminal of the third transistor is connected to the fourth signal scan line. Preferably, the first reset signal line is connected to the second terminal of the third transistor via the initialization module, and the first power signal line is connected to the first terminal of the third transistor via the storage module.

[0009] In one possible embodiment of this application, the initialization module includes a fourth transistor; The first terminal of the fourth transistor is connected to the second terminal of the third transistor; The second terminal of the fourth transistor is connected to the first reset signal line, and the control terminal of the fourth transistor is connected to the fifth signal scan line.

[0010] In one possible embodiment of this application, the data writing module includes a second transistor, the driving module includes a first transistor, and the storage module includes a storage capacitor; The second terminal of the second transistor is connected to the data line, the first terminal of the second transistor is connected to the second terminal of the first transistor, and the control terminal of the second transistor is connected to the first scan signal line; The second terminal of the first transistor is connected to the first power signal line, the control terminal of the first transistor is connected to the second terminal of the storage capacitor, and the first terminal of the first transistor is connected to the light-emitting module. The first end of the storage capacitor is connected to the first power signal line, and the second end of the storage capacitor is connected to the first end of the third transistor.

[0011] In one possible embodiment of this application, the light-emitting control module includes a fifth transistor and a sixth transistor, the second terminal of the fifth transistor is connected to the first power signal line, and the first terminal of the fifth transistor is connected to the second terminal of the driving module; The second terminal of the sixth transistor is connected to the first terminal of the driving module, and the first terminal of the sixth transistor is connected to the first terminal of the light-emitting module; The control terminals of the fifth transistor and the sixth transistor are connected to the light-emitting control signal line; The second end of the light-emitting module is connected to the second power signal line, wherein the voltage signal provided by the first power signal line is greater than the voltage signal provided by the second power signal line.

[0012] In one possible embodiment of this application, the first reset module includes a seventh transistor and an eighth transistor; The second terminal of the seventh transistor is connected to the fourth reset signal line, and the first terminal of the seventh transistor is connected to the second terminal of the drive module; The second terminal of the eighth transistor is connected to the second reset signal line, and the first terminal of the eighth transistor is connected to the first terminal of the light-emitting module; The control terminals of the seventh transistor and the eighth transistor are connected to the second scan signal line.

[0013] A second aspect of this application also provides a driving method for a pixel circuit, applied to the pixel circuit in any possible embodiment of the first aspect, the method comprising: During the reset phase, when the operating level of the second scan signal of the first reset module is entirely within the display light-emitting area, the third reset signal provided by the third reset signal line is applied to the first end of the light-emitting module to reset the first end of the light-emitting module.

[0014] A third aspect of this application also provides a display panel, the display panel including the pixel circuitry provided in any possible embodiment of the first aspect.

[0015] Compared to existing technologies, the pixel circuit, pixel circuit driving method, and display panel provided in this application embodiment are improved by adding a second reset module to the pixel circuit. This second reset module is configured to apply a third reset signal provided by a third reset signal line to the first terminal of the light-emitting module during the reset phase when the operating level of the second scan signal controlling the first reset module is entirely within the display light-emitting area. This stabilizes the reset voltage at the first terminal of the light-emitting module, mitigating the differences in reset voltage caused by variations in the load of the second reset signal line across different time periods. This, in turn, improves the multi-screen display performance of the display panel and enhances its display quality. Attached Figure Description

[0016] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 A schematic diagram illustrating the high-frequency scanning signal SP2 and multi-screen display in related technologies is provided. Figure 2 This is one of the schematic diagrams of the pixel circuit provided in the embodiments of this application; Figure 3 This is a second schematic diagram of the pixel circuit provided in the embodiments of this application; Figure 4 This is the third schematic diagram of the pixel circuit provided in the embodiments of this application; Figure 5 This is the fourth schematic diagram of the pixel circuit provided in the embodiments of this application; Figure 6 This is the fifth schematic diagram of the pixel circuit provided in the embodiments of this application; Figure 7 This is the sixth schematic diagram of the pixel circuit provided in the embodiments of this application; Figure 8 This is a schematic diagram of a possible circuit structure for a pixel circuit provided in an embodiment of this application; Figure 9 A timing diagram showing the second scanning signal operating at all levels when it is located in the display light-emitting area, as provided in the embodiments of this application. Figure 10 A timing diagram showing the working level of the second scanning signal in an embodiment of this application when it is located in the display light-emitting area; Figure 11 This is a partial flowchart illustrating the driving method for the pixel circuit provided in an embodiment of this application. Detailed Implementation

[0018] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0019] Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0020] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0021] In the description of this application, it should be noted that the terms "upper," "lower," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship commonly used when the product is in use. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. In addition, the terms "first," "second," "third," "fourth," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0022] It should be noted that, where there is no conflict, different features in the embodiments of this application can be combined with each other.

[0023] In low-frequency display applications, due to the low screen refresh rate, the driving transistor DTFT in the pixel circuit is in a biased state for a long time. This will cause the output characteristics of the driving transistor to deviate, and in low-frequency displays, there is a brightness difference between the hold frame and the write frame, which can lead to screen flickering.

[0024] To address the aforementioned problems, an improved pixel circuit is provided in the related art. For example, an 8T1C pixel circuit is formed by adding a transistor T8 to the original 7T1C pixel circuit. Specifically, by adding a transistor T8 to perform high-frequency reset of the source or drain of the driving transistor, the low-frequency flicker phenomenon is improved.

[0025] However, in practical applications, the newly added transistor T8 will also initialize the first terminal of the light-emitting module (e.g., the anode of the light-emitting diode). Since transistor T8 is controlled by the high-frequency scanning signal SP2, please refer to... Figure 1 When the timing of the high-frequency scanning signal SP2 scans the pixel row in the blanking area of ​​the display panel, the load of the gate drive circuit GIP and the reset signal line of the corresponding pixel row will decrease. At this time, the reset signal line will be more fully initialized when the first end of the light-emitting module is initialized due to the reduced load. This will result in a dark Mura defect area appearing in the vicinity of the pixel row controlled by the high-frequency scanning signal, thus dividing the entire display panel into multiple different display areas, i.e., split-screen display defect.

[0026] After analyzing the above problems, the inventors discovered that the main cause of these technical issues lies in the varying reset voltage applied to the first terminal of the light-emitting module at different times. Specifically, when the operating level (e.g., low level) of the high-frequency scan signal SP2 is entirely within the display light-emitting area (V-active area), the reset signal provided by the reset signal line is pulled low due to the large load. Conversely, when the operating level of the high-frequency scan signal SP2 is partially within the blanking area (V-blank area), the reset signal provided by the reset signal line changes little due to the small load. This results in an unstable reset signal on the reset signal line at different times. When the reset signal on the reset signal line is used to set the first terminal of the light-emitting module, the varying set voltage leads to different initialization levels of the light-emitting module, resulting in poor display across multiple screens.

[0027] To reduce the voltage differences in initializing the light-emitting module at different times, the inventors have innovatively designed the following technical solution. The specific implementation of this application will be described in detail below with reference to the accompanying drawings.

[0028] Please refer to Figure 2 , Figure 2 A block diagram of the pixel circuit provided in an embodiment of this application is shown. The pixel circuit 10 may include an initialization module 110, a data writing module 120, a storage module 130, a driving module 140, a threshold compensation module 150, a light emission control module 160, a light emission module 170, a first reset module 180, and a second reset module 190.

[0029] The storage module 130 is connected between the control terminal of the drive module 140 and the first power signal line ELVDD. The initialization module 110 and the storage module 130 are connected in series between the first reset signal line VREFN1 and the first power signal line ELVDD.

[0030] The threshold compensation module 150 is connected between the control terminal and the first terminal of the drive module 140. The data writing module 120 is connected to the second terminal of the drive module 140. The light-emitting module 170, the light-emitting control module 160, and the drive module 140 are connected in series between the first power signal line ELVDD and the second power signal line ELVSS. Optionally, one of the voltages on the first power signal line ELVDD and the second power signal line ELVSS is a high voltage and the other is a low voltage.

[0031] The first reset module 180 is connected between the second reset signal line VREFN2 and the first end of the light-emitting module 170, and the second reset module 190 is connected between the third reset signal line VREFN3 and the first end of the light-emitting module 170.

[0032] In this embodiment, the second reset module 190 is configured to apply the third reset signal provided by the third reset signal line VREFN3 to the first end of the light-emitting module 170 when the working level of the second scan signal controlling the first reset module 180 is all in the display light-emitting area during the reset phase. The third reset signal provided by the third reset signal line VREFN3 is the same as the second reset signal provided by the second reset signal line VREFN2.

[0033] In the pixel circuit described above, the second reset module 190 is configured to apply the third reset signal provided by the third reset signal line VREFN3 to the first terminal of the light-emitting module 170 when the working level of the second scan signal controlling the first reset module 180 is all in the display light-emitting area during the reset phase. This can stabilize the reset voltage of the first terminal of the light-emitting module 170, improve the different reset voltage of the light-emitting module caused by the load difference of the second reset signal line VREFN2 in different time periods, and thus improve the multi-screen display failure of the display panel and improve the display quality of the display panel.

[0034] Further, please refer to Figure 3 In this embodiment, the first reset module 180 is also connected to the fourth reset signal line VREFN4 and the second end of the drive module 140, used to control the frequency of the second scan signal of the first reset module 180 to be an integer multiple of the frequency of the first scan signal used to control the data writing module 120. This design can improve the problem of the drive module 140 being in a biased state for a long time, optimize the output characteristic offset of the drive module 140, and improve the flickering problem of the display panel when displaying at low frequencies.

[0035] Further, please refer to Figure 4 In this embodiment, the second reset module 190 includes a ninth transistor T9. The first terminal of the ninth transistor T9 is connected to the first terminal of the light-emitting module 170, and the second terminal of the ninth transistor T9 is connected to the third reset signal line VREFN3. The control terminal of the ninth transistor T9 is connected to the third signal scan line SP3. The third signal scan line SP3 is configured to synchronize the third scan signal provided by the third signal scan line SP3 with the second scan signal when the working level of the second scan signal controlling the first reset module 180 is entirely in the display light-emitting area, and to be in a non-working level state when the working level of the second scan signal is in the blanking area.

[0036] In this embodiment, please refer to Figure 5 The threshold compensation module 150 includes a third transistor T3. The second end of the third transistor T3 is connected to the first end of the driving module 140. The first end of the third transistor T3 is connected to the control end of the driving module 140. The control end of the third transistor T3 is connected to the fourth signal scan line SP4.

[0037] Preferably, the first reset signal line VREFN1 is connected to the second terminal of the third transistor T3 via the initialization module 110, and the first power signal line ELVDD is connected to the first terminal of the third transistor T3 via the storage module 130.

[0038] Please refer to Figure 6 The initialization module 110 includes a fourth transistor T4. The first end of the fourth transistor T4 is connected to the second end of the third transistor T3. The second end of the fourth transistor T4 is connected to the first reset signal line VREFN1. The control end of the fourth transistor T4 is connected to the fifth signal scan line SP5.

[0039] Further, please refer to Figure 7 The data writing module 120 includes a second transistor T2, the driving module 140 includes a first transistor T1, and the storage module 130 includes a storage capacitor C.

[0040] The second terminal of the second transistor T2 is connected to the data line Vdata, the first terminal of the second transistor T2 is connected to the second terminal of the first transistor T1, and the control terminal of the second transistor T2 is connected to the first scan signal line SP1.

[0041] The second terminal of the first transistor T1 is connected to the first power signal line ELVDD, the control terminal of the first transistor T1 is connected to the second terminal of the storage capacitor C, and the first terminal of the first transistor T1 is connected to the light-emitting module 170.

[0042] The first terminal of the storage capacitor C is connected to the first power signal line ELVDD, and the second terminal of the storage capacitor C is connected to the first terminal of the third transistor T3.

[0043] Further, please refer to Figure 8 The light-emitting control module 160 includes a fifth transistor T5 and a sixth transistor T6. The second end of the fifth transistor T5 is connected to the first power signal line ELVDD, and the first end of the fifth transistor T5 is connected to the second end of the driving module 140.

[0044] The second terminal of the sixth transistor T6 is connected to the first terminal of the driving module 140, and the first terminal of the sixth transistor T6 is connected to the first terminal of the light-emitting module 170.

[0045] The control terminals of the fifth transistor T5 and the sixth transistor T6 are connected to the light-emitting control signal line EM.

[0046] The second end of the light-emitting module 170 is connected to the second power signal line ELVSS. For example, the light-emitting module 170 is a light-emitting diode D. The first end of the light-emitting module 170 corresponds to the anode of the light-emitting diode D, and the second end of the light-emitting module 170 corresponds to the cathode of the light-emitting diode D. The voltage signal provided by the first power signal line ELVDD is greater than the voltage signal provided by the second power signal line ELVSS.

[0047] In this embodiment, please refer again. Figure 8 The first reset module 180 includes a seventh transistor T7 and an eighth transistor T8. The second end of the seventh transistor T7 is connected to the fourth reset signal line VREFN4, and the first end of the seventh transistor T7 is connected to the second end of the drive module 140.

[0048] The second terminal of the eighth transistor T8 is connected to the second reset signal line VREFN2, and the first terminal of the eighth transistor T8 is connected to the first terminal of the light-emitting module 170.

[0049] The control terminals of the seventh transistor T7 and the eighth transistor T8 are connected to the second scan signal line SP2.

[0050] In this embodiment, assuming the refresh rate of the display panel is f, the scanning frequency of the scanning signals provided by the first scanning signal line SP1, the fourth scanning signal line SP4 and the fifth scanning signal line SP5 is f, and the scanning frequency of the scanning signals provided by the second scanning signal line SP2 and the third scanning signal line SP3 is N*f, where N is a positive integer.

[0051] In the above circuit structure, transistors T1 to T9 can be transistors of the same channel type or transistors of different channel types. Preferably, transistors T1, T2, and T5 to T9 are transistors of one channel type, and transistors T3 and T4 are transistors of another channel type. For example, when transistors T1, T2, and T5 to T9 are PMOS transistors, the control terminal corresponds to the gate of the PMOS transistor, the first terminal corresponds to the drain of the PMOS transistor, and the second terminal corresponds to the source of the PMOS transistor. When transistors T3 and T4 are NMOS transistors, the control terminal corresponds to the gate of the NMOS transistor, the first terminal corresponds to the source of the NMOS transistor, and the second terminal corresponds to the drain of the NMOS transistor.

[0052] The following is based on Figure 8 Taking transistors T1, T2, and T5-T9 as examples, which use PMOS transistors, and transistors T3 and T4 as examples, and combining them with... Figure 9 The signal timing diagram shown illustrates the working principle of the pixel circuit when the operating level of the second scan signal SP2 is entirely within the display light-emitting area in this embodiment.

[0053] During the first time period t1 (data writing and compensation phase), the second scan signal on the second scan signal line SP2 is at a working level, for example, low; the third scan signal on the third scan signal line SP3 is at a working level, for example, low; the third scan signal on the fourth scan signal line SP4 is at a working level, for example, high; the first scan signal on the first scan signal line SP1 is at a non-working level, for example, high; the fifth scan signal on the fifth scan signal line SP5 is at a non-working level, for example, high; and the light emission control signal on the light emission control signal line EM is at a non-working level, for example, high. At this time, the data writing module 120, the driving module 140, and the threshold compensation module 150 are turned on, while the initialization module 110, the light emission control module 160, the light emission module 170, the first reset module 180, and the second reset module 190 are turned off. The data signal provided by the data signal line Vdata acts on the second terminal of the driving module 140. Specifically, the second transistor T2 and the third transistor T3 are turned on. Since the third transistor T3 connects the gate and drain of the first transistor T1 (driving transistor), the gate and drain of the first transistor T1 have the same potential. Under the action of the data signal acting on the source of the first transistor T1, the driving transistor T1 is turned on. The data signal provided by the data signal line Vdata and the threshold voltage Vth of the first transistor T1 are written to the end of the storage capacitor C connected to the gate of the first transistor T1 (point A in the figure).

[0054] During the second time period t2, the scan signals of the first scan signal line SP1, the second scan signal line SP2, the third scan signal line SP3, the fourth scan signal line SP4, and the fifth scan signal line SP5 are all at a non-operating level, and the light emission control signal on the light emission control signal line EM is also at a non-operating level. At this time, the data writing module 120 and the threshold compensation module 150 are turned off. Specifically, the second transistor T2 and the third transistor T3 are both turned off, and the data signal provided by the data signal line Vdata stops writing.

[0055] During the third time period t3 (reset phase), the scan signals of the first scan signal line SP1, the fourth scan signal line SP4, and the fifth scan signal line SP5 are all at non-operating levels, while the second scan signal line SP2 and the third scan signal line SP3 are at operating levels, and the light emission control signal on the light emission control signal line EM is at a non-operating level. At this time, the first reset module 180 and the second reset module 190 are turned on, while the initialization module 110, the data writing module 120, the drive module 140, the threshold compensation module 150, the light emission control module 160, and the light emission module 170 are turned off. Specifically, the seventh transistor T7, the eighth transistor T8, and the ninth transistor T9 are turned on, while the other transistors are turned off. The reset signal provided by the fourth reset signal line VREFN4 resets the source of the first transistor T1. The reset signals provided by the second reset signal line VREFN2 and the third reset signal line VREFN3 simultaneously reset the first terminal of the light-emitting module 170. In this way, when the operating level of the second scan signal line SP2 is all in the display light-emitting area, the problem of insufficient reset of the first terminal of the light-emitting module 170 caused by the decrease of the reset signal due to the excessive load connected to the second reset signal line VREFN2 can be alleviated.

[0056] During the fourth time period t4 (light emission stage), the light emission control signal on the light emission control signal line EM is at the working level, while the scan signals of the first scan signal line SP1, the second scan signal line SP2, the third scan signal line SP3, the fourth scan signal line SP4, and the fifth scan signal line SP5 are all at the non-working level. At this time, the light emission control module 160, the light emission module 170, and the drive module 140 are turned on, while other modules are turned off. The drive module 140 generates a drive current based on the voltage difference between its control terminal and the second terminal, driving the light emission module 170 to emit light. Specifically, the fifth transistor T5, the sixth transistor T6, and the first transistor T1 are turned on, while other transistors are turned off. The first transistor T1 generates a drive current based on the gate-source voltage difference, which flows through the turned-on sixth transistor T6 to the light emission module 170. At this time, the light emission module 170 is lit, realizing light emission. For example, the light emission module 170 is a light-emitting diode D, and the drive circuit flows from the anode of the light-emitting diode D to light up the light-emitting diode D.

[0057] It is understood that the above only illustrates the circuit timing diagram and the corresponding pixel circuit working principle when the operating level of the second scan signal SP2 is entirely within the light-emitting display area. The circuit timing diagram for when a portion of the operating level of the second scan signal SP2 is within the blanking area can be seen as follows: Figure 10 As shown, with Figure 9 In contrast, since the load corresponding to the second reset signal line VREFN2 decreases when the operating level of the second scan signal SP2 is in the blanking region, the reset signal provided by the second reset signal line VREFN2 will not change much. Therefore, during the reset phase, only the reset signal provided by the second reset signal line VREFN2 needs to be used to initialize the first terminal of the light-emitting module 170. In other words, when the operating level of the second scan signal SP2 is in the blanking region, the scan signal of the third scan signal SP3 can remain in a non-operating level state. Specifically, the working principle of the pixel circuit in the blanking region is the same as the working principle of the pixel circuit in the light-emitting display area described above, and will not be repeated here.

[0058] Based on the same inventive concept, please refer to Figure 11 This application also provides a pixel circuit driving method, which can be used to drive the pixel circuits described in the previous embodiments. The pixel circuit driving method provided in this embodiment includes: Step S11: During the reset phase, when the operating level of the second scan signal SP2 controlling the first reset module 180 is entirely within the display light-emitting area, the third reset signal provided by the third reset signal line VREFN3 is applied to the first end of the light-emitting module 170 to reset the first end of the light-emitting module 170.

[0059] The third reset signal provided by the third reset signal line VREFN3 is applied to the first terminal of the light-emitting module 170. This can stabilize the reset voltage of the first terminal of the light-emitting module 170, improve the different reset voltage of the light-emitting module 170 caused by the load difference of the second reset signal line VREFN2 in different time periods, and thus improve the multi-screen display failure of the display panel and improve the display quality of the display panel.

[0060] Optionally, during the reset phase, the first reset module 180 and the second reset module 190 are turned on, while the initialization module 110, data writing module 120, drive module 140, threshold compensation module 150, light emission control module 160, and light emission module 170 are turned off. The reset signal provided by the fourth reset signal line VREFN4 resets the second terminal of the drive module 140, and the reset signals provided by the second reset signal line VREFN2 and the third reset signal line VREFN3 simultaneously reset the first terminal of the light emission module 170.

[0061] Optionally, the driving method for the pixel circuit further includes: during the data writing and compensation phase, controlling the data writing module 120, the driving module 140, and the threshold compensation module 150 to be turned on. The data signal provided by the data signal line Vdata acts on the second terminal of the driving module 140, turning on the driving module. The data signal provided by the data signal line Vdata and the threshold voltage Vth of the driving module are written to the end of the storage capacitor C connected to the control terminal of the driving module (point A in the figure), realizing data signal writing and threshold voltage compensation.

[0062] Optionally, the driving method for the pixel circuit further includes: during the light-emitting stage, controlling the light-emitting control module 160 and the light-emitting module 170 to be turned on. The driving module 140 generates a driving current based on the voltage difference between its control terminal and the second terminal, driving the light-emitting module 170 to emit light.

[0063] Based on the same inventive concept, this application also provides a display panel, which includes the pixel circuit described in the previous embodiments. Using the pixel circuit can improve the display uniformity of the display panel and enhance the display effect.

[0064] This application provides a pixel circuit, a driving method for the pixel circuit, and a display panel. A second reset module is added to the pixel circuit. This second reset module is configured to apply a third reset signal provided by a third reset signal line to the first terminal of the light-emitting module during the reset phase, when the operating level of the second scan signal controlling the first reset module is entirely within the display light-emitting area. This stabilizes the reset voltage at the first terminal of the light-emitting module, improving the reduction of different reset voltages caused by load differences in the second reset signal line across different time periods. This, in turn, improves the multi-screen display performance of the display panel and enhances its display quality.

[0065] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A pixel circuit, characterized in that, The pixel circuit includes: an initialization module, a data writing module, a storage module, a driving module, a threshold compensation module, a light emission control module, a light emission module, a first reset module, and a second reset module; The storage module is connected between the control terminal of the drive module and the first power signal line; The initialization module and the storage module are connected in series between the first reset signal line and the first power signal line; The threshold compensation module is connected between the control terminal of the drive module and the first terminal of the drive module. The data writing module is connected to the second end of the driving module, and the light-emitting module, the light-emitting control module and the driving module are connected in series between the first power signal line and the second power signal line; The first reset module is connected between the second reset signal line and the first end of the light-emitting module, and the second reset module is connected between the third reset signal line and the first end of the light-emitting module; The second reset module is configured to apply a third reset signal provided by the third reset signal line to the first end of the light-emitting module when the working level of the second scan signal controlling the first reset module is all in the display light-emitting area during the reset phase. The third reset signal provided by the third reset signal line is the same as the second reset signal provided by the second reset signal line. The second reset module includes a ninth transistor; The first terminal of the ninth transistor is connected to the first terminal of the light-emitting module, the second terminal of the ninth transistor is connected to the third reset signal line, and the control terminal of the ninth transistor is connected to the third signal scan line. The third signal scan line is configured to synchronize the third scan signal provided by the third signal scan line with the second scan signal when the working level of the second scan signal of the first reset module is entirely in the display light-emitting area, and to be in a non-working level state when the working level of the second scan signal is in the blanking area.

2. The pixel circuit as described in claim 1, characterized in that, The first reset module is also connected to the fourth reset signal line and the first or second end of the drive module; The frequency of the second scan signal used to control the first reset module is an integer multiple of the frequency of the first scan signal used to control the data writing module.

3. The pixel circuit as described in claim 1, characterized in that, The threshold compensation module includes a third transistor; The second terminal of the third transistor is connected to the first terminal of the driving module, the first terminal of the third transistor is connected to the control terminal of the driving module, and the control terminal of the third transistor is connected to the fourth signal scan line.

4. The pixel circuit as described in claim 3, characterized in that, The first reset signal line is connected to the second terminal of the third transistor via the initialization module, and the first power signal line is connected to the first terminal of the third transistor via the storage module.

5. The pixel circuit as described in claim 4, characterized in that, The initialization module includes a fourth transistor; The first terminal of the fourth transistor is connected to the second terminal of the third transistor; The second terminal of the fourth transistor is connected to the first reset signal line, and the control terminal of the fourth transistor is connected to the fifth signal scan line.

6. The pixel circuit as described in claim 5, characterized in that, The data writing module includes a second transistor, the driving module includes a first transistor, and the storage module includes a storage capacitor. The second terminal of the second transistor is connected to the data line, the first terminal of the second transistor is connected to the second terminal of the first transistor, and the control terminal of the second transistor is connected to the first scan signal line; The second terminal of the first transistor is connected to the first power signal line, the control terminal of the first transistor is connected to the second terminal of the storage capacitor, and the first terminal of the first transistor is connected to the light-emitting module. The first end of the storage capacitor is connected to the first power signal line, and the second end of the storage capacitor is connected to the first end of the third transistor.

7. The pixel circuit as described in claim 1, characterized in that, The light-emitting control module includes a fifth transistor and a sixth transistor. The second end of the fifth transistor is connected to the first power signal line, and the first end of the fifth transistor is connected to the second end of the driving module. The second terminal of the sixth transistor is connected to the first terminal of the driving module, and the first terminal of the sixth transistor is connected to the first terminal of the light-emitting module; The control terminals of the fifth transistor and the sixth transistor are connected to the light-emitting control signal line; The second end of the light-emitting module is connected to the second power signal line, wherein the voltage signal provided by the first power signal line is greater than the voltage signal provided by the second power signal line.

8. The pixel circuit as described in claim 2, characterized in that, The first reset module includes a seventh transistor and an eighth transistor; The second terminal of the seventh transistor is connected to the fourth reset signal line, and the first terminal of the seventh transistor is connected to the second terminal of the drive module; The second terminal of the eighth transistor is connected to the second reset signal line, and the first terminal of the eighth transistor is connected to the first terminal of the light-emitting module; The control terminals of the seventh transistor and the eighth transistor are connected to the second scan signal line.

9. A driving method for a pixel circuit, characterized in that, Applied to the pixel circuit according to any one of claims 1-8, the method comprises: During the reset phase, when the operating level of the second scan signal of the first reset module is entirely within the display light-emitting area, the third reset signal provided by the third reset signal line is applied to the first end of the light-emitting module to reset the first end of the light-emitting module.

10. A display panel, characterized in that, Includes the pixel circuit described in any one of claims 1-8.

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