Semiconductor memory device

Abstract

Embodiments of the present application relate to a semiconductor memory device. The memory of the embodiments has a plurality of first cell layers including memory cells arranged in a first surface and a second cell layer including dummy cells arranged in a second surface. First wiring is connected to the memory cells arranged in a first direction in the first surface. Second wiring is connected to the dummy cells arranged in the first direction in the second surface. Third wiring is connected to the memory cells and the dummy cells arranged in a second direction in which the first and second cell layers are stacked. Fourth wiring is connected to the third wiring arranged in a third direction intersecting the first and second directions. In data readout, a first voltage is applied to a selected first wiring connected to a selected cell and a readout voltage is passed to a selected fourth wiring connected to the selected cell. A reference voltage is passed to a non-selected fourth wiring other than the selected fourth wiring. A second voltage is applied to a selected second wiring in which the second cell is provided between the non-selected fourth wiring.

Description

[0001] [Citation of relevant applications]

[0002] This application asserts priority based on the priority of a prior Japanese patent application No. 2022-099933 filed on June 21, 2022, the entire contents of which are incorporated herein by reference. Technical Field

[0003] Embodiments of the present invention relate to a semiconductor memory device. Background Technology

[0004] The industry has developed DRAM (Dynamic Random Access Memory), which is formed by arranging memory cells three-dimensionally. In DRAM, logic detects data by comparing the voltage corresponding to the data from the memory cell with a reference signal.

[0005] In a three-dimensional storage cell array, it is sometimes difficult to detect data from the storage cells. Summary of the Invention

[0006] One embodiment provides a semiconductor storage device capable of accurately detecting data from a three-dimensional memory cell array.

[0007] The semiconductor memory device of this embodiment includes: a plurality of first cell layers, each containing a plurality of first cells arranged in a first surface and used as memory cells; and at least one second cell layer, each containing a plurality of second cells arranged in a second surface and not used as memory cells, and stacked on the first cell layers. A plurality of first wirings are connected to the plurality of first cells arranged in a first direction in the first surface. A plurality of second wirings are connected to the plurality of second cells arranged in the first direction in the second surface. A plurality of third wirings are connected to the first cells and second cells arranged in a second direction on which the first and second cell layers are stacked. A plurality of fourth wirings are connected to the plurality of third wirings arranged in a third direction intersecting the first and second directions. When reading data from a selection cell selected from the plurality of first cells, the control circuit applies a first voltage to a selection first wiring connected to the selection cell among the plurality of first wirings, and transmits a readout voltage corresponding to the data to a selection fourth wiring connected to the selection cell among the plurality of fourth wirings. A reference voltage is applied to the non-selected fourth wiring (other than the selected fourth wiring) among the multiple fourth wirings to serve as the detection reference for the readout voltage. A second voltage is applied to the selected second wiring (which has a second unit positioned between it and the non-selected fourth wiring) among the multiple second wirings.

[0008] According to the aforementioned configuration, a semiconductor storage device capable of accurately detecting data from a three-dimensional memory cell array can be provided. Attached Figure Description

[0009] Figure 1 This is a schematic perspective view showing an example of the configuration of the semiconductor memory device according to the first embodiment.

[0010] Figure 2 It is a schematic three-dimensional diagram representing a bit line and its surrounding structure.

[0011] Figure 3 This is a schematic top view showing an example of the configuration of a memory cell array.

[0012] Figure 4 This is a schematic side view showing an example of the configuration of a memory cell array.

[0013] Figure 5 This is a schematic front view showing an example of the configuration of a memory cell array.

[0014] Figure 6 It is a graph representing the voltage of the select word line and select bit line during the readout operation.

[0015] Figure 7 It is a table that shows the relationship between the data selected in the memory cell and the voltage of the bit line, etc.

[0016] Figure 8 It is a top-down view showing the state of each layer of the memory cell array during data readout.

[0017] Figure 9 It is a top-down view showing the state of each layer of the memory cell array during data readout.

[0018] Figure 10 It is a top-down view showing the state of each layer of the memory cell array during data readout.

[0019] Figure 11 This is a circuit diagram showing an example of the configuration of a word line driver.

[0020] Figure 12 It is a graph showing the relationship between the select word voltage and the dummy voltage.

[0021] Figure 13 This is a schematic top view showing the state of the dummy unit layer during the data readout operation of the second embodiment.

[0022] Figure 14 This is a schematic top view showing the state of the dummy unit layer during the data readout operation of the third embodiment.

[0023] Figure 15 This is a schematic top view showing the state of the selected storage cell layer during the data readout operation in the third embodiment.

[0024] Figure 16This is a schematic top view showing the state of the dummy unit layer during the data readout operation of the third embodiment.

[0025] Figure 17 This is a circuit diagram illustrating a configuration example of the word line driver according to the third embodiment.

[0026] Figure 18 This is a schematic diagram showing an example of the configuration of the dummy unit layer in the fourth embodiment.

[0027] Figure 19 This is a diagram illustrating a configuration example of the memory cell array in the fifth embodiment.

[0028] Figure 20 This is a schematic top view showing a configuration example of the memory cell array in the sixth embodiment.

[0029] Figure 21 This is a schematic side view showing a configuration example of the memory cell array in the sixth embodiment.

[0030] Figure 22 This is a schematic perspective view showing an example of the configuration of the semiconductor memory device according to the seventh embodiment.

[0031] Figure 23 This is a schematic top view showing a configuration example of the memory cell array in the seventh embodiment.

[0032] Figure 24 This is a schematic side view showing a configuration example of the memory cell array in the seventh embodiment.

[0033] Figure 25 This is a schematic front view showing an example of the configuration of a memory cell array.

[0034] Figure 26 This is a block diagram illustrating an example of the configuration of an array of multiple memory cells. Detailed Implementation

[0035] Hereinafter, embodiments will be described with reference to the accompanying drawings. The present invention is not limited to these embodiments.

[0036] Furthermore, in this specification and the accompanying drawings, elements that are identical to those described in the drawings are labeled with the same symbols, and their detailed descriptions are appropriately omitted.

[0037] (First Embodiment)

[0038] Figure 1This is a schematic perspective view showing a configuration example of the semiconductor memory device 1 according to the first embodiment. The semiconductor memory device 1 of this embodiment is, for example, a DRAM having a three-dimensional memory cell array MCA formed by arranging memory cells MC and dummy cells DMC in a three-dimensional (solid) manner. The memory cells MC are used as memory cells to store one bit of data or multiple bits of data. The dummy cells DMC have the same configuration as the memory cells MC, but do not store data and are not used as memory cells.

[0039] Multiple memory cells (MCs) are arranged in a planar matrix within the XY plane, forming a memory cell layer (LYR). Furthermore, multiple memory cell layers (LYRs) are stacked in the Z direction. In the memory cell array (MCA), multiple memory cell layers (LYRs) are stacked approximately parallel to each other. Thus, multiple memory cells (MCs) are arranged three-dimensionally.

[0040] Multiple dummy cells (DMCs) are also arranged in a planar matrix within the XY plane, forming a single dummy cell layer (DLYR). The DLYR is stacked in the Z-direction above, below, or between the stacked LYRs in the memory cell array (MCA). The DLYRs are stacked approximately parallel to the LYRs. At least one DLYR is required relative to a single memory cell array (MCA). In the first embodiment, a single DLYR is provided within the memory cell array (MCA).

[0041] The semiconductor memory device 1 of this embodiment includes a memory cell array MCA, multiple word lines WL, multiple dummy word lines DWL, multiple bit lines VBL, multiple global bit lines GBL, multiple bit line selection transistors Tbls, multiple memory cell layer selection transistors Tlys and bTlys, and multiple dummy cell layer selection transistors DTlys and bDTlys.

[0042] Multiple word lines WL extend in the X-direction within the plane of the memory cell layer LYR and connect to multiple memory cells MC arranged in the X-direction. Within the memory cell layer LYR, the multiple word lines WL are arranged in the Y-direction. One end of each word line WL is connected to a word line driver (not shown) via a memory cell layer select transistor Tlys. The other end of each word line WL is connected to a non-selection voltage source VUW via a memory cell layer select transistor bTlys. The word lines WL are identically configured in each memory cell layer LYR.

[0043] Multiple dummy word lines (DWLs) extend in the X-direction within the plane of the dummy cell layer (DLYR) and are connected to multiple dummy cells (DMCs) arranged in the X-direction. Within the dummy cell layer (DLYR), the multiple dummy word lines (DWLs) are arranged in the Y-direction. One end of each dummy word line (DWL) is connected to a dummy word line driver (not shown) via a dummy cell layer select transistor (DTlys). The other end of each dummy word line (DWL) is connected to a non-selection voltage source (VUW) via a dummy cell layer select transistor (bDTlys).

[0044] The layer select word line MWL is connected to the gate of the memory cell layer select transistor Tlys, and turns Tlys on when the memory cell layer LYR is selected. The layer select word line bMWL is connected to the gate of the memory cell layer select transistor bTlys, and turns bTlys off when the memory cell layer LYR is selected. The layer select word line bMWL transmits an inverted (reverse logic) signal to the layer select word line MWL. Therefore, when one of the memory cell layer select transistors Tlys and bTlys is on, the other is off.

[0045] The dummy layer select word line DMWL is connected to the gate of the dummy cell layer select transistor DTlys, and DTlys is turned on when the dummy memory cell layer DLYR is selected. The dummy layer select word line bDMWL is connected to the gate of the dummy cell layer select transistor bDTlys, and bDTlys is turned off when the dummy memory cell layer DLYR is selected. The dummy layer select word line bDMWL transmits an inverse (inverse logic) signal to the dummy layer select word line DMWL. Therefore, when one of the dummy cell layer select transistors DTlys and bDTlys is on, the other is off. Furthermore, in this embodiment, since there is only one dummy cell layer DLYR, it is always in the selected state during the read operation. Hereinafter, the memory cell layer select transistors bTlys, bTlys, and dummy cell layer select transistors DTlys and bDTlys will sometimes be simply referred to as layer select transistors.

[0046] Multiple bit lines VBL extend in the stacking direction (Z direction) of multiple memory cell layers LYR and at least one dummy cell layer DLYR, and are connected to multiple memory cells MC and at least one dummy cell DMC arranged in the Z direction. The multiple memory cells MC and at least one dummy cell DMC arranged in the Z direction are connected to the common bit lines VBL, thus forming a memory string. When viewed from above in the Z direction, the multiple bit lines VBL are arranged in a matrix-like two-dimensional arrangement in the XY direction, corresponding to the memory cells MC within the memory cell layers LYR. One end of each bit line VBL is connected to the global bit line GBL via bit line selection transistors Tbls.

[0047] Multiple global bit lines (GBLs) extend in the Y-plane and are connected to one end of multiple bit lines (VBLs) arranged in the Y-direction via bit line selection transistors (Tbls). The multiple bit lines (VBLs) arranged in the Y-direction are connected to a common global bit line (GBL). The multiple global bit lines (GBLs) are arranged in the X-direction. One end of each global bit line (GBL) is connected to a sense amplifier (SA). The global bit lines (GBLs) are commonly configured relative to multiple memory cell layers (LYRs) and dummy cell layers (DLYRs) within the memory cell array (MCA).

[0048] The sense amplifier SA receives the readout voltage corresponding to the data stored in the selected memory cell MC via the selected global bit line GBL, and receives the reference voltage corresponding to the reference signal from the unselected global bit line GBL. Furthermore, the sense amplifier SA detects the data logic by amplifying the voltage difference between the readout voltage and the reference voltage.

[0049] Figure 2 This is a schematic three-dimensional diagram showing a bit line VBL and its surroundings. Each memory cell MC includes a cell transistor Tmc and a cell capacitor Cmc. The gate of the cell transistor Tmc is connected to any word line WL. One of the source and drain of the cell transistor Tmc is connected to the bit line VBL, and the other of the source and drain is connected to one end of the cell capacitor Cmc. The cell capacitor Cmc is connected between the other of the source and drain of the cell transistor Tmc and a reference voltage source (e.g., ground or the intermediate voltage VDD / 2 described below).

[0050] The dummy cell DMC can have a configuration substantially the same as the memory cell MC. Therefore, the dummy cell DMC includes a dummy cell transistor DTmc and a dummy cell capacitor DCmc. The configurations of the dummy cell transistor DTmc and the dummy cell capacitor DCmc can be the same as those of the cell transistor Tmc and the cell capacitor Cmc, respectively. For example, the gate dimensions (gate width and gate length) of the dummy cell transistor DTmc can be approximately the same as the gate dimensions of the cell transistor Tmc. The electrode dimensions of the dummy cell capacitor DCmc can also be approximately the same as the electrode dimensions of the cell capacitor Cmc. The gate of the dummy cell transistor DTmc is connected to any dummy word line DWL. One of the source and drain of the dummy cell transistor DTmc is connected to the bit line VBL, and the other of the source and drain is connected to one end of the dummy cell capacitor DCmc. The dummy cell capacitor DCmc is connected between the other of the source and drain of the dummy cell transistor DTmc and a reference voltage source (e.g., ground or the intermediate voltage VDD / 2 described below).

[0051] The memory cell MC is able to store logic data by storing charge in the cell capacitor Cmc via the cell transistor Tmc, or releasing charge from the cell capacitor Cmc.

[0052] Figure 3 This is a schematic top view showing an example of the configuration of a memory cell array (MCA). Figure 3 This indicates a top view from the Z direction. In this embodiment, bit lines VBL are provided at the intersections of word lines WL and global bit lines GBL, but are not provided at all intersections; they are configured intermittently. For example, bit lines VBL are configured at every other intersection along word lines WL in the X direction. Additionally, two bit lines VBL are configured at every other intersection along global bit lines GBL in the Y direction. Memory cell layer selection transistors Tlys and bTlys are connected to both ends of word line WL.

[0053] The bit line VBL runs through the multiple stacked memory cell layers LYR and dummy cell layers DLYR in the Z direction and is shared by them. Therefore, when viewed from the Z direction, the configuration of the bit line VBL is the same in the multiple stacked memory cell layers LYR and dummy cell layers DLYR.

[0054] By intermittently configuring the bit line VBL at the intersection of the word line WL and the global bit line GBL, a reference signal can be generated in the memory cell array MCA, which is the same as the select memory cell MC. Regarding this bit line configuration (folded bit line configuration), the reference... Figure 8 This will be explained in more detail later.

[0055] Figure 4This is a schematic side view showing an example of the configuration of a memory cell array (MCA). Figure 4 This indicates the configuration as viewed from the X direction. In this embodiment, for example, two bit lines VBL are arranged at each of the two intersection positions along the global bit line GBL in the Y direction. The bit lines VBL are connected to the global bit line GBL via bit line selection transistors Tbls.

[0056] The word lines WL are wired in correspondence with the arrangement of memory cells MC in the X direction. In this embodiment, multiple memory cell layers LYR are stacked, and a dummy cell layer DLYR is set at the bottom layer.

[0057] Figure 5 This is a schematic front view showing an example of the configuration of a memory cell array (MCA). Figure 5 This indicates the configuration as viewed from the Y direction. In this embodiment, for example, bit lines VBL are arranged along word lines WL in the X direction as global bit lines GBL. Bit lines VBL are intermittently connected to global bit lines GBL via bit line select transistors Tbls.

[0058] Word line WL is connected to multiple memory cells MC arranged in the X direction. Dummy word line DWL is connected to multiple dummy memory cells DMC arranged in the X direction. One end of word line WL and dummy word line DWL are connected to word line driver WDRV via layer select transistors Tlys and DTlys, respectively. Word line driver WDRV selectively applies a select word voltage VWLSEL (reference) to any word line WL of the multiple memory cell layers LYR. Figure 6 The select word voltage VWLSEL is the voltage applied to the gate of the cell transistor when data is read from the memory cell MC. The other ends of the word line WL and the dummy word line DWL are connected to the non-selection voltage source VUW via layer select transistors bTlys and bDTlys, respectively. Thus, the word line driver WDRV applies the select word voltage VWLSEL as the first voltage only to the selected word line WL, enabling the transfer of data from the selected memory cell MC to the bit line VBL and the global bit line GBL.

[0059] Figure 6 This is a graph representing the voltage of the select word line WL and select bit lines VBL and GBL during the readout operation. The vertical axis of the graph represents voltage, and the horizontal axis represents time. Figure 7 It is a table showing the relationship between the data selected in the memory cell MC and the voltage of the bit line VBL at time points t1 and t3.

[0060] like Figure 6As shown, during the read operation, firstly, bit lines VBL and GBL are both set to an intermediate voltage VDD / 2 between the high-level voltage VDD and the low-level voltage VSS. This intermediate voltage VDD / 2 also serves as the intermediate voltage between the voltage of the global bit line GBL when reading the first logic (e.g., data "1") and the voltage of the global bit line GBL when reading the second logic (e.g., data "0"). This intermediate voltage is used as a reference voltage for detecting the logic that selects the data in memory cell MC. The sense amplifier SA compares the read voltage corresponding to the logic that selects the data in memory cell MC with the reference voltage and amplifies the voltage difference. Furthermore, the sense amplifier SA detects the logic that selects the data in memory cell MC based on the voltage difference between the read voltage and the reference voltage.

[0061] At t0, set bit line VBL and global bit line GBL to the reference voltage (intermediate voltage) VDD / 2.

[0062] At t1, set bit line VBL and global bit line GBL to electrically floating state. At this time, as... Figure 7 As shown, for example, when the data of the selected memory cell MC is "1", charge is stored in the cell capacitor Cmc, and the source voltage of the cell transistor Tmc is charged to a high level VDD. On the other hand, for example, when the data of the selected memory cell MC is "0", no charge is stored in the cell capacitor Cmc, and the source voltage of the cell transistor Tmc is discharged to approximately 0V. In addition, the voltage VBL of the bit line VBL and the global bit line GBL remains at the reference voltage (intermediate voltage) VDD / 2.

[0063] exist Figure 6 At t2, the word line WL is boosted to a select word voltage VWLSEL that is higher than the high-level voltage VDD. Consequently, the cell transistor Tmc of the select memory cell MC becomes active. At t3, the bit line VBL and the global bit line GBL become read voltages corresponding to the charge of the cell capacitor Cmc. For example, when the data in the select memory cell MC is "1", the bit line VBL and the global bit line GBL are higher than the intermediate voltage VDD / 2 by an amount equivalent to the signal voltage Vsig. When the data in the select memory cell MC is "0", the bit line VBL and the global bit line GBL are lower than the intermediate voltage VDD / 2 by an amount equivalent to the signal voltage Vsig. Furthermore, since the cell transistor Tmc is active at this time, ... Figure 7 The source voltage Vs of the unit transistor Tmc shown is approximately equal to the voltage of bit line VBL and global bit line GBL.

[0064] After t3, the sensing amplifier SA can detect the logic for selecting the data of the memory cell MC by comparing such a read voltage Vr (Vr = VDD / 2 + Vsig or VDD / 2 - Vsig) with the reference voltage VDD / 2.

[0065] However, in practice, if the word line WL is boosted to a select word voltage VWLSEL that is higher than the high-level voltage VDD, the voltage of the bit line VBL will rise due to the capacitive coupling between the word line WL and the bit line VBL via the cell transistor Tmc. In particular, in the case of a three-dimensional memory cell array (MCA) like this embodiment, the size of the cell transistor Tmc is larger than that of the cell transistors in a planar memory cell array. For example, it is known that the gate length and gate width of the cell transistor Tmc are both larger. In this case, the capacitive coupling between the word line WL and the bit line VBL increases due to the increased gate size of the cell transistor Tmc. Because the capacitive coupling between the word line WL and the bit line VBL increases, the voltage of the bit line VBL rises even more significantly during readout when the word line WL is boosted to the select word voltage VWLSEL. Such coupling noise may be the same as or higher than the readout voltage, hindering accurate data detection.

[0066] Therefore, in this embodiment, a dummy cell layer (DLYR) is provided in the three-dimensional memory cell array (MCA). The word line driver (WDRV) selects a portion of the dummy word lines (DWLs) within the dummy cell layer (DLYR). A dummy cell (DMC) is positioned between this dummy word line (DWL) and the non-selected bit line (VBL) that transmits the reference signal. The word line driver (WDRV) applies a dummy voltage (DV) in phase with the selected word voltage (VWLSEL) to the selected dummy word line (DWL). Thus, a voltage of the same magnitude as the coupling noise entering the selected global bit line (GBL) or selected bit line (VBL) that transmits data can be intentionally applied to the non-selected global bit line (GBL) or non-selected bit line (VBL) that transmits the reference signal.

[0067] For example, Figures 8-10 This is a top-down view showing the state of each layer of the memory cell array (MCA) during data readout. Figure 8 This indicates the state of a selected storage unit layer. Figure 9 This indicates the state of other non-selected storage unit layers. Figure 10 This indicates the state of the virtual unit layer.

[0068] During the data read operation, all word lines WL of the selected memory cell layer are selectively electrically connected to the word line driver WDRV using the layer selection transistor Tlys. All word lines WL of the non-selected memory cell layer are electrically disconnected from the word line driver WDRV using the layer selection transistor Tlys. In the non-selected memory cell layer, all word lines WL are connected to the non-selection voltage source VUW using the layer selection transistor bTlys. All dummy word lines DWL of the dummy cell layer are electrically connected to the word line driver WDRV using the dummy cell layer selection transistor DTlys.

[0069] The word line driver WDRV is configured commonly relative to multiple memory cell layers LYR, and in each memory cell layer LYR, the select word voltage VWLSEL is selectively passed to the word line WL of a certain row. At this time, in Figure 8 In the selected memory cell layer, the layer selection transistor Tlys is in the on state, so the select word voltage VWLSEL is transmitted to the select word line WLsel of the selected row. Even when selecting a memory cell layer, the word line driver WDRV applies the voltage of the non-selection voltage source VUW to the other non-selected word lines WLnonsel.

[0070] Therefore, the read voltage Vr corresponding to the data from the select memory cell MCsel connected to the select word line WLsel is transmitted to the bit line VBL and the global bit line GBL. Figure 8 In this process, the read voltage Vr is obtained from three selected memory cells MCsel. The other memory cells MC are non-selected memory cells.

[0071] On the other hand, the bit line VBL and global bit line GBL, which are not connected to the selected memory cell MCsel, are set to the reference voltage (intermediate voltage) VDD / 2 and the reference voltage Vref is transmitted.

[0072] Global bit lines GBL that transmit the read voltage Vr and global bit lines GBL that transmit the reference voltage Vref are arranged alternately in the X direction. When one of two adjacent global bit lines GBL transmits the read voltage Vr, the other transmits the reference voltage Vref; conversely, when one transmits the reference voltage Vref, the other transmits the read voltage Vr. Thus, two adjacent global bit lines GBL form a bit line pair for detecting one bit of data. One bit line in the bit line pair transmits the read voltage Vr, and the other transmits the reference voltage Vref. Furthermore, in this embodiment, the bit line pairs are arranged within the same memory cell array (MCA), forming a so-called folded bit line configuration. Hereinafter, the pair of bit lines VBL connected to one of the global bit lines GBL constituting the bit line pair and connected to the other bit line VBL is sometimes also referred to as a "bit line pair".

[0073] Here, if a select word voltage VWLSEL is applied to the select word line WLsel, then as described above, coupling noise is generated on the bit line VBL due to the capacitive coupling of the cell transistor Tmc of the select memory cell MCsel. If the coupling noise component is set to Vn, then the read voltage Vr of the bit line VBL or the global bit line GBL connected to the select memory cell MCsel becomes VDD / 2±Vsig+Vn. The read voltage is the voltage in the bit line VBL or the global bit line GBL when data is read from the select memory cell MCsel.

[0074] exist Figure 9 In the non-selection memory cell layer, because the layer select transistor Tlys is in a non-conducting state, the select word voltage VWLSEL from the word line driver WDRV is not transmitted to any word line WL. Because the layer select transistor bTlys is in a conducting state, the word line WL of the non-selection memory cell layer remains at the voltage of the non-selection voltage source VUW.

[0075] Figure 10 The word line driver WDRV selectively delivers a dummy voltage DV to a dummy word line DWL in a given row within the dummy cell layer DLYR. At this time, because the dummy cell layer selection transistor DTlys is in the ON state within the dummy cell layer DLYR, the dummy voltage DV is delivered to the selected dummy word line DWLsel. The word line driver WDRV applies the voltage of the non-selection voltage source VUW to the other non-selection dummy word lines DWLnonsel.

[0076] Here, the selected dummy word line DWLsel is a dummy word line DWL with a dummy cell DMC set between it and the bit line VBL that transmits the reference voltage Vref. That is, the selected dummy word line DWLsel is connected between the selected dummy word line DWLsel and the bit line VBL that transmits the reference voltage Vref. On the other hand, the dummy cell DMC is not connected between the selected dummy word line DWLsel and the bit line VBL that transmits the read voltage Vr. If a dummy voltage DV is applied to such a selected dummy word line DWLsel, coupling noise is generated in the bit line VBL that transmits the reference voltage Vref due to the capacitive coupling of the unit transistor Tmc of the selected dummy cell DMCsel. If the coupling noise component is set as DVn, then the reference voltage connected to the bit line VBL or the global bit line GBL of the selected dummy cell DMCsel becomes VDD / 2+DVn.

[0077] Thus, in this embodiment, the readout voltage becomes VDD / 2 ± Vsig + Vn, and the reference voltage becomes VDD / 2 + DVn. Assuming the dummy voltage DV and the select word voltage VWLSEL are in phase, the noise component DVn of the reference voltage Vref is also in phase (same polarity) with the noise component Vn. Therefore, when the sense amplifier SA detects the voltage difference by comparing the readout voltage Vr with the reference voltage Vref, it eliminates the noise component DVn of the reference voltage from the noise component Vn of the readout voltage. As a result, the coupling noise component Vn contained in the readout voltage decreases, and the proportion of the signal voltage Vsig component in the readout voltage Vr increases. Therefore, the sense amplifier SA can accurately detect the signal voltage Vsig.

[0078] The noise component DVn of the reference voltage is preferably approximately equal to the noise component Vn of the readout voltage. This allows for more accurate detection of the signal voltage Vsig, as the noise component Vn can be almost entirely eliminated. However, even if the noise component DVn is different from the noise component Vn, the effect of reducing the noise component Vn can still be achieved. Therefore, as long as the noise component DVn is in phase with the noise component Vn, it does not necessarily have to be equal to the noise component Vn.

[0079] Furthermore, the intermediate voltage VDD / 2 is pre-stored in the dummy cell DMC. Therefore, even if the selected dummy cell DMC is connected to the non-selected bit line VBL that transmits the reference voltage Vref, it will not affect the reference voltage Vref, which serves as the intermediate voltage. The dummy cell DMC can be periodically retained so that it always becomes the intermediate voltage VDD / 2, or it can be written to become the intermediate voltage VDD / 2 just before a read operation.

[0080] Figure 11 This is a circuit diagram illustrating an example configuration of a word line driver WDRV. The word line driver WDRV is connected to either the layer select transistor Tlys or DTlys. The word line driver WDRV selectively applies a select word voltage VWLSEL to the select word line WLsel in the select memory cell layer LYR selected by the layer select transistor Tlys. Additionally, the word line driver WDRV selectively applies a dummy voltage DV to the select dummy word line DWLsel in the dummy cell layer DLYR selected by the dummy cell layer select transistor DTlys. Furthermore, the word line driver WDRV is provided for each of the memory cell layer LYR and the dummy cell layer DLYR, and has the same configuration in both. Therefore, the configuration of the word line driver WDRV provided in the dummy cell layer DLYR will be described below, while the description of the word line driver WDRV provided in the memory cell layer LYR will be omitted.

[0081] The word line driver WDRV has inverters IN<0> to IN<11> that receive selection signals SEL<0> to SEL<3> and output drive voltages DRV<0> to DRV<2> or the voltage of the non-selection power supply VUW.

[0082] The drive voltages DRV<0> to DRV<2> are input to inverters IN<0> to IN<3>, IN<4> to IN<7>, and IN<8> to IN<11>, respectively. Any one of the drive voltages DRV<0> to DRV<2> is selectively activated as a dummy voltage DV, while the other two are deactivated as the voltage of the non-selective voltage source VUW. Therefore, one of the three sets of inverters IN<0> to IN<3>, IN<4> to IN<7>, and IN<8> to IN<11> outputs a dummy voltage DV.

[0083] Inverters IN<0> to IN<3> receive selection signals SEL<0> to SEL<3> and output the drive voltage DRV<0> or the voltage of the non-selected power supply VUW as output X<0> to X<3>. Inverters IN<4> to IN<7> receive selection signals SEL<0> to SEL<3> and output the drive voltage DRV<1> or the voltage of the non-selected power supply VUW as output X<4> to X<7>. Inverters IN<8> to IN<11> receive selection signals SEL<0> to SEL<4> and output the drive voltage DRV<2> or the voltage of the non-selected power supply VUW as output X<8> to X<11>.

[0084] Any one of the selection signals SEL<0> to SEL<3> is stepped down to a low level signal, while the other three are stepped up to a high level signal. Therefore, in the set of inverters (IN<0> to IN<3>, IN<4> to IN<7>, or IN<8> to IN<11>) of the dummy voltage DV in the output drive voltages DRV<0> to DRV<2>, only one inverter IN (i being any one of 0 to 11) outputs the high-level dummy voltage DV as output X. Thus, in the word line driver WDRV, one output X from output X<0> to X<11> becomes the dummy voltage DV, while the other 11 outputs X<k> (k≠i) become the voltage of the non-selected voltage source VUW.

[0085] In this way, the word line driver WDRV uses a combination of drive signals DRV<0> to DRV<2> and selection signals SEL<0> to SEL<3> to boost any one of the outputs X<0> to X<11> to a dummy voltage DV. Therefore, the word line driver WDRV can selectively drive one of the multiple dummy word lines DWL in the dummy cell layer DLYR.

[0086] Furthermore, the word line driver WDRV corresponding to the memory cell layer LYR has essentially the same configuration. The word line driver WDRV corresponding to the selected memory cell layer LYR uses a combination of drive signals DRV<0> to DRV<2> and selection signals SEL<0> to SEL<3> to boost any one of the outputs X<0> to X<11> to the selected word voltage VWLSEL. Thus, the word line driver WDRV can selectively drive one of the multiple word lines WL of the selected memory cell layer.

[0087] As described above, the semiconductor memory device 1 of this embodiment has a dummy cell layer DLYR provided in a three-dimensional memory cell array MCA. In the dummy cell layer DLYR, a dummy voltage DV, in phase with the select word voltage VWLSEL, is applied to the dummy word line DWL, where a dummy cell DMC is provided between it and the non-select bit line VBL that transmits the reference signal. This allows a voltage of the same magnitude as the coupling noise entering the select global bit line GBL or the select bit line VBL that transmits data to be intentionally added to the non-select global bit line GBL or the non-select bit line VBL that transmits the reference signal. As a result, in the sense amplifier SA, the coupling noise Vn contained in the readout voltage Vr is to some extent eliminated by the coupling noise DVn contained in the reference voltage Vref, thereby improving the sensing range of the signal voltage Vsig and enabling accurate detection.

[0088] The intermediate voltage VDD / 2 is pre-stored in the dummy cell DMC. Therefore, even if the selected dummy cell DMC is connected to the non-selected bit line VBL that transmits the reference voltage Vref, it will not affect the reference voltage Vref.

[0089] (Example of variation)

[0090] Figure 12 This is a graph showing the relationship between the select word voltage VWLSEL and the dummy voltage DV. The vertical axis of the graph represents voltage, and the horizontal axis represents time. The select word voltage VWLSEL and the dummy voltage DV are in phase and preferably approximately equal. However, as mentioned above, the dummy voltage DV can be different as long as it has the same polarity as the select word voltage VWLSEL. Furthermore, the dummy voltage DV can also be boosted approximately simultaneously with the select word voltage VWLSEL. However, the dummy voltage DV can also be boosted at a different time sequence than the select word voltage VWLSEL. The dummy voltage DV only needs to be boosted before the time point t3 when the sense amplifier SA detects the readout voltage Vr.

[0091] (Second Implementation)

[0092] Figure 13This is a schematic top view showing the state of the dummy cell layer DLYR during the data readout operation of the second embodiment. In the second embodiment, during the data readout operation, multiple dummy word lines DWL of the multiple dummy cell layer DLYR are selected, and a dummy voltage DV is applied to the multiple selected dummy word lines DWLsel. When n dummy word lines DWL (n is an integer of 2 or more) are selected, the dummy voltage DV can be approximately one-nth of the selected word voltage VWLSEL.

[0093] For example, in Figure 13 In this example, two dummy word lines DWL are selected as select dummy word lines DWLsel. Approximately half the dummy voltage DV of the select word voltage VWLSEL is applied to these two select dummy word lines DWLsel.

[0094] If we set the capacitance between the word line WL and the bit line VBL as C1, and the capacitance between the bit line VBL and the reference voltage source (e.g., ground) as C2, then the voltage across the select bit line VBL will increase by an amount equivalent to VWLSEL × C1 / (C1 + C2) due to the select word voltage VWLSEL. In other words, the coupling noise Vn of the read voltage Vr becomes VWLSEL × C1 / (C1 + C2).

[0095] Since the dummy cell DMC has the same configuration as the memory cell MC, when only one dummy word line DWLsel is selected, the coupling noise DVn of the reference voltage Vref is the same as the dummy voltage DV. In other words, the coupling noise DVn of the reference signal becomes DV×C1 / (C1+C2).

[0096] On the other hand, similar to the second embodiment, when two dummy word lines DWL are selected as select dummy word lines DWLsel, the coupling capacitance between the two select dummy word lines DWLsel and the one select bit line VBL becomes 2 × C1 / (C1 + C2). Therefore, the coupling noise DVn of the reference signal becomes DV × 2 × C1 / (C1 + C2). In other words, when there are two select dummy word lines DWLsel, the coupling noise DVn of the reference signal becomes twice as high. Conversely, even if the dummy voltage DV is halved, the coupling noise DVn of the reference signal can be maintained simply by increasing the number of select dummy word lines DWLsel.

[0097] Therefore, in the second embodiment, there are two select dummy word lines DWLsel, and the dummy voltage DV is approximately half the select word voltage VWLSEL. This allows the same coupling noise DVn as that applied when the select word voltage VWLSEL is applied to one select dummy word line DWLsel to be added to the reference voltage Vref.

[0098] The other configurations and operations of the second embodiment are the same as those of the first embodiment. Therefore, the second embodiment can achieve the same effects as the first embodiment. Furthermore, according to the second embodiment, the voltage of the selected dummy word line DWLsel can be reduced to half of the selected word voltage VWLSEL. Therefore, since the opportunity to boost the power supply voltage to a higher voltage is reduced, power consumption can be reduced.

[0099] Alternatively, the number of dummy word lines (DWLsel) can be 3 or more. When the number of dummy word lines (DWLsel) is n (n is an integer greater than or equal to 2), the dummy voltage (DV) can be approximately one-nth of the selected word voltage (VWLSEL). Thus, by increasing the number of dummy word lines (DWLsel), the dummy voltage (DV) can be reduced.

[0100] (Third Implementation)

[0101] Figure 14 and Figure 16 This is a schematic top view showing the state of the dummy unit layer DLYR during the data readout operation in the third embodiment. Figure 15 This is a schematic top view showing the state of the selected storage unit layer LYR during the data readout operation in the third embodiment.

[0102] In the third embodiment, during the data readout operation, all dummy word lines DWL with dummy cells DMC positioned between them and the non-selected bit line VBL of the transmission reference voltage Vref are selected as selected dummy word lines DWLsel. The word line driver WDRV applies a dummy voltage DV to the selected dummy word lines DWLsel. That is, the word line driver WDRV applies a dummy voltage DV to all dummy word lines DWL within the dummy cell layer DLYR. At this time, when the number of selected dummy word lines DWLsel is n, the dummy voltage DV can be approximately one-nth of the selected word voltage VWLSEL.

[0103] In the third embodiment, such as Figure 10 or Figure 13 As shown, the word line driver WDRV can also be connected to one side of the dummy word line DWL, and the non-selective voltage source VUW can be connected to the other side. In this case, the word line driver WDRV becomes Figure 11 The configuration shown activates two of the selection signals SEL<0> to SEL<3> as low-level signals.

[0104] However, as Figure 14As shown, word line drivers WDRV1 and WDRV2 can also be positioned at both ends of a dummy word line DWL. In this case, the first word line driver WDRV1 is connected to the dummy word line DWL that has a dummy cell DMC connected between it and one of the bit line pairs, and is electrically disconnected from the dummy word line DWL that has a dummy cell DMC connected between it and the other bit line pair. Furthermore, the second word line driver WDRV2 is electrically disconnected from the dummy word line DWL that has a dummy cell DMC connected between it and one of the bit line pairs, and is connected to the dummy word line DWL that has a dummy cell DMC connected between it and the other bit line pair.

[0105] With this configuration, the first and second word line drivers WDRV1 and WDRV2 only need to apply either the dummy voltage DV or the voltage of the non-selective voltage source VUW to all connected dummy word lines DWL. For example, as Figure 8 As shown, when one of the bit line pairs transmits the read voltage Vr, the first word line driver WDRV1... Figure 14 As shown, a dummy voltage DV is applied to all dummy word lines DWL that have a dummy cell DMC between them and another bit line VBL that transmits the reference voltage Vref in the bit line pair.

[0106] exist Figure 14 In the shown state, the first word line driver WDRV1 is connected to all dummy word lines DWL corresponding to the bit lines carrying the reference voltage Vref, but disconnected from all dummy word lines DWL corresponding to the bit lines carrying the readout voltage Vr. Therefore, the first word line driver WDRV1 applies a dummy voltage DV to all dummy word lines DWL connected to it. On the other hand, the second word line driver WDRV2 applies the voltage of the non-selective voltage source VUW to all dummy word lines DWL connected to it.

[0107] On the other hand, for example, such as Figure 15 As shown, when the other bit line pair transmits the read voltage Vr, the second word line driver WDRV2, as Figure 16 As shown, a dummy voltage DV is applied to all dummy word lines DWL where a dummy cell DMC is set between the bit line VBL and the bit line pair that transmits the reference voltage Vref.

[0108] exist Figure 16 In the illustrated state, the second word line driver WDRV2 is connected to all dummy word lines DWL corresponding to the bit lines carrying the reference voltage Vref, but disconnected from all dummy word lines DWL corresponding to the bit lines carrying the readout voltage Vr. Therefore, the second word line driver WDRV2 applies a dummy voltage DV to all dummy word lines DWL connected to it. On the other hand, in this case, the first word line driver WDRV1 applies the voltage of the non-selective voltage source VUW to all dummy word lines DWL connected to it.

[0109] Figure 17 This is a circuit diagram illustrating an example configuration of the word line drivers WDRV1 and WDRV2 according to the third embodiment. In the third embodiment, as described above, the word line drivers WDRV1 and WDRV2 selectively apply either the dummy voltage DV or the voltage from the non-selective voltage source VUW to all connected dummy word lines DWL. Therefore, the internal configurations of each of the word line drivers WDRV1 and WDRV2 are as follows: Figure 17 As shown, it may include one inverter IN. In this case, when the selection signal SEL is low, the dummy voltage DV is output as output X. When the selection signal SEL is high, the voltage of the non-selected voltage source VUW is output as output X.

[0110] Thus, according to the third embodiment, the configuration of the word line driver WDRV is simplified, and the number of transistors constituting the word line driver WDRV is reduced. Therefore, miniaturization of the semiconductor memory device 1 is achieved. Furthermore, when the number of dummy word lines DWLSEL is n, the dummy voltage DV can be approximately one-nth of the selected word voltage VWLSEL. Therefore, low power consumption of the semiconductor memory device 1 is achieved.

[0111] The other configurations of the third embodiment can be the same as the corresponding configurations of the first embodiment. Therefore, the third embodiment can achieve the same effects as the first embodiment.

[0112] (Fourth implementation)

[0113] Figure 18 This is a schematic diagram illustrating a configuration example of the dummy cell layer (DLYR) according to the fourth embodiment. In the fourth embodiment, multiple dummy cell layers (DLYRs) are arranged within a single memory cell array (MCA). The configuration of each of the multiple dummy cell layers (DLYRs) can be compared with... Figure 10 The configuration shown is the same. Furthermore, the word line driver WDRV can also be common to multiple dummy cell layers DLYR. Therefore, during data readout, the word line driver WDRV selects the dummy word line DWL in the same row of multiple dummy cell layers DLYR as the selected dummy word line DWLsel. The word line driver WDRV applies a dummy voltage DV to the selected dummy word line DWLsel. When the number of dummy cell layers DLYR is n, the number of selected dummy word lines DWLsel also becomes n. Therefore, the dummy voltage DV can be approximately one-nth of the selected word voltage VWLSEL. By changing the number of dummy cell layers DLYR, the dummy voltage DV can be adjusted.

[0114] In this way, multiple dummy cell layers (DLYR) can be set to increase the number of selected dummy word lines (DWLsel) and decrease the dummy voltage (DV). Other configurations in the fourth embodiment can be the same as those in the first embodiment. Therefore, the fourth embodiment can achieve the same effects as the first embodiment.

[0115] Furthermore, the fourth embodiment can also be combined with the second or third embodiment. This increases the number of dummy word lines DWLsel, thereby further reducing the voltage of the dummy voltage DV.

[0116] (Fifth Embodiment)

[0117] Figure 19 This diagram illustrates a configuration example of the memory cell array (MCA) according to the fifth embodiment. In the fifth embodiment, multiple dummy cell layers (DLYRs) are distributed within the memory cell array (MCA) in the Z-direction (stacking direction). For example, dLYR1 is disposed on the upper layer of the memory cell array (MCA), dLYR2 is disposed on the middle layer, and dLYR3 is disposed on the lower layer. The dLYRs are not only disposed on the upper and lower layers of the memory cell array (MCA), but also among the multiple memory cell layers (LYRs).

[0118] In this way, by distributing multiple virtual cell layers (DLYRs) in the Z direction, even if the electrical characteristics of the memory cells (MCs) within the memory cell layer (LYR) are uneven depending on their position in the Z direction, the electrical characteristics of the virtual cells (DMCs) in the virtual cell layer (DLYR) can be adapted to the electrical characteristics of the memory cells (MCs) in their vicinity.

[0119] For example, a bit line VBL extends in the Z direction, penetrating the memory cell layer LYR and the dummy cell layer DLYR within the memory cell array MCA. The bit line aperture formed when creating such a bit line VBL sometimes has a tapered inner surface, wider in the upper layer of the memory cell array MCA and narrowing towards the lower layers. Therefore, the diameter of the bit line VBL is wider in the upper layer of the memory cell array MCA and narrows towards the lower layers. Due to this tapered shape of the bit line VBL, there may be a situation where the electrical characteristics of the memory cell MC (e.g., the channel area of ​​the cell transistor Tmc, etc.) are uneven between the upper and lower layers of the memory cell array MCA.

[0120] However, according to the fifth embodiment, by distributing the multiple dummy cell layers DLYRs in the Z direction, the electrical characteristics of the dummy cells DMC of the dummy cell layers DLYRs can be adapted to the electrical characteristics of the nearby memory cells MC. Therefore, the noise component DVn of the reference voltage can be appropriately eliminated to eliminate the noise component Vn of the read voltage.

[0121] The other configurations of the fifth embodiment can be the same as those of the first embodiment. Therefore, the fifth embodiment can achieve the same effects as the first embodiment. Furthermore, the fifth embodiment can also be combined with any of the second to fourth embodiments. Thus, the fifth embodiment can achieve the effects of any of the second to fourth embodiments. For example, during the readout operation, multiple dummy word lines DWL can be selected from any one of the dummy cell layers DLYR1 to DLYR3 to apply a dummy voltage DV. Multiple dummy word lines DWL can also be selected from any multiple layers of dummy cell layers DLYR1 to DLYR3 to apply a dummy voltage DV. Furthermore, the dummy cell layer DLYR can be two layers or four or more layers.

[0122] (Sixth Embodiment)

[0123] Figure 20 This is a schematic top view showing a configuration example of the memory cell array (MCA) of the sixth embodiment. Figure 20 This represents a top view from the Z direction. In this embodiment, similar to the first embodiment, the bit line VBL is intermittently arranged at the intersection of the word line WL and the global bit line GBL. However, in the sixth embodiment, for example, the bit line VBL is arranged at every other intersection along the word line WL in the X direction, and at every other intersection along the global bit line GBL in the Y direction.

[0124] Figure 21 This is a schematic side view showing a configuration example of the memory cell array MCA in the sixth embodiment. Figure 21 This indicates the configuration as viewed from the X direction. In the sixth embodiment, for example, the bit line VBL is arranged at every other intersection position along the global bit line GBL in the Y direction.

[0125] The front view of the storage cell array MCA can be compared with Figure 5 same.

[0126] Thus, when viewed from above in the Z direction, the bit line VBL can also be intermittently staggered at the intersections of the word line WL and the global bit line GBL. In this case, when viewed from the X direction, the bit line VBL is intermittently connected column by column to the arrangement of the global bit line GBL in the Y direction.

[0127] Two adjacent global bit lines (GBLs) form a bit line pair for detecting 1 bit of data. One bit line pair transmits the readout voltage Vr, and the other transmits the reference voltage Vref. This sixth embodiment is also known as a so-called folded bit line configuration.

[0128] The other configurations of the sixth embodiment can be the same as those of the first embodiment. Therefore, the sixth embodiment can achieve the same effects as the first embodiment. The sixth embodiment can also be combined with any of the second to fifth embodiments. Thus, the sixth embodiment can achieve the same effects as any of the second to fifth embodiments.

[0129] (Seventh Embodiment)

[0130] Figure 22 This is a schematic perspective view showing a configuration example of the semiconductor memory device 1 according to the seventh embodiment. Figure 23 This is a schematic top view showing a configuration example of the memory cell array (MCA) of the seventh embodiment. Figure 23 This indicates a top-down view from the Z direction. Figure 24 This is a schematic side view showing a configuration example of the memory cell array MCA in the seventh embodiment. Figure 24 This indicates the composition as viewed from the X direction. Figure 25 This is a schematic front view showing an example of the configuration of a memory cell array (MCA). Figure 25 This indicates the composition as viewed from the Y direction.

[0131] In the seventh embodiment, the difference from the first embodiment is that, as Figures 22-25 As shown, bit lines VBL are configured corresponding to the intersection positions of word lines WL and global bit lines GBL. In this case, for example, bit lines VBL are configured at each of the intersection positions arranged along word lines WL in the X direction, and at each of the intersection positions arranged along global bit lines GBL in the Y direction. Other configurations of the seventh embodiment may be the same as those of the first embodiment.

[0132] Thus, with the bit lines VBL configured to correspond to the intersections of the word line WL and the global bit line GBL, during the read operation, the read voltage Vr is output from the selected memory cell MC between the selected word line WL and each bit line VBL via all global bit lines GBL. The reference voltage Vref cannot be output from the memory cell array MCA, which is the target of the read operation.

[0133] Therefore, in the seventh embodiment, the reference voltage Vref is generated using another memory cell array (MCA). For example, Figure 26 This is a block diagram illustrating an example configuration of multiple memory cell arrays MCA1 to MCA3. Sensing amplifiers SA are arranged on both sides of memory cell array MCA2. Memory cell array MCA1 is adjacent to memory cell array MCA2 in the Y direction (the extension direction of the global bit line GBL) across one sensing amplifier SA, and memory cell array MCA3 is adjacent to memory cell array MCA2 in the Y direction across another sensing amplifier SA.

[0134] The memory cell arrays MCA1 to MCA3 have reference Figures 22-25 The structures described can be identical to each other.

[0135] The sensing amplifier SA between the memory cell arrays MCA1 and MCA2 is connected to the global bit line GBL of both memory cell arrays MCA1 and MCA2, and uses the reference voltage Vref from the other memory cell array to detect the read voltage Vr from one of the memory cell arrays MCA1 and MCA2.

[0136] The sensing amplifier SA between the memory cell arrays MCA2 and MCA3 is connected to the global bit line GBL of both memory cell arrays MCA2 and MCA3, and uses the reference voltage Vref from the other memory cell array to detect the read voltage Vr from one of the memory cell arrays MCA2 and MCA3.

[0137] For example, the storage cell array MCA1 from Figure 24 and Figure 25 Each of the memory cell layers LYR shown transmits the read voltage Vr to the global bit line GBL. The memory cell array MCA2 from... Figure 24 and Figure 25 The dummy cell layer DLYR shown transmits the reference voltage Vref to the global bit line GBL.

[0138] like Figure 26 As shown, the selected global bit line GBLsel and the non-selected global bit line GBLselnon are adjacent in their extension direction (Y direction).

[0139] Thus, in the seventh embodiment, bit line pairs are respectively arranged in multiple adjacent memory cell arrays (MCAs), forming a so-called open bit line configuration. In the open bit line configuration, for example, the memory cell array MCA2 with the global bit line GBLsel selected is different from the memory cell arrays MCA1 and MCA3 with the global bit line GBLnonsel selected. Therefore, the word line WL and dummy word line DWL corresponding to the global bit line GBLsel selected are different from the word line WL and dummy word line DWL corresponding to the global bit line GBLnonsel selected.

[0140] When memory cell array MCA2 acts as the selected memory cell array MCA1, transmitting the read voltage Vr, memory cell array MCA1 or MCA3 acts as the non-selected memory cell array MCA1, generating a reference voltage Vref. Two sense amplifiers compare the read voltage Vr from memory cell array MCA1 with the reference voltage Vref from memory cell array MCA2 or MCA3. This enables the logic to detect the data in the selected memory cell MCsel.

[0141] Thus, this embodiment can be applied even with an open bitline configuration. Other configurations of the seventh embodiment can be the same as those of the first embodiment. Therefore, the seventh embodiment can achieve the same effects as the first embodiment. Furthermore, the seventh embodiment can also be combined with any of the second to sixth embodiments. In this case, the seventh embodiment can also achieve the effects of any of the second to sixth embodiments.

[0142] Several embodiments of the present invention have been described, but these embodiments are provided as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other ways and can be omitted, substituted, or modified in various ways without departing from the spirit of the invention. These embodiments or variations thereof are included in the scope or spirit of the invention, and are included in the scope of the invention as set forth in the claims and its equivalents.

Claims

1. A semiconductor memory device comprising: Multiple first-unit layers, each containing multiple first-units used as storage units and arranged in the first face; At least one second unit layer, comprising a plurality of second units not used as storage units and arranged in the second face, and stacked in the first unit layer; Multiple first wirings are connected to multiple first units arranged in a first direction within the first surface; Multiple second wirings are connected to multiple second units arranged in the first direction within the second surface; Multiple third wirings are connected to the first unit and the second unit arranged in a second direction in the stacked first unit layer and the second unit layer; A plurality of fourth wirings are connected to a plurality of third wirings arranged in a third direction intersecting the first direction and the second direction; and Control circuit; The control circuit When reading data from the selection unit selected from the plurality of first units, a first voltage is applied to the selection first line connected to the selection unit among the plurality of first lines, and a readout voltage corresponding to the data is transmitted to the selection fourth line connected to the selection unit among the plurality of fourth lines. The reference voltage, which serves as the detection reference for the readout voltage, is transmitted to the non-selected fourth wirings (other than the selected fourth wirings) among the plurality of fourth wirings. A second voltage is applied to the selected second wiring of the second unit, which is located between the second unit and the non-selected fourth wiring, among the plurality of second wirings.

2. The semiconductor memory device according to claim 1, wherein the second voltage has the same polarity as the first voltage.

3. The semiconductor memory device of claim 1, wherein the second voltage is applied to one of the selected second wirings of the plurality of second wirings. The first voltage and the second voltage are equal.

4. The semiconductor memory device of claim 1, wherein the second voltage is applied to n selected second wirings of the plurality of second wirings, where n is an integer greater than or equal to 2. The second voltage is one-nth of the first voltage.

5. The semiconductor memory device of claim 1, wherein the second voltage is applied to all the second wirings within the second cell layer.

6. The semiconductor memory device according to claim 1, comprising a plurality of the second unit layers.

7. The semiconductor memory device of claim 6, wherein the second unit layer is disposed between the plurality of the first unit layers.

8. The semiconductor memory device of claim 1, wherein the second voltage is applied before the readout voltage is detected.

9. The semiconductor memory device of claim 1, further comprising a sensing amplifier connected to the fourth wiring and comparing the readout voltage with the reference voltage.

10. The semiconductor memory device of claim 1, wherein the reference voltage is an intermediate voltage between the readout voltage when the data of the selection unit is in the first logic state and the readout voltage when the data of the selection unit is in the second logic state.

11. The semiconductor memory device of claim 1, wherein the selected fourth wiring and the non-selected fourth wiring are adjacent in the first direction.

12. The semiconductor memory device of claim 11, wherein the selected fourth wiring and the non-selected fourth wiring are disposed commonly relative to the plurality of first wirings and the plurality of second wirings.

13. The semiconductor memory device of claim 11, wherein, viewed from the second direction, the first cell is intermittently disposed at the intersection of the first wiring and the fourth wiring. Viewed from the second direction, the second unit is intermittently positioned at the intersection of the second wiring and the fourth wiring.

14. The semiconductor memory device of claim 1, wherein the selected fourth wiring and the non-selected fourth wiring are adjacent in the third direction.

15. The semiconductor memory device of claim 14, wherein the plurality of first lines corresponding to the selected fourth line are different from the plurality of first lines corresponding to the non-selected fourth line. The plurality of second wirings corresponding to the selected fourth wiring are different from the plurality of second wirings corresponding to the non-selected fourth wiring.

16. The semiconductor memory device of claim 14, wherein, viewed from the second direction, the first unit is disposed at each intersection of the first wiring and the fourth wiring. Viewed from the second direction, the second unit is located at each intersection of the second wiring and the fourth wiring.

17. The semiconductor memory device of claim 1, wherein the first unit comprises: a first transistor, the gate of which is connected to the first wiring, and one of the source and drain of which is connected to the third wiring; and a first capacitor connected to the other of the source and drain of the first transistor; The second unit includes: a second transistor, the gate of which is connected to the second wiring, and one of the source and drain connected to the third wiring; and a second capacitor connected to the other of the source and drain of the second transistor.

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