Storage circuit, method of operating a storage circuit, storage array, memory, and electronic device

Abstract

Embodiments of the present disclosure provide a storage circuit, a method of operating the storage circuit, a storage array, a memory, and an electronic device. The storage circuit includes a first transistor storing first storage data, a second transistor storing second storage data, a third transistor coupled to the first transistor and configured to write the first storage data to the first transistor, a fourth transistor coupled to the second transistor and the third transistor and configured to write the second storage data to the second transistor, a fifth transistor coupled to the first transistor and configured to receive first input data and determine whether the first input data matches the first storage data, and a sixth transistor coupled to the second transistor and the fifth transistor and configured to receive second input data and determine whether the second input data matches the second storage data. In this way, the storage area of the integrated circuit can be reduced, while effectively reducing the manufacturing cost of the integrated circuit.

Description

Technical Field

[0001] This disclosure relates primarily to the field of integrated circuits. More specifically, this disclosure relates to a circuit, a method of operating a circuit, a memory array, a memory, and an electronic device. Background Technology

[0002] In the field of integrated circuits, XOR logic circuits are commonly used logic gates, for example, in encryption or decryption operations, as well as in matching and searching operations. The basic unit of content-addressable memory (CAM) circuits is an XOR logic unit built upon memory; that is, it performs an XOR operation between the input data and the stored data to achieve comparison. When the input data and the stored data are the same, the address where the stored data is stored will output a high level, thus enabling effective addressing. Because CAM circuits can perform parallel searches within memory, they are used to accelerate pattern matching tasks. Furthermore, CAM circuits can also be applied to machine learning.

[0003] Most existing content-addressable memory (COM) circuits are based on static random access memory (SRAM). Due to the characteristics of SRAM, as integrated circuits process increasingly more data, the storage area required for SRAM-based integrated circuits inevitably increases, significantly limiting their widespread use. How to further reduce the storage area of ​​integrated circuits while simultaneously lowering their cost is a major challenge for designers. Summary of the Invention

[0004] At least in order to reduce the storage area overhead of integrated circuits, embodiments of this disclosure provide a circuit, a method of operating the circuit, a storage array, a memory, and an electronic device.

[0005] In a first aspect of this disclosure, a storage circuit is provided, comprising: a first transistor configured to store first stored data; a second transistor configured to store second stored data; a third transistor coupled to the first transistor and configured to write the first stored data into the first transistor; a fourth transistor coupled to the second transistor and the third transistor and configured to write the second stored data into the second transistor; a fifth transistor coupled to the first transistor and configured to receive first input data and determine whether the first input data matches the first stored data; and a sixth transistor coupled to the second transistor and the fifth transistor and configured to receive second input data and determine whether the second input data matches the second stored data.

[0006] According to embodiments of this disclosure, six transistors can be used to realize both the storage function and the matching function of the storage circuit. In the storage mode, writing two types of stored data is achieved by storing first and second stored data into the first and second transistors respectively. In the matching mode, it is possible to determine whether the input data matches the pre-stored stored data.

[0007] In one implementation of the first aspect, the gates of the third transistor and the fourth transistor are commonly coupled to a first voltage terminal, and the third and fourth transistors are configured to receive a first control signal from the first voltage terminal and to turn on or off according to the first control signal. Since the third and fourth transistors can receive the control signal via the commonly coupled first voltage terminal, they respectively complete the switching on or off with the first and second transistors. In this way, the storage circuit can be flexibly switched to read / write mode, facilitating the writing of stored data.

[0008] In one implementation of the first aspect, the gates of the fifth transistor and the sixth transistor are commonly coupled to a second voltage terminal, and the fifth and sixth transistors are configured to receive a second control signal from the second voltage terminal and to turn on or off according to the second control signal. Since the fifth and sixth transistors can receive the control signal via the commonly coupled second voltage terminal, they respectively complete the switching on or off with the first and second transistors. In this way, the storage circuit can be flexibly switched to a matching mode, facilitating the matching and comparison of stored data with input data.

[0009] In one implementation of the first aspect, the first terminals of the third transistor and the fourth transistor are jointly coupled to a third voltage terminal. In this manner, since the third voltage terminal is coupled to both the third and fourth transistors, the reading, writing, and matching functions of the circuit can be assisted by controlling the voltage at the third voltage terminal.

[0010] In one implementation of the first aspect, the first terminals of the fifth transistor and the sixth transistor are jointly coupled to a matching line. Since the matching line can effectively reflect the operating states of the fifth and sixth transistors, this method allows for accurate determination of whether the data to be matched is consistent with the stored data.

[0011] In one implementation of the first aspect, the first terminals of the first transistor and the second transistor are coupled to a reference voltage terminal. In this way, since a pull-down discharge path can be provided for the matching line when necessary, the operating states of the fifth and sixth transistors can be identified by changing the output level of the matching line, thereby assisting in determining whether the input data matches. Because the first and second transistors are included in the pull-down discharge path, compared to existing solutions, it is not necessary to provide additional transistors for data matching, thus significantly reducing the number of transistors and alleviating the area overhead problem caused by a large number of transistors in the memory cells of integrated circuits, thereby effectively reducing the manufacturing cost of the memory circuit.

[0012] In one implementation of the first aspect, one or both of the first transistor and the second transistor are semi-floating gate transistors, wherein the first transistor includes a control gate and a select gate, and the second transistor includes a control gate and a select gate. In this manner, the advantages of fast write / erase speeds and low storage area of ​​semi-floating gate transistors can be fully utilized, greatly controlling the cost increase caused by the area overhead of content-addressable memory circuits.

[0013] In one implementation of the first aspect, one or both of the first transistor and the second transistor are floating-gate transistors.

[0014] In a second aspect of this disclosure, a method for operating the circuit of the first aspect of this disclosure is provided. The gates of the third transistor and the fourth transistor are commonly coupled to a first voltage terminal, and the gates of the fifth transistor and the sixth transistor are commonly coupled to a second voltage terminal. The method includes: applying a first voltage level to the first voltage terminal; and applying a second voltage level to the second voltage terminal, wherein the second voltage level is lower than the first voltage level, to turn on the third and fourth transistors and turn off the fifth and sixth transistors, thereby putting the circuit into a read-write mode. In this way, the circuit can be switched to read-write mode to store data to be read or written into the first and second transistors.

[0015] In one implementation of the second aspect, the second level can be a low level and the first level can be a high level.

[0016] In one implementation of the second aspect, the method further includes: applying a third voltage level to the first voltage terminal; and applying a fourth voltage level to the second voltage terminal, wherein the fourth voltage level is higher than the third voltage level, to disconnect the third and fourth transistors and turn on the fifth and sixth transistors, so that the circuit is in a matching mode. In this manner, the circuit can be switched to a matching mode to determine the consistency of the data to be matched stored in the first and second transistors.

[0017] In one implementation of the second aspect, the first transistor and the second transistor are semi-floating gate transistors. The method further includes: applying a fifth voltage level to the control gate and the select gate of the first transistor; and applying a sixth voltage level to the control gate and the select gate of the second transistor, wherein the fifth voltage level and the sixth voltage level are associated with the data to be read or written. In this way, a predetermined read / write function can be performed by applying voltages to the control gate and the select gate.

[0018] In one implementation of the second aspect, the third level can be a low level and the fourth level can be a high level.

[0019] In one implementation of the second aspect, the first transistor and the second transistor are semi-floating gate transistors. The method further includes: applying a seventh level to the control gate and the select gate of the first transistor; and applying an eighth level to the control gate and the select gate of the second transistor, wherein the seventh level and the eighth level are associated with the data to be matched. In this way, a predetermined matching function can be accomplished by applying voltages to the control gate and the select gate.

[0020] In a third aspect of this disclosure, a memory array is provided. The memory array device includes a plurality of memory circuits according to the first aspect of this disclosure, wherein the plurality of memory circuits are arranged in an array.

[0021] In a fourth aspect of this disclosure, a memory is provided. The memory includes: a controller; and a memory array as described in the third aspect of this disclosure.

[0022] In a fifth aspect of this disclosure, an electronic device is provided. The electronic device includes a circuit board; and a memory, as described in the fourth aspect of this disclosure, disposed on the circuit board.

[0023] These and other aspects of this disclosure will become more apparent in the description of the following embodiments(s). Attached Figure Description

[0024] The above and other features, advantages, and aspects of the embodiments of this disclosure will become more apparent from the accompanying drawings and the following detailed description. In the drawings, the same or similar reference numerals denote the same or similar elements. The drawings are not necessarily drawn to scale, wherein: Figure 1 shows a schematic diagram of an SRAM-based circuit in the prior art; Figure 2 A schematic structural diagram of a circuit according to an embodiment of the present disclosure is shown; Figure 3 It shows Figure 2 A schematic diagram of the circuit in read / write mode; Figure 4 It shows Figure 2 A schematic diagram of the circuit in matching mode; Figure 5 Characteristic graphs of a semi-floating gate transistor according to embodiments of the present disclosure are shown; and Figure 6 A schematic diagram of a circuit arrangement including a plurality of circuits arranged in an array, according to an embodiment of the present disclosure, is shown. Detailed Implementation

[0025] Embodiments of this disclosure will now be described in more detail with reference to the accompanying drawings. While some embodiments of this disclosure are shown in the drawings, it should be understood that this disclosure can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of this disclosure. It should be understood that the accompanying drawings and embodiments of this disclosure are for illustrative purposes only and are not intended to limit the scope of protection of this disclosure.

[0026] In the description of embodiments of this disclosure, the term "comprising" and similar terms should be understood as open-ended inclusion, i.e., "including but not limited to". The term "based on" should be understood as "at least partially based on". The term "one embodiment" or "this embodiment" should be understood as "at least one embodiment". The terms "first", "second", etc., may refer to different or the same objects. In the context of this disclosure, terms such as "coupled", "linked", "connected", etc., describe connecting associated components in various ways, including not only physical or mechanical means, but also other means, such as electrical or magnetic means, whether direct or indirect. Other explicit and implicit definitions may also be included below.

[0027] Figure 1 shows a schematic diagram of a prior art SRAM-based dual-state content-addressable memory circuit structure 1'. As shown, circuit structure 1' includes multiple transistors M1, M2, M3, and M4, as well as an SRAM cell M5. Since a single SRAM cell M5 is actually composed of 6 transistors, the entire circuit structure 1' includes a total of 10 transistors. This significantly increases the area occupied by circuit structure 1' and also increases its manufacturing cost. Even worse, if more states of functionality are to be implemented, such as constructing a tri-state content-addressable memory circuit, even more transistors are required, leading to even higher costs. This greatly limits its application.

[0028] In order to address the aforementioned problems in the prior art, embodiments of this disclosure provide an improved circuit structure. Figure 2 A schematic diagram of a storage circuit 1 according to an embodiment of the present disclosure is shown. (As shown) Figure 2 As shown, the storage circuit 1 includes a first transistor 10 and a second transistor 20 for data storage. The first transistor 10 can be used to store first stored data, and the second transistor 20 can be used to store second stored data. The combination of the first and second stored data can represent various different storage states in the storage circuit 1. For example, in some embodiments, the first stored data can be 0 or 1, and the second stored data can also be 0 or 1, as will be further described below. According to embodiments of this disclosure, the first transistor 10 and the second transistor 20 are semi-floating gate transistors. A semi-floating gate transistor is a good type of storage transistor, having two gates: a control gate and a selection gate. Figure 2 As shown, taking the first transistor 10 as an example, its control gate is represented by 11 and its select gate by 14; taking the second transistor 20 as an example, its control gate is represented by 21 and its select gate by 24. According to the construction of a semi-floating gate transistor, the area below the select gate can be considered as an embedded tunneling field-effect transistor, while the area below the control gate is a floating gate. Using this construction, since the floating gate is not completely covered by the gate oxide layer, a charge channel for the floating gate layer is formed in the oxide layer gap, which does not damage the gate oxide layer, thus achieving ideal erase / write cycles and speed. In other embodiments, the first transistor 10 and the second transistor 20 can also be floating gate transistors. It should be noted that the first transistor 10 and the second transistor 20 are not required to be transistors of exactly the same type; for example, the first transistor 10 can be a semi-floating gate transistor, while the second transistor 20 is a floating gate transistor.

[0029] The storage circuit 1 also includes a third transistor 30 and a fourth transistor 40, which are respectively configured to form a read / write circuit with the first transistor 10 and the second transistor 20. Figure 2 As shown in the illustrated embodiment, the source 32 of the third transistor 30 is coupled to the drain 13 of the first transistor 10, and the source 42 of the fourth transistor 40 is coupled to the drain 23 of the second transistor 20. The drain 43 of the fourth transistor 40 can be coupled to the drain 33 of the third transistor 30. It should be noted that this is only one implementation method; the drains and sources of the first transistor 10 and the second transistor 20 can be interchanged, and the drains and sources of the third transistor 30 and the fourth transistor 40 can also be interchanged. Any adjustment can be made as long as such adjustment can achieve the predetermined connection between the transistors.

[0030] exist Figure 2 In the illustrated embodiment, multiple voltage terminals can be provided, including a first voltage terminal V. row Second voltage terminal V sw and the third voltage terminal V dThis will be described in detail below. The first terminal of the third transistor 30 can be coupled to the first terminal of the third transistor 40 to the third voltage terminal V. d .exist Figure 2 In the illustrated embodiment, the drain 33 of the third transistor 30 and the drain 43 of the fourth transistor 40 can be coupled together to the third voltage terminal V. d In an alternative embodiment, the source 32 of the third transistor 30 and the source 42 of the fourth transistor 40 may also be coupled together to the third voltage terminal V. d .

[0031] The storage circuit 1 may further include a fifth transistor 50 and a sixth transistor 60, respectively configured to form a matching circuit with the first transistor 10 and the second transistor 20. For example... Figure 2 As shown, the source 52 of the fifth transistor 50 is coupled to the drain 13 of the first transistor 10, and the source 62 of the sixth transistor 60 is coupled to the drain 23 of the second transistor 20. The drain 63 of the sixth transistor 60 can be coupled to the drain 53 of the fifth transistor 50. It should also be noted that this is merely one implementation; the drains and sources of the first transistor 10 and the second transistor 20 can be interchanged, as can the drains and sources of the fifth transistor 50 and the sixth transistor 60. Any adjustment can be made as long as the predetermined connection between the transistors is achieved.

[0032] In general, the storage circuit 1 can have two modes: read-write mode and matching mode. In read-write mode, the data to be stored is stored in the first transistor 10 and the second transistor 20 through the read-write circuit composed of the first transistor 10 and the third transistor 30, and the second transistor 20 and the fourth transistor 40, respectively. In matching mode, through the matching circuit composed of the first transistor 10 and the fifth transistor 50, and the second transistor 20 and the sixth transistor 60, the input data is compared with the data already stored in the first transistor 10 and the second transistor 20 to determine whether the input data is consistent with the previously stored data.

[0033] According to embodiments of this disclosure, in the storage circuit 1, switching between read / write mode and match mode can be achieved using only six transistors, thereby realizing the predetermined read / write and match functions. Compared to the conventional scheme using ten transistors, this scheme can significantly reduce storage area overhead. It should be understood that... Figure 2The specific structure of the storage circuit 1 shown is merely illustrative and not limiting. Some details of the storage circuit 1 can be adjusted to meet various practical needs without departing from the spirit of the embodiments of this disclosure. Furthermore, since the first transistor 10 and / or the second transistor 20 used for data storage can be semi-floating gate transistors or floating gate transistors with fast erase / write speeds and low storage area, the area overhead of the storage circuit 1 can be reduced, and the storage efficiency of the storage circuit 1 can be optimized.

[0034] The operation of the storage circuit 1 in different modes according to embodiments of the present disclosure is described in detail below.

[0035] Combination Figure 3 To describe Figure 2 The diagram illustrates the illustrative operation of storage circuit 1 in read / write mode. When reading and writing data, a mapping must first be established between the states of the first transistor 10 and the second transistor 20 and the data to be read or written. Table 1 shows a feasible read / write mapping scheme according to an embodiment of this disclosure. As shown in columns 1-4 of the table, when the first data stored in the first transistor 10 is 0 and the second data stored in the second transistor 20 is 0, it can represent a state where the data in storage circuit 1 is X, where data X includes cases where the read / write data is 0 and the read / write data is 1. When the first data stored in the first transistor 10 is 1 and the second data stored in the second transistor 20 is 0, it can represent a case where the read / write data in storage circuit 1 is 1. When the first data stored in the first transistor 10 is 0 and the second data stored in the second transistor 20 is 1, it can represent a case where the read / write data in storage circuit 1 is 0. It should be understood that such a correspondence can be defined by the user according to actual needs. The specific correspondence is not limited to the cases listed in the table. For example, storing 1 in the first transistor 10 and storing 0 in the second transistor 20 can represent the state of reading / writing as 0 in the storage circuit 1, and storing 0 in the first transistor 10 and storing 1 in the second transistor 20 can represent the state of reading / writing as 1 in the storage circuit 1.

[0036] Table 1. Circuit Data Read / Write Mapping

[0037] In read / write mode, referring to Figure 1, the second voltage terminal V needs to be... sw Connect to low level, because the second voltage terminal V sw This is the voltage terminal jointly coupled to the gate 51 of the fifth transistor 50 and the gate 61 of the sixth transistor 60. Therefore, at this time, the fifth transistor 50 and the sixth transistor 60 can be considered to be disconnected. Figure 3 The fifth transistor 50 and the sixth transistor 60 are represented by a lighter color to make them appear as if they were made of a different color. Figure 3The display of other parts is clearer. Furthermore, the first voltage terminal V... row When connected to a high level, since the gate 31 of the third transistor 30 and the gate 41 of the fourth transistor 40 are both coupled to the first voltage terminal V. row At this point, the third transistor 30 and the fourth transistor 40 can be considered to be operating normally, and are respectively coupled to the first transistor 10 and the second transistor 20, thus forming a read / write circuit. That is, by making the second voltage terminal V... sw Connect to low level and make the first voltage terminal V row When a high level is applied, storage circuit 1 is switched to read / write mode. In this read / write mode, the data to be stored can be read and written to the first transistor 10 and the second transistor 20.

[0038] In some embodiments, the storage circuit 1 may be initialized first. For the first transistor 10, when the voltage terminal V coupled to its control gate 11 is... CG1 Apply a positive voltage to the voltage terminal V coupled to its select gate 14. SG1 A positive voltage is applied, and at the third voltage terminal V coupled to its drain 13 d When a negative voltage is applied, if the first transistor 10 is a semi-floating gate transistor, the charge in the semi-floating gate transistor will be discharged into the channel and thus erased, and the corresponding state of the first transistor 10 will be 0. Similarly, for the second transistor 20, when a negative voltage is applied to the voltage terminal V coupled to its control gate 21... CG2 Apply a positive voltage to the voltage terminal V coupled to its select gate 24. SG2 A positive voltage is applied, and at the third voltage terminal V coupled to its drain 23 d When a negative voltage is applied, the state of the second transistor 20 is 0. According to Table 1, since the data stored in both the first transistor 10 and the second transistor 20 is 0, the storage circuit 1 is in its initial state.

[0039] According to Table 1, if the data to be stored is 1, then the voltage terminal V can be... CG1 and voltage terminal V SG1 Set to negative voltage, voltage terminal V CG2 and voltage terminal V SG2 No voltage is applied, and the third voltage terminal V is... d Set to a positive voltage. Specifically, for the first transistor 10, when the voltage terminal V coupled to its control gate 11 is... CG1 Apply a negative voltage to the voltage terminal V coupled to its select gate 11. SG1 Apply a negative voltage, and at the third voltage terminal V coupled to its drain 13 dWhen a positive voltage is applied, based on the characteristic of the first transistor 10 as a semi-floating gate transistor, the state of the first transistor 10 is 1. At this time, the voltage terminal V coupled to the control gate 21 of the second transistor 20... CG2 The voltage terminal V coupled to the select gate 24 SG2 Without applying voltage, the state of the second transistor 20 remains at 0. According to the correspondence in Table 1, since the data stored in the first transistor 10 and the second transistor 20 are 1 and 0 respectively, the storage circuit 1 is in the read / write state.

[0040] According to Table 1, if the data to be stored is 0, then the voltage terminal V can be... CG2 and voltage terminal V SG2 Set to negative voltage, voltage terminal V CG1 and voltage terminal V SG1 No voltage is applied, and the third voltage terminal V is... d Set to a positive voltage. Specifically, for the second transistor 20, when the voltage terminal V coupled to its control gate 21 is... CG2 Apply a negative voltage to the voltage terminal V coupled at its selection 24. SG2 A negative voltage is applied, and at the third voltage terminal V coupled to its drain 23 d When a positive voltage is applied, based on the characteristic of the second transistor 20 as a semi-floating gate transistor, the state of the second transistor 20 is 1. At this time, the voltage terminal V coupled to the control gate 11 of the first transistor 10... CG1 The voltage terminal V coupled to the select gate 14 SG1 Without applying voltage, the state of the first transistor 10 remains at 0. According to the correspondence in Table 1, since the data stored in the first transistor 10 and the second transistor 20 are 0 and 1 respectively, the storage circuit 1 is in the read / write 0 state.

[0041] Through the illustrative process described above, the voltage terminal V can be controlled. CG1 V SG1 V CG2 V CG2 and V d The voltage enables the first transistor 10 and the second transistor 20 to read and write corresponding data, thereby obtaining different read and write states of the storage circuit 1.

[0042] The following is combined with Figure 4 To describe Figure 2 The schematic diagram shows the operation of the storage circuit 1 in matching mode. First, the first voltage terminal V is... row Connect to low level, return to reference Figure 1, because the first voltage terminal V rowIt is the voltage terminal that is jointly coupled to the gate 31 of the third transistor 30 and the gate 41 of the fourth transistor 40. Therefore, at this time, the third transistor 30 and the fourth transistor 40 can be considered to be disconnected. Figure 4 The third transistor 30 and the fourth transistor 40 are represented by a lighter color, so that... Figure 4 The display of other parts is clearer. Furthermore, the second voltage terminal V... sw When connected to a high level, since the gate 51 of the fifth transistor 50 and the gate 61 of the sixth transistor 60 are both coupled to the second voltage terminal V... sw At this point, the fifth transistor 50 and the sixth transistor 60 can be considered to be operating normally, and are respectively coupled to the first transistor 10 and the second transistor 20, thus forming a matching circuit. That is, by making the first voltage terminal V... row Connect to a low level and make the second voltage terminal V sw When a high-level signal is applied, storage circuit 1 is switched to matching mode. In this matching mode, the input data can be compared with the data read and written to the first transistor 10 and the second transistor 20 in the previous steps using read / write mode, thereby determining whether the two are consistent based on the output state of storage circuit 1.

[0043] When matching the input data with the stored data, a mapping needs to be established between the voltage at the voltage terminal in storage circuit 1 and the input data. Table 2 shows a feasible matching mapping scheme according to an embodiment of this disclosure.

[0044] Table 2 Data Matching Mapping for Circuits

[0045] In some embodiments, as shown in Table 2, voltage includes voltage V. a and V b Its value can be determined based on the characteristics of the semi-floating gate transistor. Figure 5 The diagram shows a schematic characteristic curve of a semi-floating gate transistor, and illustrates V. a and V b The approximate value of V, where V a Less than V b From the characteristic curve of the semi-floating gate transistor, it can be seen that when the voltage is V... a At this time, regardless of whether the half-floating gate transistor is in the "0" or "1" state, the input is "0". When the voltage is V b When the half-floating gate transistor is in the "0" state, the input is "0", and when the half-floating gate transistor is in the "1" state, the input is "1". Referring to Table 2, for example, when the input data is 1, the voltage terminal V... CG1 and voltage terminal V SG1 The voltage is set to V aAnd the voltage terminal V CG2 and voltage terminal V SG2 The voltage is set to V b This is equivalent to encoding the input data as 1, which is done through the various voltage terminals V. CG1 V SG1 V CG2 V CG2 The above combinations are used to map the input data to 1. It should be understood that the voltage matching schemes in Table 2 are merely illustrative and not limiting. In other embodiments, other voltage correspondences may be used depending on actual needs.

[0046] The following describes in detail how the storage circuit 1 according to an embodiment of the present disclosure implements the matching function.

[0047] Assuming the first transistor 10 stores a first data value of 1 and the second transistor 20 stores a second data value of 0, referring to Table 1 in the read / write modes, this indicates that the data read / written in the preceding read / write mode is 1. In this case, if the input data is 0, according to the correspondence in Table 2, the voltage terminal V coupled to the control gate 11 of the first transistor 10... CG1 The voltage terminal V coupled to the select gate 14 of the first transistor 10 SG1 The voltage terminal V coupled to the control gate 21 of the second transistor 20 CG2 The voltage of the second transistor 20 and the voltage terminal V coupled to the select gate 24 of the second transistor 20. SG2 V b V b V a and V a Combining Figure 5 It can be seen that V b The voltage is high and the first data stored in the first transistor 10 is 1, therefore the first transistor 10 can be turned on via the control gate 11 and the select gate 14. At this time, the first transistor 10 and the fifth transistor 50 form a matching circuit. In some embodiments, the first terminal of the fifth transistor 50 is coupled to the matching line ML. Figure 2 In the illustrated embodiment, the first electrode may be the drain 53 of the fifth transistor 50. It should be understood that, in alternative embodiments, the first electrode may also be the source 52 of the fifth transistor 50. In some embodiments, the first electrode of the first transistor 10 is coupled to a reference voltage terminal V. ref In some embodiments, the reference voltage terminal V ref It can be the ground end. In Figure 2In the illustrated embodiment, the first electrode can be the source 12 of the first transistor 10. It should be understood that, in alternative embodiments, the first electrode can also be the drain 13 of the first transistor 10. Since the first transistor 10 and the fifth transistor 50 form a matching circuit, the voltage V pre-charged on the matching line ML... dd It will then be coupled to the reference voltage terminal V through this matching circuit. ref This causes the voltage output by the matching line ML to be low, which precisely indicates that the input data ("0") is inconsistent with the pre-stored data ("1"), which also means that the input data and the pre-stored data do not match.

[0048] If the input data is 1, according to the correspondence in Table 2, the voltage terminal V coupled to the control gate 11 of the first transistor 10 is... CG1 The voltage terminal V coupled to the select gate 14 of the first transistor 10 SG1 The voltage terminal V coupled to the control gate 21 of the second transistor 20 CG2 The voltage of the second transistor 20 and the voltage terminal V coupled to the select gate 24 of the second transistor 20. SG2 V a V a V b and V b For the first transistor 10, from Figure 5 It can be seen that, due to V a The voltage is low, therefore the first transistor 10 cannot be turned on via the control gate 11 or the select gate 14. In this case, the first transistor 10 and the fifth transistor 50 cannot form a matching circuit. Similarly, since the second transistor 20 stores 0 data, it cannot form a matching circuit with the sixth transistor 60. In other words, neither of the matching circuits on either side is turned on, and the pre-charged voltage V on the matching line ML is low. dd It will not be coupled to the reference voltage terminal V through any circuit. ref This causes the voltage output by the matching line ML to be high, which precisely indicates that the input data ("1") is consistent with the pre-stored data ("1"), meaning that the input data and the pre-stored data are matched.

[0049] Assuming the first transistor 10 stores 0 data and the second transistor 20 stores 1 data, referring to Table 1, this indicates that the data read / written in the preceding read / write mode is 0. In this case, if the input data is 0, according to the correspondence in Table 2, the voltage terminal V coupled to the control gate 11 of the first transistor 10... CG1 The voltage terminal V coupled to the select gate 14 of the first transistor 10 SG1The voltage terminal V coupled to the control gate 21 of the second transistor 20 CG2 The voltage of the second transistor 20 and the voltage terminal V coupled to the select gate 24 of the second transistor 20. SG2 V b V b V a and V a For the first transistor 10, since its stored data is 0, the first transistor 10 and the fifth transistor 50 cannot form a matched circuit. For the second transistor 20, since V... a The voltage is low, therefore the second transistor 20 cannot be turned on via the control gate 21 or the selection gate 24. In this case, the second transistor 20 and the sixth transistor 50 cannot form a matching circuit. That is, the matching circuits on both sides are not turned on, and the pre-charged voltage V on the matching line ML... dd It will not be coupled to the reference voltage terminal V through any circuit. ref This causes the voltage output by the matching line ML to be high, which precisely indicates that the input data ("0") is the same as the pre-stored data ("0"), meaning that the input data and the pre-stored data are matched.

[0050] If the input data is 1, according to the correspondence in Table 2, the voltage terminal V coupled to the control gate 11 of the first transistor 10 is... CG1 The voltage terminal V coupled to the select gate 14 of the first transistor 10 SG1 The voltage terminal V coupled to the control gate 21 of the second transistor 20 CG2 The voltage of the second transistor 20 and the voltage terminal V coupled to the select gate 24 of the second transistor 20. SG2 V a V a V b and V b Because of V b The voltage is high and the second data stored in the second transistor 20 is 1, therefore the second transistor 20 can be turned on via the control gate 21 and the select gate 24. At this time, the second transistor 20 and the sixth transistor 60 form a matching circuit. In some embodiments, the first terminal of the sixth transistor 60 is coupled to the matching line ML. Figure 2 In the illustrated embodiment, the first electrode may be the drain 63 of the sixth transistor 60. It should be understood that, in alternative embodiments, the first electrode may also be the source 62 of the sixth transistor 60. In some embodiments, the first electrode of the second transistor 20 is coupled to a reference voltage terminal V. ref .exist Figure 2In the illustrated embodiment, the first electrode can be the source 22 of the second transistor 20. It should be understood that, in alternative embodiments, the first electrode can also be the drain 23 of the second transistor 20. Since the second transistor 20 and the sixth transistor 60 form a matching circuit, the voltage V pre-charged on the matching line ML... dd This matching circuit is coupled to the reference voltage terminal V. ref This causes the voltage output by the matching line ML to be low, which precisely indicates that the input data ("1") is not consistent with the pre-stored data ("0"), and also means that the input data and the pre-stored data do not match.

[0051] Therefore, considering the above situations, it can be seen that by appropriately setting the data read / write and data matching scheme of the storage circuit 1, not only can data be read and written, but it can also be used to determine whether the input data and the written data are consistent. According to an embodiment of this disclosure, by setting the semi-floating gate transistor as the matching line ML and the reference voltage terminal V... ref A portion of the pull-down circuit between the transistors can fully utilize the semi-floating gate transistor, thereby eliminating the overhead of additional transistors and further reducing the manufacturing cost of the memory circuit 1. Furthermore, since the control gate and select gate of the semi-floating gate transistor according to embodiments of this disclosure are separate, read and write operations can be more flexible. By applying different voltages to the select gate and control gate to perform data retention operations, the data retention time is extended.

[0052] In some embodiments, if the first data stored in the first transistor 10 is 0 and the second data stored in the second transistor 20 is 0, as shown in Table 1, this indicates that the data read and written in the preceding read / write mode is X. In this case, regardless of whether the input data is 0 or 1, since the data stored in both the first transistor 10 and the second transistor 20 is 0, the first transistor 10 and the fifth transistor 50 cannot form a matching circuit, and similarly, the second transistor 20 and the sixth transistor 60 cannot form a matching circuit. That is, the matching circuits on both sides are not conducting, and the voltage output by the matching line ML is high. Using this method, when the storage circuit 1 is used as a content-addressable memory circuit, it can not only realize the function of a two-state content-addressable memory, but also realize the function of a three-state content-addressable memory simultaneously.

[0053] The above combination Figures 2 to 5 The operation of storage circuit 1 is described, specifically for the operation of one bit of data. In another aspect of this disclosure, a circuit arrangement 600 comprising multiple storage circuits 1 is proposed. Figure 6As shown, the storage circuits 1 in the circuit device 600 are arranged in an array and can be configured in parallel, wherein the storage circuits 1 can be the storage circuits 1 in any of the embodiments described above. Figure 6 As shown, the circuit device 600 also includes multiple modules for coupling multiple storage circuits 1 together to realize the complete circuit device 600, such as a data decoding / word line control module 602, a mode control / bit line control module 604, a matching circuit module 606, etc. In this array, each row of storage circuits 1 shares a matching line ML, while storage circuits 1 in the same column share a gate line. The number of storage circuits 1 in the same row corresponds to the number of bits of input data. Only when every bit of data is completely matched can the matching line ML remain high. Conversely, if any bit of data is not matched, the matching line ML will go low. Therefore, different data can be stored in different rows of the circuit device 600. When external data is input, the data in all rows is matched simultaneously in parallel. The matching line ML of the row containing the matched data remains high, which means that the storage address of the data can be located, thereby completing the content-addressable memory function of the circuit device 600.

[0054] In some embodiments, the storage circuit 1 according to embodiments of the present disclosure can be used to manufacture content-addressable memory. It should be understood that this is merely illustrative and not limiting. The storage circuit 1 according to embodiments of the present disclosure can perform other functions, such as calculating Hamming distance, thereby playing a role in neural networks.

[0055] Compared to existing solutions, the embodiments of this disclosure use semi-floating gate transistors, which fully utilize the advantages of fast erase / write speed and low storage area of ​​semi-floating gate transistors, greatly reducing the area overhead of content-addressable memory circuits.

[0056] Although the subject matter has been described using language specific to structural features and / or methodological logic, it should be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or actions described above. Rather, the specific features and actions described above are merely illustrative examples of implementing the claims.

Claims

1. A storage circuit, comprising: The first transistor is configured to store the first stored data; The second transistor is configured to store the second stored data; A third transistor, wherein a first or second terminal of the third transistor is coupled to a second or first terminal of the first transistor, and the third transistor is configured to write the first stored data into the first transistor; A fourth transistor, wherein the first or second terminal of the fourth transistor is coupled to the second or first terminal of the second transistor, and the second or first terminal of the fourth transistor is coupled to the second or first terminal of the third transistor, and the fourth transistor is configured to write the second stored data to the second transistor; A fifth transistor, wherein the first or second terminal of the fifth transistor is coupled to the second or first terminal of the first transistor, the fifth transistor being configured to receive first input data and determine whether the first input data matches the first stored data; as well as A sixth transistor, wherein the second or first terminal of the sixth transistor is coupled to the second or first terminal of the second transistor, and the second or first terminal of the sixth transistor is coupled to the second or first terminal of the fifth transistor, is configured to receive second input data and determine whether the second input data matches the second stored data. The first terminals of the fifth transistor and the sixth transistor are both coupled to the matching line. The first terminal of the first transistor and the first terminal of the second transistor are coupled to the reference voltage terminal.

2. The storage circuit of claim 1, wherein the gate of the third transistor and the gate of the fourth transistor are jointly coupled to a first voltage terminal, and the third transistor and the fourth transistor are configured to: receive a first control signal from the first voltage terminal, and turn on or off according to the first control signal.

3. The storage circuit according to any one of claims 1 to 2, wherein the gate of the fifth transistor and the gate of the sixth transistor are commonly coupled to a second voltage terminal, and the fifth transistor and the sixth transistor are configured to receive a second control signal from the second voltage terminal and to turn on or off according to the second control signal.

4. The storage circuit according to any one of claims 1 to 3, wherein the first terminal of the third transistor and the first terminal of the fourth transistor are coupled together to a third voltage terminal.

5. The memory circuit according to any one of claims 1 to 4, wherein one or both of the first transistor and the second transistor are semi-floating gate transistors, and wherein the first transistor includes a control gate and a select gate, and the second transistor includes a control gate and a select gate.

6. The storage circuit according to any one of claims 1 to 5, wherein one or both of the first transistor and the second transistor are floating gate transistors.

7. A method of operating a memory circuit according to any one of claims 1 to 6, wherein the gate of the third transistor and the gate of the fourth transistor are commonly coupled to a first voltage terminal, and the gate of the fifth transistor and the gate of the sixth transistor are commonly coupled to a second voltage terminal. The method includes: Apply a first voltage level to the first voltage terminal; as well as A second voltage level is applied to the second voltage terminal, wherein the second voltage level is lower than the first voltage level, to turn on the third transistor and the fourth transistor and turn off the fifth transistor and the sixth transistor, thereby putting the circuit into read / write mode.

8. The method according to claim 7, further comprising: Apply a third voltage level to the first voltage terminal; as well as A fourth level is applied to the second voltage terminal, wherein the fourth level is higher than the third level, to disconnect the third transistor and the fourth transistor and turn on the fifth transistor and the sixth transistor, so that the circuit is in a matched mode.

9. The method of claim 7, wherein the first transistor and the second transistor are semi-floating gate transistors, the method further comprising: A fifth level is applied to the control gate and the selection gate of the first transistor; as well as A sixth level is applied to the control gate and select gate of the second transistor, wherein the fifth level and the sixth level are associated with the data to be read or written.

10. The method of claim 8, wherein the first transistor and the second transistor are semi-floating gate transistors, the method further comprising: A seventh level is applied to the control gate and the selection gate of the first transistor; as well as An eighth level is applied to the control gate and the selection gate of the second transistor, wherein the seventh level and the eighth level are associated with the data to be matched.

11. A memory array comprising a plurality of memory circuits according to any one of claims 1 to 6, wherein the plurality of memory circuits are arranged in an array.

12. A memory comprising: Controller; as well as The storage array according to claim 11.

13. An electronic device, comprising: Circuit board; as well as The memory according to claim 12 is disposed on the circuit board.

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