Semiconductor structure and its fabrication method

Abstract

This application provides a semiconductor structure and a method for fabricating the semiconductor structure to solve the problem of high pattern roughness after transfer in related technologies. The semiconductor structure includes a substrate, a first mask layer disposed on the substrate, a photoresist layer covering the top surface of the first mask layer, and a composite anti-reflection layer disposed between the first mask layer and the photoresist layer. The composite anti-reflection layer includes a first layer and a second layer, with the second layer located on the side of the first layer away from the first mask layer. The extinction coefficient of the second layer is greater than that of the first layer. Compared to dielectric anti-reflection layers with low extinction coefficients in related technologies, this application embodiment, by providing a second layer with a higher extinction coefficient, can improve the absorption capacity of the composite anti-reflection layer for reflected light, improve photolithography accuracy, and reduce the roughness of the transferred pattern.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for fabricating the semiconductor structure. Background Technology

[0002] In a semiconductor structure, a light source from an exposure unit passes through a mask with several patterns, transferring the patterns from the mask to the underlying photoresist layer. When the semiconductor substrate beneath the photoresist layer has high reflectivity, the light source will be reflected off the substrate surface, resulting in incorrect pattern transfer.

[0003] In related technologies, a dielectric antireflective layer is typically placed between the substrate and the photoresist layer to absorb reflected light from the light source. However, these technologies also suffer from the problem of high pattern roughness after transfer. Summary of the Invention

[0004] This application provides a semiconductor structure and a method for fabricating the semiconductor structure to solve the problem of high pattern roughness after transfer in related technologies.

[0005] In a first aspect, embodiments of this application provide a semiconductor structure including a substrate, a first mask layer disposed on the substrate, a photoresist layer covering the top surface of the first mask layer, a composite anti-reflection layer disposed between the first mask layer and the photoresist layer, the composite anti-reflection layer including a first layer and a second layer, the second layer being located on the side of the first layer away from the first mask layer, and the extinction coefficient of the second layer being greater than the extinction coefficient of the first layer.

[0006] In one possible implementation, the composite antireflective layer is formed by plasma chemical vapor deposition, with the second layer and the first layer formed within the same reaction chamber.

[0007] In one possible implementation, an etch stop layer is provided between the substrate and the first mask layer, the etch stop layer having a different etch selectivity than the first layer.

[0008] In one possible implementation, a second mask layer is disposed between the substrate and the etch stop layer, the etch stop layer being made of the same material as the second layer, and the extinction coefficient of the etch stop layer being greater than that of the first layer.

[0009] In one possible implementation, the thickness of the second layer ranges from 2nm to 10nm.

[0010] In one possible implementation, there is an interface between the second layer and the first layer.

[0011] In one possible implementation, the material of the first mask layer and / or the second mask layer includes carbon.

[0012] In one possible implementation, both the first and second layers are made of silicon oxynitride, and the mass percentages of silicon, oxygen, and nitrogen in the second layer differ from those in the first layer.

[0013] Secondly, embodiments of this application also provide a method for fabricating a semiconductor structure, comprising:

[0014] A substrate is provided, on which a first mask layer is disposed;

[0015] A composite anti-reflection layer is formed on the first mask layer. The composite anti-reflection layer includes a second layer and a first layer. The second layer is located on the side of the first layer away from the first mask layer. The extinction coefficient of the second layer is greater than that of the first layer.

[0016] A photoresist layer is formed on the composite antireflective layer.

[0017] In one possible implementation, the composite antireflective layer is formed using a plasma chemical vapor deposition process, with the second layer and the first layer formed within the same reaction chamber.

[0018] In one possible implementation, the plasma chemical vapor deposition process includes a first deposition stage and a second deposition stage, wherein the reactant gases in the first deposition stage include silane, nitrous oxide, nitrogen, and helium, and the reactant gases in the second deposition stage include silane, nitrous oxide, and helium.

[0019] In one possible implementation, after providing the substrate and before forming the composite antireflective layer, the method further includes forming an etch stop layer located between the substrate and the first mask layer, the etch stop layer having a different etch selectivity than the first layer.

[0020] In one possible implementation, after providing the substrate and before forming the etch stop layer, the method further includes: forming a second mask layer located between the substrate and the etch stop layer, the etch stop layer being made of the same material as the second layer, and the extinction coefficient of the etch stop layer being greater than that of the first layer.

[0021] In one possible implementation, after forming the photoresist layer, the method further includes:

[0022] The photomask pattern is transferred to the photoresist layer using a photolithography process;

[0023] Using the photoresist layer as a mask, a portion of the composite antireflective layer and the first mask layer are removed;

[0024] Remove the remaining composite anti-reflective layer.

[0025] In one possible implementation, removing the remaining composite antireflective layer includes: removing the remaining second layer using dry etching and removing the remaining first layer using wet etching.

[0026] This application provides a semiconductor structure and a method for fabricating the semiconductor structure. The semiconductor structure includes a substrate, a first mask layer disposed on the substrate, a photoresist layer covering the top surface of the first mask layer, and a composite anti-reflection layer disposed between the first mask layer and the photoresist layer. The composite anti-reflection layer includes a first layer and a second layer, with the second layer located on the side of the first layer away from the first mask layer. The extinction coefficient of the second layer is greater than that of the first layer. Compared with dielectric anti-reflection layers with low extinction coefficients in related technologies, this application embodiment, by providing a second layer with a higher extinction coefficient, can improve the absorption capacity of the composite anti-reflection layer for reflected light, improve photolithography accuracy, and reduce the roughness of the transferred pattern. Attached Figure Description

[0027] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0028] Figure 1 This is a schematic diagram of the structure in which the light source propagates in the dielectric antireflective layer.

[0029] Figure 2 This is a schematic diagram of a semiconductor structure provided in an embodiment of this application;

[0030] Figure 3 A flowchart illustrating the steps of a method for fabricating a semiconductor structure, as provided in this application embodiment;

[0031] Figure 4 This is a schematic diagram of the structure for forming a photoresist layer in a method for fabricating a semiconductor structure according to an embodiment of this application;

[0032] Figure 5 This is a schematic diagram of the structure in which a mask pattern is transferred to a photoresist layer in a method for fabricating a semiconductor structure according to an embodiment of this application.

[0033] Figure 6 This is a schematic diagram of a semiconductor structure fabrication method involving the removal of the remaining second layer, provided in an embodiment of this application.

[0034] Figure 7 This is a schematic diagram of a semiconductor structure fabrication method provided in this application, in which the remaining first layer is removed. Detailed Implementation

[0035] The inventors of this application discovered during their research that, in the fabrication of semiconductor structures, a dielectric anti-reflective layer is typically placed between the substrate and the photoresist layer to increase the accuracy of the photolithography process. It is worth noting that, referring to... Figure 1 The dielectric anti-reflection layer 60 can achieve good phase shift and form destructive interference, thereby absorbing reflected light from the light source of the exposure equipment, avoiding dimensional deviations, and thus improving the accuracy of the photolithography process. The extinction coefficient of the dielectric anti-reflection layer 60 characterizes its ability to absorb reflected light; a larger extinction coefficient indicates stronger light absorption and less susceptibility to reflection. However, the dielectric anti-reflection layer 60 in related technologies is a single film layer with a low extinction coefficient, resulting in poor absorption of reflected light and high pattern roughness after transfer.

[0036] In view of this, embodiments of this application provide a semiconductor structure and a method for fabricating the semiconductor structure. The semiconductor structure includes a substrate, a first mask layer disposed on the substrate, a photoresist layer covering the top surface of the first mask layer, and a composite anti-reflection layer disposed between the first mask layer and the photoresist layer. The composite anti-reflection layer includes a first layer and a second layer, with the second layer located on the side of the first layer away from the first mask layer. The extinction coefficient of the second layer is greater than that of the first layer. Compared with dielectric anti-reflection layers with low extinction coefficients in related technologies, embodiments of this application, by providing a second layer with a higher extinction coefficient, can improve the absorption capacity of the composite anti-reflection layer for reflected light, improve photolithography accuracy, and reduce the roughness of the transferred pattern.

[0037] To make the objectives, technical solutions, and advantages of this disclosure clearer, the technical solutions in the embodiments of this disclosure will be described in more detail below with reference to the accompanying drawings. In the drawings, the same or similar reference numerals denote the same or similar components or components having the same or similar functions throughout. The described embodiments are some, but not all, embodiments of this disclosure. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain this disclosure, and should not be construed as limiting this disclosure. All other embodiments obtained by those skilled in the art based on the embodiments of this disclosure without creative effort are within the scope of protection of this disclosure. The embodiments of this disclosure will be described in detail below with reference to the accompanying drawings.

[0038] It should be noted that the semiconductor structure provided in this application embodiment can be a memory device or a non-memory device. Memory devices may include, for example, Dynamic Random Access Memory (DRAM), Static Random Access Memory (SRAM), flash memory, Electrically Erasable Programmable Read-Only Memory (EEPROM), Phase Change Random Access Memory (PRAM), or Magnetoresistive Random Access Memory (MRAM). Non-memory devices may be logic devices (e.g., microprocessors, digital signal processors, or microcontrollers) or similar devices. This application embodiment uses DRAM memory devices as an example for illustration.

[0039] Reference Figure 2 The semiconductor structure provided in this application includes a substrate 10, and a first mask layer 21, a composite anti-reflection layer 40 and a photoresist layer 50 disposed on the substrate 10.

[0040] In this composite anti-reflective layer, a first mask layer 21 covers the top surface of the substrate 10, a photoresist layer 50 covers the top surface of the first mask layer 21, and a composite anti-reflective layer 40 is located between the first mask layer 21 and the photoresist layer 50. The composite anti-reflective layer 40 includes a first layer 41 and a second layer 42. The first layer 41 covers the top surface of the first mask layer 21, and the second layer 42 is located on the side of the first layer 41 away from the first mask layer 21. The extinction coefficient of the second layer 42 is greater than that of the first layer 41. When light from the exposure unit reaches the second layer 42 in the composite anti-reflective layer 40, the higher extinction coefficient of the second layer 42 results in a good phase shift, which can form destructive interference. This absorbs the reflected light from the exposure unit, improving photolithography accuracy and reducing the roughness of the transferred pattern.

[0041] This application provides a semiconductor structure including a substrate 10. A first mask layer 21 is disposed on the substrate 10, and a photoresist layer 50 is covered on the top surface of the first mask layer 21. A composite anti-reflection layer 40 is disposed between the first mask layer 21 and the photoresist layer 50. The composite anti-reflection layer 40 includes a first layer 41 and a second layer 42. The second layer 42 is located on the side of the first layer 41 away from the first mask layer 21, and the extinction coefficient of the second layer 42 is greater than that of the first layer 41. Compared with dielectric anti-reflection layers with low extinction coefficients in related technologies, this application embodiment improves the absorption capacity of the composite anti-reflection layer 40 for reflected light by providing a second layer 42 with a higher extinction coefficient, thereby improving photolithography accuracy and reducing the roughness of the transferred pattern.

[0042] It is worth noting that the "roughness" in this application refers to edge roughness and linewidth roughness. Edge roughness describes the roughness of the pattern edge, representing the deviation between the pattern edge and the ideal shape. Edge roughness can characterize the deviation between the edge point in different regions of the pattern and the center line of the line edge. Linewidth roughness describes the deviation of the linewidth from the target value due to edge roughness. Linewidth roughness can characterize the deviation between the linewidth value and the average linewidth value between two edge points in different regions. In this embodiment, by providing a second layer 42 with a higher extinction coefficient, the absorption capacity of the composite anti-reflection layer 40 for reflected light can be improved, reducing the roughness of the transferred pattern edge, thereby reducing edge roughness and linewidth roughness and improving the performance of the semiconductor structure.

[0043] It is worth noting that after the photolithography process transfers the pattern onto the photoresist layer 50, a portion of the composite anti-reflection layer 40 and a portion of the first mask layer 21 need to be removed using the photoresist layer 50 as a mask, so that the first mask layer 21 has a first mask pattern. After forming the first mask pattern, a portion of the substrate 10 needs to be removed using the first mask pattern as a mask to transfer the photolithographic pattern onto the substrate 10. Specifically, after forming the first mask pattern but before removing a portion of the substrate 10, the remaining composite anti-reflection layer 40 also needs to be removed to prevent it from covering the first mask layer 21. The remaining composite anti-reflection layer 40 will increase the aspect ratio of the structure in the first mask pattern, making it impossible to maintain an upright shape, thus causing structural defects. In this embodiment, since the extinction coefficient of the second layer 42 is greater than that of the first layer 41, the first layer 41, which has a lower extinction coefficient, is easily removed by wet etching, preventing the remaining composite anti-reflection layer 40 from covering the first mask layer 21, thereby avoiding structural defects.

[0044] In this embodiment, both the first layer 41 and the second layer 42 can be made of silicon oxynitride, but the mass percentages of silicon, oxygen, and nitrogen in the first layer 41 and the second layer 42 are different. In some embodiments, the mass percentages of silicon, oxygen, and nitrogen in the second layer 42 can range from 40% to 70%, 15% to 35%, and 1% to 7%, respectively. For example, the mass percentage of silicon in the second layer 42 can be 40%, 60%, or 70%, the mass percentage of oxygen can be 15%, 20%, or 35%, and the mass percentage of nitrogen can be 1%, 5%, or 7%. In some embodiments, the mass percentages of silicon, oxygen, and nitrogen in the first layer 41 can range from 20% to 50%, 40% to 70%, and 5% to 15%, respectively. For example, the mass percentage of silicon in the first layer 41 can be 20%, 37%, or 50%, the mass percentage of oxygen can be 40%, 60%, or 70%, and the mass percentage of nitrogen can be 5%, 10%, or 15%. By setting the first layer 41 and the second layer 42 with the aforementioned element mass percentages, the extinction coefficient of the second layer 42 can be made greater than that of the first layer 41. In one specific implementation, the extinction coefficient of the first layer 41 can range from 0.1 to 0.5, for example, 0.1, 0.2, or 0.25. The extinction coefficient of the second layer 42 can range from 1 to 1.4, for example, 1, 1.2, or 1.3. By setting the first layer 41 and the second layer 42 with the aforementioned element mass percentages, it is beneficial to ensure that the second layer 42 has good light absorption and reflection capabilities while ensuring that the first layer 41 can be removed by wet etching, thereby improving the performance of the semiconductor structure.

[0045] In this embodiment, the composite antireflective layer 40 can be formed by plasma chemical vapor deposition (PCVDC), and the second layer 42 and the first layer 41 can be formed within the same reaction chamber. In PCVDC, the source gas is ionized to form plasma under a high-frequency or DC electric field. Using low-temperature plasma as an energy source, a suitable amount of reactive gas is introduced, and plasma discharge activates the reactive gas, causing a chemical reaction that forms a solid film. Since the first layer 41 and the second layer 42 are formed within the same reaction chamber, they can be formed using the same deposition process, which simplifies the fabrication process of the composite antireflective layer 40 and improves the fabrication efficiency of the semiconductor structure. Furthermore, since the first layer 41 and the second layer 42 are formed within the same reaction chamber, the reactive gases used to fabricate them are the same, ensuring that the materials of the first layer 41 and the second layer 42 are identical. This further simplifies the fabrication process of the composite antireflective layer 40 and reduces the fabrication cost of the semiconductor structure.

[0046] In this embodiment, the process of fabricating the composite antireflective layer 40 using plasma chemical vapor deposition (PCVDC) may include a first deposition stage and a second deposition stage, wherein the first and second deposition stages occur within the same reaction chamber. The first deposition stage is used to deposit and form a first layer 41, and the second deposition stage is used to deposit and form a second layer 42. For example, in this embodiment, by changing the set parameters of the PCVDC equipment, and thus changing the reaction gases in the first and second deposition stages, first layers 41 and second layers 42 with different extinction coefficients can be prepared.

[0047] Furthermore, by fabricating the first layer 41 and the second layer 42 through the above deposition process, an interface can be formed between the first layer 41 and the second layer 42. Because of this interface, it is advantageous to use different etching methods to remove the first layer 41 and the second layer 42 separately, avoiding the remaining composite anti-reflection layer 40 covering the first mask layer 21, thereby preventing structural defects. Furthermore, the interface between the first layer 41 and the second layer 42 also helps to improve the optical properties of the second layer 42, further absorbing reflected light and reducing the roughness of the transferred pattern. Of course, in some other embodiments, the first layer 41 and the second layer 42 can also be interleaved and bonded together; this embodiment does not limit this.

[0048] Furthermore, the thickness of the second layer 42 can be adjusted by controlling the deposition time of the second deposition stage. In this embodiment, the thickness of the second layer 42 can range from 2nm to 10nm, for example, the thickness of the second layer 42 can be 2nm, 5nm, or 10nm. By limiting the thickness of the second layer 42, it is beneficial to remove the remaining second layer 42, avoid the remaining composite anti-reflection layer 40 covering the first mask layer 21, and thus avoid structural defects. Furthermore, by limiting the thickness of the second layer 42, it is also beneficial to further improve the optical properties of the second layer 42, further absorb reflected light, and reduce the roughness of the transferred pattern.

[0049] Continue to refer to Figure 2 An etch stop layer 30 may also be provided between the substrate 10 and the first mask layer 21. The etch stop layer 30 has a different etch selectivity than the first layer 41. During the removal of the remaining composite antireflective layer 40, when the first layer 41 is etched away, the etching stops at the etch stop layer 30 because the etch selectivity of the first layer 41 is different from that of the etch stop layer 30, thus avoiding further etching of the substrate 10.

[0050] Continue to refer to Figure 2A second mask layer 22 may be disposed between the substrate 10 and the etch stop layer 30. The etch stop layer 30 and the composite anti-reflection layer 40 are made of the same material, and the extinction coefficient of the etch stop layer 30 is greater than that of the first layer 41. Since the etch stop layer 30 and the composite anti-reflection layer 40 are made of the same material, it is beneficial to further simplify the semiconductor structure fabrication process and improve the semiconductor structure fabrication efficiency. Furthermore, the fact that the extinction coefficient of the etch stop layer 30 is greater than that of the first layer 41 helps to ensure that the etch selectivity ratios of the first layer 41 and the etch stop layer 30 are different, thereby avoiding further etching of the substrate 10.

[0051] In this embodiment, the first mask layer 21 and / or the second mask layer 22 are made of carbon. In one specific implementation, the first mask layer 21 and / or the second mask layer 22 can be formed using a spin coating process, which helps to reduce the manufacturing cost of the semiconductor structure.

[0052] Based on the above embodiments, referring to Figure 3 and Figure 4 As shown, this application provides a method for fabricating a semiconductor structure, comprising the following steps:

[0053] S101. Provide a substrate, on which a first mask layer is disposed.

[0054] The substrate 10 can provide a structural basis for subsequent structures and processes. The material of the substrate 10 may include any one or more of silicon, germanium, silicon-germanium, silicon carbide, silicon-on-insulator substrate 10, and germanium-on-insulator substrate 10. In this embodiment, the substrate 10 may be made of silicon.

[0055] In this embodiment, after providing the substrate 10, a first mask layer 21 is formed on the substrate 10. As described in the above embodiment, the first mask layer 21 can be made of carbon. In the specific formation process, a spin coating process can be used to form the first mask layer 21 on the substrate 10, thereby simplifying the semiconductor structure fabrication process and improving the semiconductor structure fabrication efficiency.

[0056] In this embodiment, after forming the first mask layer 21, the method further includes:

[0057] S102. A composite anti-reflection layer is formed on the first mask layer. The composite anti-reflection layer includes a second layer and a first layer. The second layer is located on the side of the first layer away from the first mask layer. The extinction coefficient of the second layer is greater than that of the first layer.

[0058] In this embodiment, a composite antireflective layer 40 can be formed using plasma chemical vapor deposition (PCVD), with a second layer 42 and a first layer 41 formed within the same reaction chamber. Since the first layer 41 and the second layer 42 are formed within the same reaction chamber, they can be formed by the same deposition process, which simplifies the fabrication process of the composite antireflective layer 40 and improves the fabrication efficiency of the semiconductor structure.

[0059] In this embodiment, the plasma chemical vapor deposition process may include a first deposition stage and a second deposition stage. By changing the setting parameters of the plasma chemical vapor deposition equipment, the reaction gases in the first and second deposition stages can be changed, thereby preparing a first layer 41 and a second layer 42 with different extinction coefficients.

[0060] In this embodiment, both the first layer 4 and the second layer 42 are made of silicon oxynitride. The reaction gases in the first deposition stage include silane, nitrous oxide, nitrogen, and helium. The flow rates of silane can range from 90 sccm to 120 sccm, nitrous oxide from 300 sccm to 400 sccm, nitrogen from 9000 sccm to 12000 sccm, and helium from 10000 sccm to 13000 sccm. For example, in the first deposition stage, the flow rate of silane can be 90 sccm, 100 sccm, or 120 sccm; the flow rate of nitrous oxide can be 300 sccm, 350 sccm, or 400 sccm; the flow rate of nitrogen can be 9000 sccm, 11000 sccm, or 12000 sccm; and the flow rate of helium can be 10000 sccm, 11000 sccm, or 13000 sccm.

[0061] The reactant gases in the second deposition stage include silane, nitrogen dioxide, and helium. The flow rates of silane can range from 150 sccm to 320 sccm, nitrogen dioxide from 50 sccm to 100 sccm, and helium from 9000 sccm to 13000 sccm. For example, in the second deposition stage, the flow rates of silane can be 150 sccm, 250 sccm, or 320 sccm; the flow rates of nitrogen dioxide can be 50 sccm, 80 sccm, or 100 sccm; and the flow rates of helium can be 9000 sccm, 11000 sccm, or 13000 sccm.

[0062] Through the above manufacturing process, the extinction coefficient of the second layer 42 can be made greater than that of the first layer 41. In one specific implementation, the extinction coefficient of the first layer 41 can range from 0.1 to 0.5, for example, 0.1, 0.2, or 0.25. The extinction coefficient of the second layer 42 can range from 1 to 1.4, for example, 1, 1.2, or 1.3.

[0063] In this embodiment, after the composite anti-reflection layer 40 is formed on the first mask layer 21, the method further includes:

[0064] S103. A photoresist layer is formed on the composite antireflective layer.

[0065] In this embodiment, the composite anti-reflection layer 40 is located between the photoresist layer 50 and the first mask layer 21. When the light source from the exposure machine is transmitted to the second layer 42 in the composite anti-reflection layer 40, the second layer 42 has a high extinction coefficient and therefore has a good phase shift, which can form destructive interference, thereby absorbing the reflected light from the light source of the exposure machine, improving the photolithography accuracy, and reducing the roughness of the transferred pattern.

[0066] This application provides a method for fabricating a semiconductor structure, including: providing a substrate 10, on which a first mask layer 21 is disposed; forming a composite anti-reflection layer 40 on the first mask layer 21, the composite anti-reflection layer 40 including a second layer 42 and a first layer 41, the second layer 42 being located on the side of the first layer 41 away from the first mask layer 21, and the extinction coefficient of the second layer 42 being greater than the extinction coefficient of the first layer 41; and forming a photoresist layer 50 on the composite anti-reflection layer 40. Compared with dielectric anti-reflection layers with low extinction coefficients in related technologies, this application embodiment, by providing a second layer 42 with a higher extinction coefficient, can improve the absorption capability of the composite anti-reflection layer 40 for reflected light, improve photolithography accuracy, and reduce the roughness of the transferred pattern.

[0067] In this embodiment, after forming the photoresist layer 50 on the composite anti-reflection layer 40, the method further includes: transferring the mask pattern to the photoresist layer 50 using a photolithography process. In one specific implementation, the photoresist layer 50 in the exposed portion can be altered through an exposure process, and then a portion of the photoresist layer 50 can be removed through a development process, thereby transferring the mask pattern to the photoresist layer 50.

[0068] In this embodiment, refer to Figure 5After forming the photoresist layer 50 on the composite anti-reflection layer 40, the method further includes: after transferring the mask pattern to the photoresist layer 50, removing a portion of the composite anti-reflection layer 40 and the first mask layer 21 using the photoresist layer 50 as a mask. After forming the first mask pattern, it is necessary to continue removing a portion of the substrate 10 using the first mask pattern as a mask, so that the photolithographic pattern can be transferred onto the substrate 10.

[0069] In this embodiment, after forming the photoresist layer 50 on the composite anti-reflection layer 40, the method further includes: removing the remaining composite anti-reflection layer 40 after removing a portion of the composite anti-reflection layer 40 and the first mask layer 21, to prevent the remaining composite anti-reflection layer 40 from covering the first mask layer 21. The remaining composite anti-reflection layer 40 would increase the aspect ratio of the structure in the first mask pattern, making it impossible to maintain an upright shape, thus causing structural defects. In this embodiment, since the extinction coefficient of the second layer 42 is greater than that of the first layer 41, the first layer 41, which has a lower extinction coefficient, is easily removed by wet etching, preventing the remaining composite anti-reflection layer 40 from covering the first mask layer 21, thereby avoiding structural defects.

[0070] In one possible implementation, refer to Figure 6 and Figure 7 The step of removing the remaining composite anti-reflective layer 40 may include: removing the remaining second layer 42 using dry etching, and removing the remaining first layer 41 using wet etching. Removing the remaining first layer 41 and second layer 42 using the above etching method can prevent the remaining composite anti-reflective layer 40 from covering the first mask layer 21, thereby avoiding structural defects. As described in the above embodiments, for composite anti-reflective layers 40 with different extinction coefficients, structures with lower extinction coefficients are easier to remove by wet etching, while structures with higher extinction coefficients are not easily removed by wet etching.

[0071] In this embodiment, dry etching can be used to remove the second layer 42, which has a higher extinction coefficient. During the dry etching process, the etching gas may include, for example, trifluoromethane (CHF3) and tetrafluoromethane (CF4). The etching rate for the first layer 41 ranges from 50 nm / min to 60 nm / min, and the etching rate for the second layer 42 ranges from 20 nm / min to 42 nm / min. Therefore, dry etching is advantageous for removing the second layer 42, which has a higher extinction coefficient.

[0072] In this embodiment, after removing the remaining second layer 42, the first layer 41 with a higher extinction coefficient can be removed by wet etching. During wet etching, the etching solution may include dilute hydrofluoric acid, with a volume ratio of hydrofluoric acid to water ranging from 1:25 to 1:35, for example, 1:25, 1:30, or 1:35. The wet etching rate for the first layer 41 is 70 nm / min to 95 nm / min, and the etching rate for the second layer 42 is 0.2 nm / min to 0.8 nm / min. Therefore, wet etching is advantageous for removing the second layer 42 with a higher extinction coefficient.

[0073] In this embodiment, after providing the substrate 10 and before forming the first mask layer 21, the method further includes forming an etch stop layer 30. The etch stop layer 30 is located between the substrate 10 and the first mask layer 21, and the etch stop layer 30 has a different etch selectivity than the first layer 41. As described in the above embodiment, during the removal of the remaining composite anti-reflective layer 40, when etching away the first layer 41, the etching stops at the etch stop layer 30 because the etch selectivity of the first layer 41 and the etch stop layer 30 is different, thereby preventing further etching of the substrate 10.

[0074] In this embodiment, after providing the substrate 10 and before forming the first mask layer 21, the method further includes forming a second mask layer 22. The second mask layer 22 is located between the substrate 10 and the etch stop layer 30. The etch stop layer 30 is made of the same material as the composite anti-reflection layer 40, and the extinction coefficient of the etch stop layer 30 is greater than that of the first layer 41. As described in the above embodiment, since the etch stop layer 30 and the composite anti-reflection layer 40 are made of the same material, it is beneficial to further simplify the semiconductor structure fabrication process and improve the semiconductor structure fabrication efficiency. Furthermore, the fact that the extinction coefficient of the etch stop layer 30 is greater than that of the first layer 41 helps to ensure that the etch selectivity ratios of the first layer 41 and the etch stop layer 30 are different, thereby avoiding further etching of the substrate 10.

[0075] Furthermore, since a second mask layer 22 is provided, in this embodiment, after the first mask pattern is formed on the first mask layer 21, the first mask pattern can be used as a mask to continue removing part of the etch stop layer 30 and part of the second mask layer 22, so as to form a second mask pattern on the second mask layer 22.

[0076] As described in the above embodiments, the material of the second mask layer 22 can be carbon. In the specific formation process, the second mask layer 22 can be formed on the substrate 10 by spin coating, thereby simplifying the semiconductor structure fabrication process and improving the semiconductor structure fabrication efficiency.

[0077] In the foregoing description, it should be understood that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linkage" should be interpreted broadly. For example, they can refer to a fixed connection or an indirect connection through an intermediate medium, or the internal connection of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this disclosure according to the specific circumstances. The terms "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this disclosure and simplifying the description, and do not indicate or imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this disclosure. In the description of this disclosure, "a plurality of" means two or more, unless otherwise precisely and specifically specified.

[0078] The terms “first,” “second,” “third,” “fourth,” etc. (if present) in the specification, claims, and accompanying drawings of this disclosure are used to distinguish similar objects and are not necessarily used to describe a particular order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this disclosure described herein can be implemented, for example, in orders other than those illustrated or described herein. Furthermore, the terms “comprising” and “having,” and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0079] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this disclosure, and are not intended to limit them. Although this disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this disclosure.

Claims

1. A semiconductor structure, characterized in that, The system includes a substrate, on which a first mask layer is disposed, the top surface of which is covered with a photoresist layer, and a composite anti-reflection layer is disposed between the first mask layer and the photoresist layer. The composite anti-reflection layer includes a first layer and a second layer, the second layer being located on the side of the first layer away from the first mask layer, and the extinction coefficient of the second layer being greater than that of the first layer. The composite anti-reflection layer is formed by plasma chemical vapor deposition, and the second layer and the first layer are formed in the same reaction chamber. An etch stop layer is disposed between the substrate and the first mask layer, and the etch stop layer has a different etch selectivity than that of the first layer. A second mask layer is disposed between the substrate and the etch stop layer, the etch stop layer being made of the same material as the second layer, and the extinction coefficient of the etch stop layer being greater than that of the first layer.

2. The semiconductor structure according to claim 1, characterized in that, The thickness of the second layer ranges from 2nm to 10nm.

3. The semiconductor structure according to claim 1, characterized in that, There is an interface between the second layer and the first layer.

4. The semiconductor structure according to claim 1, characterized in that, Both the first and second layers are made of silicon oxynitride, and the mass percentages of silicon, oxygen, and nitrogen in the second layer are different from those in the first layer.

5. The semiconductor structure according to claim 1, characterized in that, The material of the first mask layer and / or the second mask layer includes carbon.

6. A method for fabricating a semiconductor structure, characterized in that, include: A substrate is provided, on which a first mask layer is disposed; A composite anti-reflection layer is formed on the first mask layer. The composite anti-reflection layer includes a second layer and a first layer. The second layer is located on the side of the first layer away from the first mask layer. The extinction coefficient of the second layer is greater than that of the first layer. A photoresist layer is formed on the composite antireflective layer; After providing the substrate and before forming the composite antireflective layer, the method further includes: forming an etch stop layer located between the substrate and the first mask layer, wherein the etch stop layer has a different etch selectivity than the first layer; after providing the substrate and before forming the etch stop layer, the method further includes: forming a second mask layer located between the substrate and the etch stop layer, wherein the etch stop layer is made of the same material as the second layer, and the extinction coefficient of the etch stop layer is greater than the extinction coefficient of the first layer.

7. The method for fabricating a semiconductor structure according to claim 6, characterized in that, The composite antireflective layer is formed using plasma chemical vapor deposition, with the second layer and the first layer formed within the same reaction chamber.

8. The method for fabricating a semiconductor structure according to claim 7, characterized in that, The plasma chemical vapor deposition process includes a first deposition stage and a second deposition stage. The reaction gases in the first deposition stage include silane, nitrous oxide, nitrogen, and helium, and the reaction gases in the second deposition stage include silane, nitrous oxide, and helium.

9. The method for fabricating a semiconductor structure according to any one of claims 6-8, characterized in that, After forming the photoresist layer, it also includes: The photomask pattern is transferred to the photoresist layer using a photolithography process; Using the photoresist layer as a mask, a portion of the composite antireflective layer and the first mask layer are removed; Remove the remaining composite anti-reflective layer.

10. The method for fabricating a semiconductor structure according to claim 9, characterized in that, Removing the remaining composite anti-reflective layer includes: removing the remaining second layer by dry etching and removing the remaining first layer by wet etching.

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