Method for manufacturing through silicon via in semiconductor substrate

Abstract

The application provides a method for manufacturing a through silicon via in a semiconductor substrate, comprising: forming a plurality of via trenches penetrating from a second main surface of the semiconductor substrate to a first main surface, and each end of the via trenches on the first main surface being covered by a corresponding via bottom electrode; forming an auxiliary electrode on the sidewall adjacent to the opening in the via trench; and plating a metal plug in the via trench through the plating electrode. The via bottom electrode is connected to the plating electrode through the electrode wire, a voltage is applied to the plating electrode, the metal plug is plated in the via trench with the via bottom electrode as the first seed layer, and the auxiliary electrode on the inner sidewall near the opening of the via trench is further used as the second seed layer in the later stage of plating, so that the self-bottom-up filling mode is realized, the plating rate is accelerated, the filling quality of the through silicon via is improved, and the manufacturing difficulty of the through silicon via is reduced.

Description

Technical Field

[0001] This invention relates to the field of manufacturing and packaging of semiconductor integrated circuits and microelectromechanical systems, and in particular to a method for manufacturing through-silicon vias (TSVs). Background Technology

[0002] Through-silicon vias (TSVs) are widely used in advanced packaging of semiconductor integrated circuits (ICs) and microelectromechanical systems (MEMS). For example, through TSV interconnect structures, MEMS and their driving circuits can be stacked and packaged together, which has the characteristics of high transmission bandwidth and low transmission delay.

[0003] Conventional through-silicon via (TSV) fabrication processes involve etching deep holes on a substrate, followed by electroplating using a seed layer deposited within the deep holes to achieve metal filling. However, blind vias fabricated on thicker substrates have higher aspect ratios, making it difficult to uniformly deposit the seed layer metal onto the sidewalls of the via using physical sputtering. Simultaneously, it is also challenging to uniformly fill the high aspect ratio vias with metal filler. Therefore, achieving high-density TSVs on thicker substrates is inherently challenging. To address this, a voltage is often applied to the bottom electrode of the via to achieve bottom-up metal filling.

[0004] On the other hand, via-middle technology, as the mainstream technology for manufacturing TSVs, enables the connection between the TSV and the metal in the circuit without etching multiple interconnect layers, making the process relatively simple. However, because there are devices on the front side of the substrate, it is difficult to connect the bottom electrode of the via to the plating voltage. Therefore, the lead-in method of the bottom electrode is critical in the fabrication of this type of TSV. The currently used lead-in method introduces unnecessary parameters such as parasitic capacitance, affecting the performance of the circuit. Summary of the Invention

[0005] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a method for fabricating through-silicon vias (TSVs) in a semiconductor substrate, which solves the problems of high aspect ratio and high efficiency metal filling in TSVs, as well as parasitic capacitance caused by the lead wire method of the bottom electrode in the existing fabrication process.

[0006] To achieve the above and other related objectives, the present invention provides a method for fabricating through-silicon vias (TSVs) in a semiconductor substrate, comprising the following steps:

[0007] A semiconductor substrate is provided, the semiconductor substrate including opposing first and second main surfaces;

[0008] A conductive pattern is formed on a first main surface of the semiconductor substrate. The conductive pattern includes an electroplating electrode, an electrode connection line, and a plurality of via bottom electrodes. The plurality of via bottom electrodes are electrically connected to the electroplating electrode through the electrode connection line. The electroplating electrode is at least partially exposed on the first main surface of the semiconductor substrate.

[0009] A plurality of through-hole trenches are formed from the second main surface of the semiconductor substrate to the first main surface. Each through-hole trench is paired with a through-hole bottom electrode, and the end of each through-hole trench on the first main surface of the semiconductor substrate is covered by the corresponding through-hole bottom electrode.

[0010] An auxiliary electrode is formed on the sidewall adjacent to the opening within the through-hole trench;

[0011] Electroplating a metal plug in the through-hole trench using the electroplating electrode includes:

[0012] Using the bottom electrode of the through-hole as the first seed layer, metal filling is performed from bottom to top; subsequently...

[0013] When the metal filling in the through-hole trench reaches the point of engagement with the auxiliary electrode, the metal filling is further performed using the auxiliary electrode as a second seed layer.

[0014] The end face of the metal plug opposite to the bottom electrode of the through hole is not lower than the second main surface of the semiconductor substrate.

[0015] Optionally, the end face of the auxiliary electrode near the bottom electrode of the through hole is between 10 micrometers and 200 micrometers away from the second main surface of the semiconductor substrate.

[0016] Optionally, the substrate is a silicon substrate, and the silicon substrate is etched by a deep reactive ion etching process to form a plurality of via trenches extending from the second main surface of the silicon substrate to the first main surface, wherein the aspect ratio of the via trenches is between 5:1 and 20:1.

[0017] Optionally, the auxiliary electrodes in any two through-hole trenches are electrically isolated from each other.

[0018] Optionally, the main portion of the electrode connection is distributed within the scribe line of the semiconductor substrate, and the width of the electrode connection is less than or equal to the width of the scribe line. The fabrication method further includes removing the main portion of the electrode connection from the chip during chip separation processing along the scribe line of the semiconductor substrate to achieve electrical separation between the plurality of through-silicon vias.

[0019] Optionally, the manufacturing method further includes: forming an insulating film covering the surface of the electrode interconnects.

[0020] Optionally, the material of the metal plug is selected from elemental copper, tungsten, nickel, tin, or gold, or an alloy of the above metals.

[0021] Optionally, the cross-section of the through-hole groove is a cylindrical shape with approximately vertical sidewalls, a cone shape without a sharp point, an arc-shaped sidewall, or a shape with an asymmetrical center.

[0022] Optionally, the manufacturing method further includes: processing the end face of the metal plug away from the bottom electrode of the through hole by chemical mechanical polishing, so that the polished end face is substantially flush with the second main surface of the semiconductor substrate.

[0023] As described above, the method for fabricating through-silicon vias in a semiconductor substrate according to the present invention has the following beneficial effects:

[0024] This invention provides a method for fabricating through-silicon vias (TSVs) in a semiconductor substrate. The bottom electrode of the TSV is connected to an electroplating electrode via an electrode wire. A voltage is applied to the electroplating electrode, and the bottom electrode of the TSV is used as a first seed layer to electroplat a metal plug in the TSV trench. In the later stage of electroplating, an auxiliary electrode located on the inner sidewall near the opening of the TSV trench is used as a second seed layer. This method achieves a bottom-up filling mode, accelerates the electroplating rate, improves the filling quality of the TSV, and reduces the manufacturing difficulty of the TSV and even the entire device.

[0025] This invention removes the main part of the electrode interconnects from the chip during the chip separation process along the dicing track of the semiconductor substrate. On the one hand, the performance of the electrical structure on the front side of the substrate is guaranteed, and on the other hand, the adverse effects such as the introduction of parasitic capacitance and other parameters on the electrical structure on the front side of the substrate are reduced, which can improve the reliability of TSV electrical interconnects. Attached Figure Description

[0026] The accompanying drawings, which form part of this specification, are used to provide a further understanding of the embodiments of this application and to illustrate the implementation of this application, together with the textual description, to explain the principles of this application. Obviously, the drawings described below are merely some embodiments of this application.

[0027] Figure 1 The diagram shown is a top view of a through-silicon via structure manufactured according to an embodiment of the present invention.

[0028] Figure 2 The diagram shown is a cross-sectional schematic of a through-silicon via structure manufactured according to an embodiment of the present invention.

[0029] Figures 3A to 3F The diagram shows the structural schematic of each step in the method for fabricating through-silicon vias in a semiconductor substrate according to Embodiment 1 of the present invention.

[0030] Figures 4A to 4F The diagram shows the structural schematic of each step in the method for fabricating through-silicon vias in a semiconductor substrate according to Embodiment 2 of the present invention.

[0031] Figure 5 The diagram shown is a top view of a single chip obtained by the method of fabricating through-silicon vias in a semiconductor substrate according to an embodiment of the present invention.

[0032] Component designation explanation

[0033] 10 substrate

[0034] 20 Electrical Structure

[0035] 30 lanes

[0036] 40 Insulating film

[0037] 50 Conductive Patterns

[0038] 51. Bottom electrode of through hole

[0039] 52 Electrode Connections

[0040] 53 Electroplating Electrode

[0041] 60 Through-hole groove

[0042] 70 Metal plugs

[0043] 80 Auxiliary Electrode Detailed Implementation

[0044] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0045] It should be emphasized that the term "including / comprises" as used herein refers to the presence of a feature, whole, step, or component, but does not exclude the presence or addition of one or more other features, wholes, steps, or components.

[0046] Features described and / or illustrated for one embodiment may be used in the same or similar manner in one or more other embodiments, combined with features in other embodiments, or substituted for features in other embodiments.

[0047] In the detailed description of embodiments of the present invention, for ease of explanation, the cross-sectional views illustrating the device structure may be partially enlarged and not to scale. Furthermore, the schematic diagrams are merely examples and should not limit the scope of protection of the present invention. In actual fabrication, the three-dimensional spatial dimensions of length, width, and depth should be included.

[0048] For ease of description, spatial relation terms such as “below,” “under,” “lower than,” “below,” “above,” and “upper” may be used herein to describe the relationship between one element or feature shown in the accompanying drawings and other elements or features. It will be understood that these spatial relation terms are intended to include directions other than those depicted in the drawings for devices in use or operation. Furthermore, when a layer is referred to as being “between” two layers, it may be the only layer between the two layers, or there may be one or more layers in between.

[0049] In the context of this application, the structure described above the first feature may include embodiments in which the first and second features are formed in direct contact, or embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

[0050] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the illustrations only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0051] In the manufacturing process of through-silicon vias (TSVs), electroplating is one of the commonly used techniques for forming metal fillers. Conventional processes for electroplating metal fillers in TSV trenches, such as using the substrate with the TSV as the plating cathode, can achieve good metal filling results. However, when the substrate thickness increases to a certain extent, it becomes difficult to uniformly deposit a seed layer on the sidewalls of the TSV, making it difficult to achieve seamless metal filling from the bottom to the top of the TSV, resulting in gapped metal plugs within the TSV trench. Therefore, for high-density, high aspect ratio TSVs on thick substrates, high-quality bottom-up metal filling can be achieved by connecting the bottom electrode of the TSV to the plating cathode or by applying a certain voltage.

[0052] However, in the via-middle process, since the via fabrication process is performed after the electrical structure is formed in the device area of ​​the semiconductor substrate in the front-end manufacturing process of integrated circuits, it is necessary to lead the bottom electrode of the via to other areas through wires so that an electroplating voltage can be applied to the bottom of the via when electroplating the metal filler. After the electroplating process is completed, the connection between the bottom electrodes of each via needs to be disconnected to ensure the performance of the electrical structure on the front side of the substrate.

[0053] To achieve efficient metal filling within high aspect ratio through-silicon vias (TSVs), this invention provides a method for fabricating TSVs in a semiconductor substrate, the method comprising the following steps:

[0054] A semiconductor substrate is provided, the semiconductor substrate including opposing first and second main surfaces;

[0055] A conductive pattern is formed on a first main surface of the semiconductor substrate. The conductive pattern includes an electroplating electrode, an electrode connection line, and a plurality of via bottom electrodes. The plurality of via bottom electrodes are electrically connected to the electroplating electrode through the electrode connection line. The electroplating electrode is at least partially exposed on the first main surface of the semiconductor substrate.

[0056] A plurality of through-hole trenches are formed from the second main surface of the semiconductor substrate to the first main surface. Each through-hole trench is paired with a through-hole bottom electrode, and the end of each through-hole trench on the first main surface of the semiconductor substrate is covered by the corresponding through-hole bottom electrode.

[0057] An auxiliary electrode is formed on the sidewall adjacent to the opening within the through-hole trench;

[0058] Electroplating a metal plug in the through-hole trench using the electroplating electrode includes:

[0059] Using the bottom electrode of the through-hole as the first seed layer, metal filling is performed from bottom to top; subsequently...

[0060] When the metal filling in the through-hole trench reaches the point of engagement with the auxiliary electrode, the metal filling is further performed using the auxiliary electrode as a second seed layer.

[0061] The end face of the metal plug opposite to the bottom electrode of the through hole is not lower than the second main surface of the semiconductor substrate.

[0062] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. See also Figure 1 It shows a top view schematic diagram of a through-silicon via (TSV) structure obtained by the method for fabricating TSVs in a semiconductor substrate according to the present invention. Figure 2 Displayed as Figure 1 A schematic cross-sectional view of the through-silicon via structure along line A-A'. (See diagram below.) Figures 1-2 As shown, this embodiment provides a method for fabricating a through-silicon via (TSV) in a semiconductor substrate, comprising: forming a TSV bottom electrode 51, an electrode connection line 52, and an electroplating electrode 53 on a first main surface of a semiconductor substrate 10; forming an electrical structure 20 above the TSV bottom electrode 51; covering the surface of the electrode connection line 52 with an insulating film 40; etching a TSV trench 60 on a second main surface of the semiconductor substrate 10; forming an auxiliary electrode 80 on the sidewall of the TSV trench 60 near the end face of the second main surface; applying a voltage to the electroplating electrode 53; and electroplating a metal plug 70.

[0063] After the electroplating of the metal plug 70 is completed, the manufacturing method further includes: chip separation processing of the semiconductor substrate, removing the electrode connection 52 from the chip, and realizing electrical separation between the plurality of through-silicon vias.

[0064] In one embodiment, the fabrication method includes the following steps: 1) forming a via bottom electrode 51, an electrode connection 52, and an electroplating electrode 53 on a first main surface of a semiconductor substrate 10, wherein the main portion of the electrode connection is distributed inside the scribe line, and the width of the electrode connection is smaller than the width of the scribe line; 2) forming an electrical structure 20 above the first main surface of the semiconductor substrate, the electrical structure 20 including structures such as integrated circuits (ICs) and MEMS devices, and covering the surface of the electrode connection with an insulating film; 3) etching a plurality of via trenches 60 extending from the second main surface of the semiconductor substrate to the first main surface; 4) forming an auxiliary electrode 80 on the sidewall of the via trench near the opening; 5) applying a voltage to the electroplating electrode and electroplating a metal plug along the through direction of the via trench; 6) separating the semiconductor substrate chip along the scribe line 30 to remove the electrode connection from the chip, thereby achieving electrical separation between the plurality of silicon vias.

[0065] In one embodiment, N via trenches are etched on the second main surface of the semiconductor substrate, where N is a complex number greater than or equal to 2.

[0066] In one embodiment, the bottom electrode of the through hole is provided on both sides of the dicing channel along the extension direction of the dicing channel.

[0067] In one embodiment, forming a conductive pattern on the first main surface of the semiconductor substrate includes: forming a conductive thin film on the first main surface of the semiconductor substrate using a sputtering method or a vacuum evaporation method; and patterning the conductive thin film using an etching method or a lift-off method to form a conductive pattern 50 on the first main surface of the semiconductor substrate.

[0068] In one embodiment, the electroplating electrodes are uniformly distributed on a semiconductor substrate, and the electroplating electrodes are at least partially exposed on a first main surface of the semiconductor substrate.

[0069] In one embodiment, after the electrode wiring is formed, an insulating film is formed on the surface of the electrode wiring by chemical vapor deposition to prevent the electrode wiring from being exposed on the first main surface.

[0070] In one embodiment, after the conductive pattern is formed, at step 2), an electrical structure 20 is formed over a first main surface of the semiconductor substrate, wherein the electrical structure includes an integrated circuit and a MEMS device.

[0071] In one embodiment, at step 2), the insulating film is coated onto the surface of the electrode wiring by chemical vapor deposition.

[0072] In one embodiment, the through-hole trench is formed by an etching method, which includes one of a wet etching method and a plasma etching method.

[0073] In one embodiment, a via trench 60 is formed using a deep reactive ion etching method, wherein the aspect ratio of the via trench is in the range of 5:1 to 20:1.

[0074] In one embodiment, the cross-section of the through-hole groove is approximately cylindrical with vertical sidewalls, conical without a pointed tip, with arc-shaped sidewalls, and asymmetrical at the center.

[0075] In one embodiment, the end face of the auxiliary electrode near the bottom electrode of the via is between 10 micrometers and 200 micrometers away from the second main surface of the semiconductor substrate, and the auxiliary electrodes in any two via trenches are electrically isolated from each other.

[0076] In one embodiment, the material of the metal plug is selected from any of the following metals: copper, tungsten, nickel, tin, or gold, or an alloy of the above metals.

[0077] In one embodiment, the end face of the metal plug away from the bottom electrode of the through hole is processed by chemical mechanical polishing (CMP) so that the polished end face is substantially flush with the second main surface.

[0078] In one embodiment, after the through-silicon via is fabricated, structures such as IC circuits and MEMS devices are further formed above the first main surface of the semiconductor substrate.

[0079] like Figures 3A to 3F The diagram shows a cross-sectional view along A-A' of the structure obtained at each stage of the method for fabricating through-silicon vias in a semiconductor substrate according to Embodiment 1 of the present invention.

[0080] like Figure 3A As shown, step 1) is performed first, providing a semiconductor substrate 10; a conductive thin film is formed on the first main surface of the semiconductor substrate using a sputtering deposition method at room temperature; the conductive thin film is patterned using an etching method or a lift-off process to form a conductive pattern 50, the conductive pattern including a plurality of via bottom electrodes 51, electrode lines 52, and electroplating electrodes 53. The via bottom electrodes 51, electrode lines 52, and electroplating electrodes 53 are essentially the same conductive pattern layer, and each via bottom electrode 51 has an approximate potential. It should be noted that the position and / or number of via bottom electrodes 51 can be appropriately determined according to the subsequently formed silicon vias so that each via trench is paired with a via bottom electrode, and the end of the via trench on the first main surface of the semiconductor substrate is covered by the corresponding via bottom electrode.

[0081] like Figure 3B As shown, step 2) is then performed to complete the fabrication process of the remaining devices on the first main surface of the semiconductor substrate 10. The main portion of the electrode interconnects 52 is distributed in the dicing channels 30. Step 2) further includes: covering the surface of the electrode interconnects 52 with the insulating film 40 by chemical vapor deposition.

[0082] like Figure 3C As shown, step 3) is then performed, where an etching method is used to form a via trench 60 extending from the second main surface of the semiconductor substrate 10 to the first main surface. The etching method for forming the via trench 60 includes: spin-coating photoresist onto the second main surface of the semiconductor substrate 10; then, defining a pattern corresponding to the via trench on the second main surface of the semiconductor substrate 10 through exposure and development operations; etching the second main surface of the semiconductor substrate 10 based on the developed photoresist pattern until the bottom electrode surface of the via is exposed; and finally, removing any remaining photoresist.

[0083] like Figure 3D As shown, step 4) is then performed, in which an auxiliary electrode 80 is formed on the sidewall of the through-hole trench 60 near the opening by a sputtering method. Preferably, the end face of the auxiliary electrode 80 near the bottom electrode of the through hole is between 10 micrometers and 200 micrometers away from the second main surface of the semiconductor substrate.

[0084] like Figure 3EAs shown, step 5) is then performed, where a voltage is applied to the electroplating electrode 53 to electroplat the metal plug 70. This includes: using the bottom electrode 51 of the through-hole as a first seed layer to fill the through-hole trench 60 with metal from bottom to top; when the metal filling in the through-hole trench reaches the point where it is electrically connected to the auxiliary electrode 80, that is, when the metal filler in the through-hole trench is joined with the auxiliary electrode 80 located on the sidewall of the through-hole trench, the auxiliary electrode 80 is further used as a second seed layer to fill with metal. This achieves an overall bottom-to-top filling pattern in the through-hole trench, and also improves the manufacturing efficiency and metal filling quality of the metal plug 70. The end face of the metal plug 70 away from the bottom electrode of the through-hole is not lower than the second main surface of the semiconductor substrate. After the electroplating of the metal plug 70 is completed, the end face of the metal plug 70 away from the bottom electrode of the through-hole is processed by chemical mechanical polishing, and the polished end face is substantially flush with the second main surface of the semiconductor substrate.

[0085] like Figure 3F As shown, then step 6) is performed to separate the semiconductor substrate 10 along the dicing channel 30; while cutting the dicing channel 30, the electrode connection 52 located in the dicing channel 30 is removed from the chip, so that the plurality of through-silicon vias are electrically separated, and the performance of the electrical structure on the front side of the substrate is guaranteed.

[0086] like Figures 4A to 4F As shown, this is a cross-sectional schematic diagram along A-A' of the structure obtained at each stage of the method for fabricating through-silicon vias in a semiconductor substrate according to Embodiment 2 of the present invention.

[0087] like Figure 4A As shown, step 1) is performed first, providing a semiconductor substrate 10; a conductive thin film is formed on the first main surface of the semiconductor substrate using a sputtering deposition method at room temperature; the conductive thin film is patterned using an etching method or a lift-off process to form a conductive pattern 50, the conductive pattern including a plurality of via bottom electrodes 51, electrode lines 52, and electroplating electrodes 53. The via bottom electrodes 51, electrode lines 52, and electroplating electrodes 53 are essentially the same conductive pattern layer, and each via bottom electrode 51 has an approximate potential.

[0088] like Figure 4B As shown, step 2) is then performed to complete the required device fabrication process on the first main surface of the semiconductor substrate 10. The main portion of the electrode interconnects 52 is distributed in the dicing channels 30. Step 2) further includes: covering the surface of the electrode interconnects 52 with the insulating film 40 by chemical vapor deposition.

[0089] Next, step 3) is performed, where an etching method is used to form a via trench 60 extending from the second main surface of the semiconductor substrate 10 to the first main surface. The step of forming the via trench 60 using the etching method includes: spin-coating photoresist onto the second main surface of the semiconductor substrate 10; then, defining a pattern corresponding to the via trench on the second main surface of the semiconductor substrate 10 through exposure and development operations; etching the second main surface of the semiconductor substrate 10 based on the developed photoresist pattern until the bottom electrode surface of the via is exposed; finally, removing any remaining photoresist. The cross-section of the via trench can be of any shape, as long as it can be substantially filled from bottom to top without holes by the electroplating method. For example, the cross-section of the via trench can be a cylindrical shape with approximately vertical sidewalls, a cone without a sharp point, an arc-shaped sidewall, or a shape with an asymmetrical center. In one example, such as... Figure 4C As shown, the cross-section of the through-hole groove 60 is a cone shape without a sharp point.

[0090] like Figure 4D As shown, step 4) is then performed, by applying voltage to the electroplating electrode 53, using the bottom electrode 51 of the through hole as a seed layer to perform electroplating to fill the through hole trench with metal plug 70 from bottom to top, so that the end face of the metal plug 70 away from the bottom electrode of the through hole is not lower than the second main surface of the semiconductor substrate; then, the end face of the metal plug 70 away from the bottom electrode of the through hole is processed by chemical mechanical polishing, and the polished end face is substantially flush with the second main surface of the semiconductor substrate.

[0091] like Figure 4E As shown, step 5) is then performed, whereby a voltage is applied to the electroplating electrode 53, and electroplating is performed using the bottom electrode 51 of the through-hole as the first seed layer to fill the through-hole trench 60 with metal plug 70 from bottom to top. When the metal filling in the through-hole trench reaches the point of electrical connection with the auxiliary electrode 80, that is, when the metal filler in the through-hole trench is joined with the auxiliary electrode 80 located on the inner sidewall near the opening of the through-hole trench, the auxiliary electrode 80 is further used as the second seed layer for metal filling, thereby improving the efficiency of electroplating and the quality of metal filling. The end face of the formed metal plug 70 away from the bottom electrode of the through-hole is not lower than the second main surface of the semiconductor substrate. After the electroplating of the metal plug 70 is completed, the end face of the metal plug 70 away from the bottom electrode of the through-hole is processed by chemical mechanical polishing, and the polished end face is substantially flush with the second main surface of the semiconductor substrate.

[0092] like Figure 4FAs shown, then step 6) is performed to separate the semiconductor substrate 10 along the dicing channel 30; while cutting the dicing channel 30, the electrode connection 52 located in the dicing channel 30 is removed from the chip, so that the plurality of through-silicon vias are electrically separated, and the performance of the electrical structure on the front side of the substrate is guaranteed.

[0093] like Figure 5 As shown, after the chip separation process is completed, the main part of the electrode interconnect 52 is removed from the chip, leaving only a portion of the electrode interconnect 52 within a single chip. This reduces the adverse effects of parasitic capacitance introduced into the electrical structure on the front side of the substrate. The through-silicon via (TSV) fabrication method described in this solution can reduce the fabrication difficulty of MEMS device packaging structures implemented using TSVs and even TSVs, thereby reducing the overall cost of the device.

[0094] This invention provides a microfabrication method, which has the following beneficial effects:

[0095] By electroplating electrodes, with the bottom electrode of the through-hole as the first seed layer, metal plugs are electroplated in the through-hole trench. When the metal filler in the through-hole trench is electrically connected to the auxiliary electrode, the auxiliary electrode is further used as the second seed layer. This achieves a bottom-up filling mode, accelerates the electroplating rate, and improves the filling quality of the through-silicon via. This invention can achieve electroplating effects that are difficult to achieve with existing technologies with a simpler structure, thereby reducing the overall cost of the device and the manufacturing difficulty of through-silicon vias and even the entire device.

[0096] This invention ensures the performance of the electrical structure on the front side of the substrate by disconnecting the electrical connection between the through-hole electrodes after electroplating. The lead-in method of the bottom electrode of the through hole can also reduce the adverse effects such as the introduction of parasitic capacitance parameters on the electrical structure on the front side of the substrate, thereby improving the reliability of TSV electrical interconnection.

[0097] Therefore, this invention effectively overcomes the various shortcomings of the prior art and has high industrial application value.

[0098] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method for fabricating through-silicon vias (TSVs) in a semiconductor substrate, characterized in that, Includes the following steps: A semiconductor substrate is provided, the semiconductor substrate including opposing first and second main surfaces; A conductive pattern is formed on a first main surface of the semiconductor substrate. The conductive pattern includes an electroplating electrode, an electrode connection line, and a plurality of via bottom electrodes. The plurality of via bottom electrodes are electrically connected to the electroplating electrode through the electrode connection line. The electroplating electrode is at least partially exposed on the first main surface of the semiconductor substrate. A plurality of through-hole trenches are formed from the second main surface of the semiconductor substrate to the first main surface. Each through-hole trench is paired with a through-hole bottom electrode, and the end of each through-hole trench on the first main surface of the semiconductor substrate is covered by the corresponding through-hole bottom electrode. An auxiliary electrode is formed on the sidewall adjacent to the opening within the through-hole trench; Electroplating a metal plug in the through-hole trench using the electroplating electrode includes: Using the bottom electrode of the through-hole as the first seed layer, metal filling is performed from bottom to top; subsequently... When the metal filling in the through-hole trench reaches the point of engagement with the auxiliary electrode, the metal filling is further performed using the auxiliary electrode as a second seed layer. The end face of the metal plug opposite to the bottom electrode of the through hole is not lower than the second main surface of the semiconductor substrate.

2. The manufacturing method according to claim 1, characterized in that: The distance between the end face of the auxiliary electrode near the bottom electrode of the through hole and the second main surface of the semiconductor substrate is between 10 micrometers and 200 micrometers.

3. The manufacturing method according to claim 1, characterized in that: The substrate is a silicon substrate, and the silicon substrate is etched by a deep reactive ion etching process to form a plurality of through-hole trenches extending from the second main surface of the silicon substrate to the first main surface, wherein the depth-to-width ratio of the through-hole trenches is between 5:1 and 20:

1.

4. The manufacturing method according to claim 1 or 2, characterized in that: The auxiliary electrodes in any two through-hole trenches are electrically isolated from each other.

5. The manufacturing method according to claim 1, characterized in that: The main portion of the electrode interconnect is distributed within the scribe line of the semiconductor substrate, and the width of the electrode interconnect is less than or equal to the width of the scribe line. The fabrication method further includes removing the main portion of the electrode interconnect from the chip during chip separation processing along the scribe line of the semiconductor substrate, thereby achieving electrical separation between the plurality of through-silicon vias.

6. The manufacturing method according to claim 1, characterized in that, The manufacturing method further includes: forming an insulating film covering the surface of the electrode interconnects.

7. The manufacturing method according to claim 1, characterized in that: The material of the metal plug is selected from any of the following metals: elemental copper, tungsten, nickel, tin or gold, or alloys of the above metals.

8. The manufacturing method according to claim 1, characterized in that: The cross-section of the through-hole groove is a cylindrical shape with approximately vertical sidewalls, a cone shape without a sharp point, an arc-shaped sidewall, or a shape with an asymmetrical center.

9. The method for fabricating a through-silicon via according to claim 1, characterized in that, The manufacturing method further includes: processing the end face of the metal plug away from the bottom electrode of the through hole by chemical mechanical polishing, so that the polished end face is substantially flush with the second main surface of the semiconductor substrate.

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