Packaging structure and packaging method

Abstract

A packaging structure and a packaging method, the packaging method comprising: providing a packaging module, the packaging module comprising: an interposer comprising opposite first and second bonding surfaces, the interposer comprising a plurality of interconnection unit regions, adjacent interconnection unit regions being spaced apart, and interconnection structures being formed in the interconnection unit regions; one or more device chips bonded on the first bonding surface of the interposer and electrically connected with the interconnection structures; and bonding an interconnection chip on the second bonding surface of the interposer, the interconnection chip being located on the interposer between adjacent interconnection unit regions and electrically connected with the interconnection structures of adjacent interconnection unit regions. The embodiments of the present application optimize packaging process and packaging performance.

Description

Technical Field

[0001] This invention relates to the field of semiconductor packaging, and more particularly to a packaging structure and packaging method. Background Technology

[0002] The rise and development of new technologies such as the Internet of Things, big data, and artificial intelligence have driven an exponential increase in computing demands, gradually pushing high-performance computing (HPC), which faces massive computations and frequent data access, to its limits. Traditional high-performance computing uses tens of thousands of processors arranged sequentially from chips to form modules, chassis, racks, and even systems. On the one hand, this results in a large footprint and difficult heat dissipation, making it far from suitable for the development needs of a series of emerging devices such as wearables and mobile communications. On the other hand, as Moore's Law approaches its physical limits, doubling performance through feature size reduction is becoming increasingly unsustainable.

[0003] System on Wafer (SOW) emerged to address this need. This technology eliminates the need for a substrate in traditional solutions, directly soldering connectors and power modules onto the processor wafer. It utilizes Redistribution Layer (RDL) technology to directly interconnect processors and peripheral modules. It also offers advantages such as low-latency inter-chip communication, high bandwidth density, and low power delivery network (PDN) impedance, all characteristic of wafer-level integration. Furthermore, it directly attaches the wafer to the heat dissipation module, effectively solving the heat dissipation problem.

[0004] However, the performance of the packaging structure still needs to be improved. Summary of the Invention

[0005] The problem solved by the embodiments of the present invention is to provide a packaging structure and packaging method that optimizes the packaging process and packaging performance.

[0006] To address the aforementioned problems, embodiments of the present invention provide a packaging structure, comprising: an interposer having a first bonding surface and a second bonding surface opposite to each other, the interposer having a plurality of interconnect cell regions spaced apart from each other, and interconnect structures formed within each interconnect cell region; one or more device chips bonded to the first bonding surface of the interposer, the device chips being electrically connected to the interconnect structures; and interconnect chips bonded to the second bonding surface of the interposer, the interconnect chips being located on the interposer between adjacent interconnect cell regions and electrically connected to the interconnect structures of adjacent interconnect cell regions.

[0007] Accordingly, embodiments of the present invention also provide a packaging method, comprising: providing a packaging module, the packaging module comprising: an interposer, including a first bonding surface and a second bonding surface opposite to each other, the interposer comprising a plurality of interconnect cell regions spaced apart from each other, and interconnect structures formed within the interconnect cell regions; one or more device chips, bonded to the first bonding surface of the interposer and electrically connected to the interconnect structures; and bonding interconnect chips to the second bonding surface of the interposer, the interconnect chips being located on the interposer between adjacent interconnect cell regions and electrically connected to the interconnect structures of adjacent interconnect cell regions.

[0008] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages:

[0009] The packaging structure provided in this embodiment of the invention includes an interposer comprising multiple interconnect unit regions spaced apart from each other; one or more device chips are bonded to a first bonding surface of the interposer, and the device chips are electrically connected to the interconnect structure; interconnect chips are bonded to a second bonding surface of the interposer, and the interconnect chips are located on the interposer between adjacent interconnect unit regions and electrically connected to the interconnect structure of adjacent interconnect unit regions. This achieves global interconnection of the interposer through the interconnect structure and the interconnect chips, thereby enabling electrical connections between device chips. Furthermore, it helps reduce the process requirements and difficulty of forming the interposer, while also achieving high-density interconnection, optimizing the packaging process and packaging performance.

[0010] In the packaging method provided by this invention, the packaging module includes an interposer and one or more device chips. The interposer includes multiple interconnect unit regions, which are spaced apart from each other. One or more device chips are bonded to a first bonding surface of the interposer, and the device chips are electrically connected to the interconnect structure. Interconnect chips are bonded to a second bonding surface of the interposer. The interconnect chips are located between adjacent interconnect unit regions and are electrically connected to the interconnect structure of adjacent interconnect unit regions. Thus, the global interconnection of the interposer is achieved through the interconnect structure and the interconnect chips, thereby enabling electrical connections between device chips. Furthermore, this method helps to reduce the process requirements and difficulty of forming the interposer, while also achieving high-density interconnection and optimizing the packaging process and packaging performance. Attached Figure Description

[0011] Figures 1 to 2 This is a schematic diagram of an embodiment of the packaging structure of the present invention;

[0012] Figures 3 to 4 This is a schematic diagram of another embodiment of the packaging structure of the present invention;

[0013] Figures 5 to 6This is a schematic diagram of another embodiment of the packaging structure of the present invention;

[0014] Figures 7 to 13 This is a schematic diagram of the structure corresponding to each step in one embodiment of the packaging method of the present invention;

[0015] Figures 14 to 15 This is a schematic diagram of the structure corresponding to each step in another embodiment of the packaging method of the present invention;

[0016] Figures 16 to 17 This is a schematic diagram of the structure corresponding to each step in another embodiment of the packaging method of the present invention. Detailed Implementation

[0017] As can be seen from the background technology, the performance of current packaging structures needs to be improved.

[0018] To address the aforementioned technical problems, embodiments of the present invention provide a packaging structure in which an interposer includes multiple interconnect unit regions spaced apart from adjacent interconnect unit regions; one or more device chips are bonded to a first bonding surface of the interposer, and the device chips are electrically connected to the interconnect structure; interconnect chips are bonded to a second bonding surface of the interposer, and the interconnect chips are located on the interposer between adjacent interconnect unit regions and electrically connected to the interconnect structure of adjacent interconnect unit regions. This achieves global interconnection of the interposer through the interconnect structure and the interconnect chips, thereby enabling electrical connections between device chips. Furthermore, it reduces the process requirements and difficulty of forming the interposer, while also achieving high-density interconnection, optimizing the packaging process and packaging performance.

[0019] To make the above-mentioned objects, features and advantages of the embodiments of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings. Figures 1 to 2 This is a schematic diagram of an embodiment of the packaging structure of the present invention. Figure 1 This is a top view. Figure 2 for Figure 1 The corresponding sectional view.

[0020] In this embodiment, the packaging structure includes: an interposer 10, including a first bonding surface 101 and a second bonding surface 102 facing each other; the interposer 10 includes a plurality of interconnect cell regions 10a, which are spaced apart from each other; and interconnect structures are formed in each interconnect cell region 10a; one or more device chips 20 are bonded to the first bonding surface 101 of the interposer 10, and the device chips 20 are electrically connected to the interconnect structures; and interconnect chips 50 are bonded to the second bonding surface 102 of the interposer 10, and the interconnect chips 50 are located on the interposer 10 between adjacent interconnect cell regions 10a and are electrically connected to the interconnect structures of adjacent interconnect cell regions 10a.

[0021] Intermediate board 10 is used to interconnect the device chips 20. Interconnecting the device chips 20 through intermediate board 10 helps to shorten the interconnection distance between the device chips 20 and improve the efficiency and stability of information transmission.

[0022] The first bonding surface 101 is used to bond one or more device chips 20; the second bonding surface 102 is used to subsequently bond interconnect chips.

[0023] Interconnection cell region 10a is used to form interconnection structures. Specifically, the interconnection structures are used to realize interconnection between device chips 20.

[0024] In this embodiment, adjacent interconnect unit regions 10a are spaced apart, that is, the interconnect structures within adjacent interconnect unit regions 10a are spaced apart. The interconnect chip 50 realizes the electrical connection between the interconnect structures of adjacent interconnect unit regions 10a. Thus, during the formation of the interposer 10, the design requirements for the interconnect structures within the interconnect unit regions 10a can be reduced, the process difficulty of forming the interconnect structure can be reduced, and the design flexibility and process flexibility of forming the interposer 10 can be improved.

[0025] In this embodiment, the plurality of interconnection unit regions 10a are arranged in an array. In other embodiments, based on actual design requirements, the plurality of interconnection unit regions can also be arranged in other ways, such as staggered arrangement.

[0026] It should be noted that, in this embodiment, for ease of illustration and explanation, only a portion of the interconnection unit area 10a is shown in the top view.

[0027] In this embodiment, the interconnect structure is made of a metallic material, such as one or more of copper, aluminum, tungsten, cobalt, nickel, titanium, tantalum, titanium nitride, and tantalum nitride.

[0028] In this embodiment, the intermediate board 10 includes a redistribution layer (RDL interposer), and the interconnect structure includes one or more redistribution layers (RDLs) as an example for illustration. Using a redistribution layer allows for the redistribution of electrical connection ports of the device chip 20, supports a larger number of pins, reduces the circuit connection distance between device chips, increases chip packaging density, and significantly reduces signal trace width and spacing, thereby increasing signal density per unit area and improving circuit performance. Furthermore, the design of the redistribution layer can replace part of the internal circuitry of the device chip 20, thereby reducing design costs.

[0029] In this embodiment, during the formation of the package structure, the forming step of the interposer 10 includes: forming an interconnect structure pattern in the interconnect unit area 10a; forming the interconnect structure pattern includes the step of sequentially exposing each exposure window area 10b. The interconnect structure pattern is used to define the pattern of the interconnect structure.

[0030] In this embodiment, during the formation of the intermediate substrate 10, a photolithography process is used to form an interconnect structure pattern. Specifically, a stepper (step and repeat) photolithography process is used to form the interconnect structure pattern. Therefore, forming the interconnect structure pattern includes the step of sequentially exposing each exposure window area 10b.

[0031] Specifically, in each exposure process, only a local area (i.e., exposure window area 10b) is exposed. After the current exposure window area 10b is exposed, the process moves to the next exposure window area 10b and repeats until all exposure window areas 10b are exposed. Correspondingly, in this embodiment, the exposure window area 10b refers to the exposure reticle field for each exposure process.

[0032] In a specific implementation, each interconnect unit region 10a includes an exposure window region 10b, or each interconnect unit region 10a includes multiple connected exposure window regions 10b, and adjacent exposure window regions 10b have overlapping areas.

[0033] When each interconnect unit region 10a includes multiple connected exposure window regions 10b, there is an overlapping area between adjacent exposure window regions 10b. The adjacent exposure window regions 10b can be stitched together through the overlapping area. By repeatedly exposing adjacent exposure window regions 10b, an exposure pattern of larger size and / or area can be obtained, that is, an interconnect structure pattern of larger size and / or area (e.g., an interconnect structure pattern with a larger length).

[0034] In the semiconductor field, the more times adjacent exposure window regions 10b are stitched together, the higher the probability of misalignment between the exposure patterns of adjacent exposure window regions 10b. In this embodiment, the intermediate board 10 is partially interconnected through interconnect unit regions 10a, with adjacent interconnect unit regions 10a spaced apart. Subsequently, electrical connections between adjacent interconnect unit regions 10a are achieved through interconnect chips, thereby realizing the global interconnection of the intermediate board 10. Correspondingly, during the formation of the intermediate board 10, the number of times adjacent exposure window regions 10b are stitched together can be reduced, which helps to reduce the requirements of the exposure process for forming the interconnect structure pattern, thereby reducing the process difficulty of forming the interconnect structure pattern, improving the exposure quality and the accuracy of the interconnect structure.

[0035] As an example, in the intermediate board 10, a portion of the interconnect unit area 10a includes one exposure window area 10b, and a portion of the interconnect unit area 10a includes multiple connected exposure window areas 10b. More specifically, in this embodiment, a portion of the interconnect unit area 10a includes three connected exposure window areas 10b.

[0036] In practice, the number of exposure window areas 10b included in the interconnection unit area 10a in the interposer 10 is determined based on actual design requirements.

[0037] As an example, each interconnect unit region 10a includes a plurality of interconnected exposure window regions 10b, and adjacent exposure window regions 10b have overlapping areas; in each interconnect unit region 10a, the plurality of exposure window regions 10b are arranged along the row direction (e.g., Figure 1 Arranged in the X direction (as shown in the middle), or, multiple exposure window areas 10b along the column direction (e.g., Figure 1 Arranged in the Y direction; or, in each of the interconnecting unit regions 10a, a plurality of exposure window regions 10b are arranged along the row and column directions.

[0038] When multiple exposure window areas 10b are arranged along the row direction and / or column direction, there is an overlapping area between adjacent exposure window areas 10b arranged along the row direction and / or column direction, so that adjacent exposure windows 10b can be stitched together through the overlapping area, thereby obtaining an interconnection structure pattern with a larger area and size.

[0039] In this embodiment, the example is taken as if multiple connected exposure window areas 10b in the interconnection unit area 10a are arranged along the row direction.

[0040] It should be noted that when each interconnect unit area 10a includes multiple exposure window areas 10b, the interconnect unit area 10a and the multiple device chips 20 are vertically opposite each other. The electrical connection between the multiple device chips 20 is realized by utilizing the interconnect structure formed by the multiple exposure window areas 10b.

[0041] When each interconnect unit region 10a includes an exposure window region 10b, each interconnect unit region 10a is vertically opposite to one or more device chips 20, and the interconnect structure of each interconnect unit region 10a is used to realize electrical connection between multiple device chips 20.

[0042] The packaging structure further includes a packaging layer 30, which is located on the first bonding surface 101 of the interposer 10 and covers the sidewalls of the one or more device chips 20.

[0043] The encapsulation layer 30 is used to achieve encapsulation integration between one or more device chips 20 and the interposer 10. The encapsulation layer 30 also serves to provide insulation, sealing and moisture protection, which helps to improve the reliability of the encapsulation.

[0044] As one embodiment, the encapsulation layer 30 is made of a molding compound, such as epoxy resin. Epoxy resin has advantages such as low shrinkage, good adhesion, good corrosion resistance, excellent electrical properties, and low cost. In other embodiments, other suitable encapsulation materials can also be used for the encapsulation layer.

[0045] One or more device chips 20 are bonded to the first bonding surface 101 for electrical connection and package integration between the intermediate board 10 and the interconnect chip 50, thereby achieving a specific function.

[0046] In practice, when there are multiple device chips 20, the types of device chips 20 can be the same or different. For example, one device chip 20 can be a logic control chip, and another device chip 20 can be a memory chip.

[0047] The device chip 20 is electrically connected to the interconnect structure, thereby enabling electrical connections between device chips 20 through the interconnect structure and subsequent interconnect chips. Specifically, in this embodiment, interconnect terminals are formed on the device chip 20, and the interconnect terminals are electrically connected to the interconnect structure.

[0048] It should be noted that when each interconnect unit area 10a includes multiple exposure window areas 10b, the interconnect unit area 10a and the multiple device chips 20 are vertically opposite each other. The electrical connection between the multiple device chips 20 is realized by utilizing the interconnect structure formed by the multiple exposure window areas 10b.

[0049] When each interconnect unit region 10a includes an exposure window region 10b, each interconnect unit region 10a is vertically opposite to one or more device chips 20, and the interconnect structure of each interconnect unit region 10a is used to realize electrical connection between multiple device chips 20.

[0050] Specifically, the device chip 20 includes a first chip surface 201 and a second chip surface 202 opposite to each other; the packaging structure also includes a first conductive structure 25 located between the second chip surface 202 and the first bonding surface 101 of the interposer 10.

[0051] Accordingly, in this embodiment, the interconnection terminal is electrically connected to the first conductive structure 25 so as to realize the electrical connection between the device chip 20 and the first conductive structure 25.

[0052] As one embodiment, the first conductive structure 25 is a conductive bump. In this embodiment, the material of the first conductive structure 25 includes one or more of tin, copper, aluminum, tungsten, cobalt, nickel, titanium, tantalum, titanium nitride, and tantalum nitride. As an example, the material of the first conductive structure 25 is tin.

[0053] It should be noted that in this embodiment, the bonding between the device chip 20 and the first bonding surface 101 of the interposer 10 is achieved through the first conductive structure 25 as an example. In other embodiments, the first conductive structure may be omitted based on actual process requirements.

[0054] In this embodiment, the first chip surface 201 is taken as the front side of the chip, and the second chip surface 202 is taken as the back side of the chip. Here, the front side of the chip refers to the side of the device chip 20 facing the device, and the back side of the chip refers to the side of the device chip 20 facing away from the device.

[0055] In other embodiments, the first chip surface may be the back of the chip, and the second chip surface may be the front of the chip.

[0056] In this embodiment, the interposer 10 includes a plurality of interconnect unit regions 20a, which are spaced apart from each other. One or more device chips 20 are bonded to a first bonding surface 101 of the interposer 10, and the device chips 20 are electrically connected to the interconnect structure. Furthermore, interconnect chips 50 are bonded to a second bonding surface 102 of the interposer 10. The interconnect chips 50 are located between adjacent interconnect unit regions 10a and are electrically connected to the interconnect structure of adjacent interconnect unit regions 10a. Thus, the interconnect structure and the interconnect chips 50 achieve global interconnection of the interposer 10, thereby enabling electrical connection between device chips 20. This also helps to reduce the process requirements and difficulty of forming the interposer 10, while achieving high-density interconnection and optimizing the packaging process and packaging performance.

[0057] The interconnect chip 50 serves as a bridge to enable interconnection between adjacent interconnect cell regions 10a. Specifically, in this embodiment, the interconnect chip 50 is also located on top of a portion of the interconnect structure in the adjacent interconnect cell region 10a to enable electrical connection between the interconnect chip 50 and the interconnect structure.

[0058] Specifically, the interconnect chip 10 has one or more interconnect lines (not shown), and the surface of the interconnect chip 10 has external terminals (not shown), which are electrically connected to the interconnect lines. Specifically, there are at least two external terminals, which are electrically connected to the interconnect structures of adjacent interconnect unit regions 10a, thereby enabling them to connect adjacent interconnect unit regions 10a.

[0059] In this embodiment, the interconnect and the external terminal are made of metallic materials, such as one or more of copper, aluminum, tungsten, cobalt, nickel, titanium, tantalum, titanium nitride, and tantalum nitride.

[0060] In this embodiment, the interconnect chip 50 includes a first interconnect chip 51 and a second interconnect chip 52. The first interconnect chip 51 is electrically connected to the interconnect structure of adjacent interconnect cell regions 10a along the row direction, and the second interconnect chip 52 is electrically connected to the interconnect structure of adjacent interconnect cell regions 10a along the column direction.

[0061] As an example, there may be multiple second interconnect chips 52 connecting the same adjacent interconnect cell region 10a. Each interconnect chip 52 connects to the interconnect structure of the exposure window region 10b of the adjacent interconnect cell region 10a along the column direction, thereby increasing the interconnect density of adjacent interconnect cell regions 10a. In other embodiments, the number of second interconnect chips connecting the same adjacent interconnect cell region may be only one.

[0062] In this embodiment, the packaging structure further includes a second conductive structure 90, located between the interconnect chip 50 and the interposer 10. As one embodiment, the second conductive structure 90 is a conductive bump.

[0063] In this embodiment, the material of the second conductive structure 90 includes one or more of tin, copper, aluminum, tungsten, cobalt, nickel, titanium, tantalum, titanium nitride, and tantalum nitride. As an example, the material of the second conductive structure 90 is tin.

[0064] In this embodiment, the bonding between the second bonding surface 102 of the interposer 10 and the interconnect chip 50 is achieved through the second conductive structure 90 as an example. In other embodiments, the second conductive structure may be omitted based on actual process requirements.

[0065] In this embodiment, the packaging structure further includes: a power connector 80, which is bonded to the second bonding surface 102 of the intermediate plate 10, and the power connector 80 is electrically connected to the interconnect structure; and an input / output connector 70, which is bonded to the second bonding surface 102 of the intermediate plate 10, and the input / output connector 70 is electrically connected to the interconnect structure.

[0066] The power connector 80 is used to realize the electrical connection between the intermediate board 10 and the power module, so as to realize the power supply to the intermediate board 10, and then realize the power supply to the device chip 20 through the intermediate board 10.

[0067] The input / output connector 70 is used to connect the intermediate board 10 to the external circuit.

[0068] As an example, the input / output connector 70 includes a photonic integrated circuit (PIC) connector, which enables optical (e.g., fiber optic) interconnection of relatively distant interconnect ports on the interposer 10, thereby facilitating the shortest possible circuit and information transmission paths.

[0069] The packaging structure provided in this embodiment can be formed by the packaging method of this embodiment of the invention, or by other packaging methods.

[0070] Figures 3 to 4 This is a schematic diagram of another embodiment of the packaging structure of the present invention. Figure 3 This is a top view. Figure 7 yes Figure 3 The corresponding cross-sectional view. The similarities between this embodiment and the previous embodiment will not be repeated here. The difference between this embodiment and the previous embodiment is that each interconnect unit area 10a includes an exposure window area 10b.

[0071] In this embodiment, when each interconnect unit region 10a includes an exposure window region 10b, each interconnect unit region 10a is vertically opposite to one or more device chips 20, and when each interconnect unit region 10a is vertically opposite to multiple device chips 20, the interconnect structure of each interconnect unit region 10a is used to realize the electrical connection between multiple device chips 20.

[0072] The packaging structure provided in this embodiment can be formed by the packaging method of this embodiment of the invention, or by other packaging methods.

[0073] Figures 5 to 6 This is a schematic diagram of another embodiment of the packaging structure of the present invention. Figure 5 This is a sectional view. Figure 6 for Figure 5A magnified view at point B. The similarities between this embodiment and the previous embodiments will not be repeated here. The differences between this embodiment and the previous embodiments are:

[0074] In this embodiment, the intermediary board 210 is an adapter board, and the intermediary board 210 includes a substrate 250 and a backend metal layer 280 located on the substrate 250; the interconnect structure is the backend metal layer 280. The backend metal layer 280 is used to realize the electrical connection between device chips 220.

[0075] As an example, the adapter is a silicon interposer, and the substrate 250 is made of silicon. In other embodiments, depending on actual process requirements, the substrate may also be made of other semiconductor materials or insulating materials.

[0076] The back-end interconnect structure layer 280 is formed by a back-end process. Specifically, in this embodiment, a back-end dielectric structure layer (not shown) is formed on the substrate 250, and the back-end interconnect structure layer 280 is formed within the back-end dielectric structure layer.

[0077] The material of the back-end interconnect structure layer 280 is a metallic material, such as one or more of copper, aluminum, tungsten, cobalt, nickel, titanium, tantalum, titanium nitride, and tantalum nitride.

[0078] In this embodiment, the adapter board further includes a through-hole structure 240 penetrating the substrate 250, and the through-hole structure 240 is electrically connected to the rear interconnect structure layer 280.

[0079] In this embodiment, the adapter board further includes a through-hole structure 240 penetrating the substrate 250, and the through-hole structure 240 is electrically connected to the rear interconnect structure layer 280.

[0080] The via structure 240 is electrically connected to the back interconnect structure layer, thereby facilitating the electrical connection between the back interconnect structure layers 280 of adjacent interconnect unit areas through the via structure 240 and the back interconnect structure layer 280, and thus realizing the electrical connection between the device chips 220.

[0081] Specifically, the interconnect chip 260 is electrically connected to the via structure 240 of the adjacent interconnect unit region; or, the interconnect chip 260 is electrically connected to the rear interconnect structure layer 280 of the adjacent interconnect unit region.

[0082] In this embodiment, the side of the adapter board with the rear interconnect structure layer 280 faces the device chip 220, thereby shortening the interconnect distance between the rear interconnect structure layer 280 and the device chip 220. Correspondingly, the interconnect chip 260 is electrically connected to the via structure 240 of the adjacent interconnect unit area, so that the interconnect chip 260 can realize the electrical connection between the rear interconnect structure layers 280 of the adjacent device unit areas through the via structure 240 of the adjacent interconnect unit area, and then realize the electrical connection between the device chips 220 through the interconnect chip 260, the via structure 240 and the rear interconnect structure layer 280.

[0083] In other embodiments, when the side of the adapter board with the back interconnect structure layer faces away from the device chip, the interconnect chip is electrically connected to the back interconnect structure layer of the adjacent interconnect unit area, and the device chip is electrically connected to the via structure. Thus, the interconnect chip can achieve electrical connection between device chips through the back interconnect structure layer and the via structure.

[0084] In this embodiment, the adapter board is formed by semiconductor manufacturing process, and the through-hole structure 240 can have higher density, smaller spacing and size, thereby improving the interconnection density between device chips 220.

[0085] In this embodiment, the through-hole structure 240 is a through-silicon via (TSV) structure. The TSV structure, through vertical interconnection, can reduce the interconnection length between the device chip 220 and the substrate 250, which is beneficial for reducing signal delay, lowering capacitance / inductance, achieving low power consumption and high-speed communication, increasing bandwidth, and enabling miniaturization of device integration.

[0086] In this embodiment, the perforated structure 240 is made of a metallic material, such as one or more of copper, aluminum, tungsten, cobalt, nickel, titanium, tantalum, titanium nitride, and tantalum nitride. As an example, the perforated structure 240 is made of copper.

[0087] In this embodiment, the packaging structure further includes a second conductive structure 270 located between the interconnect chip 260 and the interposer 210. The second conductive structure 270 is used to achieve bonding between the interconnect chip 260 and the interposer 210. More specifically, the second conductive structure 270 enables electrical connection between the interconnect chip 260 and the through-hole structure 240.

[0088] As one embodiment, the second conductive structure 270 is a conductive bump.

[0089] In this embodiment, the material of the second conductive structure 270 includes one or more of tin, copper, aluminum, tungsten, cobalt, nickel, titanium, tantalum, titanium nitride, and tantalum nitride. As an example, the material of the second conductive structure 270 is tin.

[0090] The packaging structure provided in this embodiment can be formed by the packaging method of this embodiment of the invention, or by other packaging methods.

[0091] Accordingly, the present invention also provides a packaging method. Figures 7 to 13 This is a schematic diagram of the structure corresponding to each step in one embodiment of the packaging method of the present invention. The packaging method of this embodiment will be described in detail below with reference to the accompanying drawings.

[0092] refer to Figure 7 A packaging module 100 is provided, the packaging module 100 including: an interposer 10 including a first bonding surface 101 and a second bonding surface 102 opposite to each other, the interposer 10 including a plurality of interconnect unit regions 10a, adjacent interconnect unit regions 10a being spaced apart, and interconnect structures (not shown) formed in the interconnect unit regions 10a; and one or more device chips 20, bonded to the first bonding surface 101 of the interposer 10 and electrically connected to the interconnect structures.

[0093] The packaging module 100 is used for subsequent bonding of interconnect chips to achieve package integration between the interposer 10, the device chip 20 and the interconnect chip.

[0094] The packaging module 100 includes the interposer 10 and the one or more device chips 20 to achieve package integration between the interposer 10 and the device chips 20.

[0095] In this embodiment, by first providing the packaging module 100 and then bonding interconnect chips on the packaging module 100, the intermediate board 10 and the device chip 20 are packaged and integrated first, and then the interconnect chips are bonded, which helps to improve the packaging reliability between the intermediate board 10 and the device chip 20.

[0096] Intermediate board 10 is used to interconnect the device chips 20. Interconnecting the device chips 20 through intermediate board 10 helps to shorten the interconnection distance between the device chips 20 and improve the efficiency and stability of information transmission.

[0097] The first bonding surface 101 is used to bond one or more device chips 20; the second bonding surface 102 is used to subsequently bond interconnect chips.

[0098] Interconnection cell region 10a is used to form interconnection structures. Specifically, the interconnection structures are used to realize interconnection between device chips 20.

[0099] In this embodiment, adjacent interconnect unit regions 10a are spaced apart, that is, the interconnect structures within adjacent interconnect unit regions 10a are spaced apart. Subsequently, the electrical connection between the interconnect structures of adjacent interconnect unit regions 10a is realized through interconnect chips. In this way, the design requirements for the interconnect structures within the interconnect unit regions 10a can be reduced during the formation of the interposer 10, the process difficulty of forming the interconnect structure can be reduced, and the design flexibility and process flexibility of forming the interposer 10 can be improved.

[0100] In this embodiment, the plurality of interconnection unit regions 10a are arranged in an array. In other embodiments, based on actual design requirements, the plurality of interconnection unit regions can also be arranged in other ways, such as staggered arrangement.

[0101] It should be noted that, in this embodiment, for ease of illustration and explanation, only a portion of the interconnection unit area 10a is shown in the top view.

[0102] In this embodiment, the intermediate board 10 includes a redistribution layer (RDL interposer), and the interconnect structure includes one or more redistribution layers (RDLs) as an example for illustration. Using a redistribution layer allows for the redistribution of electrical connection ports of the device chip 20, supports a larger number of pins, reduces the circuit connection distance between device chips, increases chip packaging density, and significantly reduces signal trace width and spacing, thereby increasing signal density per unit area and improving circuit performance. Furthermore, the design of the redistribution layer can replace part of the internal circuitry of the device chip 20, thereby reducing design costs.

[0103] In this embodiment, the interconnect structure is made of a metallic material, such as one or more of copper, aluminum, tungsten, cobalt, nickel, titanium, tantalum, titanium nitride, and tantalum nitride.

[0104] One or more device chips 20 are bonded to the first bonding surface 101 for electrical connection and package integration between them via the interposer 10 and subsequent interconnect chips, thereby achieving specific functions.

[0105] In practice, when there are multiple device chips 20, the types of device chips 20 can be the same or different. For example, one device chip 20 can be a logic control chip, and another device chip 20 can be a memory chip.

[0106] In this embodiment, during the step of providing the packaging module 100, the packaging module 100 further includes a packaging layer 30 formed on the first bonding surface 101 of the interposer 10 and covering the sidewalls of the one or more device chips 20.

[0107] The encapsulation layer 30 is used to achieve encapsulation integration between one or more device chips 20 and the interposer 10. The encapsulation layer 30 also serves to provide insulation, sealing and moisture protection, which helps to improve the reliability of the encapsulation.

[0108] As one embodiment, the encapsulation layer 30 is made of molding material, such as epoxy resin. Epoxy resin has advantages such as low shrinkage, good adhesion, good corrosion resistance, excellent electrical properties, and low cost. In other embodiments, other suitable encapsulation materials can also be used for the encapsulation layer.

[0109] The following detailed description, in conjunction with the accompanying drawings, outlines the specific steps involved in providing the packaging module 100.

[0110] like Figures 7 to 8 As shown, Figure 7 This is a top view. Figure 8 for Figure 7 A cross-sectional view of the interconnection unit area forms the intermediate plate 10.

[0111] In this embodiment, the step of forming the intermediate plate 10 includes: forming an interconnect structure pattern in the interconnect unit area 10a; forming the interconnect structure pattern includes the step of sequentially exposing each exposure window area 10b.

[0112] Interconnection structure patterns are used to define the graphics of interconnection structures. In this embodiment, photolithography is used to form the interconnection structure patterns.

[0113] Specifically, in this embodiment, a stepper (step and repeat system) lithography process is used to form the interconnect structure pattern. Therefore, forming the interconnect structure pattern includes the step of sequentially exposing each exposure window area 10b.

[0114] By sequentially exposing each exposure window region 10b to form an interconnect structure pattern, the resolution of the formed interconnect structure pattern can be improved, that is, an interconnect structure pattern with smaller size and spacing can be obtained.

[0115] In practice, a stepper lithography machine is used to perform step-by-step lithography to form interconnect structure patterns. Specifically, in each exposure process, only a local area (i.e., exposure window area 10b) is exposed. After the current exposure window area 10b is exposed, the process is repeated in the next exposure window area 10b until all exposure window areas 10b are exposed.

[0116] Correspondingly, in this embodiment, the exposure window area 10b refers to the exposure reticle field for each exposure process.

[0117] In a specific implementation, each interconnect unit region 10a includes an exposure window region 10b, or each interconnect unit region 10a includes multiple connected exposure window regions 10b, and adjacent exposure window regions 10b have overlapping areas.

[0118] When each interconnect unit region 10a includes multiple connected exposure window regions 10b, there is an overlapping area between adjacent exposure window regions 10b. The adjacent exposure window regions 10b can be stitched together through the overlapping area. By repeatedly exposing adjacent exposure window regions 10b, an exposure pattern of larger size and / or area can be obtained, that is, an interconnect structure pattern of larger size and / or area (e.g., an interconnect structure pattern with a larger length).

[0119] In the semiconductor field, the more times adjacent exposure window regions 10b are stitched together, the higher the probability of misalignment between the exposure patterns of adjacent exposure window regions 10b. In this embodiment, the intermediate board 10 is partially interconnected through interconnect unit regions 10a, with adjacent interconnect unit regions 10a spaced apart. Subsequently, electrical connections between adjacent interconnect unit regions 10a are achieved through interconnect chips, thereby realizing the global interconnection of the intermediate board 10. Correspondingly, during the formation of the intermediate board 10, the number of times adjacent exposure window regions 10b are stitched together can be reduced, which helps to reduce the requirements of the exposure process for forming the interconnect structure pattern, thereby reducing the process difficulty of forming the interconnect structure pattern, improving the exposure quality and the accuracy of the interconnect structure.

[0120] As an example, in the intermediate board 10, a portion of the interconnect unit area 10a includes one exposure window area 10b, and a portion of the interconnect unit area 10a includes multiple connected exposure window areas 10b. More specifically, in this embodiment, a portion of the interconnect unit area 10a includes three connected exposure window areas 10b.

[0121] In practice, the number of exposure window areas 10b included in the interconnection unit area 10a in the interposer 10 is determined based on actual design requirements.

[0122] As an example, each interconnect unit region 10a includes a plurality of interconnected exposure window regions 10b, and adjacent exposure window regions 10b have overlapping areas; in each interconnect unit region 10a, the plurality of exposure window regions 10b are arranged along the row direction (e.g., Figure 7 Arranged in the X direction (as shown in the middle), or, multiple exposure window areas 10b along the column direction (e.g., Figure 7 Arranged in the Y direction; or, in each of the interconnecting unit regions 10a, a plurality of exposure window regions 10b are arranged along the row and column directions.

[0123] When multiple exposure window areas 10b are arranged along the row direction and / or column direction, there is an overlapping area between adjacent exposure window areas 10b arranged along the row direction and / or column direction, so that adjacent exposure windows 10b can be stitched together through the overlapping area, thereby obtaining an interconnection structure pattern with a larger area and size.

[0124] In this embodiment, the example is taken as if multiple connected exposure window areas 10b in the interconnection unit area 10a are arranged along the row direction.

[0125] More specifically, in this embodiment, the intermediary board 10 includes a redistribution board; the interconnection structure includes one or more redistribution layers. Accordingly, in this embodiment, the step of providing the intermediary board 10 includes: forming one redistribution layer; or, sequentially forming multiple redistribution layers.

[0126] In this embodiment, the steps of forming each redistribution layer include: forming a dielectric layer (not shown); forming interconnect vias (not shown) in the dielectric layer located in the interconnect cell region 10a, the interconnect vias exposing the lower redistribution layer; forming seed layers (not shown) on the bottom and sidewalls of the interconnect vias and on the dielectric layer; forming a pattern definition layer (not shown) on the seed layer; forming a plurality of interconnect openings (not shown) in the pattern definition layer located in the interconnect cell region 10a, the interconnect openings exposing the seed layers located in the interconnect vias and on the top of a portion of the dielectric layer; forming a conductive layer (not shown) on the seed layers exposed by the interconnect openings; removing the pattern layer; removing the seed layers exposed by the conductive layer, the remaining seed layers and the conductive layers on the seed layers are used to constitute the redistribution layer.

[0127] The dielectric layer is used to achieve isolation between redistribution layers. The dielectric layer is made of an insulating dielectric material, and in this embodiment, it is also made of a photolithographic material, which facilitates the patterning of the dielectric layer to form the interconnect vias through a photolithography process.

[0128] As an example, the material of the dielectric layer includes photosensitive polyimide (PI), photosensitive polybenzoxazole (PBO), or photosensitive benzocyclobutene (BCB). In this embodiment, the material of the dielectric layer is photosensitive polyimide.

[0129] Interconnect vias expose the underlying redistribution layer so that the resulting redistribution layer can be electrically connected to the underlying redistribution layer.

[0130] Accordingly, in this embodiment, the step of forming interconnect vias located in the interconnect cell region 10a in the dielectric layer includes: patterning the dielectric layer using a photolithography process to form the interconnect vias.

[0131] The seed layer is used as a seed layer for the subsequent formation of the conductive layer, and improves the adhesion between the conductive layer and the dielectric layer, reduces the generation of voids in the conductive layer, and improves the conductivity of the redistribution layer.

[0132] As an example, the seed layer is formed using a sputtering process.

[0133] The pattern definition layer is used to form interconnect openings after subsequent patterning processing, thereby defining the pattern of the interconnect structure. Specifically, the pattern definition layer is subsequently patterned using a photolithography process; therefore, the pattern definition layer is a photosensitive material. As an example, the material of the pattern definition layer is photoresist.

[0134] Interconnect openings are used to form patterns for interconnect structures and to provide spatial locations for forming interconnect structures. More specifically, in this embodiment, interconnect openings are used to define patterns for subsequent conductive layers and to provide spatial locations for forming conductive layers, thereby defining patterns for redistribution layers.

[0135] Specifically, the step of forming a plurality of interconnect openings located in the interconnect unit region 10a in the pattern definition layer includes: using a photolithography process to pattern the pattern definition layer and form a plurality of interconnect openings located in the interconnect unit region 10a in the pattern definition layer; the photolithography process includes sequentially exposing the pattern definition layer of each exposure window region 10b.

[0136] Accordingly, after the exposure processing of the pattern definition layer for each exposure window area 10b is completed, the pattern definition layer is also developed in order to form interconnect openings in the pattern definition layer.

[0137] The conductive layer, together with the seed layer, forms a redistribution layer. Specifically, the conductive layer can be formed using an electrochemical plating process. In other embodiments, a sputtering process can also be used to form the conductive layer.

[0138] In this embodiment, the material of the pattern definition layer is photoresist. The process for removing the pattern definition layer may include one or both of an ashing process and a wet photoresist stripping process.

[0139] The exposed seed layer of the conductive layer is removed to enable the patterning of the redistribution layer. As an example, a wet etching process is used to remove the exposed seed layer of the conductive layer.

[0140] It should be noted that, in this embodiment, before forming the intermediate plate 10, the method further includes: providing a support substrate 40; therefore, the intermediate plate 10 is formed on the support substrate 40.

[0141] Specifically, the supporting substrate 40 is used to provide support for the formation of the intermediate plate 10, and also provides an operating platform for subsequent processes.

[0142] In a specific implementation, the carrier substrate 40 can be a carrier wafer, which is circular in shape; or the carrier substrate 40 can be a carrier panel, which is square in shape.

[0143] like Figure 9 As shown, one or more device chips 20 are bonded on the first bonding surface 101 of the interposer 10, and the device chips 20 are electrically connected to the interconnect structure.

[0144] The device chip 20 is electrically connected to the interconnect structure, thereby enabling electrical connections between device chips 20 through the interconnect structure and subsequent interconnect chips.

[0145] Specifically, in this embodiment, interconnect terminals are formed on the device chip 20, and the interconnect terminals are electrically connected to the interconnect structure.

[0146] It should be noted that when each interconnect unit area 10a includes multiple exposure window areas 10b, the interconnect unit area 10a and the multiple device chips 20 are vertically opposite each other. The electrical connection between the multiple device chips 20 is realized by utilizing the interconnect structure formed by the multiple exposure window areas 10b.

[0147] When each interconnect unit region 10a includes an exposure window region 10b, each interconnect unit region 10a is vertically opposite to one or more device chips 20, and when each interconnect unit region 10a is vertically opposite to multiple device chips 20, the interconnect structure of each interconnect unit region 10a is used to realize electrical connection between multiple device chips 20.

[0148] Specifically, the device chip 20 includes a first chip surface 201 and a second chip surface 202 opposite to each other; the step of bonding one or more device chips 20 on the first bonding surface 101 of the interposer 10 includes: achieving bonding between the second chip surface 202 and the first bonding surface 101 of the interposer 10 through a first conductive structure 25.

[0149] Accordingly, in this embodiment, the interconnection terminal is electrically connected to the first conductive structure 25 so as to realize the electrical connection between the device chip 20 and the first conductive structure 25.

[0150] Specifically, in this embodiment, the first conductive structure 25 is formed on the first bonding surface 101 of the intermediary plate 10 to achieve bonding between the second chip surface 202 and the first conductive structure 25; or, the first conductive structure 25 is formed on the second chip surface 202 to achieve bonding between the first conductive structure 25 and the first bonding surface 101 of the intermediary plate 10; or, a first sub-conductive structure (not shown) is formed on the first bonding surface 101 of the intermediary plate 10, and a second sub-conductive structure (not shown) is formed on the second chip surface 202 to achieve bonding between the first sub-conductive structure and the second sub-conductive structure, wherein the first sub-conductive structure and the second sub-conductive structure are used to constitute the first conductive structure 25.

[0151] As one embodiment, the first conductive structure 25 is a conductive bump. In this embodiment, the first conductive structure 25 is formed using a bumping process.

[0152] In this embodiment, the material of the first conductive structure 25 includes one or more of tin, copper, aluminum, tungsten, cobalt, nickel, titanium, tantalum, titanium nitride, and tantalum nitride. As an example, the material of the first conductive structure 25 is tin.

[0153] It should be noted that in this embodiment, the bonding between the device chip 20 and the first bonding surface 101 of the interposer 10 is achieved through the first conductive structure 25 as an example. In other embodiments, the first conductive structure may be omitted based on actual process requirements.

[0154] In this embodiment, the first chip surface 201 is taken as the front side of the chip, and the second chip surface 202 is taken as the back side of the chip. Here, the front side of the chip refers to the side of the device chip 20 facing the device, and the back side of the chip refers to the side of the device chip 20 facing away from the device.

[0155] Accordingly, in this embodiment, flip chip technology is used to achieve bonding between the device chip 20 and the interposer 10.

[0156] In other embodiments, the first chip surface may be the back of the chip, and the second chip surface may be the front of the chip.

[0157] like Figures 10 to 11 As shown, an encapsulation layer 30 covering the sidewalls of the one or more device chips 20 is formed on the first bonding surface 101 of the interposer 10.

[0158] In this embodiment, the step of forming the encapsulation layer 30 includes: as follows Figure 10As shown, an encapsulation material layer 35 covering the one or more device chips 20 is formed on the first bonding surface 101 of the interposer 10; as Figure 11 As shown, the encapsulation material layer 35 above the device chip 20 is removed, exposing the side of the device chip 20 opposite to the interposer 10. The remaining encapsulation material layer 35 covering the sidewall of the device chip 20 is used as the encapsulation layer 30.

[0159] As an example, a molding process is used to form the encapsulation material layer 35.

[0160] As an example, a grinding process is used to remove the packaging material layer 35 above the device chip 20.

[0161] It should be noted that, in this embodiment, for ease of illustration and explanation, the encapsulation layer 30 is only shown in the cross-sectional view.

[0162] In this embodiment, after forming the encapsulation material layer 35 and before removing the encapsulation material layer 35 above the device chip 20, the method further includes removing the carrier substrate.

[0163] In this embodiment, after the intermediate plate 10 is formed, one or more device chips 20 are bonded on the first bonding surface 101 of the intermediate plate 10. The surface flatness of the intermediate plate 10 is good, which is beneficial to providing a flat surface and a high-quality bonding surface for bonding the device chips 20. This is beneficial to improving the bonding reliability of bonding the device chips 20 on the first bonding surface 101 of the intermediate plate 10. It is also beneficial to achieve a higher interconnection density between the intermediate plate 10 and the device chips 20 (e.g., increasing the density of the first conductive structure 25). In addition, bonding the device chips 20 after forming the intermediate plate 10 is beneficial to perform electrical performance testing on the device chips 20 before bonding them, which is beneficial to improving the packaging yield.

[0164] It should be noted that, in this embodiment, the steps of providing the packaging module are only an example for illustration, and the steps of providing the packaging module are not limited to this.

[0165] For example, in other embodiments, the step of providing the packaging module includes: providing a carrier plate; attaching one or more device chips to the carrier plate; forming the interposer on the one or more device chips; and removing the carrier plate.

[0166] Accordingly, in this embodiment, after one or more device chips are attached to the carrier board and before the interposer is formed, the method further includes forming an encapsulation layer on the carrier board that covers the sidewalls of the device chips. A detailed description of the encapsulation layer can be found in the corresponding descriptions in the foregoing embodiments, and will not be repeated here.

[0167] In this embodiment, the detailed steps for forming the interposer on one or more device chips are described in the corresponding descriptions of the foregoing embodiments, and will not be repeated here.

[0168] refer to Figures 12 to 13 , Figure 12 This is a top view. Figure 13 for Figure 12 The corresponding cross-sectional view shows that an interconnect chip 50 is bonded on the second bonding surface 102 of the interposer 10. The interconnect chip 50 is located on the interposer 10 between adjacent interconnect cell regions 10a and is electrically connected to the interconnect structure of the adjacent interconnect cell regions 10a.

[0169] In this embodiment, the packaging module 100 includes an interposer 10 and one or more device chips 20. The interposer 10 includes multiple interconnect unit regions 20a, which are spaced apart from each other. One or more device chips 20 are bonded to a first bonding surface 101 of the interposer 10, and the device chips 20 are electrically connected to the interconnect structure. Furthermore, interconnect chips 50 are bonded to a second bonding surface 102 of the interposer 10. The interconnect chips 50 are located between adjacent interconnect unit regions 10a and are electrically connected to the interconnect structure of adjacent interconnect unit regions 10a. Thus, the global interconnection of the interposer 10 is achieved through the interconnect structure and the interconnect chips 50, thereby enabling electrical connections between the device chips 20. This also helps to reduce the process requirements and difficulty of forming the interposer 10, while achieving high-density interconnection and optimizing the packaging process and packaging performance.

[0170] The interconnect chip 50 serves as a bridge to enable interconnection between adjacent interconnect cell regions 10a. Specifically, in this embodiment, the interconnect chip 50 is also located on top of a portion of the interconnect structure in the adjacent interconnect cell region 10a to enable electrical connection between the interconnect chip 50 and the interconnect structure.

[0171] Specifically, the interconnect chip 10 has one or more interconnect lines (not shown), and the surface of the interconnect chip 10 has external terminals (not shown), which are electrically connected to the interconnect lines. Specifically, there are at least two external terminals, which are electrically connected to the interconnect structures of adjacent interconnect unit regions 10a, thereby enabling them to connect adjacent interconnect unit regions 10a.

[0172] In this embodiment, the interconnect and the external terminal are made of metallic materials, such as one or more of copper, aluminum, tungsten, cobalt, nickel, titanium, tantalum, titanium nitride, and tantalum nitride.

[0173] In this embodiment, in the step of bonding the interconnect chip 50 on the second bonding surface 102 of the interposer 10, the interconnect chip 50 includes a first interconnect chip 51 and a second interconnect chip 52. The first interconnect chip 51 is electrically connected to the interconnect structure of the adjacent interconnect cell region 10a along the row direction, and the second interconnect chip 52 is electrically connected to the interconnect structure of the adjacent interconnect cell region 10a along the column direction.

[0174] As an example, there may be multiple second interconnect chips 52 connecting the same adjacent interconnect cell region 10a. Each interconnect chip 52 connects to the interconnect structure of the exposure window region 10b of the adjacent interconnect cell region 10a along the column direction, thereby increasing the interconnect density of adjacent interconnect cell regions 10a. In other embodiments, the number of second interconnect chips connecting the same adjacent interconnect cell region may be only one.

[0175] In this embodiment, the step of bonding the interconnect chip 50 on the second bonding surface 102 of the intermediary plate 10 includes: achieving bonding between the interconnect chip 50 and the intermediary plate 10 through the second conductive structure 90.

[0176] Specifically, a second conductive structure 90 is formed on the second bonding surface 102 of the interposer 10 to achieve bonding between the second conductive structure 90 and the interconnect chip 50; or, a second conductive structure 90 is formed on the interconnect chip 50 to achieve bonding between the second conductive structure 90 and the second bonding surface 102 of the interposer 10; or, a third sub-conductive structure (not shown) is formed on the second bonding surface 102 of the interposer 10; a fourth sub-conductive structure is formed on the interconnect chip 50; and bonding between the third sub-conductive structure and the fourth sub-conductive structure is achieved, wherein the third sub-conductive structure and the fourth sub-conductive structure are used to constitute the second conductive structure.

[0177] As one embodiment, the second conductive structure 90 is a conductive bump. In this embodiment, a bumping process is used to form the second conductive structure 90.

[0178] In this embodiment, the material of the second conductive structure 90 includes one or more of tin, copper, aluminum, tungsten, cobalt, nickel, titanium, tantalum, titanium nitride, and tantalum nitride. As an example, the material of the second conductive structure 90 is tin.

[0179] In this embodiment, the bonding between the second bonding surface 102 of the interposer 10 and the interconnect chip 50 is achieved through the second conductive structure 90 as an example. In other embodiments, the second conductive structure may be omitted based on actual process requirements.

[0180] It should be noted that, in this embodiment, the packaging method further includes: bonding a power connector 80 to the second bonding surface 102 of the intermediate plate 10, wherein the power connector 80 is electrically connected to the interconnect structure; and bonding an input / output connector 70 to the second bonding surface 102 of the intermediate plate 10, wherein the input / output connector 70 is electrically connected to the interconnect structure.

[0181] The power connector 80 is used to realize the electrical connection between the intermediate board 10 and the power module, so as to realize the power supply to the intermediate board 10, and then realize the power supply to the device chip 20 through the intermediate board 10.

[0182] The input / output connector 70 is used to connect the intermediate board 10 to the external circuit.

[0183] As an example, the input / output connector 70 includes a photonic integrated circuit (PIC) connector, which enables optical (e.g., fiber optic) interconnection of relatively distant interconnect ports on the interposer 10, thereby facilitating the shortest possible circuit and information transmission paths.

[0184] It should be noted that, in specific implementations, the interconnect unit region 10a may include a first region (not shown) for bonding interconnect chips 50 and a second region (not shown) for bonding connectors (e.g., the power connector and the input / output connector), wherein the interconnect density of the first region is higher than that of the second region.

[0185] In practice, during the formation of the interconnect structure pattern in the first region, multiple exposure window areas 10b are sequentially exposed to form the interconnect structure pattern. Specifically, a stepper lithography machine is used to sequentially expose the first region to form the interconnect structure pattern.

[0186] In practice, during the formation of the interconnect structure pattern in the second region, a global exposure method is used to perform a one-time exposure process in the second region, thereby forming the interconnect structure pattern. Specifically, a mask aligner is used for global exposure processing.

[0187] In this embodiment, the interconnect density of the first region is higher than that of the second region. By using different exposure methods in regions with different interconnect densities, higher exposure quality can be achieved in regions with higher interconnect density, while also saving time, which is conducive to improving production capacity.

[0188] Figures 14 to 15This is a schematic diagram of the structure corresponding to each step in another embodiment of the packaging method of the present invention. Figure 14 This is a top view. Figure 15 yes Figure 14 The corresponding sectional view. The similarities between this embodiment and the previous embodiments will not be repeated here. The differences between this embodiment and the previous embodiments are:

[0189] Each interconnect unit area 10a includes an exposure window area 10b.

[0190] In this embodiment, when each interconnect unit region 10a includes an exposure window region 10b, each interconnect unit region 10a is vertically opposite to one or more device chips 20, and the interconnect structure of each interconnect unit region 10a is used to realize electrical connection between multiple device chips 20.

[0191] Figures 16 to 17 This is a schematic diagram of the structure corresponding to each step in another embodiment of the packaging method of the present invention. Figure 16 This is a sectional view. Figure 17 for Figure 16 A magnified view at point B. The similarities between this embodiment and the previous embodiments will not be repeated here. The differences between this embodiment and the previous embodiments are:

[0192] In this embodiment, the intermediary board 210 is an adapter board, and the intermediary board 210 includes a substrate 250 and a backend metal layer 280 located on the substrate 250; the interconnect structure is the backend metal layer 280. The backend metal layer 280 is used to realize the electrical connection between device chips 220.

[0193] As an example, the adapter is a silicon interposer, and the substrate 250 is made of silicon. In other embodiments, depending on actual process requirements, the substrate may also be made of other semiconductor materials or insulating materials.

[0194] The back-end interconnect structure layer 280 is formed by a back-end process. Specifically, in this embodiment, a back-end dielectric structure layer (not shown) is formed on the substrate 250, and the back-end interconnect structure layer 280 is formed within the back-end dielectric structure layer.

[0195] The material of the back-end interconnect structure layer 280 is a metallic material, such as one or more of copper, aluminum, tungsten, cobalt, nickel, titanium, tantalum, titanium nitride, and tantalum nitride.

[0196] In this embodiment, the adapter board further includes a through-hole structure 240 penetrating the substrate 250, and the through-hole structure 240 is electrically connected to the rear interconnect structure layer 280.

[0197] The via structure 240 is electrically connected to the back interconnect structure layer, thereby facilitating the electrical connection between the back interconnect structure layers 280 of adjacent interconnect unit areas through the via structure 240 and the back interconnect structure layer 280, and thus realizing the electrical connection between the device chips 220.

[0198] Specifically, the interconnect chip 260 is electrically connected to the via structure 240 of the adjacent interconnect unit region; or, the interconnect chip 260 is electrically connected to the rear interconnect structure layer 280 of the adjacent interconnect unit region.

[0199] In this embodiment, the side of the adapter board with the rear interconnect structure layer 280 faces the device chip 220, thereby shortening the interconnect distance between the rear interconnect structure layer 280 and the device chip 220. Correspondingly, the interconnect chip 260 is electrically connected to the via structure 240 of the adjacent interconnect unit area, so that the interconnect chip 260 can realize the electrical connection between the rear interconnect structure layers 280 of the adjacent device unit areas through the via structure 240 of the adjacent interconnect unit area, and then realize the electrical connection between the device chips 220 through the interconnect chip 260, the via structure 240 and the rear interconnect structure layer 280.

[0200] In other embodiments, when the side of the adapter board with the back interconnect structure layer faces away from the device chip, the interconnect chip is electrically connected to the back interconnect structure layer of the adjacent interconnect unit area, and the device chip is electrically connected to the via structure. Thus, the interconnect chip can achieve electrical connection between device chips through the back interconnect structure layer and the via structure.

[0201] In this embodiment, the step of forming the intermediate plate 210 includes: providing a substrate 250 and the back-end interconnect structure layer 280; forming a plurality of through-hole structures 240 that penetrate the substrate 250 to a depth of a portion thereof, wherein the through-hole structures 240 are in contact with the back-end interconnect structure layer 280; and removing the portion of the substrate 250 above the end of the through-hole structure 240 to expose the through-hole structure 240.

[0202] In this embodiment, the adapter board is formed by semiconductor manufacturing process, and the through-hole structure 240 can have higher density, smaller spacing and size, thereby improving the interconnection density between device chips 220.

[0203] In this embodiment, the through-hole structure 240 is a through-silicon via (TSV) structure. The TSV structure, through vertical interconnection, can reduce the interconnection length between the device chip 220 and the substrate 250, which is beneficial for reducing signal delay, lowering capacitance / inductance, achieving low power consumption and high-speed communication, increasing bandwidth, and enabling miniaturization of device integration.

[0204] In this embodiment, the perforated structure 240 is made of a metallic material, such as one or more of copper, aluminum, tungsten, cobalt, nickel, titanium, tantalum, titanium nitride, and tantalum nitride. As an example, the perforated structure 240 is made of copper.

[0205] In this embodiment, the step of bonding the interconnect chip 260 on the second bonding surface of the interposer 210 includes: achieving bonding between the interconnect chip 260 and the interposer 210 through the second conductive structure 270. More specifically, the second conductive structure 270 achieves electrical connection between the interconnect chip 260 and the through-hole structure 240.

[0206] As one embodiment, the second conductive structure 270 is a conductive bump.

[0207] In this embodiment, the material of the second conductive structure 270 includes one or more of tin, copper, aluminum, tungsten, cobalt, nickel, titanium, tantalum, titanium nitride, and tantalum nitride. As an example, the material of the second conductive structure 270 is tin.

[0208] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A packaging structure, characterized in that, include: An interposer includes opposing first and second bonding surfaces. The interposer includes multiple interconnect cell regions spaced apart from each other. Interconnect structures are formed within each interconnect cell region. Each interconnect cell region includes an exposure window region, or the interconnect cell region includes multiple connected exposure window regions with overlapping areas between adjacent exposure window regions. One or more device chips are bonded to the first bonding surface of the interposer, and the device chips are electrically connected to the interconnect structure. An interconnect chip is bonded to the second bonding surface of the interposer, the interconnect chip being located on the interposer between adjacent interconnect cell regions and electrically connected to the interconnect structure of the adjacent interconnect cell regions.

2. The packaging structure as described in claim 1, characterized in that, The multiple interconnection unit regions are arranged in an array; The interconnection unit area includes multiple connected exposure window areas, and adjacent exposure window areas have overlapping areas; in each interconnection unit area, the multiple exposure window areas are arranged along the row direction, or, the multiple exposure window areas are arranged along the column direction; or, in each interconnection unit area, the multiple exposure window areas are arranged along both the row and column directions.

3. The packaging structure as described in claim 1, characterized in that, Each interconnect unit region includes an exposure window region; each interconnect unit region is vertically opposite to one or more of the device chips, and the interconnect structure of each interconnect unit region is used to realize electrical connections between multiple device chips.

4. The packaging structure according to any one of claims 1 to 3, characterized in that, The intermediate board is a redistribution structure board; the interconnection structure includes one or more redistribution layers.

5. The packaging structure according to any one of claims 1 to 3, characterized in that, The intermediate board is a transition board, which includes a substrate and a rear interconnect structure layer located on the substrate; the interconnect structure is the rear interconnect structure layer. The adapter board also includes a through-hole structure penetrating the substrate, and the through-hole structure is electrically connected to the rear interconnect structure layer; The interconnect chip is electrically connected to the via structure of the adjacent interconnect unit region; or, the interconnect chip is electrically connected to the rear interconnect structure layer of the adjacent interconnect unit region.

6. The packaging structure as described in claim 1, characterized in that, The plurality of interconnection unit regions are arranged in an array; the interconnection chip includes a first interconnection chip and a second interconnection chip, wherein the first interconnection chip is electrically connected to the interconnection structure of adjacent interconnection unit regions along the row direction, and the second interconnection chip is electrically connected to the interconnection structure of adjacent interconnection unit regions along the column direction.

7. The packaging structure as described in claim 1, characterized in that, The packaging structure further includes: a power connector, bonded to the second bonding surface of the interposer, and electrically connected to the interconnect structure; and an input / output connector, bonded to the second bonding surface of the interposer, and electrically connected to the interconnect structure.

8. A packaging method, characterized in that, include: A packaging module is provided, the packaging module comprising: an interposer having a first bonding surface and a second bonding surface opposite to each other, the interposer having a plurality of interconnect cell regions spaced apart from each other, and interconnect structures formed in the interconnect cell regions; and one or more device chips bonded to the first bonding surface of the interposer and electrically connected to the interconnect structures. The step of forming the intermediate plate includes: forming an interconnect structure pattern in the interconnect unit area; forming the interconnect structure pattern includes the step of sequentially exposing each exposure window area; each interconnect unit area includes one exposure window area, or each interconnect unit area includes multiple connected exposure window areas, and there is an overlapping area between adjacent exposure window areas; An interconnect chip is bonded on the second bonding surface of the interposer plate. The interconnect chip is located on the interposer plate between adjacent interconnect cell regions and is electrically connected to the interconnect structure of the adjacent interconnect cell regions.

9. The packaging method as described in claim 8, characterized in that, The steps of providing the packaging module include: forming the interposer; bonding one or more device chips to a first bonding surface of the interposer, the device chips being electrically connected to the interconnect structure; or... The steps of providing a packaging module include: providing a carrier board; attaching one or more device chips to the carrier board; forming the interposer on the one or more device chips; and removing the carrier board.

10. The packaging method as described in claim 8 or 9, characterized in that, The multiple interconnection unit regions are arranged in an array; Each interconnect unit area includes multiple connected exposure window areas, and adjacent exposure window areas have overlapping areas; in each interconnect unit area, the multiple exposure window areas are arranged along the row direction, or, the multiple exposure window areas are arranged along the column direction; or, in each interconnect unit area, the multiple exposure window areas are arranged along both the row and column directions.

11. The packaging method as described in claim 8 or 9, characterized in that, Each interconnect unit region includes an exposure window region; after one or more device chips are bonded on the first bonding surface of the interposer, each interconnect unit region is vertically opposite to one or more device chips, and the interconnect structure of each interconnect unit region is used to realize electrical connections between multiple device chips.

12. The packaging method according to any one of claims 8 to 11, characterized in that, The interposer board includes a redistribution structure board; the interconnection structure includes one or more redistribution layers.

13. The packaging method as described in claim 12, characterized in that, The steps of providing the packaging module include forming the intermediate board; The steps of forming the interposer include: forming a redistribution layer; or, sequentially forming multiple redistribution layers; The steps of forming each of the redistribution layers include: forming a dielectric layer; forming interconnect vias in the dielectric layer located in the interconnect cell region, the interconnect vias exposing the lower redistribution layer; forming a seed layer on the bottom and sidewalls of the interconnect vias and on the dielectric layer; forming a pattern definition layer on the seed layer; forming a plurality of interconnect openings in the pattern definition layer located in the interconnect cell region, the interconnect openings exposing the seed layer located within the interconnect vias and the seed layer located on top of a portion of the dielectric layer; forming a conductive layer on the seed layer exposed by the interconnect openings; removing the pattern definition layer; removing the seed layer exposed by the conductive layer, the remaining seed layer and the conductive layer on the seed layer constituting the redistribution layer.

14. The packaging method as described in claim 13, characterized in that, Each interconnect unit area includes an exposure window area, or each interconnect unit area includes multiple connected exposure window areas, with overlapping areas between adjacent exposure window areas; The step of forming a plurality of interconnect openings located in the interconnect cell region in the pattern definition layer includes: using a photolithography process to pattern the pattern definition layer and forming a plurality of interconnect openings located in the interconnect cell region in the pattern definition layer; The photolithography process includes sequentially exposing the graphic definition layer of each exposure window area.

15. The packaging method according to any one of claims 8 to 11, characterized in that, The intermediate board is a transition board, which includes a substrate and a rear interconnect structure layer located on the substrate; the interconnect structure is the rear interconnect structure layer. The adapter board also includes a through-hole structure penetrating the substrate, and the through-hole structure is electrically connected to the rear interconnect structure layer; The interconnect chip is electrically connected to the via structure of the adjacent interconnect unit region; or, the interconnect chip is electrically connected to the rear interconnect structure layer of the adjacent interconnect unit region.

16. The packaging method as described in claim 8, characterized in that, The multiple interconnection unit regions are arranged in an array; In the step of bonding interconnect chips on the second bonding surface of the interposer, the interconnect chips include a first interconnect chip and a second interconnect chip. The first interconnect chip is electrically connected to the interconnect structure of adjacent interconnect cell regions along the row direction, and the second interconnect chip is electrically connected to the interconnect structure of adjacent interconnect cell regions along the column direction.

17. The packaging method as described in claim 8, characterized in that, In the step of providing a packaging module, the packaging module further includes a packaging layer formed on a first bonding surface of the interposer and covering the sidewalls of the one or more device chips.

18. The packaging method as described in claim 8, characterized in that, The packaging method further includes: bonding a power connector to the second bonding surface of the intermediate plate, wherein the power connector is electrically connected to the interconnect structure; and bonding an input / output connector to the second bonding surface of the intermediate plate, wherein the input / output connector is electrically connected to the interconnect structure.

Images