Trench gate field effect transistor

Abstract

A trench gate field effect transistor includes a epitaxial structure with an epitaxial layer, a plurality of trenches, a plurality of gate electrode units disposed in the trenches, a plurality of source electrode units, a plurality of insulating units, a plurality of well regions in the epitaxial layer, a plurality of sources, and a plurality of contact electrode units for external electrical connection. Each trench has a first region, a necking region, and a second region with a width smaller than that of the first region. Each gate electrode unit has two first gate electrode portions in the first region, two second gate electrode portions in the necking region, and a third gate electrode portion in the second region. Each source electrode unit has a first source electrode portion between the first gate electrode portions and a second source electrode portion connected to the first source electrode portion and extending to the second region. Thus, the volume restriction in the structural design can be reduced, and the miniaturization of the trench gate field effect transistor is facilitated.

Description

Technical Field

[0001] This invention relates to a gate field-effect transistor, and more particularly to a trench gate field-effect transistor. Background Technology

[0002] As market demand for high-frequency power components gradually increases, the demand for trench gate field-effect transistors (MOSFETs) with low on-resistance and low rated voltage is also growing. The basic structure of a trench gate MOSFET includes an epitaxial multilayer structure, multiple trenches formed downwards from the top surface of the epitaxial multilayer structure, multiple gate electrodes disposed in the trenches, multiple source electrodes between the trenches, a drain electrode located on the bottom surface of the epitaxial multilayer structure, and multiple metal contact electrodes disposed on the epitaxial multilayer structure for connection to the gate electrodes and sources, respectively. By placing the gate electrodes in the trenches, the trench gate MOSFET can reduce on-resistance by increasing the trench density (i.e., shortening the width of the mesa between adjacent trenches) or shortening the distance between the gate electrode and the source, thereby reducing conduction energy loss and facilitating the miniaturization of the trench gate MOSFET.

[0003] However, increasing the trench density increases the capacitance between the source and gate electrodes, causing the Miller effect. Furthermore, the configuration of the metal contact electrodes also limits the space available for miniaturizing and reducing on-resistance in trench gate field-effect transistors. Summary of the Invention

[0004] The purpose of this invention is to provide a trench gate field-effect transistor that can reduce the on-resistance of the trench gate field-effect transistor and facilitate its miniaturization.

[0005] The trench gate field-effect transistor of the present invention includes an epitaxial multilayer structure, multiple trenches, multiple gate electrode units, multiple source electrode units, multiple insulating units, isolation units, contact electrode units, and a drain electrode.

[0006] The epitaxial multilayer structure has a first conductivity type doping and includes an epitaxial substrate, an epitaxial layer formed on the epitaxial substrate, a plurality of platform regions located on the epitaxial layer and spaced apart from each other along a first direction, a plurality of well regions formed from the top surface of the platform regions and having a second conductivity type doping, and a plurality of sources disposed in the well regions and having a first conductivity type doping.

[0007] The trenches are formed by extending downward from the surface of the epitaxial layer along a second direction intersecting the first direction, and the trenches are spaced apart from each other along the first direction. Each trench has a first region extending along the second direction, a necking region extending from one end of the first region along the second direction and gradually narrowing in width, and a second region extending away from the first region from one end of the necking region in the opposite direction to the first region. Each trench also has an upper half region distributed along the depth direction and a lower half region located below the upper half region. Any two adjacent trenches define either of the plateau regions of the epitaxial layer.

[0008] The gate electrode units are respectively disposed in the upper half of the trench, and each gate electrode unit has two first gate electrode portions located in the first region and spaced apart along the width direction of the trench, two second gate electrode portions located in the necking region, and one third gate electrode portion located in the second region. One end of each of the two second gate electrode portions is connected to the corresponding first gate electrode portion, and the other end is connected to each other and connected to the third gate electrode portion.

[0009] The source electrode units are respectively disposed in the trench. Each source electrode unit has a first source electrode portion located between the two first gate electrode portions and a second source electrode portion. The first source electrode portion extends downward from the top surface adjacent to the trench to the lower half of the trench. The second source electrode portion is connected to the first source electrode portion located in the lower half of the trench and extends to the second region via the necking region.

[0010] The insulating units are respectively filled in the trench, and each insulating unit covers the gate electrode unit and the source electrode unit.

[0011] The isolation unit is coated on the surface of the epitaxial layer and has electrical insulating properties.

[0012] The contact electrode unit is formed on the isolation unit for external electrical connection, including a gate contact electrode that passes through the isolation unit and is electrically connected to a third gate electrode portion located in the second region, and a source contact electrode that passes through the isolation unit and is electrically connected to the source electrode and a first source electrode portion located in the first region.

[0013] The drain electrode is disposed on the surface of the epitaxial substrate opposite to the epitaxial layer.

[0014] Preferably, in the trench gate field-effect transistor of the present invention, the gate contact electrode and the source contact electrode each have a plurality of conductive blocks that pass through the isolation unit and are electrically connected to the third gate electrode portion, the source electrode and the first source electrode portion, and extended electrode portions that are electrically connected to the conductive blocks and located on the isolation unit.

[0015] Preferably, in the trench gate field-effect transistor of the present invention, the isolation unit includes a first isolation layer coated on the surface of the epitaxial layer and a second isolation layer formed on the first isolation layer.

[0016] Preferably, in the trench gate field-effect transistor of the present invention, the material of the isolation unit is selected from at least one of oxide and phosphosilicate glass.

[0017] Preferably, in the trench gate field-effect transistor of the present invention, the thickness of the epitaxial layer is between 3 μm and 15 μm, and the depth of the trench is between 2 μm and 9 μm.

[0018] Preferably, in the trench gate field-effect transistor of the present invention, the center distance between any two adjacent first regions is between 2.5 μm and 5 μm, the width of the plateau region between the first regions of the two adjacent trenches is between 1 μm and 2.8 μm, and the width of the plateau region between the second regions of the two adjacent trenches is between 1.5 μm and 3.5 μm.

[0019] Preferably, in the trench gate field-effect transistor of the present invention, the center distance between any two adjacent first regions is between 2.5 μm and 3.5 μm, the width of the plateau region between the first regions of the two adjacent trenches is between 1 μm and 1.3 μm, and the width of the plateau region between the second regions of the two adjacent trenches is between 1.5 μm and 2 μm.

[0020] Preferably, in the trench gate field-effect transistor of the present invention, each plateau region has ion implantation regions respectively adjacent to the periphery of the sidewall of each trench and located below the well region, and the ion implantation regions distributed on the periphery of the first region of any two adjacent trenches are connected to each other, and the ion implantation regions distributed on the periphery of the second region are spaced apart, wherein the ion implantation regions are doped with a first conductivity type and the doping concentration is higher than the doping concentration of the epitaxial layer.

[0021] Preferably, in the trench gate field-effect transistor of the present invention, each insulating unit has a first insulating layer corresponding to the lower half of the trench and a second insulating layer corresponding to the upper half of the trench, and the thickness of the first insulating layer is greater than that of the second insulating layer.

[0022] Preferably, in the trench gate field-effect transistor of the present invention, the thickness of the first insulating layer is between 200 nm and 1000 nm.

[0023] The beneficial effects of the present invention are as follows: by disposing the source contact electrode and the gate contact electrode in the first region and the second region of the trench respectively, the volume limitation in structural design is reduced, which helps to miniaturize the trench gate field-effect transistor. In addition, by reducing the width of the platform region located in any two adjacent first regions, the on-resistance of the trench gate field-effect transistor can be reduced. Furthermore, by disposing the third gate electrode portion and the second source electrode portion located in the second region in the upper half region and the lower half region of the trench respectively, the capacitance area between them can be reduced. Therefore, while increasing the density of the trench, the capacitance value between them can be reduced. Attached Figure Description

[0024] Figure 1 This is a top view schematic diagram illustrating an embodiment of the trench gate field-effect transistor of the present invention;

[0025] Figure 2 This is a sectional view, along Figure 1 The cross-sectional structure of the trench gate field-effect transistor is illustrated by the II-II section line.

[0026] Figure 3 This is a sectional view, along Figure 1 Section III-III illustrates the cross-sectional structure of the trench gate field-effect transistor.

[0027] Figure 4 This is a sectional view, along Figure 1 The IV-IV section line illustrates the cross-sectional structure of the trench gate field-effect transistor.

[0028] Figures 5(a) to 5(h) This is a flowchart illustrating the fabrication method of the trench gate field-effect transistor, and the flowchart corresponds to... Figure 2 sectional structure;

[0029] Figures 6(a) to 6(h) This is a flowchart illustrating the fabrication method of the trench gate field-effect transistor, and the flowchart corresponds to... Figure 3 The cross-sectional structure. Detailed Implementation

[0030] Before the invention is described in detail, it should be noted that similar elements are represented by the same numbers in the following description. Furthermore, it should be noted that the accompanying drawings are only for illustrating the structural and / or positional relationships between elements and are not related to the actual dimensions of each element.

[0031] See Figures 1 to 4 The trench gate field-effect transistor of the present invention includes an epitaxial multilayer structure 2, multiple trenches 3, multiple gate electrode units 4, multiple source electrode units 5, multiple insulating units 6, isolation units 7, contact electrode units 8, and a drain electrode 9. Wherein, Figure 1 The isolation unit 7 and the contact electrode unit 8, which are formed on the topmost surface, are not shown. This is used to show the relative positions of the epitaxial multilayer structure 2, the trench 3, the gate electrode unit 4, and the source electrode unit 5 in the top view. Figures 2 to 4 They are respectively along Figure 1 The cross-sectional structure along the II-II, III-III, and IV-IV sections is shown, and the isolation unit 7, the contact electrode unit 8, and the drain electrode 9 located on the bottom surface of the epitaxial multilayer structure 2 are shown.

[0032] The epitaxial multilayer structure 2 includes an epitaxial substrate 21 with a first conductivity type doping, an epitaxial layer 22 formed on the epitaxial substrate 21 with the same conductivity type doping as the epitaxial substrate 21 but with a lower doping concentration, a plurality of mesa regions 23 located on the epitaxial layer 22 and spaced apart from each other along a first direction X parallel to the surface of the epitaxial layer 22, a plurality of well regions 24 formed downward from the top surface of the mesa regions 23 and having a second conductivity type doping, a plurality of sources 25 disposed in the well regions 24 and having a first conductivity type doping, and a plurality of ion implantation regions 26 located below the well regions 24 and having a first conductivity type doping. The first conductivity type doping and the second conductivity type doping are dopants with opposite conductivity types. In this embodiment, the first conductivity type doping is n-type doping and the second conductivity type doping is p-type doping as an example.

[0033] The trenches 3 are formed by extending downward from the surface of the epitaxial layer 22 along the depth direction Z and along a second direction Y parallel to the surface of the epitaxial layer 22 and intersecting the first direction X, and the trenches 3 are spaced apart from each other along the first direction X (in Figure 1 Only two adjacent grooves 3 along the first direction X are shown in the image.

[0034] Each trench 3 has a first region 31 extending along the second direction Y, a narrowing region 32 extending from one end of the first region 31 along the second direction Y and gradually decreasing in width, and a second region 33 extending from the narrowing region 32 away from the first region 31 in a direction away from the first region 31. That is, the width of the first region 31 along the first direction X is greater than the width of the second region 33, and the width of the narrowing region 32 gradually decreases from the first region 31 towards the second region 33. In addition, each trench 3 also has an upper half region 34 distributed along the depth direction Z, and a lower half region 35 located below the upper half region 34.

[0035] In this context, any two adjacent trenches 3 define one of the plateau regions 23 in the epitaxial layer 22. Therefore, the width Wa of the plateau region 23 between any two adjacent first regions 31 of the trenches 3 is narrower than the width Wb between the second regions 33. The well regions 24 are formed downwards along the depth direction Z from the top surface of each plateau region 23, and each well region 24 has a contact region 241 with the same doping type and a higher doping concentration as the well region 24. The source electrode 25 is approximately located between the necking region 32 of the trench 3 and the second region 33 (see [reference]). Figure 1 , Figure 3 The ion implantation regions 26 are formed adjacent to the outer periphery of the sidewall of each trench 3 and located below the well region 24, and their doping concentration is higher than that of the epitaxial layer 22. The ion implantation regions 26 located on the periphery of the first region 31 of the trench 3 are interconnected (see [reference]). Figure 2 The ion implantation regions 26 located around the second region 33 of the trench 3 are spaced apart (see [reference]). Figure 3 , Figure 4 ).

[0036] It should be noted that the thickness of the epitaxial layer 22 and the depth of the trench 3 may vary depending on the application and requirements of the actual device. In this embodiment, the thickness of the epitaxial layer 22 is between 3μm and 15μm, the depth of the trench 3 is between 2μm and 9μm, the center distance between the first regions 31 of any two adjacent trenches 3 is between 2.5μm and 5μm, the width Wa of the platform region 23 between the first regions 31 of the two adjacent trenches 3 is between 1μm and 2.8μm, and the width Wb of the platform region 23 between the second regions 33 of the two adjacent trenches 3 is between 1.5μm and 3.5μm, but this is not a limitation.

[0037] In some embodiments, the center distance between any two adjacent first regions 31 is between 2.5 μm and 3.5 μm, the width Wa of the platform region 23 between the first regions 31 of the two adjacent trenches 3 is between 1 μm and 1.3 μm, and the width Wb of the platform region 23 between the second regions 33 of the two adjacent trenches 3 is between 1.5 μm and 2 μm.

[0038] The gate electrode units 4 are respectively disposed in the trench 3 and located in the upper half region 34. Each gate electrode unit 4 has two first gate electrode portions 41 corresponding to the first region 31 and spaced apart along the width of the trench 3 (i.e. along the first direction X), two second gate electrode portions 42 corresponding to the necking region 32, and one third gate electrode portion 43 corresponding to the second region 33. One end of each of the two second gate electrode portions 42 is connected to the corresponding first gate electrode portion 41, and the other end is connected to each other and to the third gate electrode portion 43, so that the top view structure of the gate electrode unit 4 is generally Y-shaped.

[0039] The source electrode units 5 are respectively disposed in the trench 3. Each source electrode unit 5 has a first source electrode portion 51 located between the two first gate electrode portions 41 and a second source electrode portion 52. The first source electrode portion 51 extends downward from the upper half region 34 to the lower half region 35 from the top surface adjacent to the trench 3. The second source electrode portion 52 is located in the lower half region 35, connected to the first source electrode portion 51 located in the lower half region 35, and extends along the second direction Y through the necking region 32 to the second region 33, and is located below the second and third gate electrode portions 42 and 43.

[0040] In this embodiment, the gate electrode unit 4 and the source electrode unit 5 are made of polycrystalline silicon material.

[0041] The insulating unit 6 can be selected from insulating dielectric materials such as silicon oxide, silicon nitride, or silicon oxynitride, and is respectively filled in the trench 3 and covers the gate electrode unit 4 and the source electrode unit 5, so that the gate electrode unit 4 and the source electrode unit 5 are electrically isolated from each other. Each insulating unit 6 has a first insulating layer 61 corresponding to the lower half region 35 of the trench 3, and a second insulating layer 62 corresponding to the upper half region 34 of the trench 3. The first insulating layer 61 covers the first source electrode portion 51 and the second source electrode portion 52 located in the lower half region 35, and the second insulating layer 62 covers the first source electrode portion 51 and the gate electrode unit 4 located in the upper half region 34, and is located above the second source electrode portion 52 and the first insulating layer 61, and the top surface of the gate electrode unit 4 and the first source electrode portion 51 is exposed from the second insulating layer 62. In this embodiment, the material of the insulating unit 6 is silicon oxide, and the thickness of the second insulating layer 62 is less than the thickness of the first insulating layer 61. Preferably, the thickness of the first insulating layer 61 is between 200 nm and 1000 nm.

[0042] The isolation unit 7 is coated on the surface of the epitaxial layer 22 and has electrical insulating properties. It includes a first isolation layer 71 coated on the surface of the epitaxial layer 22, a second isolation layer 72 formed on the first isolation layer 71, and a plurality of openings 73 penetrating the isolation unit 7. Some of the openings 73 are formed corresponding to the first region 31 and are located at the first source electrode portion 51 (see...). Figure 2 The opening 73 is formed in the second region 33 and is located in the third gate electrode portion 43 (see...). Figure 4 The openings 73 in other parts are formed in the platform region 23 and are located at the source electrode 25 (see Figure 3 The opening 73 on the source electrode 25 has a length along the second direction Y that is approximately equal to the length of the source electrode 25. In this embodiment, the first isolation layer 71 of the isolation unit 7 is selected from low-temperature oxide (LTO), and the second isolation layer 72 is selected from borophosphorus silicate glass (BPSG).

[0043] In some embodiments, the first isolation layer 71 of the isolation unit 7 may also be selected from silicon oxide, the second isolation layer 72 may be selected from phosphor silicate glass (PSG), or the isolation unit 7 may also be a single-layer structure formed from one of the aforementioned materials without particular limitation.

[0044] The contact electrode unit 8 is made of conductive material and is available for external electrical connection. It has a gate contact electrode 81 and a source contact electrode 82. The gate contact electrode 81 is composed of a conductive block 811 filled in the opening 73 aligned with the third gate electrode portion 43 and electrically connected to the third gate electrode portion 43 located in the second region 33, and an extension electrode portion 812 extending outward from the conductive block 811 and formed on the surface of the isolation unit 7. The source contact electrode 82 is composed of a conductive block 821 filled in the opening 73 aligned with the first source electrode portion 51 and the source 25 and electrically connected to the first source electrode portion 51 located in the first region 31 and the source 25 located in the platform region 23, respectively, and an extension electrode portion 822 extending outward from the conductive block 821 and formed on the surface of the isolation unit 7. The conductive block 821 electrically connected to the source 25 extends to the corresponding well region 24 and contacts the contact area 241 (see...). Figure 3 In this embodiment, the conductive blocks 811 and 821 are selected from titanium, tungsten, or titanium-tungsten alloy, and the extended electrode portions 812 and 822 are selected from aluminum.

[0045] The drain electrode 9 is disposed on the surface of the epitaxial substrate 21 opposite to the epitaxial layer 22, and can be selected from conductive materials such as metal, transparent conductive metal oxide or conductive polymer.

[0046] Through the structural design of the trench 3, the present invention designs the end of the trench 3 (i.e., the first region 31) to have a larger width and the front end of the trench 3 (i.e., the second region 33) to have a smaller width. Therefore, under the same component size, it is easier to place the first source electrode portion 51 and the first gate electrode portion 41 in the first region 31 with a larger width (see...). Figure 1 and Figure 2 Furthermore, the width Wa of the platform region 23 corresponding to the first gate electrode portion 41 between two adjacent trenches 3 can be further reduced, thus allowing for more space in the structural design and contributing to the miniaturization of the trench gate field-effect transistor. Reducing the width Wa of the platform region 23 also more effectively lowers the on-resistance of the trench gate field-effect transistor and provides a good clamping effect. In addition, the present invention further extends the external electrical connection position of the gate electrode unit 4 located within the trench 3 to the second region 33 (see...). Figure 1 and Figure 3By placing the source electrode unit 5 and the gate electrode unit 4 located in the trench 3 at different electrical connection points (i.e., the first region 31 and the second region 33), the problems of short circuits or poor yield caused by contact electrode process defects due to excessively thin lines and small processable areas when the external electrical connection points of the source electrode unit 5 and the gate electrode unit 4 are located in the same region during device miniaturization can be reduced. In summary, the present invention contributes to the miniaturization of the trench gate field-effect transistor.

[0047] In cooperation Figures 5(a) to 6(h) The following steps illustrate the fabrication method of the trench gate field-effect transistor described in this embodiment. Among them, Figures 5(a) to 5(h) This describes the first region 31 corresponding to the groove 3 (corresponding to...). Figure 2 A flow diagram of the cross-sectional structure. Figures 6(a) to 6(h) This indicates that the same process corresponds to the second region 33 of the trench 3 (corresponding to...). Figure 3 A flowchart of the cross-sectional structure.

[0048] First, step (a) is performed. An epitaxial substrate formed by epitaxial growth and having a first conductivity type doped is provided. The epitaxial substrate has the epitaxial substrate 21 and the epitaxial layer 22 formed on the epitaxial substrate 21 with a doping concentration lower than that of the epitaxial substrate 21.

[0049] Next, step (b) is performed. Using a patterned shield (not shown), a plurality of trenches 3 of substantially the same depth, spaced apart from each other, are etched downwards from the surface of the epitaxial layer 22, with each trench 3 having a different width at the front and back. Specifically, each trench 3 has the following characteristics: Figure 1 The first region 31 shown, the necking region 32 extending from one side of the first region 31, and the second region 33 extending from the necking region 32 in a direction away from the first region 31, and having as shown Figure 2 The upper half region 34 and the lower half region 35 are shown to be distributed along the depth direction Z.

[0050] Next, step (c) is performed. First, an insulating protective layer (not shown) of a predetermined height is formed on the surface of the epitaxial layer 22. Then, oblique ion implantation is performed from the sidewalls of the trenches 3 at an angle of 4 to 15 degrees. The ion implantation region 26, as shown in Figures 5(a) and 6(a), is formed on the periphery of the sidewall of each trench 3 adjacent to the epitaxial layer 22 (but not at the position adjacent to the bottom of the trench 3). Afterward, the insulating protective layer is removed. Step (c) uses an oblique ion implantation method to control the ion implantation region 26 to be on the channel surface and not formed at the bottom of the trench 3, thus avoiding voltage drop in the product. As shown in Figure 5(a), since the width of each trench 3 in the first region 31 is relatively large (i.e., the width Wa of the platform region 23 located between the first regions 31 of adjacent trenches 3 is relatively small), the ion implantation regions 26 distributed around the first regions 31 of adjacent trenches 3 will be connected to each other. As shown in Figure 6(a), since the width of the trench 3 in the second region 33 is relatively small (i.e., the width Wb of the platform region 23 located between the second regions 33 of adjacent trenches 3 is relatively large), the ion implantation regions 26 distributed around the second regions 33 of adjacent trenches 3 will be spaced apart.

[0051] Next, step (d) is performed. An insulating layer 60 is formed on the inner wall of the trench 3 by deposition, thermal oxidation, or polymerization deposition using TEOS as a precursor, to obtain a first semi-finished product 100 with the structure shown in Figures 5(a) and 6(a).

[0052] Next, step (e) is performed. Polycrystalline silicon material P is deposited and filled in the trench 3 of the first semi-finished product 100 to obtain the structure shown in Figure 5(b) and Figure 6(b).

[0053] Next, step (f) is performed. The polysilicon material P structure located in the upper half region 34 of the second region 33 and the necking region 32 of each trench 3 is selectively removed by patterned masking (not shown). The polysilicon material P remaining in the lower half region 35 of the second region 33 and the necking region 32 forms the second source electrode portion 52, while the polysilicon material P that is not removed and remains in the first region 31 becomes the first source electrode portion 51. The patterned masking is then removed to obtain the structure shown in FIG5(c) and FIG6(c).

[0054] Next, step (f) is performed. The insulating layer 60 structure located in the upper half region 34 of the trench 3 is removed by etching, and the insulating material remaining in the lower half region 35 of the trench 3 forms the first insulating layer 61, thereby obtaining the second semi-finished product 200 as shown in Figures 5(d) and 6(d). At this time, the first source electrode portion 51 of the second semi-finished product 200 (see Figure 5(d)) is spaced apart from the sidewall of the trench 3.

[0055] Referring to Figures 5(e) and 6(e), a second insulating layer 62 is deposited within the trench 3 of the second semi-finished product 200 to cover the sidewalls of the trench 3, the side surface of the first source electrode portion 51, and the top surface of the first insulating layer 61 and the second source electrode portion 52, to obtain the third semi-finished product 300. At this time, the second insulating layer 62 located in the first region 31 forms two small trenches 3a on the first source electrode portion 51 and the sidewall of the trench 3.

[0056] Next, step (g) is performed. Polycrystalline silicon material is filled into the trenches 3 and small trenches 3a of the third semi-finished product 300, and the gate electrode unit 4 is formed in the upper half region 34 of each trench 3. The polycrystalline silicon material filled in the small trenches 3a of the first region 31 becomes as follows: Figure 1 The first gate electrode portion 41, located on both sides of the first source electrode portion 51, is filled with polysilicon material in the necking region 32 and the second region 33 to form the second gate electrode portion 42 and the third gate electrode portion 43.

[0057] Next, referring to Figures 5(f) and 6(f), step (h) is performed. A well region 24 with second conductivity type doping is formed from the top surface of the platform region 23 downwards in the upper half region 34. Then, after forming a patterned shield, the source electrode 25 with first conductivity type doping is formed in the well region 24 at the position corresponding to the necking region 32 of the trench 3 and the second region 33 by processes such as ion implantation and tempering, thereby obtaining the fourth semi-finished product 400.

[0058] Next, referring to Figures 5(g) and 6(g), step (i) is performed. An isolation unit 7, consisting of the first isolation layer 71 and the second isolation layer 72, is sequentially deposited onto the surface of the epitaxial layer 22 of the fourth semi-finished product 400 using a dielectric insulating material. Then, a portion of the structure of the isolation unit 7 is removed by etching to form the opening 73, exposing the corresponding polysilicon material and the source electrode 25, thus obtaining the fifth semi-finished product 500 as shown in Figures 5(g) and 6(g). In this embodiment, the first isolation layer 71 is selected from low-temperature oxides, the second isolation layer 72 is selected from borosilicate glass, and the opening 73 corresponds to the first source electrode portion 51 in the first region 31, the third gate electrode portion 43 in the second region 33, and the source electrode 25 in the plateau region 23 of each trench 3, and extends from the opening 73 corresponding to the source electrode 25 to the well region 24. Next, ion implantation is performed from the opening 73 corresponding to the source electrode 25, and a contact region 241 is formed at the bottom of the epitaxial layer 22 corresponding to the opening 73. This contact region 241 is doped in the same way as the well region 24, and the doping concentration is higher than that of the well region 24.

[0059] Next, step (j) is performed. Conductive material is deposited and filled into the opening 73 to form conductive blocks 811 and 821, which are electrically connected to the corresponding first source electrode portion 51, the third gate electrode portion 43, and the source electrode 25, respectively. Then, extended electrode portions 812 and 822, connected to the conductive blocks 811 and 821, are formed on the surface of the isolation unit 7 using conductive material, constituting the source contact electrode 82 and the gate contact electrode 81, which are electrically independent of each other.

[0060] Finally, step (k) is performed. The drain electrode 9 is formed on the side of the epitaxial substrate 21 opposite to the epitaxial layer 22 using a conductive material (as shown in Figures 5(h) and 6(h)), thus obtaining the trench gate field-effect transistor of this embodiment. In this embodiment, the conducting blocks 811 and 821 are selected from titanium, tungsten, or a titanium-tungsten alloy; the extended electrode portions 812 and 822 are selected from aluminum; and the drain electrode 9 is selected from conductive materials such as metal, transparent conductive metal oxide, or conductive polymer.

[0061] In the aforementioned fabrication method, since the gate contact electrode 81 and the source contact electrode 82 are respectively disposed at the front end (second region 33) and the end end (first region 31) of the trench 3, there is more space in the structural design, which improves the contact electrode process defects caused by the limited size and space of the existing gate field-effect transistor, reduces the occurrence of short circuits or poor yield, improves the stability of the process, and helps to miniaturize the trench gate field-effect transistor.

[0062] In summary, the trench gate field-effect transistor of the present invention reduces the impact of volume constraints in structural design by configuring the trench 3 into a first region 31 with a larger width and a second region 33 located on the other side with a smaller width. Therefore, with the same component size, it is easier to arrange the source contact electrode 82 and the gate contact electrode 81 at the external electrical connection positions located in different regions within the trench 3, which helps to further reduce the width of the plateau region 23 and reduce the on-resistance of the trench gate field-effect transistor. At the same time, it helps to miniaturize the trench gate field-effect transistor, thus achieving the purpose of the present invention.

Claims

1. A trench gate field-effect transistor, characterized in that: Include: An epitaxial multilayer structure having a first conductivity type doping includes an epitaxial substrate, an epitaxial layer formed on the epitaxial substrate, a plurality of platform regions located on the epitaxial layer and spaced apart from each other along a first direction, a plurality of well regions formed from the top surface of the platform regions and having a second conductivity type doping, and a plurality of sources disposed in the well regions and having a first conductivity type doping; Multiple trenches are formed from the surface of the epitaxial layer downward and extending along a second direction intersecting the first direction, and the trenches are spaced apart from each other along the first direction. Each trench has a first region extending along the second direction, a necking region extending along the second direction from one end of the first region and gradually narrowing in width, and a second region extending away from the first region from one end of the necking region in the opposite direction to the first region. Each trench also has an upper half region distributed along the depth direction and a lower half region located below the upper half region. Any two adjacent trenches define either of the plateau regions of the epitaxial layer. Multiple gate electrode units are respectively disposed in the upper half of the trench, and each gate electrode unit has two first gate electrode portions located in the first region and spaced apart along the width direction of the trench, two second gate electrode portions located in the necking region, and one third gate electrode portion located in the second region. One end of each of the two second gate electrode portions is connected to the corresponding first gate electrode portion, and the other end is connected to each other and connected to the third gate electrode portion. Multiple source electrode units are respectively disposed in the trench. Each source electrode unit has a first source electrode portion located between the two first gate electrode portions and a second source electrode portion. The first source electrode portion extends downward from the top surface adjacent to the trench to the lower half of the trench. The second source electrode portion is connected to the first source electrode portion located in the lower half of the trench and extends to the second region via the necking region. Multiple insulating units are respectively filled in the trench, and each insulating unit covers the gate electrode unit and the source electrode unit; The isolation unit is coated on the surface of the epitaxial layer and has electrical insulating properties; A contact electrode unit is formed on the isolation unit for external electrical connection, including a gate contact electrode that passes through the isolation unit and is electrically connected to a third gate electrode portion located in the second region, and a source contact electrode that passes through the isolation unit and is electrically connected to the source electrode and a first source electrode portion located in the first region; and The drain electrode is disposed on the surface of the epitaxial substrate opposite to the epitaxial layer.

2. The trench gate field-effect transistor according to claim 1, characterized in that: The gate contact electrode and the source contact electrode each have a plurality of conductive blocks that pass through the isolation unit and are electrically connected to the third gate electrode portion, the source electrode and the first source electrode portion, and extended electrode portions that are electrically connected to the conductive blocks and located on the isolation unit.

3. The trench gate field-effect transistor according to claim 1, characterized in that: The isolation unit includes a first isolation layer covering the surface of the epitaxial layer, and a second isolation layer formed on the first isolation layer.

4. The trench gate field-effect transistor according to claim 1, characterized in that: The material of the isolation unit is selected from at least one of oxides and phosphosilicate glass.

5. The trench gate field-effect transistor according to claim 1, characterized in that: The thickness of the epitaxial layer is between 3 μm and 15 μm, and the depth of the trench is between 2 μm and 9 μm.

6. The trench gate field-effect transistor according to claim 1, characterized in that: The center distance between any two adjacent first regions is between 2.5 μm and 5 μm, the width of the platform region between the first regions of the two adjacent trenches is between 1 μm and 2.8 μm, and the width of the platform region between the second regions of the two adjacent trenches is between 1.5 μm and 3.5 μm.

7. The trench gate field-effect transistor according to claim 6, characterized in that: The center distance between any two adjacent first regions is between 2.5 μm and 3.5 μm, the width of the platform region between the first regions of the two adjacent trenches is between 1 μm and 1.3 μm, and the width of the platform region between the second regions of the two adjacent trenches is between 1.5 μm and 2 μm.

8. The trench gate field-effect transistor according to claim 1, characterized in that: Each platform region has ion implantation regions adjacent to the periphery of the sidewall of each trench and located below the well region. The ion implantation regions distributed on the periphery of the first region of any two adjacent trenches are connected to each other, and the ion implantation regions distributed on the periphery of the second region are spaced apart. The ion implantation regions are doped with a first conductivity type and the doping concentration is higher than the doping concentration of the epitaxial layer.

9. The trench gate field-effect transistor according to claim 1, characterized in that: Each insulating unit has a first insulating layer corresponding to the lower half of the trench and a second insulating layer corresponding to the upper half of the trench, wherein the thickness of the first insulating layer is greater than that of the second insulating layer.

10. The trench gate field-effect transistor according to claim 9, characterized in that: The thickness of the first insulating layer is between 200 nm and 1000 nm.

Images