Method for manufacturing a silicon carbide semiconductor device

Abstract

Provided is a method for manufacturing a silicon carbide semiconductor device. The method includes the following steps: epitaxially growing an n-type silicon carbide layer as a measurement target layer; stabilizing surface electrons of the silicon carbide layer after the epitaxial growth; and after the stabilization of the surface electrons, charging the surface of the silicon carbide layer, and then measuring an n-type impurity concentration of the silicon carbide layer by measuring a surface potential of the silicon carbide layer.

Description

[0001] This application is a divisional application of Chinese patent application filed on February 13, 2020, with application number "202080016354.9" and title "Silicon Carbide Semiconductor Device and Manufacturing Method Thereof". Technical Field

[0002] The present invention relates to a SiC semiconductor device having a semiconductor element with a MOS structure made of silicon carbide (hereinafter referred to as SiC) and a method for manufacturing the same. Background Technology

[0003] Conventionally, SiC semiconductor devices with trench gate structures have been used to increase channel density and enable high current flow. These SiC semiconductor devices have the following structure: a p-type substrate region and an n-type drift layer are sequentially formed on top of an n-type drift layer. + Type source region, from n + The surface of the source region penetrates the p-type matrix region to achieve n + A trench gate is formed using an n-type drift layer method. Specifically, after epitaxially growing a p-type substrate region on an n-type drift layer, n-type impurities are incorporated into the p-type substrate region through ion implantation, causing a portion of the p-type substrate region to invert into an n-type state, thus forming an n-type drift layer. + Type source pole region (e.g., see Patent Document 1).

[0004] Existing technical documents

[0005] Patent documents

[0006] Patent Document 1: International Publication No. 2016 / 063644 Summary of the Invention

[0007] However, due to n + The entire source region is formed with a high concentration of n-type impurity layer, which increases the saturation current value when the load is short-circuited, making it impossible to obtain the short-circuit withstand capability of SiC semiconductor devices.

[0008] Furthermore, the film thickness non-uniformity during epitaxial growth increases with the thickness of the grown film. However, since the non-uniformity of the ion implantation range is not significant, the film thickness non-uniformity in the p-type substrate region after ion implantation corresponds to the non-uniformity of the epitaxially grown film thickness. Therefore, when forming n-type substrate regions using ion implantation... + In the case of the source pole region, n + The thickness non-uniformity of the p-type source region is less, while the thickness non-uniformity of the p-type matrix region is greater. Therefore, there is a problem of non-uniformity in the threshold Vt.

[0009] Furthermore, if n is formed through ion implantation +In the source region, due to the damage caused by ion implantation, the sides of the trench gate become tilted when a trench gate is formed. This leads to the following problems: decreased channel mobility, and the increased width of the trench gate at the trench inlet side, making device miniaturization more difficult.

[0010] Therefore, the inventors of this invention are concerned with not only forming a p-type matrix region through epitaxial growth, but also with n... + The p-type source region was also studied through epitaxial growth. In this way, the thickness inhomogeneity was separately allocated to the p-type matrix region and the n-type matrix region. + The n-type source region allows for a reduction in the thickness non-uniformity of the p-type matrix region. However, to make the n-type source region... + Epitaxial growth of the source region requires the introduction of a high concentration of n-type dopant gas into the epitaxial growth apparatus. + After the formation of the n-type source region, n-type dopant remains in the epitaxial growth apparatus, contaminating the growth furnace. Consequently, dopant contamination occurs during the subsequent formation of p-type or n-type layers, leading to the problem of unstable impurity concentration management.

[0011] The object of the present invention is to provide a SiC semiconductor device and a method thereof that can achieve improved short-circuit withstand capability, suppress unevenness of threshold Vt and tilting of the trench gate sidewalls, and easily manage impurity concentration.

[0012] One embodiment of the present invention provides a SiC semiconductor device comprising a semiconductor element, the semiconductor element including: a substrate of a first or second conductivity type, made of SiC; a drift layer formed on the substrate, made of SiC of a first conductivity type with a lower impurity concentration than the substrate; a substrate region formed on the drift layer, made of SiC of a second conductivity type; a source region formed on the substrate region, made of SiC of a first conductivity type with a higher impurity concentration than the drift layer; a trench gate structure comprising a gate insulating film covering the inner wall surface of the gate trench and a gate electrode disposed on the gate insulating film within a gate trench formed deeper than the substrate region from the surface of the source region, and multiple trenches arranged in a strip-like manner with one direction as the length direction; an interlayer insulating film covering the gate electrode and the gate insulating film, and having contact holes formed therein; a source electrode making ohmic contact with the source region through the contact holes; and a drain electrode formed on the back side of the substrate. Furthermore, the source region has a first source region consisting of an epitaxial growth layer formed on the substrate region side, and a second source region consisting of an ion implantation layer connected to the source electrode and having a higher concentration of first conductivity type impurities than the first source region.

[0013] In this way, the source region is constructed using a first source region with a lower concentration and a second source region with a higher concentration. Furthermore, the first source region is formed by epitaxial growth, and the second source region is formed by ion implantation. Therefore, a SiC semiconductor device can be obtained that achieves improved short-circuit withstand capability, suppression of threshold Vt non-uniformity and trench gate side tilt, and easy management of impurity concentration.

[0014] Another technical solution of the present invention relates to a method for manufacturing a SiC semiconductor device according to the above-mentioned technical solution of the present invention.

[0015] Specifically, the process includes the following steps: preparing a substrate of a first or second conductivity type made of SiC; forming a drift layer on the substrate, made of SiC of a first conductivity type with a lower impurity concentration than the substrate; forming a substrate region on the drift layer, made of SiC of a second conductivity type; forming a source region on the substrate region, the source region being made of SiC of a first conductivity type with a higher impurity concentration than the drift layer, having a first source region disposed on the substrate region side, and a second source region on the first source region with a higher impurity concentration than the first source region; and transferring the source region... After multiple gate trenches, deeper than the substrate region, are formed in a strip-like pattern along one length direction on the surface of the domain, a gate insulating film is formed on the inner wall of the gate trench, and a gate electrode is formed on the gate insulating film, thereby forming a trench gate structure; a source electrode electrically connected to the source region is formed; and a drain electrode is formed on the back side of the substrate; in the process of forming the substrate region, the substrate region is formed by epitaxial growth; in the process of forming the source region, after forming the first source region by epitaxial growth, the second source region is formed by ion implantation of a first conductivity type impurity into the first source region.

[0016] In this way, the first source region is formed by epitaxial growth, and the second source region is formed by ion implantation. As a result, it is possible to manufacture a SiC semiconductor device that achieves improved short-circuit withstand capability, suppression of threshold Vt non-uniformity and trench gate side tilt, and easy management of impurity concentration.

[0017] Another embodiment of the present invention provides a method for manufacturing a SiC semiconductor device, comprising the following steps: epitaxially growing an n-type SiC layer, which is the target layer for measurement; stabilizing the surface electrons of the SiC layer after epitaxial growth; and after stabilizing the surface electrons, charging the surface of the SiC layer by applying a charge, and measuring the n-type impurity concentration of the SiC layer by measuring the surface potential of the SiC layer.

[0018] In this way, after stabilizing the surface electrons of the SiC layer, the surface potential of the SiC layer is measured. This allows for the accurate measurement of the n-type impurity concentration in the SiC layer.

[0019] Furthermore, the bracketed reference numerals assigned to each constituent element indicate an example of the correspondence between that constituent element and the specific constituent elements described in the embodiments described later. Attached Figure Description

[0020] Figure 1 This is a cross-sectional view of the SiC semiconductor device according to the first embodiment.

[0021] Figure 2 yes Figure 1 The figure shows a three-dimensional cross-sectional view of a SiC semiconductor device.

[0022] Figure 3 This is a graph showing the results of a simulation investigation of the electron current density when the entire n-type source region is set to a high concentration.

[0023] Figure 4 This is a graph showing the results of a simulation investigation of the electron current density when the n-type source region is constructed using the first and second source regions.

[0024] Figure 5 This is a graph showing the results of simulation investigation of the change in drain current by changing the impurity concentration in the first source region.

[0025] Figure 6 This is a graph showing the results of a simulation investigation into the relationship between the n-type impurity concentration and the on-resistance in the first source region.

[0026] Figure 7A It means Figure 1 A three-dimensional cross-sectional view of the manufacturing process of the SiC semiconductor device shown.

[0027] Figure 7B It continues Figure 7A The figure represents a three-dimensional cross-sectional view of the manufacturing process of a SiC semiconductor device.

[0028] Figure 7C It continues Figure 7B The figure represents a three-dimensional cross-sectional view of the manufacturing process of a SiC semiconductor device.

[0029] Figure 7D It continues Figure 7C The figure represents a three-dimensional cross-sectional view of the manufacturing process of a SiC semiconductor device.

[0030] Figure 7E It continues Figure 7D The figure represents a three-dimensional cross-sectional view of the manufacturing process of a SiC semiconductor device.

[0031] Figure 7F It continues Figure 7EThe figure represents a three-dimensional cross-sectional view of the manufacturing process of a SiC semiconductor device.

[0032] Figure 7G It continues Figure 7F The figure represents a three-dimensional cross-sectional view of the manufacturing process of a SiC semiconductor device.

[0033] Figure 8 This is a cross-sectional view of the SiC semiconductor device according to the second embodiment.

[0034] Figure 9 This is a graph showing the results of investigating the voltage distribution during reverse conduction when the entire n-type source region is set to a high impurity concentration.

[0035] Figure 10 This is a graph showing the results of investigating the voltage distribution during reverse conduction when the first source region is formed by grounding the p-type substrate region.

[0036] Figure 11 This is a graph showing the results of investigating the voltage distribution during reverse conduction in the case of an undoped layer.

[0037] Figure 12 This is a diagram illustrating the process for determining the concentration of n-type impurities as described in the third embodiment.

[0038] Figure 13 This is a perspective view showing the measurement status of the n-type impurity concentration as described in the third embodiment.

[0039] Figure 14 This is a graph showing the relationship between the time of exposure to the atmosphere after epitaxial growth of the n-type layer and the measured n-type concentration.

[0040] Figure 15 This is a graph showing the relationship between the concentration evaluation values ​​before and after HF treatment.

[0041] Figure 16 This is a diagram illustrating the process for determining the concentration of n-type impurities, as another example of the third embodiment.

[0042] Figure 17 This is a diagram showing the process for determining the concentration of n-type impurities as described in the fourth embodiment. Detailed Implementation

[0043] Hereinafter, embodiments of the present invention will be described based on the accompanying drawings. Furthermore, in each of the following embodiments, the same reference numerals will be used to describe the same or equivalent parts.

[0044] (First Embodiment)

[0045] The first embodiment will be described. In the SiC semiconductor device of this embodiment, a semiconductor element is formed with Figure 1 and Figure 2 The diagram shows an inverted vertical MOSFET with a trench gate structure. These vertical MOSFETs are formed within a cell region of a SiC semiconductor device, and this cell region is surrounded to form an outer peripheral breakdown structure, thus constituting the SiC semiconductor device. However, only vertical MOSFETs are illustrated here. Additionally, the following... Figure 1 and Figure 2 As shown, the width direction of the vertical MOSFET is defined as the X direction, the depth direction of the vertical MOSFET intersecting the X direction is defined as the Y direction, and the thickness direction or depth direction of the vertical MOSFET, i.e., the normal direction relative to the XY plane, is defined as the Z direction.

[0046] like Figure 1 and Figure 2 As shown, in SiC semiconductor devices, n-type semiconductors made of SiC are used. + Type substrate 1 serves as a semiconductor substrate. In n... + n-type substrate 1 is formed on its main surface by means of SiC － Type 2. n + The surface of substrate 1 is a (0001) Si plane, for example, with an n-type impurity concentration of 5.9 × 10⁻⁶. 18 / cm 3 The thickness is 100 μm. － For example, the concentration of n-type impurities in layer 2 is 7.0 × 10⁻⁶. 15 ~2.0×10 16 / cm 3 The thickness is 8.0 μm.

[0047] In n － Above the top layer 2, a JFET portion 3 made of SiC and an electric field blocking layer 4 are formed. － Type 2 in from n + The substrate 1 is separated from the position where it is connected to the JFET section 3.

[0048] JFET section 3 and electric field blocking layer 4 constitute a saturation current suppression layer, and are arranged extending in the X direction and alternately and repeatedly arranged in the Y direction. That is, from n + When viewed from the normal direction of the main surface of the substrate 1, at least a portion of the JFET portion 3 and the electric field blocking layer 4 are respectively in the form of multiple narrow strips, i.e. strips, arranged alternately.

[0049] Furthermore, in this embodiment, the JFET portion 3 is formed below the electric field blocking layer 4. Therefore, although the strip-shaped portion of the JFET portion 3 is connected below the electric field blocking layer 4, each strip-shaped portion is disposed between the plurality of electric field blocking layers 4.

[0050] Regarding the strip-shaped portions of JFET section 3, each narrow strip-shaped portion has a width of, for example, 0.25 μm, and the spacing between the forming intervals is, for example, 0.6 to 2.0 μm. Furthermore, the thickness of JFET section 3 is, for example, 1.5 μm, and the n-type impurity concentration is higher than that of n-type impurities. － Layer 2 height, for example, is 5.0 × 10 16 ~2.0×10 18 / cm 3 .

[0051] The electric field blocking layer 4 is composed of a p-type impurity layer. As described above, the electric field blocking layer 4 is strip-shaped, and each narrow strip portion of the strip-shaped electric field blocking layer 4 has a width of, for example, 0.15 μm and a thickness of, for example, 1.4 μm. Furthermore, the p-type impurity concentration of the electric field blocking layer 4 is, for example, 3.0 × 10⁻⁶. 17 ~1.0×10 18 / cm 3 In this embodiment, the p-type impurity concentration of the electric field blocking layer 4 is fixed in the depth direction. Furthermore, the electric field blocking layer 4 is related to the n-type impurity concentration. － The surface on the opposite side of the type layer 2 and the surface of the JFET part 3 are on the same plane.

[0052] Furthermore, an n-type current dispersing layer 5 made of SiC is formed on top of the JFET section 3 and the electric field blocking layer 4. As described later, the n-type current dispersing layer 5 is a layer that allows the current flowing through the channel to diffuse in the X direction; for example, the n-type impurity concentration is higher than that of the n-type current dispersing layer. － The n-type layer 2 is high. In this embodiment, the n-type current dispersing layer 5 extends in the Y direction, and the n-type impurity concentration is the same as or higher than that of the JFET section 3, for example, the thickness is 0.5 μm.

[0053] Additionally, for convenience, the drift layer is divided into n... － The n-type layer 2, JFET section 3, and n-type current dispersing layer 5 will be described, but they are all components of the drift layer and are interconnected.

[0054] A p-type substrate region 6 made of SiC is formed on the n-type current dispersing layer 5. Furthermore, an n-type source region 8 is formed on the p-type substrate region 6. The n-type source region 8 is formed on the portion of the p-type substrate region 6 corresponding to the n-type current dispersing layer 5.

[0055] Regarding the p-type substrate region 6, its thickness is thinner than that of the electric field barrier layer 4, and its p-type impurity concentration is lower, for example, 3 × 10⁻⁶. 17 / cm 3 The thickness is 0.4–0.6 μm.

[0056] The n-type source region 8 has a structure in which the n-type impurity concentration differs on the p-type substrate region 6 side and on the opposite side, i.e., the device surface side. Specifically, the n-type source region 8 has a structure having a first source region 8a disposed on the p-type substrate region 6 side and a second source region 8b disposed on the device surface side.

[0057] Regarding the first source region 8a, the n-type impurity concentration is lower than that of the second source region 8b, and it is composed of an epitaxial growth layer. In this embodiment, it is connected to the p-type substrate region 6. For example, the n-type impurity concentration in the first source region 8a is 2.0 × 10⁻⁶. 16 ~1.0×10 17 / cm 3 The thickness is 0.2 to 0.5 μm, preferably 0.3 μm or more.

[0058] The second source region 8b is used to achieve contact with the source electrode 15 described later. It is composed of an ion implantation layer with a high concentration of n-type impurities. For example, the n-type impurity concentration in the second source region 8b is 1.0 × 10⁻⁶. 18 ~5.0×10 19 / cm 3 The thickness is 0.1–0.2 μm.

[0059] Furthermore, specifically, a p-type deep layer 9 is formed downwards from the p-type substrate region 6, in the portion between the surface of the JFET section 3 and the electric field blocking layer 4 and the p-type substrate region 6 where the n-type current dispersing layer 5 is not formed. In this embodiment, the p-type deep layer 9 is arranged in a strip shape, with the Y direction being the length direction, intersecting the strip-shaped portion in the JFET section 3 and the length direction of the electric field blocking layer 4. Multiple strips are arranged in the X direction to form a strip shape. The p-type substrate region 6 and the electric field blocking layer 4 are electrically connected via this p-type deep layer 9. The formation spacing of the p-type deep layer 9 corresponds to the cell spacing, which is described later as the formation interval of the trench gate structure, and the p-type deep layer 9 is arranged between adjacent trench gate structures.

[0060] Furthermore, a p-type interconnect layer 10 is formed on the p-type substrate region 6 at a position corresponding to the p-type deep layer 9—in other words, at a position different from the n-type source region 8 and on the opposite side of the trench gate structure, separated by the n-type source region 8. The p-type interconnect layer 10 is used to electrically connect the p-type substrate region 6 to the source electrode 15 (described later). In this embodiment, the p-type interconnect layer 10 has a structure where the p-type impurity concentration differs on the p-type substrate region 6 side and its opposite side, i.e., the device surface side. Specifically, the p-type interconnect layer 10 has a structure having a first region 10a disposed on the p-type substrate region 6 side and a second region 10b disposed on the device surface side.

[0061] Region 10a is configured to be the same depth as or deeper than the first source region 8a, with a lower p-type impurity concentration than the second region 10b, and is a structure that connects to the p-type substrate region 6. For example, the p-type impurity concentration in region 10a is 2.0 × 10⁻⁶. 17 ~1.0×10 19 / cm 3 The thickness is 0.2 to 0.5 μm, preferably 0.3 μm or more. However, in this embodiment, since the first region 10a is formed by ion implantation into the first source region 8a, the carrier concentration, i.e., the concentration of p-type impurities that function as carriers, is set to 2.0 × 10⁻⁶. 17 ~1.0×10 19 / cm 3 .

[0062] The second region 10b, with the same depth as the second source region 8b, is used to achieve contact with the source electrode 15 described later, and has a high concentration of p-type impurities. For example, the p-type impurity concentration in the second region 10b is 2.0 × 10⁻⁶. 18 ~1.0×10 20 / cm 3 The thickness is 0.2–0.3 μm. However, in this embodiment, since the second region 10b is formed by ion implantation into the second source region 8b, the carrier concentration, i.e., the concentration of p-type impurities that function as carriers, is 2.0 × 10⁻⁶. 18 ~1.0×10 20 / cm 3 .

[0063] Furthermore, as described later, in this embodiment, a p-type interconnect layer 10 is formed by ion implantation of p-type impurities into the n-type source region 8. In this case, the p-type impurity concentration in the first region 10a and the second region 10b refers to the concentration of impurities in the p-type impurities that function as charge carriers. A portion of the p-type impurities cancels out the n-type impurities contained in the first source region 8a before implantation and does not function as charge carriers. Therefore, when the p-type interconnect layer 10 is formed by ion implantation, considering the activation rate, for example, if p-type impurities are implanted at a dose 2 to 10 times the n-type impurity concentration in the first source region 8a and the second source region 8b, the aforementioned p-type impurity concentration can be obtained.

[0064] Furthermore, a gate trench 11 is formed such that the n-type source region 8 and the p-type substrate region 6 are penetrated to reach the n-type current dispersion layer 5, for example, with a width of 0.4 μm and a depth 0.2 to 0.4 μm deeper than the combined film thickness of the p-type substrate region 6 and the n-type source region 8. The aforementioned p-type substrate region 6 and n-type source region 8 are arranged in a manner that connects to the sidewalls of the gate trench 11. The gate trench 11 is formed in such a manner that... Figure 2 The X direction is the width direction, and the direction intersecting the length direction of the JFET section 3 and the electric field blocking layer 4 is a narrow strip layout with the Y direction as the length direction and the Z direction as the depth direction. Furthermore, although in Figure 1 and Figure 2 Although not illustrated, the gate trench 11 is arranged in the form of multiple strips at equal intervals in the X direction, with a p-type substrate region 6 and an n-type source region 8 disposed between each strip. In addition, a p-type deep layer 9 and a p-type interconnect layer 10 are disposed in the middle of each gate trench 11.

[0065] On the side of the gate trench 11, the p-type substrate region 6 forms a channel region connecting the n-type source region 8 and the n-type current dispersing layer 5 when the vertical MOSFET is operated. The inner wall of the gate trench 11, including this channel region, is covered by a gate insulating film 12. A gate electrode 13 made of doped polysilicon (Poly-Si) is formed on the surface of the gate insulating film 12. The gate insulating film 12 and the gate electrode 13 completely fill the gate trench 11, forming a trench gate structure.

[0066] The trench gate structure has a sidewall of gate trench 11 that is generally parallel to the Z direction, has a rounded inclination at the entrance side of the opening, and has a slightly wider opening width compared to the bottom. More specifically, the portion of the sidewall of gate trench 11 that is in contact with the first source region 8a, the p-type substrate region 6, and the n-type current dispersing layer 5 is generally parallel to the Z direction, while the portion that is in contact with the second source region 8b is in a rounded inclination.

[0067] Furthermore, a source electrode 15 and a gate wiring layer (not shown) are formed on the surface of the n-type source region 8 and the surface of the gate electrode 13, separated by an interlayer insulating film 14. The source electrode 15 and the gate wiring layer are made of various metals, such as Ni / Al. Among these various metals, at least the portion in contact with the n-type source region 8, specifically the n-type SiC, is made of a metal capable of ohmic contact with the n-type SiC. Furthermore, among these various metals, at least the portion in contact with the second region 10b, specifically the p-type SiC, is made of a metal capable of ohmic contact with the p-type SiC. Additionally, the source electrode 15 is partially electrically insulated from the SiC by being formed on the interlayer insulating film 14, but is electrically contacted with the n-type source region 8 and the p-type deep layer 9 through contact holes formed in the interlayer insulating film 14.

[0068] On the other hand, in n + On the back side of the substrate 1, a surface with n is formed. + The drain electrode 16 is electrically connected to the substrate 1. This configuration forms a vertical MOSFET with an n-channel inverted trench gate structure. Multiple such vertical MOSFETs are arranged to form a cell region. Furthermore, a peripheral breakdown voltage structure (not shown) formed by a guard ring or the like is formed and surrounded by this cell region where the vertical MOSFETs are formed, thus constituting a SiC semiconductor device.

[0069] This SiC semiconductor device with a vertical MOSFET, configured in this way, operates by applying a gate voltage Vg of 20V to the gate electrode 13, for example, with the source voltage Vs set to 0V and the drain voltage Vd set to 1-1.5V. That is, the vertical MOSFET forms a channel region in the p-type substrate region 6, the portion connected to the gate trench 11, by applying the gate voltage Vg. This enables conduction between the n-type source region 8 and the n-type current dispersing layer 5. Therefore, the vertical MOSFET operates as follows: it allows current to flow from the n-type source region 8... + Type substrate 1, processed by n － The drift layer, consisting of the n-type layer 2, the JFET section 3, and the n-type current dispersion layer 5, flows from the channel region through the n-type source region 8 and between the drain and source.

[0070] Furthermore, if the vertical MOSFET in such a semiconductor device is applied to an inverter circuit with upper and lower arms, the parasitic diode built into the vertical MOSFET functions as a freewheeling diode. Specifically, through n － The PN junction formed by the n-type layer (including the drift layer 2) and the p-type layer (including the electric field blocking layer 4, the p-type substrate region 6, or the p-type deep layer 9) constitutes a parasitic diode, which functions as a freewheeling diode.

[0071] Inverter circuits and the like are used when using a DC power supply and supplying AC current to loads such as AC motors. For example, inverter circuits and the like connect multiple bridge circuits with their upper and lower arms connected in series in parallel with respect to a DC power supply, and supply AC current to the load by repeatedly switching the upper and lower arms of each bridge circuit on and off.

[0072] Specifically, in each bridge circuit of an inverter circuit, current is supplied to the load by turning on the upper arm's vertical MOSFET and turning off the lower arm's vertical MOSFET. Then, the upper arm's vertical MOSFET is turned off and the lower arm's vertical MOSFET is turned on, stopping the current supply. Furthermore, during the switching of the vertical MOSFETs on and off in each arm, the parasitic diode in the vertical MOSFET on the off side functions as a freewheeling diode, performing reverse conduction to allow freewheeling current to flow between the source and drain. In this way, AC drive is performed on the load based on the inverter circuit, etc.

[0073] When such an operation is performed, if a load short circuit occurs, a voltage of, for example, 600–1200V or higher is applied to the drain as the drain-source voltage Vds. At this time, if the entire n-type source region 8 is composed of a high-concentration n-type impurity layer, the saturation current value during a load short circuit becomes large, and the short-circuit withstand capability of the SiC semiconductor device cannot be obtained. This can be attributed to the fact that, due to the high concentration of n-type impurities in the source region 8, almost no depletion region is generated, and current flows throughout the entire region of the n-type source region 8.

[0074] However, in the SiC semiconductor device of this embodiment, since the n-type source region 8 includes a first source region 8a with a lower concentration and a second source region 8b with a higher concentration, the saturation current value during a load short circuit can be reduced. This can be attributed to the fact that, since the first source region 8a has a low concentration, depletion occurs over a large area of ​​the first source region 8a, and no current flows through the depleted portion. Thus, the short-circuit withstand capability of the SiC semiconductor device according to this embodiment can be improved.

[0075] Here, through simulation, the electron current density was investigated for the case where the entire n-type source region 8 is of high concentration and for the case where it is composed of the first source region 8a and the second source region 8b as in this embodiment. Figure 3 and Figure 4 These are graphs showing the results. In the graphs, the narrower the spacing of the hoods, the higher the electron current density. Furthermore, the change in drain current was investigated by varying the impurity concentration in the first source region 8a. Figure 5 This indicates the result.

[0076] In addition, Figures 3-5In the simulation, the source voltage Vs was set to 0V, the gate voltage Vg to 20V, and the drain voltage Vd to 750V. Furthermore, in Figure 3 In the simulation, the n-type impurity concentration of the entire n-type source region 8 was set to 1.0 × 10⁻⁶. 19 / cm 3 Similarly, in Figure 4 In the simulation, the n-type source region 8 is constructed using the first source region 8a and the second source region 8b, and the n-type impurity concentration of the first source region 8a is set to 1.0 × 10⁻⁶. 16 / cm 3 The n-type impurity concentration in the second source region 8b is set to 1.0 × 10⁻⁶. 19 / cm 3 .exist Figure 5 In the simulation, the n-type source region 8 is constructed using the first source region 8a and the second source region 8b, and the n-type impurity concentration of the second source region 8b is set to 1.0 × 10⁻⁶. 19 / cm 3 This causes a change in the concentration of n-type impurities in the first source region 8a.

[0077] like Figure 3 As shown, when the n-type impurity concentration is set to high throughout the entire n-type source region 8, the electron current density increases throughout the entire n-type source region 8. This can be attributed to the fact that, due to the high concentration in the n-type source region 8, almost no depletion region is generated, and current flows throughout the entire n-type source region 8.

[0078] On the other hand, such as Figure 4 As shown, when the n-type source region 8 is constructed using the first source region 8a and the second source region 8b, the electron current density in the first source region 8a decreases. This can be attributed to the fact that, since the first source region 8a has a low concentration, depletion occurs over a large area of ​​the first source region 8a, and no current flows through the depleted portion.

[0079] Based on the simulation results, it can be said that by constructing the n-type source region 8 using the first source region 8a and the second source region 8b, the saturation current value under load short circuit can be reduced. Therefore, it can be seen that by adopting the structure of this embodiment, the short-circuit withstand capability of the SiC semiconductor device can be improved.

[0080] Furthermore, regarding the first source region 8a, the n-type impurity concentration only needs to be lower than that of the second source region 8b; however, if the concentration is not at a certain level, the saturation current value cannot be reduced to the desired value. Specifically, if the drain current under load short-circuit conditions is 14000 A / cm... 2 The desired short-circuit withstand capability can then be obtained. Furthermore, as... Figure 5 As shown, the drain current becomes 14000 A / cm when the load is short-circuited. 2 The following case assumes that the n-type impurity concentration in the first source region 8a is 1.0 × 10⁻⁶. 17 / cm 3 The following situation applies. Therefore, by setting the n-type impurity concentration of the first source region 8a to 1.0 × 10⁻⁶, as in the SiC semiconductor device of this embodiment,... 17 / cm 3 The following can improve short-circuit withstand capability.

[0081] However, if the n-type impurity concentration in the first source region 8a is too low, the resistance of the first source region 8a will be too high, increasing the on-resistance Ron. The relationship between the n-type impurity concentration and the on-resistance Ron in the first source region 8a was investigated, and the results were obtained... Figure 6 The results are shown. Given the high-speed switching operation of SiC semiconductor devices, a preferred on-resistance Ron is 1.2 mΩcm. 2 The following. According to Figure 6 The result is that if the n-type impurity concentration in the first source region 8a is less than 2.0 × 10⁻⁶, 16 / cm 3 If the concentration of n-type impurities is higher than that, the on-resistance Ron increases sharply. However, if the concentration of n-type impurities is higher than that, the on-resistance Ron can be reduced to 1.2 mΩcm. 2 Therefore, by setting the n-type impurity concentration of the first source region 8a to 2.0 × 10⁻⁶, as in the SiC semiconductor device of this embodiment,... 16 / cm 3 The above measures can suppress the degradation of the on-resistance Ron.

[0082] Thus, by setting the n-type impurity concentration in the first source region 8a to 2.0 × 10⁻⁶, 16 ~1.0×10 17 / cm 3 This can improve short-circuit withstand capability and suppress the degradation of on-resistance Ron.

[0083] Furthermore, the SiC semiconductor device of this embodiment includes a JFET portion 3 and an electric field blocking layer 4. Therefore, when the vertical MOSFET is operating, the JFET portion 3 and the electric field blocking layer 4 function as saturation current suppression layers. By exerting the saturation current suppression effect, a structure that achieves low on-resistance and maintains low saturation current can be obtained. Specifically, since a structure is formed by alternately and repeatedly forming the strip-shaped portion of the JFET portion 3 and the electric field blocking layer 4, the operation as shown below is performed.

[0084] First, when the drain voltage Vd is, for example, 1 to 1.5 V, which is the voltage applied during normal operation, the depletion layer extending from the electric field barrier layer 4 towards the JFET section 3 extends only a width smaller than the width of the strip-shaped portion in the JFET section 3. Therefore, even if the depletion layer extends into the JFET section 3, a current path is ensured. Furthermore, since the n-type impurity concentration in the JFET section 3 is higher than that in the n-type... － The high layer 2 allows for the formation of a current path with low resistance, thus enabling low on-resistance.

[0085] Furthermore, if the drain voltage Vd becomes higher than the normal operating voltage due to a load short circuit, the depletion layer extending from the electric field barrier layer 4 towards the JFET section 3 extends further than the width of the strip-shaped portion in the JFET section 3. Moreover, the JFET section 3 is immediately clamped off before the n-type current dispersion layer 5. At this time, the relationship between the drain voltage Vd and the width of the depletion layer is determined based on the width of the strip-shaped portion in the JFET section 3 and the n-type impurity concentration. Therefore, the width of the strip-shaped portion and the n-type impurity concentration in the JFET section 3 are set such that the JFET section 3 is clamped off when the drain voltage Vd becomes slightly higher than the normal operating voltage. Thus, the JFET section 3 can be clamped off even at a lower drain voltage Vd. In this way, by ensuring that the JFET section 3 is clamped off immediately when the drain voltage Vd is higher than the normal operating voltage, a low saturation current can be maintained, thereby improving the withstand capability of the SiC semiconductor device based on load short circuits, etc.

[0086] In this way, the JFET section 3 and the electric field barrier layer 4 function as saturation current suppression layers, thereby achieving the effect of saturation current suppression, and thus further obtaining a SiC semiconductor device that can balance low on-resistance and low saturation current.

[0087] Furthermore, by including the electric field blocking layer 4 in a manner that sandwiches the JFET portion 3, a structure is formed in which the strip-shaped portion of the JFET portion 3 and the electric field blocking layer 4 are alternately and repeatedly formed. Therefore, even if the drain voltage Vd becomes a high voltage, extending from below to n － The extension of the depletion layer in layer 2 is also suppressed by the electric field blocking layer 4, preventing it from extending into the trench gate structure. Therefore, by exerting an electric field suppression effect that reduces the electric field acting on the gate insulating film 12, damage to the gate insulating film 12 can be suppressed, resulting in a device with high withstand voltage and high reliability. Furthermore, since the extension of the depletion layer into the trench gate structure can be prevented in this way, the n-type layer constituting part of the drift layer can be... － The high n-type impurity concentration in the type layer 2 and JFET section 3 enables the achievement of low on-resistance.

[0088] Thus, it is possible to obtain a SiC semiconductor device with a vertical MOSFET that has low on-resistance and high reliability.

[0089] Next, refer to Figures 7A to 7G The cross-sectional view shown illustrates the manufacturing method of a SiC semiconductor device having an n-channel inverted trench gate structure of the present embodiment, using a cross-sectional view of the manufacturing process.

[0090] [ Figure 7A The process shown]

[0091] First, n is prepared as a semiconductor substrate. + Substrate 1. Furthermore, through epitaxial growth using a CVD (chemical vapor deposition) apparatus (not shown), in n... + n-type substrate 1 is formed on the main surface of the substrate 1. － Type 2. At this point, it is also possible to use pre-set n... － Type 2 grows in n + The so-called epitaxial substrate on the main surface of substrate 1. Furthermore, in n － The JFET portion 3, made of SiC, is epitaxially grown on top of the model layer 2.

[0092] In addition, regarding epitaxial growth, it is carried out by introducing a gas such as nitrogen, which is an n-type dopant, in addition to silane or propane, which are the raw material gases for SiC.

[0093] [ Figure 7B The process shown]

[0094] After the mask 17 is placed on the surface of the JFET section 3, the mask 17 is patterned to open the planned formation area of ​​the electric field barrier layer 4. Next, the electric field barrier layer 4 is formed by ion implantation of p-type impurities. Then, the mask 17 is removed.

[0095] In addition, while the electric field barrier layer 4 is formed here by ion implantation, it can also be formed by methods other than ion implantation. For example, the JFET portion 3 can be selectively and anisotropically etched to form a recess at a position corresponding to the electric field barrier layer 4. After epitaxially growing a p-type impurity layer thereon, the p-type impurity layer can be planarized on the portion above the JFET portion 3 to form the electric field barrier layer 4. In this way, the electric field barrier layer 4 can also be formed by epitaxial growth. When epitaxially growing p-type SiC, a gas used as a p-type dopant, such as trimethylaluminum (hereinafter referred to as TMA), can be introduced in addition to the SiC feed gas.

[0096] [ Figure 7C The process shown]

[0097] Next, an n-type current dispersing layer 5 is formed by epitaxially growing n-type SiC on the JFET portion 3 and the electric field barrier layer 4. Furthermore, a mask (not shown) with an opening for the planned formation region of the p-type deep layer 9 is disposed on the n-type current dispersing layer 5. Then, the p-type deep layer 9 is formed by implanting p-type impurity ions from the mask. While an example of forming the p-type deep layer 9 by ion implantation is shown, it can also be formed by methods other than ion implantation. For example, similar to the electric field barrier layer 4, after forming a recess in the n-type current dispersing layer 5, a p-type impurity layer can be epitaxially grown, and then the p-type impurity layer can be planarized to form the p-type deep layer 9.

[0098] [ Figure 7D The process shown]

[0099] Using a CVD apparatus (not shown), a p-type substrate region 6 and a first source region 8a of an n-type source region 8 are epitaxially grown sequentially on an n-type current dispersion layer 5 and a p-type deep layer 9. For example, in the same CVD apparatus, after heating the growth furnace to a specified temperature through a heating process, a p-type substrate region 6 is first formed by epitaxial growth using a gas that serves as a p-type dopant, introduced along with carrier gas and SiC raw material gas. Next, the introduction of the p-type dopant is stopped, and an n-type dopant is introduced to form the first source region 8a. However, at this point, the first source region 8a is made to have a thickness equal to or greater than that of the second source region 8b. Without a cooling process, the temperature is maintained constant after the formation of the p-type substrate region 6, allowing the first source region 8a to grow epitaxially, thereby shortening the process time.

[0100] Furthermore, using an ion implantation device, n-type impurity ions are implanted into the surface portion of the n-type source region 8. This forms a second source region 8b with increased n-type impurity concentration, and the portion of the n-type source region 8 located below the second source region 8b constitutes the first source region 8a. Thus, the first source region 8a can be formed by an epitaxial growth layer, and the second source region 8b can be formed by an ion implantation layer.

[0101] In this way, the p-type substrate region 6 and the n-type source region 8 can be formed with the aforementioned impurity concentration and film thickness. Here, the film thickness and impurity concentration of each part are determined as follows.

[0102] First, regarding the p-type substrate region 6, since it constitutes part of the channel region, the impurity concentration is set to form an inversion channel when the gate voltage Vg is applied, and the film thickness is set to a value that defines the channel length. Therefore, for the p-type substrate region 6, for example, the p-type impurity concentration is set to 3 × 10⁻⁶. 17 / cm 3 Set the thickness to 0.4–0.6 μm.

[0103] Regarding the first source region 8a in the n-type source region 8, the film thickness and n-type impurity concentration are set to minimize the saturation current and suppress the increase in on-resistance Ron even when a high drain voltage Vd is applied during a load short circuit. Therefore, for example, the n-type impurity concentration in the first source region 8a is set to 2.0 × 10⁻⁶. 16 ~1.0×10 17 / cm 3 Set the thickness to 0.2μm or more.

[0104] Regarding the second source region 8b, the impurity concentration is set to a level that allows for ohmic contact with the source electrode 15, and the film thickness is set to a level that prevents the entire region from disappearing due to chemical reaction with the source electrode 15. A higher n-type impurity concentration in the second source region 8b facilitates ohmic contact. However, there are also cases, as in this embodiment, where p-type impurity ions are implanted after epitaxial growth of the n-type source region 8 to form the p-type interconnect layer 10. In such cases, if the n-type impurity concentration in the n-type source region 8 is too high, the p-type interconnect layer 10 cannot achieve the desired concentration. Therefore, in this embodiment, the n-type impurity concentration in the second source region 8b is set, for example, to 1.0 × 10⁻⁶. 18 ~5.0×10 19 / cm 3 .

[0105] Furthermore, as described above, the source electrode 15 is made of various metals, and the portion in ohmic contact with the second source region 8b is, for example, made of Ni. In this case, the portion of the second source region 8b in contact with Ni becomes Ni silicide, thus forming an ohmic contact, but corresponding to the silicide formation, the second source region 8b disappears. Moreover, since the Ni silicide formed through the silicide formation reaction has a thickness of approximately 0.1 μm, the thickness of the second source region 8b is set to 0.1 μm or more so that the second source region 8b does not completely disappear due to the silicide formation reaction.

[0106] Furthermore, if the first source region 8a and the second source region 8b constituting the n-type source region 8 are made thicker, it is permissible to allow for uneven etching during the etching process when the gate electrode 13 is formed by etching back after filling the gate trench 11 with polysilicon. Therefore, it is preferable to set the combined thickness of the first source region 8a and the second source region 8b to a large value, and thus the film thickness of the first source region 8a and the film thickness of the second source region 8b are set within the range described above.

[0107] Furthermore, when the p-type substrate region 6 and the first source region 8a are formed by epitaxial growth, the film thickness non-uniformity of each part can be reduced. Moreover, regarding the p-type substrate region 6 used in the formation of the channel region, by reducing film thickness non-uniformity, the channel length can be obtained with good precision. Therefore, the threshold voltage Vth non-uniformity of the vertical MOSFET can be reduced.

[0108] For example, after epitaxially growing the p-type substrate region 6, it is also possible to incorporate n-type impurities into the p-type substrate region 6 to form both the first source region 8a and the second source region 8b together. However, in this case, the film thickness of the p-type substrate region 6 during epitaxial growth needs to be estimated based on the thickness of the first source region 8a and the second source region 8b formed by ion implantation. The film thickness non-uniformity during epitaxial growth increases as the film thickness increases, but the non-uniformity of the ion implantation range is not very large. Therefore, the film thickness non-uniformity of the p-type substrate region 6 after ion implantation becomes non-uniformity corresponding to the film thickness during epitaxial growth. Thus, for example, if the film thickness non-uniformity is ±0.21 μm when the p-type substrate region 6 has a thickness of 1.4 μm, then after forming the first source region 8a and the second source region 8b by ion implantation, the film thickness non-uniformity of the p-type substrate region 6 is also ±0.21 μm.

[0109] In contrast, as in this embodiment, when each part is formed by epitaxial growth, the thickness non-uniformity of the p-type substrate region 6 is not a non-uniformity including the thicknesses of the first source region 8a and the second source region 8b, but rather a non-uniformity corresponding only to the thickness of the p-type substrate region 6. For example, when the thickness of the p-type substrate region 6 is set to 0.4 to 0.6 μm, the thickness non-uniformity is ±0.06 to 0.09 μm. Therefore, by forming each part by epitaxial growth, the thickness non-uniformity of the p-type substrate region 6 can be suppressed, and the channel length can be obtained with good accuracy.

[0110] Furthermore, when each part is formed continuously by epitaxial growth, since the lattice constant is dependent on the impurity concentration, it is preferable that the impurity concentration does not change drastically. In contrast, when an n-type source region 8 is formed on a p-type substrate region 6 as in this embodiment, the presence of a first source region 8a allows for a less drastic change in impurity concentration.

[0111] Therefore, it is possible to suppress crystal defects that occur when the impurity concentration changes drastically.

[0112] Furthermore, the high-concentration second source region 8b is formed by ion implantation rather than epitaxial growth. Therefore, it is possible to suppress the situation where, as in the case of epitaxial growth of a high-concentration second source region 8b, residual n-type dopant remains in the epitaxial growth apparatus, contaminating the growth furnace and causing dopant contamination during subsequent formation of p-type or n-type layers. Thus, it is possible to stably manage the impurity concentration of the p-type substrate region 6 and the first source region 8a formed by the epitaxial growth apparatus.

[0113] [ Figure 7E The process shown]

[0114] A mask (not shown) is disposed on the n-type source region 8, opening the planned formation location of the p-type interconnect layer 10. After implanting p-type impurity ions onto the mask, a heat treatment at 1500°C or higher is performed for activation. One or both of boron (B) and aluminum (Al) are used as the ion implantation element. Thus, the n-type source region 8 can be inverted by ion implantation of p-type impurities to form the p-type interconnect layer 10.

[0115] At this point, the second region 10b in the p-type interconnect layer 10 needs to be in 5-ohm contact with the source electrode 15. Therefore, ion implantation is performed at a dose of 2 to 10 times the n-type impurity concentration of the second source region 8b. Regarding the dose, it can be considered that if the n-type impurity concentration of the second source region 8b is twice that of the source electrode 15, it would be sufficient to achieve a carrier concentration sufficient for 5-ohm contact with the source electrode 15, but considering the activation rate, it is preferable to set it to 2 to 10 times.

[0116] Therefore, the carrier concentration in the second region 10b, that is, the p-type impurity concentration that allows the carriers to function after removing the amount eliminated between the second source region 8b and the amount that is not activated, can be, for example, 2.0 × 10⁻⁶. 18 ~1.0×10 20 / cm 3 A higher impurity concentration in the second region 10b facilitates ohmic contact with the source electrode 15. However, the second source region 8b, formed before the formation of the second region 10b, must also achieve ohmic contact with the source electrode 15. Furthermore, excessive impurity concentrations can lead to crystal defects caused by ion implantation, so they must be suppressed to a certain level. These factors need to be considered when setting the n-type impurity concentration in the second source region 8b and the p-type impurity concentration in the second region 10b. Therefore, the n-type impurity concentration in the second source region 8b and the p-type impurity concentration in the second region 10b are set, for example, to 1.0 × 10⁻⁶. 18 ~5.0×10 19 / cm 3 .

[0117] On the other hand, regarding the first region 10a, since it is not in contact with the source electrode 15 ohms, the concentration of p-type impurities can be lower than that of the second region 10b. However, here, considering the activation rate, ion implantation of p-type impurities at a dose 2 to 10 times that of the first source region 8a is performed.

[0118] Furthermore, when the p-type interconnect layer 10 is formed by ion implantation, from the viewpoint of the output of the ion implantation apparatus, it is preferable that the total film thickness of the n-type source region 8 to which the p-type impurities are implanted is 0.8 μm or less. In this way, the p-type interconnect layer 10 can be formed to reach the p-type substrate region 6 even under the output of a general ion implantation apparatus, ensuring mass production capability.

[0119] [ Figure 7F The process shown]

[0120] After forming a mask (not shown) on the n-type source region 8, the gate trench 11 in the mask is made to form a planned forming region opening. Then, the gate trench 11 is formed by performing anisotropic etching such as RIE (Reactive Ion Etching) using the mask.

[0121] [ Figure 7G The process shown]

[0122] Then, after removing the mask, a gate insulating film 12 is formed by, for example, thermal oxidation, covering the inner wall surface of the gate trench 11 and the surface of the n-type source region 8. Furthermore, after depositing polysilicon doped with p-type or n-type impurities, it is etched back, forming the gate electrode 13 by leaving polysilicon at least within the gate trench 11. Thus, the trench gate structure is completed.

[0123] When forming such a trench gate structure, if the entire n-type source region 8 is formed by ion implantation, the side of the gate trench 11 becomes tilted due to the damage caused during ion implantation. Therefore, the channel mobility decreases, and the gate trench 11 becomes wider at the entrance side, making device miniaturization difficult.

[0124] However, in this embodiment, the first source region 8a is formed by epitaxial growth, while only the second source region 8b is formed by ion implantation. Therefore, the tilting of the sidewalls of the gate trench 11 caused by ion implantation damage is suppressed, and it is tilted with a rounded shape only approximately at the portion adjacent to the second source region 8b. This suppresses the widening of the gate trench 11 at the entrance side and also promotes device miniaturization.

[0125] The subsequent processes are not shown, but are performed as follows: An interlayer insulating film 14, for example, composed of an oxide film, is formed to cover the surfaces of the gate electrode 13 and the gate insulating film 12. Furthermore, using a mask (not shown), contact holes are formed in the interlayer insulating film 14 to expose the n-type source region 8 and the p-type deep layer 9. After forming an electrode material, for example, a multi-metal laminate, on the surface of the interlayer insulating film 14, the source electrode 15 and the gate wiring layer are formed by patterning the electrode material. Furthermore, in the n... + A drain electrode 16 is formed on the back side of the substrate 1. Thus, the SiC semiconductor device of this embodiment is completed.

[0126] As explained above, in the SiC semiconductor device of this embodiment, the n-type source region 8 is constructed using a first source region 8a with a lower concentration and a second source region 8b with a higher concentration. Furthermore, the first source region 8a is formed by epitaxial growth, and the second source region 8b is formed by ion implantation. Therefore, a SiC semiconductor device with a structure that achieves improved short-circuit withstand capability, suppression of threshold Vt non-uniformity and trench gate sidewall tilt, and easy management of impurity concentration can be obtained.

[0127] (Second Implementation)

[0128] The second embodiment will be described. This embodiment has an undoped layer compared to the first embodiment, but is otherwise the same as the first embodiment, so only the parts that are different from the first embodiment will be described.

[0129] like Figure 8 As shown, in the SiC semiconductor device of this embodiment, an undoped layer 7 made of SiC is formed on a p-type substrate region 6, and an n-type source region 8 is formed thereon.

[0130] The undoped layer 7 is either a layer without any impurities or a layer in which the carrier concentration is reduced by adding both n-type and p-type impurities. The thickness of the undoped layer 7 is 0.05–0.2 μm. Preferably, neither n-type nor p-type impurities are added to the undoped layer 7, but even if they are added, the carrier concentration only needs to be 1.0 × 10⁻⁶. 16 / cm 3 The following, preferably 1.0×10 15 / cm 3 The following is acceptable. For example, the n-type impurities such as nitrogen (N) in the undoped layer 7 are set to 1.0 × 10⁻⁶. 16 / cm 3 Hereinafter, it is preferred to set it to 1.0×10 15 / cm 3 Below. Furthermore, the p-type impurities such as aluminum in the undoped layer 7 are set to 1.0 × 10⁻⁶. 16 / cm 3 Hereinafter, it is preferred to set it to 1.0×10 15 / cm 3 The following applies. Furthermore, in the case where only one of the p-type and n-type impurities is added, the impurity concentration is set to 1.0 × 10⁻⁶. 16 / cm 3 In the case of doping with both, the carrier concentration becomes 1.0 × 10⁻⁶ due to mutual cancellation. 16 / cm 3 the following.

[0131] Thus, in the SiC semiconductor device of this embodiment, an undoped layer 7 is provided between the p-type substrate region 6 and the first source region 8a. Therefore, it is possible to suppress damage to the gate insulating film 12. For this effect, refer to... Figures 9-11 Please provide an explanation. Additionally... Figures 9-11 The results of investigating the voltage distribution during reverse conduction are presented for the following scenarios: setting the entire n-type source region 8 to a high impurity concentration; forming the first source region 8a in connection with the p-type substrate region 6; and having the structure of this embodiment with an undoped layer 7. As conditions for reverse conduction, the gate voltage Vg is set to 20V and the drain-source voltage Vds is set to -5V.

[0132] In reverse conduction, the parasitic diode formed in the vertical MOSFET essentially functions as a freewheeling diode, through which freewheeling current flows. Furthermore, holes diffuse from the p-type layer side of the PN junction constituting the parasitic diode to the n-type layer side recombine with electrons in the n-type layer. At this time, due to the large recombination energy, the basal plane dislocation (BPD) in the n-type layer formed by the epitaxial film expands into a stacking defect such as a Single Shockley Stacking Fault (SSSF). Since BPDs are linear defects, their area occupied within the cell region of the SiC semiconductor device is small, having almost no impact on device operation. However, if it becomes an SSSF, it becomes a stacking defect, thus increasing the area occupied within the cell region and significantly increasing its impact on device operation. Therefore, if a gate voltage Vg is actively applied during reverse conduction to form a channel region, allowing freewheeling current to flow through the channel region, the freewheeling current can be dispersed, reducing recombination energy and suppressing the occurrence of SSSF. However, due to the flow of freewheeling current through the channel region, a high electric field is generated between the p-type substrate region 6 and the n-type source region 8, resulting in the generation of hot electrons and causing damage to the gate insulating film 12.

[0133] Specifically, such as Figure 9 As shown, when an n-type source region 8 with a high overall concentration is formed by grounding the p-type substrate region 6, a potential distribution is generated at the PN junction during reverse conduction, resulting in a high electric field exerted on the n-type source region 8. When the n-type source region 8 is formed by grounding the p-type substrate region 6, the charge carriers in the portion of the n-type source region 8 connected to the p-type substrate region 6 are accelerated by the electric field and become hot electrons. These hot electrons collide with the gate insulating film 12, causing damage to the gate insulating film 12. In particular, this problem becomes significant if the overall n-type impurity concentration of the n-type source region 8 is increased.

[0134] On the other hand, even without the undoped layer 7, when the n-type source region 8 has a first source region 8a, the PN junction is formed by the p-type substrate region 6 and the first source region 8a. Thus, even without the undoped layer 7, when the first source region 8a is present, the electric field acting on the PN junction can be suppressed to some extent due to the lower n-type impurity concentration in the first source region 8a. That is, as... Figure 10 As shown, with Figure 9 Compared to the previous case, the spacing of the equipotential lines in the PN junction is wider, and the structure with the first source region 8a can suppress the electric field to some extent.

[0135] However, without forming the undoped layer 7, since a PN junction is formed by the p-type substrate region 6 and the first source region 8a, although it is more efficient than... Figure 9 The situation can be alleviated, but the aforementioned problems may arise by generating hot electrons.

[0136] In contrast, when an undoped layer 7 is provided between the p-type substrate region 6 and the first source region 8a, as in this embodiment, such as Figure 11 As shown, the equipotential lines can be supported by the undoped layer 7, which can reduce the electric field in the n-type source region 8. Furthermore, although an electric field is generated in the undoped layer 7, there are almost no charge carriers in the undoped layer 7. Therefore, by having the undoped layer 7, damage to the gate insulating film 12 caused by hot electrons during reverse conduction can be suppressed.

[0137] Therefore, during reverse conduction, by actively allowing freewheeling current to flow not only through the parasitic diode but also through the channel region, the occurrence of SSSF and the generation of hot electrons can be suppressed, thereby suppressing damage to the gate insulating film 12.

[0138] Next, the manufacturing method of the SiC semiconductor device of this embodiment will be described. In addition to the manufacturing method described in the first embodiment, the SiC semiconductor device of this embodiment is manufactured by performing an undoped layer 7 formation process after the formation of the p-type substrate region 6 and before the formation of the n-type source region 8.

[0139] Regarding the undoped layer 7, it is formed using the epitaxial growth apparatus used in the formation of the p-type substrate region 6 and the first source region 8a. Specifically, after the formation of the p-type substrate region 6, epitaxial growth is performed continuously with the dopant gas (both p-type and n-type dopant) being stopped from being introduced into the epitaxial growth apparatus, thereby forming the undoped layer 7. If the formation of the undoped layer 7 is performed at a constant temperature after the formation of the p-type substrate region 6 without a cooling process, the process time can be shortened. Furthermore, regarding the subsequent epitaxial growth of the first source region 8a, if the temperature is kept constant after the formation of the undoped layer 7 without a cooling process, the process time can be further shortened.

[0140] Regarding the undoped layer 7, the film thickness can be arbitrarily set, but if it is too thick, the on-resistance Ron will increase. Therefore, a thickness of 0.05 to 0.2 μm is set. Furthermore, regarding the undoped layer 7, it is preferable that it is essentially free of impurities, but only if the carrier concentration is low. In particular, if the undoped layer 7 is to be formed continuously after the formation of the p-type substrate region 6, it is possible that p-type impurities remaining in the gaseous environment may be introduced, or nitrogen present in the atmosphere may be introduced as an n-type impurity. In such cases, only a low impurity concentration is acceptable. Furthermore, if it is conceivable that one type of conductivity impurity might be introduced, only the other type of conductivity impurity may be intentionally introduced, so that the two are doped and cancel each other out, thereby lowering the carrier concentration. For example, in the case where only one of the p-type and n-type impurities is doped, the impurity concentration is set to 1.0 × 10⁻⁶. 16 / cm 3 The following describes how, with both dopants added, the carrier concentration becomes 1.0 × 10⁻⁶ through mutual cancellation. 16 / cm 3 the following.

[0141] In addition, when forming the undoped layer 7, when forming the p-type interconnect layer 10, since it is necessary to connect the p-type interconnect layer 10 with the p-type substrate region 6, p-type impurities are also added to the undoped layer 7, so that this part also becomes the p-type interconnect layer 10.

[0142] As explained above, in the SiC semiconductor device of this embodiment, an undoped layer 7 is provided between the p-type substrate region 6 and the first source region 8a. Therefore, it is possible to suppress the generation of hot electrons and suppress damage to the gate insulating film 12.

[0143] (Third Implementation)

[0144] The third embodiment will be described. In this embodiment, the method for measuring the film state of the n-type layer in the first and second embodiments will be described.

[0145] In the SiC semiconductor devices of the first and second embodiments described above, an n-type current dispersing layer 5 and a first source region 8a are epitaxially grown as n-type layers. After the formation of these n-type layers, the concentration of n-type impurities is measured as the film state of the n-type layers.

[0146] However, the surface electronic state of the n-type layer does not stabilize immediately after epitaxial growth, but rather after a certain period of time. Therefore, to ensure good accuracy in determining the concentration of n-type impurities, it is necessary to wait for a specified time after epitaxial growth. Specifically, it is possible to base... Figure 12 The procedure shown is for determining the concentration of n-type impurities.

[0147] First, such as Figure 12 As shown in step S100, the MOSFET fabrication process is performed. The MOSFET fabrication process described here refers to the process up to the formation of the n-type layer (hereinafter referred to as the measurement target layer), which is the object of measurement for n-type impurity concentration, in the manufacturing process of the vertical MOSFET in the SiC semiconductor device described in the first and second embodiments. Taking the first embodiment as an example, if the measurement target layer is the n-type current dispersing layer 5, then the process continues until the formation of the n-type impurity concentration measurement target layer. Figure 7B The process shown is up to the formation of the electric field blocking layer 4. Furthermore, if the target layer for measurement is the first source region 8a, the process continues until... Figure 7D The process up to the formation of the p-type matrix region 6.

[0148] Then, as shown in step S110, an epitaxial growth process for the target layer is performed. Here, for example, the n-type current dispersion layer 5 or the first source region 8a, which is the target of measurement, is epitaxially grown. Furthermore, after epitaxial growth, as shown in step S120, a holding process is performed in an atmospheric environment for at least 10 hours as an electron stabilization process. Then, the process proceeds to step S130, where the n-type impurity concentration of the target layer is measured.

[0149] The concentration of n-type impurities in the n-type layer can be determined using a non-contact CV concentration evaluation method. This is as follows: Figure 13The method is as follows: After continuously applying charge to the surface of the n-type layer formed on the wafer 20 through corona discharge, the surface potential is repeatedly measured using a potential detector 21 disposed on the wafer 20, and the n-type impurity concentration is determined based on the QV curve. Using this method, the n-type impurity concentration of the target layer after epitaxial growth can be determined.

[0150] However, immediately following epitaxial growth, the surface electronic state of the n-type layer, the target layer for measurement, is unstable, making it impossible to accurately measure the n-type impurity concentration. Specifically, a non-contact CV concentration evaluation method was used to investigate the relationship between the elapsed time after the epitaxial growth of the n-type layer and the n-type impurity concentration. Figure 14 This indicates the result.

[0151] like Figure 14 As shown, after the epitaxial growth of the n-type layer, under conditions of exposure only to the atmosphere, the concentration of n-type impurities gradually decreases over time. Furthermore, if the elapsed time reaches 10 hours or more, preferably 18 hours or more, for example, around 24 hours, the concentration of n-type impurities stabilizes at a relatively constant value. Additionally, the changes in n-type impurity concentration corresponding to the passage of time were investigated multiple times, but concerns were raised regarding the influence of non-contact CV concentration evaluation performed each time. Therefore, it was confirmed that the n-type impurity concentration measured based on non-contact CV concentration evaluation in the first instance after 24 hours of n-type layer formation and the second instance after 30 hours were values ​​consistent with those obtained in multiple instances. Therefore, the manner of change in n-type impurity concentration can be said to be unaffected by the implementation of non-contact CV concentration evaluation.

[0152] Thus, immediately following epitaxial growth, the surface electronic state of the n-type layer, the target layer for measurement, is unstable, resulting in a high concentration of n-type impurities, making it impossible to accurately measure the n-type impurity concentration. In contrast, if maintained in an atmospheric environment for more than 10 hours, the surface electronic state of the n-type layer, the target layer for measurement, becomes stable, allowing for accurate measurement of the n-type impurity concentration.

[0153] As described above, the concentration of n-type impurities in the target layer is measured using non-contact CV concentration evaluation. Furthermore, the measurement is not performed immediately after epitaxial growth, but rather after a holding process in an atmospheric environment for more than 10 hours as part of the electron stabilization step. This allows for the accurate measurement of the n-type impurity concentration.

[0154] However, measuring the concentration of n-type impurities in the target layer after the holding process leads to a longer manufacturing time, which in turn increases manufacturing costs.

[0155] Therefore, the inventors of this invention specifically studied how to shorten the time required for measuring the film state of the n-type layer. The results showed that by acid washing the surface after epitaxial growth of the n-type layer, the concentration of n-type impurities stabilized in the same way as when exposed to the atmosphere for more than 10 hours after epitaxial growth. Figure 14 The results also show the results of acid washing and non-contact CV concentration evaluation without holding the epitaxial growth process.

[0156] By confirming the concentration of n-type impurities when acid washing occurs immediately after epitaxial growth of the n-type layer, it can be seen that, for example... Figure 13 As shown in the hollow quadrilateral, the value becomes equivalent to that of exposure to the atmosphere for more than 24 hours. For pickling, SC-2 (hydrogen peroxide hydrochloric acid aqueous solution), SPM (hydrogen peroxide sulfuric acid aqueous solution), ozone cleaning, etc., can be applied. In the case of pickling, an oxide film may form on the SiC surface, but the presence or absence of the oxide film is arbitrary. Specifically, to investigate the effect of the presence or absence of the oxide film, the n-type impurity concentration was investigated after pickling following the epitaxial growth of the n-type layer, and again after further HF treatment. The changes in the n-type impurity concentration were investigated. The results are as follows: Figure 15 As shown, there was no change in the n-type impurity concentration between the first and second investigations. This indicates that the presence or absence of an oxide film is arbitrary in the non-contact CV concentration evaluation of SiC, and the n-type impurity concentration can be measured regardless of its presence or absence. Furthermore, regarding HF treatment, it was implemented in a manner that allows for removal even if an oxide film is assumed to have formed; however, even if no oxide film was initially formed, the n-type impurity concentration can still be measured based on the non-contact CV concentration evaluation.

[0157] Thus, by performing acid washing after the epitaxial growth of the n-type layer, even after a short period of time, the stabilized value of the n-type impurity concentration can be measured. Therefore, even if the n-type current dispersion layer 5 or the first source region 8a is measured immediately after epitaxial growth, a relatively accurate measurement can be performed by measuring the n-type impurity concentration after acid washing. Furthermore, in the case of such acid washing, instead of the above-described... Figure 12 ,based on Figure 16 The measurement procedure shown is used to determine the concentration of n-type impurities. Specifically, in steps S200 and S210, the concentration of n-type impurities is determined... Figure 12 After the same steps as S100 and S110, in step S220, an acid pickling process is performed as an electronic stabilization process. Then, in step S230, through the same process as... Figure 12Step S130 uses the same method to measure the concentration of n-type impurities in the target layer. The time at which the measurement of the n-type impurity concentration begins, i.e., the elapsed time after the pickling process is completed, is arbitrary; a shorter elapsed time is also acceptable.

[0158] (Fourth implementation)

[0159] The fourth embodiment will be described. In the third embodiment described above, an n-type current dispersion layer 5 and a first source region 8a were used as examples of n-type layers, but the method can be applied to any n-type layer when measuring the n-type impurity concentration after epitaxial growth. Here, for n-type impurity concentration... + n is made on the main surface of the substrate 1 － n was measured after epitaxial growth of type 2 layer. － The concentration of n-type impurities in layer 2 will be explained.

[0160] In determining n － Given the n-type impurity concentration in layer 2, it is possible to base on Figure 17 The procedure shown is for determining the concentration of n-type impurities.

[0161] First, such as Figure 17 As shown in step S300, a SiC bulk substrate is prepared, i.e., n + Type substrate 1. Next, as shown in step S310, on n + n is made on the main surface of the substrate 1 － Layer 2 is epitaxially grown. Furthermore, in steps S320 and S330, with... Figure 16 Steps S220 and S230 are the same, and the concentration of n-type impurities is determined after the pickling process.

[0162] Thus, in n + n is made on the main surface of the substrate 1 － After epitaxial growth of layer 2, it is desired to determine n. － Even with the n-type impurity concentration in layer 2, the n-type impurity concentration can be accurately measured with good precision by acid washing without incurring time after epitaxial growth.

[0163] (Other implementation methods)

[0164] The present invention has been described according to the above embodiments, but is not limited to these embodiments, and includes various modifications or modifications within the equivalent range. In addition, various combinations and forms, and further, other combinations and forms that include only one element or more or less, also fall within the scope and spirit of the present invention.

[0165] (1) For example, in the above embodiment, the JFET portion 3 and the electric field blocking layer 4 are provided, and the n-type current dispersing layer 5 is provided. The JFET portion 3 and the n-type current dispersing layer 5 constitute part of the drift layer. However, this is only one example of the structure of the vertical MOSFET. It is also possible to have a structure without the JFET portion 3 and the electric field blocking layer 4, a structure without the n-type current dispersing layer 5, or a structure without both of these.

[0166] (2) Furthermore, the various dimensions such as impurity concentration, thickness, and width of each part constituting the SiC semiconductor device shown in the above embodiment are only one example. For example, the first region 10a may be formed to a depth deeper than the first source region 8a, or the second region 10b may be formed to a depth deeper than the second source region 8b.

[0167] (3) Furthermore, in the above embodiment, the p-type deep layer 9 and the p-type interconnect layer 10 are constructed separately, but they can also be constructed using the same p-type layer. For example, a deep trench is formed that extends from the surface of the n-type source region 8 through the undoped layer 7, the p-type substrate region 6, and the n-type current dispersion layer 5 to the electric field blocking layer 4, and the p-type layer is formed by filling the deep trench. Alternatively, p-type impurity ions are implanted from the surface of the n-type source region 8 to form a p-type layer that extends from the undoped layer 7, the p-type substrate region 6, and the n-type current dispersion layer 5 to the electric field blocking layer 4. In this way, the p-type deep layer 9 and the p-type interconnect layer 10 can be constructed from p-type layers.

[0168] (4) Furthermore, in the above embodiment, a structure was described in which the n-type source region 8 is divided into two regions with different impurity concentrations, namely the first source region 8a and the second source region 8b. However, it is also possible to divide them into two regions without explicit definition. That is, as long as the impurity concentration on the p-type substrate region 6 side of the n-type source region 8 is lower than that on the surface side in contact with the source electrode 15, and the surface side is set to have a high impurity concentration that allows for ohmic contact with the source electrode 15. In other words, the first source region 8a and the second source region 8b may have a concentration gradient in such a way that the impurity concentration gradually increases toward the source electrode 15 side.

[0169] (5) Furthermore, in the above-described third and fourth embodiments, as the layer for measuring the n-type impurity concentration after epitaxial growth, the n-type current dispersion layer 5 and the first source region 8a, as well as the n-type current dispersion layer 5 and the first source region 8a, are used as the layers. － The following explanation is based on layer 2.

[0170] Specifically, in the third embodiment, the following situation is described: after forming an epitaxial growth layer on a SiC bulk substrate, an ion implantation process is performed, followed by the formation of an n-type current dispersion layer 5 and an n-type layer such as the first source region 8a, which are the target layers for measurement. In this way, when the epitaxial growth of the SiC layer, which is the target layer for measurement, is performed after ion implantation of the epitaxial growth layer formed on the lower layer, the above-mentioned measurement of the n-type impurity concentration based on non-contact CV concentration evaluation can be performed.

[0171] Furthermore, in the fourth embodiment, it is shown that an n-layer of SiC, which serves as the measurement target layer, is formed on a SiC bulk substrate. － In the case where layer 2 is used as the epitaxial growth layer, the above-mentioned measurement of n-type impurity concentration based on non-contact CV concentration evaluation can also be performed when the epitaxial growth of the target layer is performed directly on a SiC bulk substrate.

[0172] (6) Furthermore, in the above embodiment, an n-channel vertical MOSFET with the first conductivity type set to n-type and the second conductivity type set to p-type was described as an example. However, it can also be a p-channel vertical MOSFET with the conductivity types of each component inverted. Furthermore, in the above description, a vertical MOSFET was used as an example of a semiconductor element, but the present invention can also be applied to IGBTs with the same structure. In the case of an n-channel IGBT, compared to the above embodiments, only the n-channel type is changed... + The conductivity type of substrate 1 is changed from n-type to p-type, but the other structures and manufacturing methods are the same as those in the above embodiments.

Claims

1. A method for manufacturing a silicon carbide semiconductor device, characterized in that, The process includes the following steps: An n-type silicon carbide layer, which is the target layer for measurement, is epitaxially grown. After the silicon carbide layer is epitaxially grown, the surface electrons of the silicon carbide layer are stabilized; and After stabilizing the surface electrons, the surface of the silicon carbide layer is charged by applying a charge, and the n-type impurity concentration of the silicon carbide layer is measured by measuring the surface potential of the silicon carbide layer.

2. The method for manufacturing a silicon carbide semiconductor device as described in claim 1, characterized in that, Stabilizing the surface electrons of the silicon carbide layer means maintaining it in an atmospheric environment for more than 10 hours after its formation.

3. The method for manufacturing a silicon carbide semiconductor device as described in claim 1, characterized in that, Stabilizing the surface electrons of the silicon carbide layer means that, after the silicon carbide layer is formed, the surface of the silicon carbide layer is acid-washed.

4. The method for manufacturing a silicon carbide semiconductor device as described in claim 3, characterized in that, The above-mentioned pickling is a cleaning process using one of the following: hydrochloric acid-hydrogen peroxide aqueous solution, sulfuric acid-hydrogen peroxide aqueous solution, or ozone cleaning.

5. The method for manufacturing a silicon carbide semiconductor device according to any one of claims 1 to 4, characterized in that, This includes the process of epitaxially growing an n-type layer on a silicon carbide bulk substrate; Stabilizing the surface electrons of the silicon carbide layer means stabilizing the surface electrons of the n-type layer by using the n-type layer as the silicon carbide layer. The determination of the above-mentioned n-type impurity concentration refers to the determination of the n-type impurity concentration of the above-mentioned n-type layer.

6. The method for manufacturing a silicon carbide semiconductor device according to any one of claims 1 to 4, characterized in that, The process includes the following steps: An epitaxial growth layer is formed on a silicon carbide bulk substrate; An impurity layer is formed by ion implantation of impurities into the aforementioned epitaxial growth layer; and An n-type layer is epitaxially grown on the above-mentioned epitaxial growth layer and the above-mentioned impurity layer; Stabilizing the surface electrons of the silicon carbide layer means using the n-type layer as the silicon carbide layer and stabilizing the surface electrons of the n-type layer. The determination of the above-mentioned n-type impurity concentration refers to the determination of the n-type impurity concentration of the above-mentioned n-type layer.

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