An annealing method for increasing the phosphorus content of the backside poly silicon layer of a TOPCon cell and a TOPCon cell

Abstract

The application belongs to the technical field of solar cells, and relates to an annealing method for increasing the phosphorus content of a polycrystalline silicon layer of a TOPCon cell and a TOPCon cell. The steps include: preparing a substrate, preparing a doped amorphous silicon layer containing phosphorus on the back surface of the substrate by a physical vapor deposition method; preparing an intrinsic amorphous silicon layer on the outer surface of the doped amorphous silicon layer by the physical vapor deposition method; rapidly heating to 800-900 DEG C in an atmosphere containing 5-30% oxygen by volume ratio, maintaining for 5-10 min, and cooling at a speed of 2-10 DEG C / min, so that the doped amorphous silicon layer is converted into a doped polycrystalline silicon layer, and the intrinsic amorphous silicon layer is converted into a silicon oxide layer. The doped polycrystalline silicon layer of the TOPCon cell is manufactured by the above annealing method. In the high-temperature annealing process, the existence of the oxide layer on the surface can block the escape of phosphorus in the amorphous silicon in the annealing process, ensure the doping concentration and passivation effect of the amorphous silicon, and improve the photoelectric conversion efficiency of the TOPCon cell.

Description

Technical Field

[0001] This invention relates to the field of solar cell manufacturing technology, and in particular to an annealing method for increasing the phosphorus content of the polycrystalline silicon layer on the back of a TOPCon cell and a method for improving the photoelectric conversion efficiency of a TOPCon cell. Background Technology

[0002] TOPCon (passivated contact) batteries, characterized by high efficiency, low degradation, and compatibility with existing production lines, have become the mainstream N-type battery technology. The doped amorphous silicon layer for the passivation contact on the back of TOPCon batteries is typically fabricated using three methods: LPCVD (low-pressure chemical vapor deposition), PECVD (plasma-enhanced chemical vapor deposition), and PVD (physical vapor deposition). PVD is gaining acceptance due to its fast deposition rate, good film uniformity, and the absence of gases like silanes. Currently, PVD typically involves introducing PH3 during the deposition process to create the doped amorphous silicon layer. PVD has a fast deposition rate and low temperature (200-300℃). During this process, PH3 only ionizes and does not form covalent bonds with the silicon crystal. Therefore, the doped P has poor activity. To activate the P, the doped amorphous silicon must undergo high-temperature annealing (typically >800℃) to form covalent bonds with the crystalline amorphous silicon. Crystallized amorphous silicon exhibits a polycrystalline state and is doped with phosphorus (P), resulting in a good passivation effect.

[0003] Existing technologies utilize natural cooling, which does not require a specific cooling rate. However, due to the porous nature of the amorphous silicon layer prepared by PVD, and the higher temperature required for the high-temperature annealing of PVD-prepared films, phosphorus and hydrogen from the doped amorphous silicon layer can easily escape during the high-temperature processing. Phosphorus escape reduces the phosphorus doping concentration in the amorphous silicon, affecting subsequent contact, while hydrogen escape leads to poor passivation and impacts battery efficiency.

[0004] Chinese patent CN114335236A discloses a passivated contact solar cell and its fabrication method. The method for fabricating the passivation structure of a solar cell includes preparing a doped amorphous silicon layer on a dielectric layer, followed by annealing to activate the doped amorphous silicon layer and form a polycrystalline silicon layer. The gas in the PVD process chamber here contains at least argon and / or helium. This gas atmosphere is intended to protect the doped amorphous silicon layer from oxidation, but it does not prevent the escape and loss of nitrogen and hydrogen.

[0005] Therefore, it is necessary to improve the surface treatment method of TOPCon batteries to solve the above problems. Summary of the Invention

[0006] The main objective of this invention is to provide an annealing method for increasing the phosphorus content of the polycrystalline silicon layer on the back of a TOPCon battery, which can prevent phosphorus and hydrogen in the doped amorphous silicon layer from escaping during high-temperature annealing and avoid phosphorus content loss.

[0007] This invention achieves the above objective through the following technical solution: an annealing method for increasing the phosphorus content of the polycrystalline silicon layer on the back of a TOPCon battery, comprising the following steps:

[0008] S1. Prepare a substrate. On the back surface of the substrate, a phosphorus-doped amorphous silicon layer is prepared by physical vapor deposition at a deposition temperature of 200-400℃.

[0009] S2. An intrinsic amorphous silicon layer is prepared on the outer surface of the doped amorphous silicon layer by physical vapor deposition. The thickness of the intrinsic amorphous silicon layer is 5-20 nm and the deposition temperature is 200-400 °C.

[0010] S3. In an atmosphere with an oxygen content of 5-30% by volume, the temperature is increased to 800-900℃ at a rate of 10-20℃ / min, maintained for 5-10min, and then cooled at a rate of 2-10℃ / min to convert the doped amorphous silicon layer into a doped polycrystalline silicon layer and the intrinsic amorphous silicon layer into a silicon oxide layer.

[0011] S4. Clean with hydrofluoric acid to remove the silicon oxide layer.

[0012] Specifically, the thickness of the doped amorphous silicon layer is 100-150 nm.

[0013] Specifically, the thickness of the silicon oxide layer is 10-40 nm.

[0014] Another major objective of this invention is to provide a TOPCon battery with higher photoelectric conversion efficiency.

[0015] A TOPCon battery, wherein the doped polycrystalline silicon layer is manufactured using the annealing method described above.

[0016] The beneficial effects of the technical solution of this invention are:

[0017] This process involves first preparing an intrinsic amorphous silicon layer outside a doped amorphous silicon layer, and then annealing it at high temperature in an oxygen-containing environment. This process transforms the doped amorphous silicon layer into a doped polycrystalline silicon layer and the intrinsic amorphous silicon layer into a silicon oxide layer. Because of the presence of the oxide layer on the surface, the escape of phosphorus from the amorphous silicon during the annealing process can be prevented, ensuring the doping concentration and passivation effect of the amorphous silicon and improving the photoelectric conversion efficiency. Attached Figure Description

[0018] Figure 1 This is a diagram showing the changes in the coating structure of the process of this invention.

[0019] The numbers in the image represent:

[0020] 1-Base;

[0021] 2'-Doped amorphous silicon layer, 2'-Doped polycrystalline silicon layer;

[0022] 3-Intrinsic amorphous silicon layer, 3'-Silicon oxide layer Detailed Implementation

[0023] The present invention will be further described in detail below with reference to specific embodiments.

[0024] Example:

[0025] like Figure 1 As shown, the annealing method of the present invention for increasing the phosphorus content of the polycrystalline silicon layer of TOPCon cells includes the following steps:

[0026] S1. Prepare substrate 1. Prepare a phosphorus-doped amorphous silicon layer 2 on the back surface of substrate 1 using physical vapor deposition at a deposition temperature of 200-400℃.

[0027] Physical vapor deposition (PVD) sputters silicon from a silicon target, depositing it as atoms or atomic clusters onto the surface of substrate 1. Because phosphine is present during the deposition process, phosphorus atoms remain dispersed within the silicon film after sputtering, but most have not yet formed Si-P bonds. Since this process does not require chemical changes, the required temperature is not very high, the deposition time is relatively short, and the deposition rate is fast.

[0028] Experience shows that a thickness of 100-150nm for the doped amorphous silicon layer 2 is necessary to provide sufficient passivation contact and ensure reliable battery performance.

[0029] S2. An intrinsic amorphous silicon layer 3 is prepared on the outer surface of the doped amorphous silicon layer using physical vapor deposition. The thickness of the intrinsic amorphous silicon layer 3 is 5-20 nm, and the deposition temperature is 200-300 °C.

[0030] Intrinsic amorphous silicon is pure amorphous silicon, meaning it contains almost no impurities. The intrinsic amorphous silicon layer 3 covers the surface of the doped amorphous silicon layer 2, thus isolating the doped amorphous silicon layer 2 from oxygen. During annealing, the intrinsic amorphous silicon layer is first oxidized to a silicon oxide layer. Silicon oxide has excellent density, preventing phosphorus and hydrogen from escaping during high-temperature annealing, thereby avoiding phosphorus and hydrogen loss.

[0031] S3. In an atmosphere with an oxygen content of 5-30% by volume, the temperature is increased to 800-900℃ at a rate of 10-20℃ / min and maintained for 5-10min. Then, the temperature is decreased at a rate of 2-10℃ / min to convert the doped amorphous silicon layer 2 into a doped polycrystalline silicon layer 2' and the intrinsic amorphous silicon layer 3 into a silicon oxide layer 3'.

[0032] During the heating stage of high-temperature annealing, crystallization occurs in both the doped amorphous silicon layer 2 and the intrinsic amorphous silicon layer 3. That is, the amorphous silicon film gradually transforms from an amorphous film to a polycrystalline film. In the doped amorphous silicon layer 2, P atoms will also substitute for Si atoms, thereby turning inactive P into active P.

[0033] During the high-temperature annealing stage, the outer intrinsic amorphous silicon layer comes into contact with oxygen, causing it to transform into silicon oxide. Because silicon oxide has a relatively small lattice gap, it forms a dense protective layer, preventing phosphorus and hydrogen from escaping. The intrinsic amorphous silicon layer 3 isolates the doped amorphous silicon layer 2 from oxygen, effectively annealing it in an oxygen-free environment. This process generates new Si-P and Si-H bonds, activating phosphorus and passivating hydrogen. Even if some phosphorus and hydrogen escape from the doped amorphous silicon layer 2, they cannot penetrate the protective film formed by the silicon-oxygen bonds, thus maintaining the overall phosphorus content. When the thickness of the intrinsic amorphous silicon layer 3 is 5-20 nm, the resulting silicon oxide layer 3' provides excellent isolation, preventing phosphorus escape from the amorphous silicon during annealing and ensuring the doping concentration and passivation effect of the amorphous silicon.

[0034] After the intrinsic amorphous silicon layer 3 is oxidized, the layer thickness will increase to a certain extent. Experience shows that the final thickness of the silicon oxide layer 3' is 10-40nm.

[0035] S4. Clean with hydrofluoric acid to remove the silicon oxide layer.

[0036] Because the silicon oxide layer 3' is non-conductive, and other structures need to be added to the surface of the polycrystalline silicon doped layer 2', the silicon oxide layer 3' needs to be removed after annealing. The reaction that occurs is as follows:

[0037] SiO2 + 4HF = SiF4↑ + 2H2O.

[0038] Because hydrofluoric acid does not react with Si-P bonds, it can ensure that the silicon oxide layer 3' is completely washed away without damaging the doped polycrystalline silicon layer 2'.

[0039] After high-temperature annealing, subsequent processes are performed to fabricate solar cells. A comparative experiment is then conducted between a TOPCon cell manufactured using this technology, containing a silicon oxide layer 3' as a barrier layer, and a TOPCon cell without a silicon oxide layer as a barrier layer. The experimental conditions are: total irradiance: 1000 W / m². 2 The tested battery temperature was 25.0℃, the spectral distribution was AM1.5G, and the sample area was 333.7 cm². 2 .

[0040] Table 1 shows the test data of the sample manufactured according to the present invention, and Table 2 shows the test data of the comparative sample.

[0041] Table 1:

[0042]

[0043] Table 2:

[0044]

[0045] As shown in the table above, the TOPCon cells manufactured using this process have better open-circuit voltage, fill factor, conversion efficiency, and maximum power than TOPCon cells without an oxide layer as a barrier layer. This is because the higher phosphorus content during manufacturing results in better contact performance and higher fill factor during subsequent metallization. The higher phosphorus content also leads to better passivation and a higher open-circuit voltage. Under the same illumination, this results in higher output power, thus improving the photoelectric conversion efficiency.

[0046] The above descriptions are merely some embodiments of the present invention. Those skilled in the art can make various modifications and improvements without departing from the inventive concept of the present invention, and these all fall within the scope of protection of the present invention.

Claims

1. An annealing method for increasing the phosphorus content of the polycrystalline silicon layer in a TOPCon solar cell, characterized in that... The steps include: S1. Prepare a substrate. On the back surface of the substrate, a phosphorus-doped amorphous silicon layer is prepared by physical vapor deposition at a deposition temperature of 200-400℃. S2. An intrinsic amorphous silicon layer is prepared on the outer surface of the doped amorphous silicon layer by physical vapor deposition. The thickness of the intrinsic amorphous silicon layer is 5-20 nm and the deposition temperature is 200-400 °C. S3. In an atmosphere with an oxygen content of 5-30% by volume, the temperature is increased to 800-900℃ at a rate of 10-20℃ / min, maintained for 5-10min, and then cooled at a rate of 2-10℃ / min to convert the doped amorphous silicon layer into a doped polycrystalline silicon layer and the intrinsic amorphous silicon layer into a silicon oxide layer. S4. Clean with hydrofluoric acid to remove the silicon oxide layer.

2. The annealing method for increasing the phosphorus content of the polycrystalline silicon layer in TOPCon cells according to claim 1, characterized in that: The thickness of the doped amorphous silicon layer is 100-150 nm.

3. The annealing method for increasing the phosphorus content of the polycrystalline silicon layer in TOPCon cells according to claim 1, characterized in that: The thickness of the silicon oxide layer is 10-40 nm.

4. A TOPCon battery, characterized in that: The doped polycrystalline silicon layer is manufactured using any one of the annealing methods described in claims 1-3.

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