Method and system for performing digital-to-analog conversion

Abstract

A method and system for performing digital-to-analog conversion. The method includes receiving an input digital word; encoding at least a portion of the input digital word using a randomizer encoder. The randomizer encoder includes a plurality of outputs coupled to a plurality of DAC cells, a state of each output being set by a corresponding entry of a control block. Encoding the at least a portion of the input digital word includes generating a grouping by setting at least some entries of the control block, wherein setting the at least some entries includes setting a width of the grouping based on a value represented by the at least a portion of the input digital word; and modifying the grouping based on a change in the value represented by the at least a portion of the input digital word, wherein modifying the grouping includes changing the width of the grouping in a first or second direction according to a random or pseudo-random number. The method further includes controlling the plurality of DAC cells based on the grouping for a first time interval, and controlling the plurality of DAC cells based on the modified grouping for a second time interval after the first time interval.

Description

[0001] Cross-referencing of related patent applications

[0002] This invention claims priority to U.S. Provisional Patent Application No. 63 / 353,936, filed June 21, 2022, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This invention relates to digital-to-analog conversion (DAC), and more specifically, to noise shaping in a DAC using a randomized encoder. Background Technology

[0004] A digital-to-analog converter (DAC) is an electronic circuit that converts digital data into analog signals. DACs are commonly used in audio and video applications, such as in music players to convert digital audio streams into analog audio signals, and in displays to convert digital video streams into analog video signals. Furthermore, DACs are widely used in modern communication systems. For example, ultra-high-speed converters are commonly used in optical fibers. Summary of the Invention

[0005] This invention provides a method and system for performing digital-to-analog conversion (DAC) to solve the static mismatch problem in DAC.

[0006] Some implementations relate to a method for performing digital-to-analog conversion (DAC), the method comprising: receiving an input digital word; encoding at least a portion of the input digital word using a randomized encoder, wherein the randomized encoder includes a plurality of outputs coupled to a plurality of DAC units, the state of each of the plurality of outputs being set by a corresponding entry of a control block. Encoding at least a portion of the input digital word includes: generating a group by setting at least some entries of the control block, wherein setting the at least some entries includes setting the width of the group based on a value represented by the at least a portion of the input digital word; and modifying the group based on changes in the value represented by the at least a portion of the input digital word, wherein modifying the group includes changing the width of the group in a first direction or a second direction according to a random number or a pseudo-random number. The method for performing DAC further includes controlling the plurality of DAC units based on the group at a first time interval, and controlling the plurality of DAC units based on the modified group at a second time interval after the first time interval.

[0007] Some implementations relate to a system for performing digital-to-analog conversion (DAC), the system including a plurality of DAC units and a randomized encoder. The randomized encoder includes a plurality of outputs coupled to the plurality of DAC units, the state of each of the plurality of outputs being set by a corresponding entry of a control block. The randomized encoder is configured to receive input digits and encode at least a portion of the input digits by: generating packets by setting at least some entries of the control block, wherein setting at least some entries includes setting the width of the packets based on values ​​represented by at least a portion of the input digits; and modifying the packets based on changes in the values ​​represented by at least a portion of the input digits, wherein modifying the packets includes changing the width of the packets in a first direction or a second direction according to a random number or pseudo-random number. The randomized encoder is also configured to control the plurality of DAC units based on the packets at a first time interval, and to control the plurality of DAC units based on the modified packets at a second time interval after the first time interval.

[0008] Some implementations relate to a method for performing digital-to-analog conversion (DAC), the method including receiving an input digit word and encoding at least a portion of the input digit word using a randomized encoder, wherein the randomized encoder includes a plurality of outputs coupled to a plurality of DAC units, the state of each of the plurality of outputs being set by a corresponding entry of a control block, and wherein encoding at least a portion of the input digit word includes: generating a group by setting at least some entries of the control block, wherein setting at least some entries includes setting the width of the group based on a value represented by the at least a portion of the input digit word; and modifying the group based on a change in the value represented by the at least a portion of the input digit word, wherein modifying the group includes swapping a first entry of the group with a second entry of the group. The method for performing DAC further includes controlling the plurality of DAC units based on the group at a first time interval, and controlling the plurality of DAC units based on the modified group at a second time interval after the first time interval.

[0009] This invention can compensate for the static mismatch of high-speed DACs, reduce the negative impact of switching timing offset and DC linearity error, and increase the overall dynamic range of the DAC.

[0010] The foregoing invention is provided by way of example and is not intended to be limiting. Attached Figure Description

[0011] The accompanying drawings are not intended to be drawn to scale. In the drawings, identical or nearly identical parts illustrated in different figures are represented by the same numbers. For clarity, not every part is labeled in every figure.

[0012] Figure 1 This is a block diagram illustrating some implementations of the techniques described herein for performing digital-to-analog conversion (including a randomized encoder).

[0013] Figure 2 These are additional detailed illustrations of some implementations of the technology described herein. Figure 1 A block diagram of the system's digital-to-analog converter (DAC).

[0014] Figure 3 These are examples of some implementations based on the technology described herein. Figure 1 A schematic diagram of the operation of a randomized encoder.

[0015] Figure 4A This is a graph illustrating the spectrum of the output of a DAC suffering from switching timing errors or DC linearity errors, according to some embodiments of the technology described herein.

[0016] Figure 4B This is a graph illustrating the spectrum of the output of a DAC suffering from switching timing errors or DC linearity errors according to some embodiments of the technology described herein, wherein a randomized encoder is used to encode the DAC. Detailed Implementation

[0017] I. Overview

[0018] This paper describes a technique for compensating for static mismatch (e.g., timing offsets in the switching of a high-speed digital-to-analog converter, DAC). Ideally, the current sources of a DAC are identical, resulting in a relatively flat noise spectrum in the frequency response. However, in the presence of mismatch, this response exhibits undesirable spurious content that can adversely affect the dynamic range of the DAC. Mismatch arises due to unavoidable variations in the manufacturing process and temperature gradients. This reduction in dynamic range is particularly problematic in high-speed DACs, for example, those configured to handle data rates in the gigabits per second (GSa / s) range, where dynamic range requirements are particularly stringent. The technique developed in this paper is configured to shift the spurious content caused by static errors to lower frequencies, i.e., away from the bandwidth of interest. Therefore, the bandwidth of interest is less affected by spurious content, and the overall dynamic range is increased.

[0019] The technique described in this article relates to randomizing thermometric encoders. In a current-steering DAC, the thermometric encoder is arranged such that its entries indicate which current sources will drive the current (and thus contribute to the analog output) and which current sources will not drive the current. However, it should be noted that the technique described in this article is not limited to current-steering DACs and can be applied to other types of DACs, such as voltage-mode DACs or charge-mode DACs. Therefore, not all thermometric encoders involve current sources. For illustrative purposes, the following example is described as providing a current steering mechanism.

[0020] The entries for the temperature encoder are set based on the input digital word. In some embodiments, one or more aspects of the temperature encoder are randomized. To this end, the inventors have recognized and understood that the negative impacts caused by DC linearity errors or switching timing offsets can be mitigated by randomizing the mismatch. In a temperature encoder, there are multiple codewords that can represent the same value. By randomizing the selection of the codeword used to represent a specific value, the mismatch between DAC segments can be distributed across several codewords, rather than concentrated on a few specific codewords, thereby improving the overall performance of the DAC. It should be noted that not all bits to be digitized need to be encoded in this way. In some embodiments, only the first part of the input digital word (e.g., the most significant bit) is encoded according to a randomization process of the type described herein.

[0021] The value represented by the most significant bit can modulate the width of a "packet" in the bit string. The bit string includes bits indicating whether a current source is a driving current. For each current source, there is a corresponding bit in the bit string. The type of packets described in this paper are constructed such that bits inside the packet in the bit string result in a current source that drives the current, while bits outside the packet result in a current source that does not drive the current (or vice versa). Several aspects of the packets can be randomized, as detailed below.

[0022] First, the direction in which a packet contracts or expands can be randomized, depending on the value to be encoded. For example, if the value to be encoded changes from 2 to 4, the packet expands by two elements to the left or right of the bit string in a randomized manner. The direction of contraction / expansion can be chosen based on random or pseudo-random numbers.

[0023] Secondly, pairs of values ​​within a group (and / or outside the group) can be swapped in a randomized manner. The underlying principle behind this randomization is that, for the purpose of digital-to-analog conversion of a particular input string, it is irrelevant which specific current sources drive the current, as long as the total number of current sources remains constant. The randomization process is driven by the input data itself, not by random or pseudo-random numbers. In some implementations, the swapped bits can be indicated by the current value, represented by the most significant bit, relative to the previous value.

[0024] Furthermore, the decision of whether to apply randomization can itself be randomized. This randomization can be based on the same pseudo-random numbers described above.

[0025] By applying one or more of the randomization techniques described herein, the negative effects caused by switching timing offsets or DC mismatch can be mitigated.

[0026] II. Randomized encoder

[0027] Figure 1 This is a block diagram illustrating some embodiments of the technology described herein for performing digital-to-analog conversion (including a randomized encoder). System 10 is configured to receive an input digit word and convert it to the analog domain. As a result, analog signal 112 is an analog representation of the value initially represented by the input digit word. In this example, the input digit word comprises 12 bits (B0, B1, B2, B3, B4, B5, B6, B7, B8, B9 ... 10 And B 11 However, System 10 is not limited to input bit words of any particular length. Bits B0 to B8 can be considered as the least significant bit (LSB) of the input bit word, and bits B9 to B... 11 The most significant bit (MSB) of the input digit word is considered as such. However, not all implementations are limited to this specific way of grouping LSBs and MSBs. A randomized encoder 100 is used to encode the bits corresponding to the subset of MSBs. A binary encoder 102 can be used to encode the bits corresponding to the subset of LSBs, but the same second or even third randomized encoder as described, or another randomized encoder, can also be used to encode these bits. The outputs (C0…C6) of the randomized encoder 100 are provided as input to the DAC 104, and the outputs (…C6) of the binary encoder 102… Figure 1 (Unmarked) is provided as input to DAC 106. Combiner 110 combines the analog outputs of the DAC together (e.g., adds them) to generate analog signal 112.

[0028] The diagram below illustrates DAC 104 and randomization encoder 100. DAC 106 can be implemented similarly to DAC 104. Binary encoder 102 can be implemented in any suitable manner.

[0029] Figure 2This is a block diagram illustrating DAC 104 in additional detail. DAC 104 includes multiple DAC units 105. Each DAC unit 105 includes a current source (I) and a switch (S0, S1, S2, S3, S4, S5, and S6) coupled in series with that current source. When the switch is closed, the current from the corresponding source flows through the switch, thus contributing to the total output of DAC 104. Conversely, when the switch is open, the current from the corresponding source is blocked, thus not contributing to the total output of DAC 104. The state of each switch can be controlled independently of the other switches. Nominally, the current sources can be arranged to match (to generate the same current I). In practice, mismatch may occur, for example, due to unavoidable variations in the manufacturing process or temperature gradients. Therefore, the currents generated by the various sources may differ from each other at least to some extent.

[0030] DAC 104 receives bits (C0, C1, C2, C3, C4, C5, and C6) generated by randomization encoder 100 as input. At each time step, each bit C... i (i = 0, 1, 2, 3, 4, 5 or 6) controls the corresponding switch S k The state (i = 0, 1, 2, 3, 4, 5, or 6). However, which bit controls which switch changes over time, as discussed in detail below. Bits C0, C1, C2, C3, C4, C5, and C6 are collectively referred to here as the "control block".

[0031] Figure 3 This is a schematic diagram illustrating the operation of the randomized encoder 100. The diagram illustrates how the bits of the control block are associated with the various switches of the DAC 104. In relation to bit C... i The corresponding entries include S k In this case, this indicates bit C i Control switch S k The state. For example, in C i Switch S when = 0 k It is set to disconnect, while in C i When = 1, it is set to closed (or vice versa).

[0032] Initially, in Figure 3 In the block, the control block is arranged such that bit C0 controls the state of switch S0, bit C1 controls the state of switch S1, bit C2 controls the state of switch S2, bit C3 controls the state of switch S3, bit C4 controls the state of switch S4, bit C5 controls the state of switch S5, and bit C6 controls the state of switch S6 (see...). Figure 3 (First row of the diagram). The way the bits of the control block are associated with the switches changes over time (see...). Figure 3 (The attached row of the chart in the text).

[0033] The entry in the control block indicates whether the associated switch is enabled (closed) or disabled (open). Figure 3 In this context, these entries are represented by shading of bits. For example... Figure 3 The legend in the upper right corner shows that one type of shaded indicator corresponds to a switch that should be enabled, while the other type corresponds to a switch that should be disabled. For example... Figure 3 The illustration in the lower right corner further illustrates that entries indicating the corresponding switches to be enabled can be contiguous—these entries are called "groups." Entries within a group in the control block indicate that the corresponding switch should be enabled; entries outside the group in the control block indicate that the corresponding switch should be disabled. It should be noted that in some implementations, the reverse logic is also possible (entries within a group in the control block indicate that the corresponding switch should be disabled; entries outside the group in the control block indicate that the corresponding switch should be enabled). The width of the group and the group's positioning relative to the control block entries change over time, depending on the value of the MSB bit.

[0034] III. Randomization of grouping shrinkage or expansion direction

[0035] Figure 3 The different rows of the chart represent different time intervals. Each time interval can correspond to one clock cycle or more than one clock cycle. Initially, in conjunction with... Figure 3 In the first row corresponding to the time interval, the MSB bit represents a value equal to 2. This sets the width of the block to 2 bits. During this time interval, switches S2 and S3 are enabled, while all other switches are disabled. As the value of the MSB bit changes over time, the block expands or contracts. The direction in which the block expands or contracts (left or right) can be chosen randomly, for example, based on a random number or pseudo-random number.

[0036] In Figure 3 In the second row corresponding to the time interval, the value represented by the MSB bit changes from 2 to 3. This causes the block width to expand from 2 bits to 3 bits. Whether the expansion occurs on the left or right is randomized. In this example, the randomization process results in an expansion towards the right.

[0037] In Figure 3 In the corresponding time interval of the third row, the value represented by the MSB bit changes from 3 to 4. This causes another expansion of the block width from 3 bits to 4 bits. Again, whether the expansion occurs on the left or right is randomized. This time, the randomization process results in an expansion towards the left.

[0038] In Figure 3In the fourth row corresponding to the time interval, the value represented by the MSB bit changes from 4 back to 3. This causes the block width to shrink from 4 bits to 3 bits. Whether the shrinkage occurs on the left or right is randomized. Here, the randomization process causes the shrinkage to the left.

[0039] In Figure 3 In the fifth row corresponding to the time interval, the value represented by the MSB bit changes from 3 to 5. This results in another expansion of the block width from 3 bits to 5 bits. Here, the randomization process causes an expansion to the right.

[0040] Finally, in relation to Figure 3 In the time interval corresponding to the sixth row, the value represented by the MSB bit changes from 5 back to 4. This causes another contraction in the block width from 5 bits to 4 bits. Here, the randomization process causes the contraction to the right.

[0041] In some implementations, the direction of expansion or contraction can be changed every n samples, where n is a fixed number, a random number, or a pseudo-random number. In one example of randomized n, the direction of expansion or contraction can initially be set to the left for three time intervals, then to the right for four time intervals, then to the left for two time intervals, and so on. In some implementations, a random binary decision determines whether to modify the grouping every n samples, where n can represent the number of randomized samples or a fixed number of samples.

[0042] Over time, the process of randomizing the direction of group expansion or contraction causes the current source mismatch to be distributed more evenly across the entries of the control block, thereby reducing its negative impact and increasing the SNR of the DAC.

[0043] IV. exchange

[0044] In addition to randomizing the direction of group expansion or contraction (or as an alternative), another type of randomization can be performed as part of the randomization encoder 100. This randomization process involves exchanging value pairs within groups (and / or value pairs outside groups). The basic principle behind the randomization exchange is that as long as the total number of current sources driving the current remains constant, and the exchanged value pairs have the same state when they are exchanged, it is irrelevant which / which specific current sources drive the current. The input data itself, not random numbers or pseudo-random numbers, drives this randomization process.

[0045] Refer to again Figure 3The positions of the switches corresponding to the second row of the sequence are swapped with those corresponding to the relative boundaries of the group. Without the swap, bit C2 (on the left boundary of the group) will continue to control switch S2, and bit C4 (on the right boundary of the group) will continue to control switch S4. After the swap, bit C2 controls switch S4, and bit C4 controls switch S2. Additionally, the positions of switches located outside the group and immediately adjacent to its relative boundary are also swapped. Without the swap, bit C1 will continue to control switch S1, and bit C5 will continue to control switch S5. After the swap, bit C1 controls switch S5, and bit C5 controls switch S1.

[0046] Refer to again Figure 3 The time interval corresponding to the third row will again swap the positions of the switches corresponding to the relative boundaries of the group. Without swapping, bit C1 will continue to control switch S5, and bit C4 will continue to control switch S2. After the swap, bit C1 controls switch S2, and bit C4 controls switch S5. Additionally, the positions of switches located outside the group and immediately adjacent to its relative boundary are also swapped. Without swapping, bit C0 will continue to control switch S0, and bit C5 will continue to control switch S1. After the swap, bit C0 controls switch S1, and bit C5 controls switch S0.

[0047] Refer to again Figure 3 The time interval corresponding to the fourth row will again swap the positions of the switches corresponding to the relative boundaries of the group. Without swapping, bit C1 will continue to control switch S2, and bit C3 will continue to control switch S3. After the swap, bit C1 controls switch S3, and bit C3 controls switch S2. Additionally, the positions of switches located outside the group and immediately adjacent to its relative boundary are also swapped. Without swapping, bit C0 will continue to control switch S1, and bit C4 will continue to control switch S5. After the swap, bit C0 controls switch S5, and bit C4 controls switch S1.

[0048] Refer to again Figure 3 The time interval corresponding to the fifth row will again swap the positions of the switches corresponding to the relative boundaries of the group. Without swapping, bit C1 will continue to control switch S3, and bit C5 will continue to control switch S0. After the swap, bit C1 controls switch S0, and bit C5 controls switch S3. Additionally, the positions of switches located outside the group and immediately adjacent to its relative boundary are also swapped. Without swapping, bit C0 will continue to control switch S5, and bit C6 will continue to control switch S6. After the swap, bit C0 controls switch S6, and bit C6 controls switch S5.

[0049] Finally, refer again to Figure 3 The time interval corresponding to the sixth row will again swap the positions of the switches corresponding to the relative boundaries of the group. Without swapping, bit C2 will continue to control switch S4, and bit C5 will continue to control switch S3. After the swap, bit C2 controls switch S3, and bit C5 controls switch S4. Additionally, the positions of switches located outside the group and immediately adjacent to its relative boundary are also swapped. Without swapping, bit C1 will continue to control switch S0, and bit C6 will continue to control switch S5. After the swap, bit C1 controls switch S5, and bit C6 controls switch S0.

[0050] For convenience, the selection of the switch position corresponding to the relative boundary being exchanged in the group is arbitrary. For example, a boundary switch can be swapped with another switch closest to the center of the control group. Similarly, a boundary switch can be swapped with another switch closest to the center of a switch not in the control group.

[0051] It should be understood that if a control group has fewer than two switches, an switching anomaly exists, and in this case, no switching will occur within the control group. Similarly, if a control group has more than five switches, an switching anomaly exists, and in this case, no switching will occur outside the control group.

[0052] V. Randomization of swaps

[0053] In some implementations, whether to perform the above exchange is randomized. This randomization can be based on random numbers or pseudo-random numbers. These random numbers or pseudo-random numbers can be the same as or different from the random numbers or pseudo-random numbers used in the randomization of the direction of group expansion or contraction.

[0054] For example, the exchange can be done with Figure 3 The swap is executed within the time intervals corresponding to the second and fifth lines, but it may not be executed within the time intervals corresponding to the third, fourth, and sixth lines. Again, whether to perform the swap within a specific time interval is randomized.

[0055] In some implementations, the exchange can be performed every n time intervals, where n is a fixed number, or a random or pseudo-random number.

[0056] VI. in conclusion

[0057] Therefore, some implementations relate to a method for performing digital-to-analog conversion (DAC). This method includes: receiving input digital words (e.g., B0, B1, B2, B3, B4, B5, B6, B7, B8, B9, B...). 10And B 11 The method further includes encoding at least a portion (e.g., MSB) of the input digital word using a randomized encoder (e.g., 102). The randomized encoder may include multiple outputs coupled to multiple DAC units (e.g., DAC unit 105). The state of each of the multiple outputs (e.g., whether it is 0 or 1) can be set by a corresponding entry in a control block (see...). Figure 3 The step of encoding at least a portion of the input numeric characters may further include: setting at least some entries in the control block (see...). Figure 3 Grouping can be generated by setting at least some entries. Setting the group width can include: setting the group width based on the value represented by at least a portion of the input digits. Furthermore, it can be based on a variation in the value represented by at least a portion of the input digits (e.g., from 2 to 3, such as...). Figure 3 The grouping can be modified (as shown in the second row). Modifying the grouping may include changing the width of the grouping in a first direction (e.g., to the left) or a second direction (e.g., to the right) based on a random number or pseudo-random number. Finally, the plurality of DAC units (e.g., corresponding to the grouping) can be controlled based on the grouping in a first time interval. Figure 3 (a row), and can control the plurality of DAC units again based on the modified grouping in a second time interval after the first time (e.g., corresponding to a row). Figure 3 (The following lines).

[0058] Figures 4A to 4B Presented as an example to illustrate the positive effects of the randomized encoder described in this paper. Figure 4A This is a graph illustrating the spectrum of a DAC output subjected to switching timing errors or DC linearity errors. On the other hand, Figure 4B This is a graph illustrating the spectrum of a DAC output subjected to switching timing errors or DC linearity errors, where a randomized encoder of the type described herein is used to encode the DAC. In both examples, the spectrum peaks at approximately 7 GHz (the frequency corresponding to the first harmonic of the signal). Figure 4A In the example, without DAC mismatch compensation, the noise spectrum is relatively flat in the region between 500 MHz and 10 GHz. However, compensating for the mismatch in the manner described herein results in a negative slope in the noise spectrum. This means that spurious content generated by timing errors is pushed to lower frequencies far from the bandwidth of interest.

[0059] The use of ordinal numbers (such as "first", "second", "third" etc.) to modify claim elements in claims does not in itself imply any priority, order or sequence of one claim element over another, nor does it imply the chronological order of the execution of method actions. Rather, it is merely used as a marker to distinguish one claim element with a specific name from another element with the same name (but using an ordinal number), in order to differentiate these claim elements.

[0060] Furthermore, the wording and terminology used herein are for descriptive purposes and should not be considered limiting. The use of “including,” “comprising,” “having,” “containing,” or “involving,” and variations thereof, in this document is intended to cover the items listed thereafter, their equivalents, and additional items.

[0061] The use of "coupled" or "connected" refers to circuit elements or signals that are directly connected to each other or linked through an intermediate component.

[0062] In some implementations, the terms "approximately," "roughly," and "about" may be used to indicate a value within ±10% of the target value. The terms "approximately" and "about" may include the target value.

Claims

1. A method for performing a digital-to-analog converter (DAC), the method comprising: Receive input numeric characters; At least a portion of the input digit word is encoded using a randomized encoder, wherein the randomized encoder includes a plurality of outputs coupled to a plurality of DAC units, the state of each of the plurality of outputs being set by a corresponding entry of a control block, and wherein encoding at least a portion of the input digit word includes: Grouping is generated by setting at least some entries in the control block, wherein setting the at least some entries includes: setting the width of the group based on the value represented by at least a portion of the input digits; and Modifying the grouping based on changes in the values ​​represented by at least a portion of the input digits, wherein modifying the grouping includes: changing the width of the grouping in a first direction or a second direction according to a random number or pseudo-random number; and In a first time interval, the plurality of DAC units are controlled based on the grouping, and in a second time interval following the first time interval, the plurality of DAC units are controlled based on the modified grouping.

2. The method according to claim 1, wherein, Encoding at least a portion of the input numeric word using a randomized encoder includes: encoding the most significant bit (MSB) of the input numeric word using the randomized encoder.

3. The method according to claim 2, further comprising: The least significant bit (LSB) of the input digit word is encoded using a binary encoder, which is different from the randomized encoder.

4. The method according to claim 1, wherein, The group control of the plurality of DAC units includes: Enable the first group of DAC units associated with the entries in the group; and The second group of DAC units associated with the entry located outside the group of the control block is disabled.

5. The method according to claim 1, wherein, Modifying the grouping also includes: swapping the first entry of the group with the second entry of the group.

6. The method according to claim 5, wherein, The first and second entries of the control block are boundary entries of the group.

7. The method according to claim 1, wherein, Encoding at least a portion of the input digits further includes swapping a first entry outside the group in the control block with a second entry outside the group in the control block.

8. The method according to claim 7, wherein, The first and second entries of the control block are respectively adjacent to the opposite ends of the group.

9. The method according to claim 1, wherein, The grouping is modified once for every n samples, where n represents the number of randomized samples or the fixed number of samples.

10. The method according to claim 1, further comprising: Every n samples will change the direction from the first direction to the second direction, where n represents the number of randomized samples or the number of fixed samples.

11. The method according to claim 1, further comprising: Based on a random binary decision, determine whether to modify the grouping for every n samples, where n represents the number of randomized samples or the number of fixed samples.

12. A system for performing a digital-to-analog converter (DAC), the system comprising: Multiple DAC units; as well as A randomized encoder includes multiple output terminals coupled to the plurality of DAC units, wherein the state of each of the plurality of output terminals is set by a corresponding entry of a control block, wherein the randomized encoder is configured to: Receive input numeric characters; At least a portion of the input numeric character is encoded using the following methods: Grouping is generated by setting at least some entries in the control block, wherein setting the at least some entries includes: setting the width of the group based on the value represented by at least a portion of the input numeric characters; and Modifying the grouping based on changes in the values ​​represented by at least a portion of the input digits, wherein modifying the grouping includes: changing the width of the grouping in a first direction or a second direction according to a random number or pseudo-random number; and In a first time interval, the plurality of DAC units are controlled based on the grouping, and in a second time interval following the first time interval, the plurality of DAC units are controlled based on the modified grouping.

13. The system according to claim 12, wherein, Encoding at least a portion of the input numeric word includes encoding the most significant bit (MSB) of the input numeric word.

14. The system of claim 13, further comprising a binary encoder, distinct from the encoder, the binary encoder being configured to encode the least significant bit (LSB) of the input digit word.

15. The system according to claim 12, wherein, The group control of the plurality of DAC units includes: Enable the first group of DAC units associated with the entries in the group; and The second group of DAC units associated with the entry located outside the group of the control block is disabled.

16. The system according to claim 12, wherein, Modifying the grouping also includes: swapping the first entry of the group with the second entry of the group.

17. The system according to claim 12, wherein, Encoding at least a portion of the input digits further includes swapping a first entry outside the group in the control block with a second entry outside the group in the control block.

18. A method for performing a digital-to-analog converter (DAC), the method comprising: Receive input numeric characters; At least a portion of the input digit word is encoded using a randomized encoder, wherein the randomized encoder includes multiple outputs coupled to multiple DAC units, the state of each of the multiple outputs being set by a corresponding entry of a control block, and wherein encoding at least a portion of the input digit word includes: Grouping is generated by setting at least some entries of the control block, wherein setting at least some of the entries includes: setting the width of the group based on the value represented by at least a portion of the input numeric characters; and Modifying the grouping based on changes in the values ​​represented by at least a portion of the input digits, wherein modifying the grouping includes: swapping a first entry of the grouping with a second entry of the grouping; and In a first time interval, the plurality of DAC units are controlled based on the grouping, and in a second time interval following the first time interval, the plurality of DAC units are controlled based on the modified grouping.

19. The method according to claim 18, wherein, Encoding at least a portion of the input numeric word using a randomized encoder includes: encoding the most significant bit (MSB) of the input numeric word using the randomized encoder.

20. The method according to claim 18, wherein, The first entry and the second entry of the group are the boundary entries of the group.

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