Superconducting quantum computation reflectometry time-division multiplexing method

Abstract

The application discloses a superconducting quantum computing reflection measurement time division multiplexing method, comprising the following steps: setting Qubit measurement parameters and ADC acquisition parameters into an FPGA chip, and setting a driving waveform of an analysis measurement DAC; judging whether Qubit reflection measurement triggers effectively, if yes, waiting for a DAC trigger delay time, and the DAC playing waveform data; if not, continuing to wait for triggering; waiting for a trigger delay time, and the ADC collecting and caching data; loading Xth Qubit analysis parameters; Xth Qubit analysis measurement calculation; loading Xth Qubit decision parameters; Xth Qubit quantum state decision calculation; and judging whether Xth Qubit analysis is completed. According to the method, each Qubit reflection measurement channel can complete 32 Qubit reflection measurement works only by using a set of Qubit analysis measurement and Qubit decision modules, so that the resource occupation amount in the FPGA is greatly reduced, and a technically feasible path is provided for reducing equipment power consumption, improving cost performance and improving equipment integration.

Description

Technical Field

[0001] This invention belongs to the field of wireless communication technology, specifically a time-division multiplexing method for superconducting quantum computing reflection measurement. Background Technology

[0002] Currently, in the field of superconducting quantum computing, superconducting quantum computing reflection measurement devices generally output microwave radio frequency signal pulses as excitation signals for qubit readout through methods such as orthogonal upconversion, single-sideband upconversion, or direct radio frequency generation. The excitation signal is "modulated" by different quantum states of the qubit, resulting in subtle phase and amplitude differences based on different quantum bands. After the signal is acquired by analog-to-digital converter (AD) through orthogonal downconversion, single-sideband downconversion, or radio frequency bandpass sampling, the sampled data is processed by hardware FPGA or computer to identify different qubit states.

[0003] However, with the development of superconducting quantum computing, the number of qubits in ultra-large quantum computing chips is increasing, and the number of qubits connected in series on a single readout line is also gradually increasing. Schemes that use computers to calculate and identify qubit states are becoming increasingly computationally intensive and involve larger data transmission volumes, making them unsuitable for the future development of superconducting quantum computing. Schemes using FPGAs for hardware logic computation, with their increased qubit state calculations and decision-making modules, require faster FPGA chips with more abundant resources.

[0004] Existing superconducting quantum computing reflection measurement equipment is mainly imported, employing a single-sideband double-conversion scheme. It has an internal quantum bit readout analysis and decision module, which meets most usage requirements, but the cost is very high, which is not conducive to the construction of ultra-high quantum bit number computers in the future.

[0005] Existing technologies primarily utilize RFSOC chips, JESD204B interface ADC and DAC chips, and FPGAs. The biggest problem with using RFSOC chips is insufficient resource availability, making it impossible to match the number of ADC and DAC channels to achieve 12 Qubit reflection measurement and decision per channel. While using high-speed JESD204B interface ADC and DAC chips with FPGAs allows for more Qubits per reflection measurement channel by employing a large-capacity FPGA with fewer ADC and DAC channels, this approach results in higher power consumption and cost, and severely limits system integration. Summary of the Invention

[0006] The purpose of this invention is to provide a time-division multiplexing method for superconducting quantum computing reflection measurement, to address the shortcomings of existing technologies, such as insufficient chip resources to match the number of ADC and DAC channels and achieve 12 Qubit reflection measurement and decision per reflection measurement channel. Furthermore, using a large-capacity FPGA with fewer ADC and DAC channels to support more Qubits per reflection measurement channel results in increased power consumption and cost, and severely restricts the improvement of system integration.

[0007] To solve the above-mentioned technical problems, the technical solution adopted by the present invention is as follows:

[0008] A time-division multiplexing method for superconducting quantum computing reflection measurement includes the following steps:

[0009] The parameter setting steps begin with the Qubit reflection measurement time-division multiplexing process; the Qubit measurement parameters and ADC acquisition parameters are set in the FPGA chip, and the drive waveform of the DAC for analysis and measurement is set.

[0010] Qubit reflection measurement begins; Qubit reflection measurement is initiated.

[0011] Qubit reflection measurement judgment steps: Determine whether the Qubit reflection measurement is triggered effectively. If it is, wait for the DAC trigger delay time and the DAC plays waveform data; if it is not triggered, continue to wait for triggering.

[0012] Trigger delay waiting steps: Wait for the trigger delay time, and the ADC collects and buffers the data;

[0013] Parameter loading steps: Load the Xth Qubit analysis parameter, X=1;

[0014] Analysis and measurement calculation steps: Analysis and measurement calculation for the Xth Qubit;

[0015] Decision parameter loading steps: Load the Xth Qubit decision parameter;

[0016] Quantum state decision calculation steps: Calculate the decision for the Xth Qubit quantum state;

[0017] Analysis and judgment steps: Determine whether the analysis of the Xth Qubit is complete. If it is complete, the Qubit reflection measurement time division multiplexing process ends; if it is not complete, X = X + 1, parameter loading step, and continue calculation.

[0018] According to the above technical solution, the Qubit measurement parameters include the number of Qubits, the analysis frequency of each Qubit, the initial phase for analysis and calculation, and the decision vector.

[0019] According to the above technical solution, setting the ADC acquisition parameters includes: setting the ADC to be triggered internally or externally, setting the delay time for ADC trigger acquisition, and setting the duration of ADC data acquisition.

[0020] According to the above technical solution, setting the driving waveform of the DAC for analysis and measurement includes setting the Qubit reflection measurement, DAC waveform data, and the playback duration of the DAC waveform data.

[0021] According to the above technical solution, in the parameter loading step, the loaded analysis parameters include: the data collected and cached by the ADC in the trigger delay waiting step, and the analysis parameters of Qubit X; the analysis parameters of Qubit X include: the frequency of Qubit X, the initial phase of Qubit X, and the duration of Qubit X.

[0022] According to the above technical solution, in the decision parameter loading step, the decision parameters include: the Xth Qubit analysis and measurement result and the Xth Qubit decision vector.

[0023] Compared with the prior art, the present invention has the following beneficial effects:

[0024] The method in this invention allows each Qubit reflection measurement channel to complete 32 Qubit reflection measurements using only one set of Qubit analysis and measurement and Qubit decision modules, greatly reducing the resource consumption within the FPGA and providing a technically feasible path for reducing device power consumption, improving cost-effectiveness, and increasing device integration. Attached Figure Description

[0025] Figure 1 This is a flowchart of the time-division multiplexing process of the present invention;

[0026] Figure 2 This is a flowchart of the parallel time-division multiplexing process of the present invention;

[0027] Figure 3 This is a system module diagram of the present invention. Detailed Implementation

[0028] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0029] Example 1

[0030] like Figure 1 and Figure 3As shown, the time-division multiplexing method for superconducting quantum computing reflection measurement includes the following steps:

[0031] The parameter setting steps begin with the Qubit reflection measurement time-division multiplexing process; the Qubit measurement parameters and ADC acquisition parameters are set into the FPGA chip, and the drive waveform of the DAC for analysis and measurement is set.

[0032] Qubit reflection measurement begins; Qubit reflection measurement is initiated.

[0033] Qubit reflection measurement judgment steps: Determine whether the Qubit reflection measurement is triggered effectively. If it is, wait for the DAC trigger delay time and the DAC plays waveform data; if it is not triggered, continue to wait for triggering.

[0034] The Qubit reflection measurement is triggered when the control signal (e.g., LVCMOS-3.3 signal) of the external trigger source input device is valid.

[0035] Trigger delay waiting steps: Wait for the trigger delay time, and the ADC collects and buffers the data;

[0036] Parameter loading steps: Load the Xth Qubit analysis parameter, X=1;

[0037] Furthermore, X is a positive integer, and the range of X values ​​is: X = 1, 2, 3, ... N.

[0038] Analysis and measurement calculation steps: Analysis and measurement calculation for the Xth Qubit;

[0039] Decision parameter loading steps: Load the Xth Qubit decision parameter;

[0040] Quantum state decision calculation steps: Calculate the decision for the Xth Qubit quantum state;

[0041] Analysis and judgment steps: Determine whether the analysis of the Xth Qubit is complete. If it is complete, the Qubit reflection measurement time division multiplexing process ends; if it is not complete, X = X + 1, parameter loading step, and continue calculation.

[0042] The method in this invention allows each Qubit reflection measurement channel to complete 32 Qubit reflection measurements using only one set of Qubit analysis and measurement and Qubit decision modules, greatly reducing the resource consumption within the FPGA and providing a technically feasible path for reducing device power consumption, improving cost-effectiveness, and increasing device integration.

[0043] Example 2

[0044] This embodiment is a further refinement of Embodiment 1.

[0045] Qubit measurement parameters include the number of qubits, the analysis frequency per qubit, the initial phase for analysis calculation, and the decision vector.

[0046] Setting ADC acquisition parameters includes: setting the ADC to be triggered internally or externally, setting the delay time for ADC trigger acquisition, and setting the duration of ADC data acquisition.

[0047] Setting the drive waveform for DAC analysis and measurement includes setting the Qubit reflection measurement, DAC waveform data, and the playback duration of the DAC waveform data.

[0048] In the parameter loading step, the loaded analysis parameters include: the data acquired and cached by the ADC in the trigger delay waiting step, and the analysis parameters of Qubit X; the analysis parameters of Qubit X include: the frequency of Qubit X, the initial phase of Qubit X, and the duration of Qubit X.

[0049] In the decision parameter loading step, the decision parameters include: the Xth Qubit analysis measurement result and the Xth Qubit decision vector.

[0050] The result of a Qubit analysis measurement refers to the complex vector obtained after the current measurement. The Qubit decision vector refers to the criterion for determining the state of the measurement vector.

[0051] like Figure 3 As shown, a single superconducting quantum computing measurement operation typically begins with a Trig trigger pulse, which is usually provided to the control and readout devices via a distribution device. The readout device's DA output reflects the measurement excitation signal with a delay parameter; this delay time is generally provided for the control device to perform the Qubit gate operation in response. After the control is completed, the reflection measurement device sends a readout excitation signal to the readout signal channel of the Qubit to be read. Generally, the readout signal sends one or more frequency pulses depending on the characteristics of the Qubit to be read and the actual readout requirements. After the DA sends the transmit measurement excitation signal, the AD acquisition channel generally needs to add a certain amount of delay on top of the delay of the DA output reflected measurement excitation signal, mainly to compensate for the signal transmission time of the measurement line.

[0052] The ADC acquires the reflection measurement signal, supporting a maximum depth of 32kSa, and stores it in the internal RAM of the FPGA (SoC) chip. During subsequent time-division multiplexing measurements and decision analysis, the number of analyses is determined by the Qubit setting, requiring repeated readings. Each reading inputs the data into the time-division multiplexing analysis measurement module, completing one Qubit measurement calculation. The maximum number of reads is 32.

[0053] Analysis and measurement parameters generally include Qubit frequency information, phase information, and analysis duration, which need to be written into the device's internal operating parameter register through the device's host communication interface during the device preparation phase. Qubit decision operating parameters are mainly written into the decision analysis vector for a specific Qubit, and are also stored in the device's internal operating parameter register.

[0054] During time-division multiplexing, the Qubit analysis and measurement module is designed to support only one Qubit of real-time analysis capability. This means that for a single ADC sampling channel, with the same ADC sampling rate and a longest sampling point of 32kSa (corresponding to a 2.5Gsps sampling rate duration of 13.1072us), only one set of Qubit analysis and measurement parameters can be loaded without blocking for one Qubit parameter analysis and measurement calculation. The calculation time is the same as the ADC sampling time. After completing the first set of Qubit analysis and measurement calculations, the result is stored in the analysis and measurement register and simultaneously passed to the subsequent time-division multiplexing Qubit decision calculation module. Logically, the Qubit analysis and measurement module that just completed the calculation is then reset and reloaded with the original ADC sampling data and the second set of Qubit analysis and measurement parameters. This time-division multiplexing calculation process can be performed up to 32 times as needed, yielding 32 Qubit analysis and measurement results based on a maximum of 32 sets of analysis and measurement parameters. This structural design allows a resource-constrained FPGA (SoC) to support analysis capabilities exceeding 32 Qubits for a single analysis and measurement channel.

[0055] The processing time of the Qubit decision measurement module is basically fixed, but its operating time differs from that of the Qubit analysis measurement module. In the Qubit analysis measurement module, the processing time equals the data acquisition time, meaning the processing time increases with the data acquisition time. However, the processing latency of the Qubit decision measurement module is fixed. This module is responsible for receiving the complex data input from the Qubit analysis measurement module, comparing it according to the Qubit decision measurement parameters, and determining the Qubit state result represented by the complex data input. Generally, depending on the complexity and accuracy requirements, the processing latency of a Qubit decision measurement module is approximately tens of nanoseconds. The Qubit decision measurement module stores the state result of a single measurement using a bit storage mechanism and records the number of occurrences of multiple measurement states using a technical method. Thus, for a single measurement, the user can read the previous state decision result or obtain the count value of the occurrences of different states in several past state decision results by reading the technical results. Similarly, the Qubit analysis and measurement module is time-division multiplexed, and only one Qubit decision module needs to be designed and implemented. Time-division multiplexing occurs after each new Qubit analysis and measurement result is output by the Qubit analysis and measurement module.

[0056] Example 3

[0057] This invention provides a time-division multiplexing method. In practical applications, multiple time-division multiplexing modules can be designed to work in parallel, reducing the total latency of time-division multiplexing for the same quorum analysis task. For example, two parallel modules combined with 16 time-division multiplexing can still support 32-quorum analysis, but the latency is half that of the maximum multiplexing. When using four parallel modules combined with 8 time-division multiplexing, the processing speed can be increased by four times. This method is called the parallel time-division multiplexing method.

[0058] like Figure 2 As shown, the parallel time-division multiplexing method includes the following steps:

[0059] Qubit reflection measurement time-division multiplexing process begins;

[0060] Step S1: Set the Qubit measurement parameters to the analysis FPGA logic; the Qubit measurement parameters include: Qubit reflection measurement quantity, frequency, initial phase, and decision vector;

[0061] Step S2: Set the ADC acquisition parameters to the analysis FPGA logic; wherein, setting the ADC acquisition parameters includes: internal or external trigger, trigger acquisition delay, and duration;

[0062] Step S3: Set the analysis and measurement DAC drive waveform; the settings include: Qubit reflection measurement, DAC waveform data, and duration.

[0063] Step S4: Start Qubit reflectance measurement;

[0064] Step S5: Is the trigger valid? If yes, wait for the DAC trigger delay time and the DAC plays waveform data; if not, continue waiting for the trigger.

[0065] Step S6: Wait for the trigger delay time, and the ADC collects and caches the data;

[0066] Step S7, Qubit reflection measurement time-division multiplexing process (n=1);

[0067] Furthermore, n is a positive integer, and the range of n is: n = 1, 2, 3, ... N.

[0068] Step S8: Load 4 Qubit analysis parameters; the analysis parameters include the frequency, initial phase and duration of the n*4+1 to n*4+4th analysis parameters;

[0069] Step S9 involves parallel analysis and measurement calculations using 4 Qubits, including modules n*4+1, n*4+2, n*4+3, and n*4+4.

[0070] The analysis and measurement results of the n*4+1 to n*4+4 qubits and the decision vectors of the n*4+1 to n*4+4 qubits are obtained;

[0071] Step S10: Load 4 Qubit decision parameters; that is, load the analysis and measurement results of the n*4+1 to n*4+4th qubits and the decision vectors of the n*4+1 to n*4+4th qubits.

[0072] Step S11, 4 Qubit parallel quantum state decision calculation, including: n*4+1 decision module, n*4+2 decision module, n*4+3 decision module and n*4+4 decision module;

[0073] The judgment results for the n*4+1 to n*4+4th terms are obtained;

[0074] Step S12: Determine whether X = n * 4 is completed. If completed, the Qubit reflection measurement time division multiplexing process ends. If not completed, n = n + 1, and return to step S8 to continue calculation.

[0075] The system design can be tailored to the specific needs of different users, adjusting the parallelism and time-division multiplexing length accordingly. Parallelism determines the number of Qubits processed simultaneously, reducing processing latency. Increasing the number of time-division multiplexing operations can increase the maximum supported number of Qubits.

[0076] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus.

[0077] Finally, it should be noted that the above descriptions are merely preferred embodiments of the present invention and are not intended to limit the present invention. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A time-division multiplexing method for superconducting quantum computing reflection measurement, characterized in that: Includes the following steps: The parameter setting steps begin with the Qubit reflection measurement time-division multiplexing process; the Qubit measurement parameters and ADC acquisition parameters are set in the FPGA chip, and the drive waveform of the DAC for analysis and measurement is set. Qubit reflection measurement begins; Qubit reflection measurement is initiated. Qubit reflection measurement judgment steps: Determine whether the Qubit reflection measurement is triggered effectively. If it is, wait for the DAC trigger delay time and the DAC plays waveform data; if it is not triggered, continue to wait for triggering. Trigger delay waiting steps: Wait for the trigger delay time, and the ADC collects and buffers the data; Initialization steps: X=1; Parameter loading steps: Load the analysis parameters for the Xth Qubit; Analysis and measurement calculation steps: Analysis and measurement calculation for the Xth Qubit; Decision parameter loading steps: Load the Xth Qubit decision parameter; Quantum state decision calculation steps: Calculate the decision for the Xth Qubit quantum state; Analysis and judgment steps: Determine whether the analysis of the Xth Qubit is complete. If it is complete, the Qubit reflection measurement time division multiplexing process ends; if it is not complete, X = X + 1, parameter loading step, and continue calculation.

2. The time-division multiplexing method for superconducting quantum computing reflection measurement according to claim 1, characterized in that: Qubit measurement parameters include the number of qubits, the analysis frequency per qubit, the initial phase for analysis calculation, and the decision vector.

3. The time-division multiplexing method for superconducting quantum computing reflection measurement according to claim 1, characterized in that: Setting ADC acquisition parameters includes: setting the ADC to be triggered internally or externally, setting the delay time for ADC trigger acquisition, and setting the duration of ADC data acquisition.

4. The time-division multiplexing method for superconducting quantum computing reflection measurement according to claim 1, characterized in that: Setting the drive waveform for DAC analysis and measurement includes setting the Qubit reflection measurement, DAC waveform data, and the playback duration of the DAC waveform data.

5. The time-division multiplexing method for superconducting quantum computing reflection measurement according to claim 1, characterized in that: In the parameter loading step, the loaded analysis parameters include: the data acquired and cached by the ADC in the trigger delay waiting step, and the analysis parameters of Qubit X; the analysis parameters of Qubit X include: the frequency of Qubit X, the initial phase of Qubit X, and the duration of Qubit X.

6. The time-division multiplexing method for superconducting quantum computing reflection measurement according to claim 1, characterized in that: In the decision parameter loading step, the decision parameters include: the Xth Qubit analysis measurement result and the Xth Qubit decision vector.

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