Semiconductor structure and method of forming the same

Abstract

Embodiments of the present disclosure provide a semiconductor structure and a forming method thereof. The method comprises: providing a semiconductor substrate, the semiconductor substrate comprising a plurality of spaced active pillars; etching the active pillars to form a ring-shaped groove; the ring-shaped groove does not expose a top surface and a bottom surface of the active pillars; forming a first semiconductor layer in the ring-shaped groove to form the semiconductor structure; wherein a band gap of the first semiconductor layer is smaller than a band gap of the active pillars.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and to, but is not limited to, a semiconductor structure and a method for forming the same. Background Technology

[0002] Dynamic Random Access Memory (DRAM) is a commonly used semiconductor storage device in computers, consisting of many repeating memory cells. Each memory cell typically includes a capacitor and a transistor. The source of the transistor is connected to the capacitor through memory node contacts and landing pads, thereby enabling the reading of data stored in the capacitor or the writing of data to the capacitor for storage.

[0003] Currently, 6F is widely used. 2 DRAM is fabricated using traditional arraying methods and buried word line technology. However, this process makes DRAM miniaturization extremely difficult. While new materials are used to improve DRAM performance, this undoubtedly increases the complexity of the manufacturing process and the cost. Therefore, some related technologies employ vertical transistors to fabricate 4F... 2 In DRAM, a large number of charges (or holes) accumulate in the channels of vertical transistors. These charges (or holes) have no way to leak out. The accumulation of more and more charges (or holes) will cause the vertical transistors to malfunction. Therefore, the DRAM structure formed by vertical transistors in related technologies all have a certain degree of floating body effect (FBE), which affects the performance of DRAM. Summary of the Invention

[0004] In view of this, embodiments of the present disclosure provide a semiconductor structure and a method for forming the same.

[0005] In a first aspect, embodiments of this disclosure provide a method for forming a semiconductor structure, the method comprising:

[0006] A semiconductor substrate is provided, the semiconductor substrate comprising a plurality of spaced-apart active pillars;

[0007] The active post is etched to form an annular groove; the annular groove does not expose the top and bottom surfaces of the active post;

[0008] A first semiconductor layer is formed in the annular groove to form the semiconductor structure; wherein the bandgap width of the first semiconductor layer is smaller than the bandgap width of the active pillar.

[0009] In some embodiments, forming a first semiconductor layer in the annular groove to form the semiconductor structure includes:

[0010] The first semiconductor layer is subjected to surface treatment to form a second semiconductor layer;

[0011] A bit line metal layer is formed on the surface of the second semiconductor layer to form a bit line structure.

[0012] In some embodiments, etching the active post to form an annular groove includes:

[0013] An isolation layer is formed on the surface of the semiconductor substrate;

[0014] A first sacrificial layer covering a portion of the active pillar is formed on the surface of a portion of the isolation layer;

[0015] A second sacrificial layer is formed on the surfaces of the isolation layer, the first sacrificial layer, and the active pillar;

[0016] Remove the first sacrificial layer to form the first groove;

[0017] The active post is etched through the first groove to form the annular groove.

[0018] In some embodiments, the etching selectivity between the first sacrificial layer and the active pillar is greater than the etching selectivity between the second sacrificial layer and the active pillar.

[0019] In some embodiments, after forming the first semiconductor layer and before forming the second semiconductor layer, the method further includes:

[0020] Remove the second sacrificial layer.

[0021] In some embodiments, the surface treatment of the first semiconductor layer to form the second semiconductor layer includes:

[0022] A metal layer is formed by depositing a metal material on the surface of the first semiconductor layer.

[0023] The metal layer and the first semiconductor layer are annealed to form the second semiconductor layer.

[0024] In some embodiments, prior to forming the first semiconductor layer, the method further includes:

[0025] The unetched portion of the active pillar located in the middle of the annular groove is subjected to a first doping process to form a first doped region.

[0026] In some embodiments, the method further includes:

[0027] This forms a full-ring gate structure, storage node contacts, and capacitor structure.

[0028] In some embodiments, the full-ring gate structure is formed by the following steps:

[0029] A first insulating layer is formed on the gaps between the bit line structures and on the surface of the bit line metal layer to cover a portion of the active pillar;

[0030] A gate oxide layer and a gate metal layer covering a portion of the active pillar are sequentially formed on the surface of the first insulating layer to form the full-ring gate structure.

[0031] In some embodiments, after forming the full-ring gate structure, the method further includes:

[0032] A second insulating layer is formed covering a portion of the active pillar in the gaps between the full-ring gate structures, on the surface of the gate oxide layer, and on the surface of the gate metal layer.

[0033] In some embodiments, the storage node contact is formed through the following steps:

[0034] The active pillar is etched to form a second groove and an annular pillar, wherein the bottom surface of the second groove is flush with the top surface of the second insulating layer;

[0035] The annular pillar is subjected to a second doping process to form the storage node contact.

[0036] In some embodiments, the first heavy doping is the opposite of the second heavy doping.

[0037] In some embodiments, the method further includes:

[0038] The second groove is filled with insulating material to form a third insulating layer; or...

[0039] The second groove is filled with conductive material to form a conductive layer.

[0040] In some embodiments, the capacitor structure is formed by the following steps:

[0041] A first electrode layer, a dielectric layer, and a second electrode layer are sequentially formed on the surfaces of the storage node contact and the third insulating layer to form the capacitor structure.

[0042] In some embodiments, the capacitor structure is formed by the following steps:

[0043] A first electrode layer, a dielectric layer, and a second electrode layer are sequentially formed on the surfaces of the storage node contact and the conductive layer to form the capacitor structure.

[0044] In a second aspect, embodiments of this disclosure provide a semiconductor structure, which is formed by the above-described semiconductor structure formation method, and the semiconductor structure includes:

[0045] A semiconductor substrate having a plurality of spaced-apart active pillars formed thereon; each active pillar includes an annular groove that does not expose the top and bottom surfaces of the active pillar.

[0046] A first semiconductor layer is located in the annular groove, and the bandgap width of the first semiconductor layer is smaller than the bandgap width of the active pillar.

[0047] In some embodiments, the semiconductor structure further includes: a second semiconductor layer and a bit line metal layer;

[0048] The second semiconductor layer is located on the surface of the first semiconductor layer, and the bit line metal layer is located on the surface of the second semiconductor layer.

[0049] In some embodiments, the semiconductor structure further includes: a full-ring gate structure;

[0050] The full-ring gate structure is located on the surface of a portion of the active pillars, and the full-ring gate structure includes a gate oxide layer and a gate metal layer.

[0051] In some embodiments, the semiconductor structure further includes: a first insulating layer and a second insulating layer;

[0052] The first insulating layer is located on the surface of the bit line structure and in the gap between the bit line structures.

[0053] The second insulating layer is located on the surface of the full-ring gate structure and in the gaps between the full-ring gate structures.

[0054] In some embodiments, the semiconductor structure further includes: a memory node contact and a capacitor structure;

[0055] The capacitor structure is located on the surface of the storage node contact and is electrically connected to the storage node contact.

[0056] In some embodiments, the semiconductor structure further includes: a third insulating layer;

[0057] The third insulating layer is located inside the storage node contact, and the top surface of the third insulating layer is flush with the top surface of the storage node contact.

[0058] In some embodiments, the semiconductor structure further includes: a conductive layer;

[0059] The conductive layer is located inside the storage node contact, and the top surface of the conductive layer is flush with the top surface of the storage node contact.

[0060] In some embodiments, the semiconductor structure further includes: a first heavily doped region;

[0061] The first heavily doped region is located inside the first semiconductor layer.

[0062] The semiconductor structure and its formation method provided in this disclosure include: providing a semiconductor substrate, the semiconductor substrate including a plurality of spaced-apart active pillars; etching the active pillars to form an annular groove; the annular groove not exposing the top and bottom surfaces of the active pillars; forming a first semiconductor layer in the annular groove to form a semiconductor structure; wherein the bandgap of the first semiconductor layer is smaller than the bandgap of the active pillars. In this disclosure, the first semiconductor layer can serve as the source of a transistor. Because the bandgap of the first semiconductor layer is smaller than the bandgap of the active pillars, the potential barrier between the source and the semiconductor substrate is reduced, holes accumulated in the channel are easily discharged, the parasitic bipolar transistor effect is weakened, and the occurrence of the floating body effect of the formed semiconductor structure can be effectively suppressed, thereby improving the electrical performance and fabrication yield of the semiconductor structure. Attached Figure Description

[0063] In the accompanying drawings (which are not necessarily drawn to scale), similar reference numerals may describe similar parts in different views. Similar reference numerals with different letter suffixes may indicate different examples of similar parts. The drawings illustrate, by way of example and not limitation, the various embodiments discussed herein.

[0064] Figure 1 A schematic flowchart illustrating a semiconductor structure formation method provided in an embodiment of this disclosure;

[0065] Figures 2a-2r This is a schematic diagram of the semiconductor structure formation process provided in the embodiments of this disclosure;

[0066] Figure 3a This is a three-dimensional structural diagram of a semiconductor structure provided in an embodiment of the present disclosure;

[0067] Figure 3b and 3c Provided for the embodiments of this disclosure Figure 3a A cross-sectional view of the semiconductor structure along b-b';

[0068] The annotations in the attached figures are explained as follows:

[0069] 100—Semiconductor substrate; 101—Active pillar; 102—Isolation layer; 103—First sacrificial layer; 104—Second sacrificial layer; 105—First semiconductor layer; 106—Second semiconductor layer; 107—Bit line metal layer; 108—First insulating layer; 109—Gate oxide layer; 110—Gate metal layer; 111—Second insulating layer; 101a—Sub-active pillar; 101b—Memory node contact; 30—Full-ring gate structure; 112—Third insulating layer; 113—First electrode layer; 114—Dielectric layer; 115—Second electrode layer; 116—Conductive layer; 117—First heavily doped region; 40—Capacitor structure; 300—Semiconductor structure; A—First groove; B—Annular groove; C—Second groove. Detailed Implementation

[0070] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0071] In the following description, numerous details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In other instances, to avoid confusion with this disclosure, certain technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0072] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0073] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this disclosure, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this disclosure.

[0074] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0075] This disclosure provides a method for forming a semiconductor structure. Figure 1 This is a schematic flowchart of a semiconductor structure formation method provided in an embodiment of the present disclosure, such as... Figure 1 As shown, the method for forming a semiconductor structure includes the following steps: Step S101, providing a semiconductor substrate, the semiconductor substrate including a plurality of active pillars arranged at intervals.

[0076] The semiconductor substrate may include a top surface on the front side and a bottom surface opposite the front side. Ignoring the flatness of the top and bottom surfaces, two intersecting (e.g., perpendicular) directions can be defined on the plane containing the semiconductor substrate, with the direction perpendicular to the top and bottom surfaces of the semiconductor substrate defined as the third direction. In this embodiment, the first direction is defined as the X-axis, the second direction as the Y-axis, and the third direction as the Z-axis.

[0077] In this embodiment of the disclosure, the semiconductor substrate may be a silicon substrate, or it may include other semiconductor elements, such as germanium (Ge), or include semiconductor compounds, such as silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), or indium antimonide (InSb), or include other semiconductor alloys, such as silicon germanium (SiGe), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium arsenide (GaInAs), gallium indium phosphide (GaInP), and / or gallium indium arsenide phosphide (GaInAsP) or combinations thereof.

[0078] In this embodiment of the disclosure, the semiconductor substrate includes a plurality of active pillars arranged in an array along a first direction and a second direction, the active pillars being used to form transistors in a semiconductor structure.

[0079] In this embodiment of the disclosure, the active pillar can be a square prism (e.g., a square prism, a hexagonal prism, an octagonal prism) or a cylinder.

[0080] In this embodiment of the present disclosure, a semiconductor substrate and an active pillar can be formed in one step by an etching process. Both the semiconductor substrate and the active pillar can be P-type doped. For example, in this embodiment of the present disclosure, the active pillar can be a P-type doped silicon pillar, and the band gap of the active pillar is between 1.0 electron volt (eV) and 1.3 eV.

[0081] Step S102: Etch the active post to form an annular groove; the annular groove does not expose the top and bottom surfaces of the active post.

[0082] In this embodiment of the present disclosure, a portion of the active post can be removed by wet etching along the second direction to form an annular groove. The annular groove is formed in the middle part of the active post, so the top and bottom surfaces of the active post are not exposed by the annular groove.

[0083] In this embodiment of the disclosure, a portion of the active pillars in the middle of the annular groove are not etched away. The retained portion of the active pillars (i.e., the active pillars located in the projection area of ​​the annular groove along the second direction) are subsequently used to form the source of the transistor in the semiconductor structure.

[0084] Step S103: A first semiconductor layer is formed in the annular groove to form a semiconductor structure; the band gap of the first semiconductor layer is smaller than the band gap of the active pillar.

[0085] In this embodiment of the disclosure, the first semiconductor layer can serve as the source of the transistor. The first semiconductor layer can be an N-type doped semiconductor layer, such as an N-type doped silicon-germanium layer. The band gap of the first semiconductor layer is between 0.7 eV and 0.97 eV.

[0086] In other embodiments, the material of the first semiconductor layer may also be a metal sulfide material, such as iron sulfide, manganese sulfide, titanium sulfide, or nickel sulfide.

[0087] In this embodiment, since the bandgap of the first semiconductor layer is smaller than the bandgap of the active pillar, the potential barrier between the source and the semiconductor substrate can be reduced, making it easier to dissipate the holes accumulated in the transistor channel, weakening the parasitic bipolar transistor effect, effectively suppressing the floating body effect of the formed semiconductor structure, and improving the electrical performance and fabrication yield of the semiconductor structure.

[0088] Figures 2a-2r This is a schematic diagram illustrating the semiconductor structure formation process provided in an embodiment of this disclosure. The following is in conjunction with… Figures 2a-2r The formation process of the semiconductor structure provided in the embodiments of this disclosure will be described in detail.

[0089] First, you can refer to Figure 2a and 2b Step S101 is executed, providing a semiconductor substrate 100, which includes a plurality of spaced active pillars 101.

[0090] In this embodiment of the disclosure, such as Figure 2a As shown, the semiconductor substrate 100 includes a plurality of active pillars 101 arranged in an array along the X-axis direction (first direction) and the Y-axis direction (second direction).

[0091] For ease of understanding, Figure 2b Only one active column 101 is shown in the image. Figure 2a A cross-sectional view of a-a', showing the subsequent formation process. Figures 2c to 2r All are shown from the perspective of a-a' cross-section.

[0092] Next, you can refer to Figures 2c to 2g Step S102 is executed to etch the active post to form an annular groove B; the annular groove B does not expose the top and bottom surfaces of the active post 101.

[0093] In some embodiments, the annular groove B can be formed by the following steps: forming an isolation layer 102 on the surface of a semiconductor substrate 100; forming a first sacrificial layer 103 covering a portion of the active pillar 101 on the surface of the isolation layer 102; forming a second sacrificial layer 104 on the surfaces of the isolation layer 102, the first sacrificial layer 103 and the active pillar 101; removing the first sacrificial layer 103 to form a first groove A; and etching a portion of the active pillar 101 through the first groove A to form the annular groove B.

[0094] like Figure 2cAs shown, an isolation layer 102 is formed on the surface of the semiconductor substrate 100. In this embodiment, the isolation layer 102 is used to isolate the semiconductor substrate 100 from the active pillar 101 to prevent leakage current from the semiconductor substrate 100. The material of the isolation layer 102 can be an oxide or silicon oxynitride, such as silicon oxide.

[0095] like Figure 2d As shown, a first sacrificial layer 103 covering a portion of the active pillar 101 is formed on the surface of the isolation layer 102. In this embodiment, the height h1 of the first sacrificial layer 103 is less than the height h2 of the active pillar 101. The first sacrificial layer 103 is used to define the position of the bit line structure in subsequent processes. Therefore, the first sacrificial layer 103 has a high wet etching selectivity relative to the semiconductor substrate 100 (or the active pillar 101) and the isolation layer 102. The material of the first sacrificial layer 103 can be one or any combination of silicon nitride (SiN), silicon oxynitride (SiON), amorphous carbon (aC), or silicon carbonitride oxynitride (SiOCN).

[0096] like Figure 2e As shown, a second sacrificial layer 104 is formed on the surface of the isolation layer 102, the first sacrificial layer 103, and the active pillar 101. In this embodiment of the present disclosure, the second sacrificial layer 104 is used to protect the active pillar 101 when forming the bit line structure. Therefore, the second sacrificial layer 104 has a high wet etching selectivity relative to the semiconductor substrate 100 (or the active pillar 101) and the isolation layer 102. The material of the second sacrificial layer 104 can be one or any combination of silicon nitride, silicon oxynitride, amorphous carbon, or silicon carbonitride.

[0097] It should be noted that the etching selectivity between the first sacrificial layer 103 and the active pillar 101 is greater than that between the second sacrificial layer 104 and the active pillar 101. That is, under the same etching conditions, the first sacrificial layer 103 is easier to be etched away than the second sacrificial layer 104.

[0098] like Figure 2f As shown, the first sacrificial layer 103 is removed to form the first groove A. In this embodiment of the present disclosure, the first sacrificial layer 103 can be removed by wet etching technology, for example, by using strong acids such as concentrated sulfuric acid, hydrofluoric acid, or concentrated nitric acid to etch away the first sacrificial layer 103 to form the first groove A.

[0099] like Figure 2g As shown, a portion of the active pillar 101 is etched through the first groove A to form an annular groove B. In this embodiment of the present disclosure, a portion of the active pillar 101 can be etched away using a lateral dry etching technique to form the annular groove B. The annular groove B is located in the lower middle part of the active pillar 101 and does not expose the bottom and top surfaces of the active pillar 101.

[0100] In this embodiment of the disclosure, the isolation layer 102, the first sacrificial layer 103, and the second sacrificial layer 104 can all be formed by any suitable deposition process, such as chemical vapor deposition, physical vapor deposition (PVD), atomic layer deposition (ALD), spin coating, coating process, or furnace tube process.

[0101] In some embodiments, see Figure 2h After forming the annular groove B, the method for forming the semiconductor structure further includes: performing a first doping on the unetched portion of the active pillar 101 located in the middle of the annular groove B to form a first doped region 117. In this embodiment of the present disclosure, the first doping may be P-type doping on the active pillar 101, for example, doping the active pillar 101 with trivalent impurity elements such as boron, gallium, and indium.

[0102] In this embodiment of the disclosure, the purpose of forming the first heavily doped region 117 is to form a conductive channel. This conductive channel allows holes accumulated in the transistor channel to enter the semiconductor substrate 100 through band-to-band tunneling, thereby avoiding the conduction of parasitic transistors and improving the electrical performance of the semiconductor structure.

[0103] Next, you can refer to Figure 2i Step S103 is executed to form a first semiconductor layer 105 in the annular groove B to form a semiconductor structure; the band gap of the first semiconductor layer 105 is smaller than the band gap of the active pillar 101.

[0104] In this embodiment of the disclosure, the first semiconductor layer 105 is the source of the semiconductor structure.

[0105] In some embodiments, the formation process of the first semiconductor layer 105 may include the following steps: filling a semiconductor material in an annular groove B to form the first semiconductor layer 105; the first semiconductor layer 105 filling the annular groove B. In this embodiment, the semiconductor material used to form the first semiconductor layer 105 may be silicon germanide.

[0106] In this embodiment of the disclosure, since the bandgap width of the first semiconductor layer 105 is smaller than the bandgap width of the active pillar 101, the hole current of the transistor in the final semiconductor structure increases, the potential barrier between the source and the semiconductor substrate 100 decreases, the holes accumulated in the transistor channel are easily dissipated, the parasitic bipolar transistor effect is weakened, the breakdown voltage increases, and the occurrence of the floating body effect can be effectively suppressed.

[0107] In some embodiments, please refer to Figure 2i After forming the first semiconductor layer 105, the method for forming the semiconductor structure further includes removing the second sacrificial layer 104.

[0108] In this embodiment of the disclosure, the second sacrificial layer 104 can be removed by wet etching or dry etching techniques (e.g., plasma etching, ion milling, or reactive ion etching).

[0109] In some embodiments, please refer to Figure 2j and 2k The semiconductor structure includes at least a bit line structure. Step S103 may include the following steps: performing surface treatment on the first semiconductor layer 105 to form a second semiconductor layer 106; forming a bit line metal layer 107 on the surface of the second semiconductor layer 106 to form a bit line structure.

[0110] In this embodiment of the disclosure, the material of the bit line metal layer 107 includes: tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), titanium nitride (TiN), titanium-containing metal layer, polycrystalline silicon, or any combination thereof.

[0111] In some embodiments, the first semiconductor layer 105 is surface treated, and the second semiconductor layer 106 is formed by the following steps: depositing a metal material on the surface of the first semiconductor layer 105 to form a metal layer (not shown in the figure); annealing the metal layer and the first semiconductor layer 105 to form the second semiconductor layer 106.

[0112] In this embodiment, the metal material forming the second semiconductor layer 106 can be any one of titanium (Ti), tantalum (Ta), nickel (Ni), tungsten, platinum (Pt), and palladium (Pd). The metal material is deposited on the surface of the first semiconductor layer 105, and then reacted with the first semiconductor layer 105 through rapid thermal annealing to form a metal silicide as the second semiconductor layer 106.

[0113] In this embodiment of the disclosure, the bit line structure (i.e., bit line metal layer 107) and the first semiconductor layer 105 are connected by the second semiconductor layer 106 (i.e., metal silicide). Since the metal silicide has a low resistance, the contact resistance between the bit line metal layer 107 and the first semiconductor layer 105 can be reduced, thereby reducing the power consumption of the formed semiconductor structure.

[0114] In some embodiments, after forming the bit line structure, the method for forming the semiconductor structure further includes forming a full-ring gate structure, a memory node contact, and a capacitor structure.

[0115] Please refer to Figure 2lThe full-ring gate 30 structure can be formed by the following steps: forming a first insulating layer 108 covering a portion of the active pillar 101 in the gap between the bit line structures and on the surface of the bit line metal layer 107; forming a gate oxide layer 109 and a gate metal layer 110 covering a portion of the active pillar in sequence on the surfaces of the first insulating layer 108 and the active pillar 101 to form the full-ring gate structure 30; wherein the top surface of the gate oxide layer 109 is lower than the top surface of the active pillar 101.

[0116] In this embodiment, the first insulating layer 108 serves two purposes: firstly, it isolates adjacent bit line structures to prevent leakage current in the bit line structures, thereby preventing read or write operations on specific transistors; secondly, the first insulating layer 108 also isolates the bit line structures from the subsequently formed full-ring gate structure.

[0117] In this embodiment of the present disclosure, the first insulating layer 108, the gate oxide layer 109, and the gate metal layer 110 can be formed by any suitable deposition process. The material of the first insulating layer 108 can be silicon nitride; the material of the gate oxide layer 109 can be an oxide, such as silicon oxide; and the material of the gate metal layer 110 can be any material with good conductivity, such as titanium nitride.

[0118] In this embodiment of the disclosure, the full-ring gate structure 30 has a wide channel region, which can reduce the short-channel effect, improve the control capability of the gate, and thus improve the performance of the formed semiconductor structure.

[0119] In some embodiments, please refer to Figure 2l After forming the full-ring gate structure 30, the method for forming the semiconductor structure further includes forming a second insulating layer 111 covering a portion of the active pillar 101 in the gaps between the full-ring gate structures 30, the surface of the gate oxide layer 109, and the surface of the gate metal layer 110.

[0120] In this embodiment, the second insulating layer 111 serves two purposes: firstly, it isolates adjacent full-ring gate structures 30, preventing them from conducting and thus hindering control of individual transistors; secondly, it also isolates the full-ring gate structure 30 from the subsequently formed capacitor structure. The material of the second insulating layer 111 can be silicon nitride, silicon oxide, or silicon oxynitride.

[0121] Please refer to Figure 2m and 2n The storage node contact 101b can be formed by the following steps: etching the active pillar 101 to form a second groove C and an annular pillar 101a, wherein the bottom surface of the second groove C is flush with the top surface of the second insulating layer 111; and performing a second heavy doping on the annular pillar 101a to form the storage node contact 101b.

[0122] In this embodiment, a dry etching process (e.g., plasma etching, reactive ion etching, or ion milling) can be used to etch the active pillar 101 to form an annular pillar 101a and a second groove C. The second doping can be N-type doping of the annular pillar 101a, for example, doping the active pillar 101 with pentavalent impurity elements such as phosphorus, antimony, or arsenic to improve the conductivity of the annular pillar 101a.

[0123] In this embodiment of the disclosure, the doping types of the first doping and the second doping are opposite.

[0124] In this embodiment of the disclosure, the purpose of performing a second doping on the annular post 101a is to reduce the internal resistance of the annular post 101a, improve the conductivity of the memory node contact 101b, thereby reducing the contact resistance between the formed memory node contact 101b and the drain and capacitor structures, and improving the electrical performance of the semiconductor structure.

[0125] Please continue reading Figure 2n The active pillar 101 located in the projection area of ​​the second insulating layer 111 constitutes the drain D of the semiconductor structure.

[0126] In this embodiment of the disclosure, the storage node contact is made into a hollow structure. That is, the second groove C is formed in the active pillar 101 to increase the doping area of ​​the second heavy doping, that is, to achieve more sufficient heavy doping of the annular pillar 101a, thereby reducing the contact resistance between the storage node contact 101b and the drain D and the capacitor structure.

[0127] In some embodiments, please refer to Figure 2o The method for forming a semiconductor structure further includes filling an insulating material in the second groove to form a third insulating layer 112.

[0128] In this embodiment, the third insulating layer 112 fills the second groove, and the top surface of the third insulating layer 112 is flush with the top surface of the storage node contact 101b. The insulating material can be an oxide or a nitride, such as silicon oxide, silicon nitride, or silicon oxynitride.

[0129] In this embodiment of the present disclosure, the third insulating layer 112 is located inside the storage node contact 101b, and a capacitor structure is subsequently formed on the surface of the third insulating layer 112 and the storage node contact 101b. The third insulating layer 112 can prevent leakage of the capacitor structure.

[0130] In some embodiments, please refer to Figure 2p The capacitor structure 40 can be formed by the following steps: a first electrode layer 113, a dielectric layer 114, and a second electrode layer 115 are sequentially formed on the surfaces of the storage node contact 101b and the third insulating layer 112 to form the capacitor structure 40.

[0131] In this embodiment, a first electrode layer 113, a dielectric layer 114, and a second electrode layer 115 can be formed by sequentially depositing a first electrode material, a dielectric material, and a second electrode material on the surfaces of the storage node contact 101b and the third insulating layer 112. The first electrode material, dielectric material, and second electrode material can be formed using any of the following deposition processes: chemical vapor deposition, physical vapor deposition, and atomic layer deposition. The first electrode material and the second electrode material can include metal nitrides or metal silicides, such as titanium nitride. The dielectric material can include high-k dielectric materials, such as lanthanum oxide (La₂O₃), aluminum oxide (Al₂O₃), hafnium oxide (HfO₂), hafnium oxynitride (HfON), and hafnium silicate (HfSiO₂). x The first electrode material may be one or any combination of zirconium oxide (ZrO2) or zirconium oxide (ZrO2). In other embodiments, the first electrode material and the second electrode material may also be polycrystalline silicon.

[0132] In some embodiments, please refer to Figure 2q The method for forming a semiconductor structure further includes filling a conductive material in a second groove to form a conductive layer 116.

[0133] In this embodiment, the conductive layer 116 fills the second groove, and the top surface of the conductive layer 116 is flush with the top surface of the storage node contact 101b. The conductive material can be any one of titanium, tantalum, nickel, tungsten, platinum, palladium, and polycrystalline silicon.

[0134] Please refer to Figure 2r The capacitor structure 40 can also be formed by the following steps: a first electrode layer 113, a dielectric layer 114, and a second electrode layer 115 are sequentially formed on the surfaces of the storage node contact 101b and the conductive layer 116 to form the capacitor structure 40.

[0135] In this embodiment, a first electrode layer 113, a dielectric layer 114, and a second electrode layer 115 can be formed by sequentially depositing a first electrode material, a dielectric material, and a second electrode material on the surfaces of the storage node contact 101b and the conductive layer 116. Both the first and second electrode materials can include metal nitrides or metal silicides, such as titanium nitride. The dielectric material can include a high-k dielectric material, such as lanthanum oxide, aluminum oxide, hafnium oxide, hafnium oxynitride, hafnium silicate, or zirconium oxide, or any combination thereof. The first electrode material, dielectric material, and second electrode material can be formed using any of the following deposition processes: chemical vapor deposition, physical vapor deposition, or atomic layer deposition. In other embodiments, the first and second electrode materials can also be polycrystalline silicon.

[0136] In this embodiment of the present disclosure, the conductive layer 116 is located between the storage node contacts 101b. The storage node contacts 101b and the conductive layer 116 are used to electrically connect the drain of the semiconductor structure and the capacitor structure. Therefore, the conductive layer 116 can improve the conductivity of the storage node contacts 101b, thereby reducing the contact resistance between the storage node contacts 101b and the capacitor structure and improving the electrical performance of the semiconductor structure.

[0137] It should be noted that in the embodiments of this disclosure, a transistor structure is formed on the surface of each active pillar, and the accompanying drawings only show the formation process of one transistor.

[0138] The semiconductor structure formed in the embodiments of this disclosure has a vertical transistor structure, which can improve the integration of the semiconductor structure and achieve miniaturization of the semiconductor structure size.

[0139] In this embodiment, the active pillar of the source is thinned and heavily P-type doped (i.e., the first heavy doping) to form a conductive channel. At the same time, N-type SiGe (i.e., the first semiconductor layer) is used instead of the active pillar as the source. Due to the narrow bandgap of N-type SiGe, the hole current increases. Therefore, the potential barrier between the source and the semiconductor substrate is reduced, making it easy to dissipate the holes accumulated in the transistor channel. Thus, the parasitic bipolar transistor effect is weakened, the breakdown voltage increases, and the floating body effect is effectively suppressed. In addition, the heavy P-type doping allows the holes accumulated in the transistor channel to enter the semiconductor substrate through interband tunneling, thereby avoiding the conduction of the parasitic bipolar transistor and improving the electrical performance of the prepared semiconductor structure.

[0140] This disclosure provides a semiconductor structure. Figure 3aThis is a three-dimensional structural diagram of a semiconductor structure provided in an embodiment of this disclosure. Figure 3b and 3c Provided for the embodiments of this disclosure Figure 3a The cross-sectional view of the semiconductor structure along b-b' is shown below. Figures 3a-3c As shown, the semiconductor structure 300 includes a semiconductor substrate 100 and a first semiconductor layer 105.

[0141] The semiconductor substrate 100 has a plurality of active pillars 101 arranged along the X-axis direction (first direction) and the Y-axis direction (second direction); each active pillar 101 includes an annular groove, the annular groove not exposing the top surface and bottom surface of the active pillar 101.

[0142] In this embodiment of the disclosure, the active pillar 101 is used to form the transistor of the semiconductor structure 300. The active pillar may be a P-type doped silicon pillar, and the bandgap of the active pillar is between 1.0 eV and 1.3 eV.

[0143] The first semiconductor layer 105 is located in the annular groove, and the band gap of the first semiconductor layer 105 is smaller than the band gap of the active pillar 101.

[0144] In this embodiment of the disclosure, the first semiconductor layer 105 can serve as the source of a transistor. The first semiconductor layer 105 can be an N-type doped semiconductor layer, such as an N-type doped silicon-germanium layer. The band gap of the first semiconductor layer 105 is between 0.7 eV and 0.97 eV.

[0145] In this embodiment of the disclosure, since the bandgap width of the first semiconductor layer 105 is smaller than the bandgap width of the active pillar 101, the potential barrier between the source and the semiconductor substrate can be reduced, making it easier to dissipate the holes accumulated in the transistor channel, weakening the parasitic bipolar transistor effect, effectively suppressing the occurrence of the floating body effect of the semiconductor structure, and improving the electrical performance of the semiconductor structure 300.

[0146] In some embodiments, please refer to Figures 3a-3c The semiconductor structure 300 further includes a second semiconductor layer 106 and a bit line metal layer. The second semiconductor layer 106 is located on the surface of the first semiconductor layer 105, and the bit line metal layer 107 is located on the surface of the second semiconductor layer 106. In this embodiment, the second semiconductor layer and the bit line metal layer 107 constitute a bit line structure.

[0147] In this embodiment of the disclosure, the second semiconductor layer 106 is a metal silicide layer. Since metal silicide has a low resistance, it can reduce the contact resistance between the bit line metal layer 107 and the first semiconductor layer 105, thereby reducing the power consumption of the semiconductor structure 300.

[0148] In some embodiments, please refer to Figures 3a-3c The semiconductor structure 300 also includes a full-ring gate structure 30; the full-ring gate structure 30 is located on the surface of a portion of the active pillar 101, and the full-ring gate structure 30 includes a gate oxide layer 109 and a gate metal layer 110.

[0149] In this embodiment of the disclosure, the full-ring gate structure 30 has a wide channel region, which can reduce the short-channel effect, improve the control capability of the gate, and thus improve the performance of the semiconductor structure 300.

[0150] In some embodiments, please refer to Figures 3a-3c The semiconductor structure 300 further includes: a first insulating layer 108 and a second insulating layer 111; wherein the first insulating layer 108 is located on the surface of the bit line structure and in the gap between the bit line structures; and the second insulating layer 111 is located on the surface of the full-ring gate structure 30 and in the gap between the full-ring gate structures 30.

[0151] In this embodiment, the first insulating layer 108 serves two purposes: firstly, it isolates adjacent bit line structures to prevent leakage current in the bit line structures, thus preventing read or write operations on specific transistors; secondly, the first insulating layer 108 also isolates the bit line structures from the full-ring gate structure 30. The second insulating layer 111 isolates adjacent full-ring gate structures 30 to prevent them from conducting, thus preventing control of individual transistors; thirdly, the second insulating layer 111 also isolates the full-ring gate structure 30 from the capacitor structure.

[0152] In some embodiments, please refer to Figures 3a-3c The semiconductor structure 300 further includes a memory node contact 101b and a capacitor structure 40; wherein the capacitor structure 40 is located on the surface of the memory node contact 101b and is electrically connected to the memory node contact 101b.

[0153] In this embodiment, the active pillar 101 is subjected to a second doping to form the storage node contact 101b. The second doping can be N-type doping of the annular pillar 101a, for example, doping the active pillar 101 with pentavalent impurity elements such as phosphorus, antimony, or arsenic. The storage node contact 101b formed after the second doping has lower internal resistance and higher conductivity, which reduces the contact resistance between the storage node contact 101b and the drain and capacitor structures, thereby improving the electrical performance of the semiconductor structure 300.

[0154] In some embodiments, please refer to Figure 3bThe semiconductor structure 300 further includes: a third insulating layer 112; the third insulating layer 112 is located inside the memory node contact 101b; the top surface of the third insulating layer 112 is flush with the top surface of the memory node contact 101b, and the bottom surface of the third insulating layer 112 is flush with the bottom surface of the memory node contact 101b.

[0155] In this embodiment of the present disclosure, the third insulating layer 112 can prevent leakage of the capacitor structure 40.

[0156] In some embodiments, please refer to Figure 3c The semiconductor structure 300 further includes: a conductive layer 116; the conductive layer 116 is located inside the memory node contact 101b; the top surface of the conductive layer 116 is flush with the top surface of the memory node contact 101b, and the bottom surface of the conductive layer 116 is flush with the bottom surface of the memory node contact 101b.

[0157] In this embodiment of the present disclosure, the conductive layer 116 can improve the conductivity of the storage node contact 101b, thereby reducing the contact resistance between the storage node contact 101b and the capacitor structure 40 and improving the electrical performance of the semiconductor structure 300.

[0158] In some embodiments, please refer to Figure 3b and 3c The semiconductor structure 300 also includes a first heavily doped region 117; the first heavily doped region 117 is a region formed by first heavily doping the active pillars 101 inside the first semiconductor layer 105. In this embodiment, the first heavily doping can be P-type doping of the active pillars 101, for example, doping the active pillars 101 with trivalent impurity elements such as boron, gallium, and indium. The first heavily doped region 117 can serve as a conductive channel, allowing holes accumulated in the transistor channel to enter the semiconductor substrate 100 through interband tunneling, thereby avoiding the conduction of parasitic transistors and improving the electrical performance of the semiconductor structure 300.

[0159] In some embodiments, please refer to Figure 3b and 3c The semiconductor structure 300 also includes a drain D; the active pillar 101 located in the projection area of ​​the second insulating layer 111 constitutes the drain D of the semiconductor structure.

[0160] The semiconductor structure provided in this disclosure is similar to the semiconductor structure formed by the above embodiments. For technical features not disclosed in detail in this disclosure, please refer to the above embodiments for understanding. Here, they will not be repeated.

[0161] The semiconductor structure provided in this disclosure has several advantages. First, because the transistor is a vertical structure, the integration density of the semiconductor structure can be improved, and the size of the semiconductor structure can be miniaturized. Second, because the bandgap of the first semiconductor layer in the semiconductor structure is smaller than the bandgap of the active pillar, the hole current of the transistor increases, the potential barrier between the source and the semiconductor substrate decreases, the holes accumulated in the transistor channel are easily dissipated, the parasitic bipolar transistor effect is weakened, the breakdown voltage increases, and the occurrence of the floating body effect can be effectively suppressed, thereby improving the performance of the semiconductor structure.

[0162] In the several embodiments provided in this disclosure, it should be understood that the disclosed devices and methods can be implemented in a non-target manner. The device embodiments described above are merely illustrative. For example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods, such as: multiple units or components may be combined, or integrated into another system, or some features may be ignored or not executed.

[0163] The features disclosed in the several method or device embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method or device embodiments.

[0164] The above descriptions are merely some embodiments of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, The method includes: A semiconductor substrate is provided, the semiconductor substrate comprising a plurality of spaced-apart active pillars; The active post is etched to form an annular groove; the annular groove does not expose the top and bottom surfaces of the active post; A first semiconductor layer is formed in the annular groove to form the semiconductor structure; wherein the bandgap width of the first semiconductor layer is smaller than the bandgap width of the active pillar; The process of forming a first semiconductor layer in the annular groove to form the semiconductor structure includes: The first semiconductor layer is subjected to surface treatment to form a second semiconductor layer; A bit line metal layer is formed on the surface of the second semiconductor layer to form a bit line structure.

2. The method according to claim 1, characterized in that, The etching of the active pillar to form an annular groove includes: An isolation layer is formed on the surface of the semiconductor substrate; A first sacrificial layer covering a portion of the active pillar is formed on the surface of a portion of the isolation layer; A second sacrificial layer is formed on the surfaces of the isolation layer, the first sacrificial layer, and the active pillar; Remove the first sacrificial layer to form the first groove; The active post is etched through the first groove to form the annular groove.

3. The method according to claim 2, characterized in that, The etching selectivity ratio between the first sacrificial layer and the active pillar is greater than that between the second sacrificial layer and the active pillar.

4. The method according to claim 2, characterized in that, After forming the first semiconductor layer and before forming the second semiconductor layer, the method further includes: Remove the second sacrificial layer.

5. The method according to claim 4, characterized in that, The step of surface-processing the first semiconductor layer to form the second semiconductor layer includes: A metal layer is formed by depositing a metal material on the surface of the first semiconductor layer. The metal layer and the first semiconductor layer are annealed to form the second semiconductor layer.

6. The method according to any one of claims 1 to 5, characterized in that, Before forming the first semiconductor layer, the method further includes: The unetched portion of the active pillar located in the middle of the annular groove is subjected to a first doping process to form a first doped region.

7. The method according to claim 6, characterized in that, The method further includes: This forms a full-ring gate structure, storage node contacts, and capacitor structure.

8. The method according to claim 7, characterized in that, The full-ring gate structure is formed through the following steps: A first insulating layer is formed on the gaps between the bit line structures and on the surface of the bit line metal layer to cover a portion of the active pillar; A gate oxide layer and a gate metal layer covering a portion of the active pillar are sequentially formed on the surface of the first insulating layer to form the full-ring gate structure.

9. The method according to claim 8, characterized in that, After forming the full-ring gate structure, the method further includes: A second insulating layer is formed covering a portion of the active pillar in the gaps between the full-ring gate structures, on the surface of the gate oxide layer, and on the surface of the gate metal layer.

10. The method according to claim 9, characterized in that, The storage node contact is formed through the following steps: The active pillar is etched to form a second groove and an annular pillar, wherein the bottom surface of the second groove is flush with the top surface of the second insulating layer; The annular pillar is subjected to a second doping process to form the storage node contact.

11. The method according to claim 10, characterized in that, The first doping is the opposite of the second doping.

12. The method according to claim 10 or 11, characterized in that, The method further includes: The second groove is filled with insulating material to form a third insulating layer; or... The second groove is filled with conductive material to form a conductive layer.

13. The method according to claim 12, characterized in that, The capacitor structure is formed through the following steps: A first electrode layer, a dielectric layer, and a second electrode layer are sequentially formed on the surfaces of the storage node contact and the third insulating layer to form the capacitor structure.

14. The method according to claim 12, characterized in that, The capacitor structure is formed through the following steps: A first electrode layer, a dielectric layer, and a second electrode layer are sequentially formed on the surfaces of the storage node contact and the conductive layer to form the capacitor structure.

15. A semiconductor structure, characterized in that, The semiconductor structure is formed by the semiconductor structure forming method provided in any one of claims 1 to 14, comprising: A semiconductor substrate having a plurality of spaced-apart active pillars formed thereon; each active pillar includes an annular groove that does not expose the top and bottom surfaces of the active pillar. A first semiconductor layer is located in the annular groove, and the bandgap width of the first semiconductor layer is smaller than the bandgap width of the active pillar.

16. The semiconductor structure according to claim 15, characterized in that, The semiconductor structure further includes: a second semiconductor layer and a bit line metal layer; The second semiconductor layer is located on the surface of the first semiconductor layer, and the bit line metal layer is located on the surface of the second semiconductor layer.

17. The semiconductor structure according to claim 16, characterized in that, The semiconductor structure further includes: a full-ring gate structure; The full-ring gate structure is located on the surface of a portion of the active pillars, and the full-ring gate structure includes a gate oxide layer and a gate metal layer.

18. The semiconductor structure according to claim 17, characterized in that, The semiconductor structure further includes: a first insulating layer and a second insulating layer; The first insulating layer is located on the surface of the bit line structure and in the gap between the bit line structures. The second insulating layer is located on the surface of the full-ring gate structure and in the gaps between the full-ring gate structures.

19. The semiconductor structure according to any one of claims 15 to 18, characterized in that, The semiconductor structure also includes: a memory node contact and a capacitor structure; The capacitor structure is located on the surface of the storage node contact and is electrically connected to the storage node contact.

20. The semiconductor structure according to claim 19, characterized in that, The semiconductor structure further includes: a third insulating layer; The third insulating layer is located inside the storage node contact, and the top surface of the third insulating layer is flush with the top surface of the storage node contact.

21. The semiconductor structure according to claim 19, characterized in that, The semiconductor structure further includes: a conductive layer; The conductive layer is located inside the storage node contact, and the top surface of the conductive layer is flush with the top surface of the storage node contact.

22. The semiconductor structure according to claim 20 or 21, characterized in that, The semiconductor structure further includes: a first heavily doped region; The first heavily doped region is located inside the first semiconductor layer.

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