Methods for fabricating memory and memory

Abstract

This disclosure provides a method for fabricating a memory and the memory itself. The method includes: forming a first semiconductor structure including a memory array and a first bonding layer; the memory array including a vertical transistor array, a memory cell array, and multiple bit lines; first ends of multiple memory cells being correspondingly coupled to first ends of multiple vertical transistors, and multiple bit lines being correspondingly coupled to second ends of multiple vertical transistors; the first bonding layer being located on one side of the multiple bit lines; forming a second semiconductor structure including a second substrate, a second bonding layer on the second substrate, and a release layer within the second substrate; bonding the first bonding layer and the second bonding layer; separating the second substrate at the release layer, retaining a portion between the release layer and the second bonding layer as an active layer; and forming peripheral circuitry and interconnect structures, the peripheral circuitry being at least partially located in the active layer, and the peripheral circuitry being coupled to the memory array through the interconnect structures. The fabrication method of this disclosure can improve the density of the memory.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor fabrication technology, and in particular to a method for fabricating a memory and the memory itself. Background Technology

[0002] As semiconductor technology continues to mature, the demand for high-density and high-capacity memory is increasing. Currently, planar memory cells can be converted into three-dimensional memory architectures to further improve memory density and increase storage capacity. However, the fabrication process for three-dimensional memory is currently quite limited.

[0003] The information disclosed in the background section is only intended to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute related technology known to those skilled in the art. Summary of the Invention

[0004] This disclosure provides a method for fabricating a memory, comprising: forming a first semiconductor structure, the first semiconductor structure including a memory array and a first bonding layer, the memory array including a vertical transistor array, a memory cell array located on one side of the vertical transistor array, and a plurality of bit lines located on the other side of the vertical transistor array, the first ends of a plurality of memory cells in the memory cell array being correspondingly coupled to the first ends of a plurality of vertical transistors in the vertical transistor array, the plurality of bit lines being correspondingly coupled to the second ends of the plurality of vertical transistors, and the first bonding layer being located on the side of the plurality of bit lines away from the vertical transistor array; forming a second semiconductor structure, the second semiconductor... The bulk structure includes a second substrate, a second bonding layer on the second substrate, and a release layer within the second substrate; the first bonding layer and the second bonding layer are bonded to bond the first semiconductor structure and the second semiconductor structure; the second substrate is separated in the release layer, retaining a portion of the second substrate between the release layer and the second bonding layer as an active layer; peripheral circuits and interconnect structures are formed, the peripheral circuits being at least partially located in the active layer, and the interconnect structures including contact plugs that penetrate at least through the active layer, the second bonding layer, and the first bonding layer, the peripheral circuits being at least partially coupled to the memory array through the contact plugs.

[0005] In some embodiments of this disclosure, forming the first semiconductor structure includes: providing a first substrate and forming the vertical transistor array on the first substrate; forming the memory cell array on a side of the vertical transistor array away from the first substrate; thinning the first substrate from the side of the first substrate away from the vertical transistor array until the second ends of the plurality of vertical transistors are exposed; forming the plurality of bit lines on the side of the second ends of the plurality of vertical transistors away from the memory cell array; and forming the first bonding layer on the side of the plurality of bit lines away from the vertical transistor array.

[0006] In some embodiments of this disclosure, forming the vertical transistor array on the first substrate includes: forming an active pillar array in the first substrate; forming a plurality of word lines on the sidewalls of a plurality of active pillars in the active pillar array, each active pillar including a first end and a second end located on opposite sides of the corresponding word line; doping the first ends of the plurality of active pillars to form a first source-drain region, the first source-drain region serving as a first end of the plurality of vertical transistors; and after exposing the second ends of the plurality of vertical transistors and before forming the plurality of bit lines, doping the second ends of the plurality of active pillars to form a second source-drain region, the second source-drain region serving as a second end of the plurality of vertical transistors.

[0007] In some embodiments of this disclosure, the method further includes: before forming the first bonding layer, forming a plurality of first connection plugs and at least one second connection plug, wherein the plurality of first connection plugs are respectively coupled to the ends of the plurality of word lines, and the at least one second connection plug is coupled to the second end of the plurality of memory cells; wherein, after forming the first bonding layer, the plurality of first connection plugs are located between the plurality of word lines and the first bonding layer, and the at least one second connection plug is located between the plurality of memory cells and the first bonding layer.

[0008] In some embodiments of this disclosure, forming the peripheral circuit and the interconnect structure includes: forming the peripheral circuit on the active layer; forming a dielectric layer covering the active layer and the peripheral circuit; forming the interconnect structure, the interconnect structure including contact plugs penetrating the dielectric layer, the active layer, the second bonding layer and the first bonding layer, the contact plugs including a plurality of first contact plugs corresponding to the plurality of first connection plugs, at least one second contact plug corresponding to the at least one second connection plug, and a plurality of third contact plugs corresponding to the plurality of bit lines.

[0009] In some embodiments of this disclosure, forming the interconnect structure includes: forming a via through the dielectric layer, the active layer, the second bonding layer, and the first bonding layer before forming the contact plug; forming a spacer layer at least on the inner wall of the via through the active layer; filling the via with the contact plug, wherein the spacer layer is located at least between the inner wall of the via in the active layer and the contact plug.

[0010] In some embodiments of this disclosure, forming the plurality of bit lines on the side away from the memory cell array at the second ends of the plurality of vertical transistors includes: forming an insulating layer on the side where the second ends of the plurality of vertical transistors are located; and forming the plurality of bit lines in the insulating layer.

[0011] In some embodiments of this disclosure, forming the second semiconductor structure includes: providing the second substrate; forming the second bonding layer on one side of the second substrate; injecting hydrogen ions into the second substrate from the side where the second bonding layer is formed to form the release layer; and separating the second substrate from the release layer by: heating the second substrate such that the second substrate is separated with the release layer as a boundary.

[0012] This disclosure also provides a memory, including: a memory array, a first bonding layer, a second bonding layer, an active layer, peripheral circuitry, and an interconnect structure.

[0013] The memory array includes a vertical transistor array, a memory cell array located on one side of the vertical transistor array, and multiple bit lines located on the other side of the vertical transistor array. The first ends of multiple memory cells in the memory cell array are correspondingly coupled to the first ends of multiple vertical transistors in the vertical transistor array, and the multiple bit lines are correspondingly coupled to the second ends of the multiple vertical transistors.

[0014] A first bonding layer is located on the side of the plurality of bit lines away from the vertical transistor array. A second bonding layer is located on the side of the first bonding layer away from the plurality of bit lines and is bonded to the first bonding layer. An active layer is located on the side of the second bonding layer away from the first bonding layer. The peripheral circuitry is at least partially located in the active layer, and the interconnect structure includes contact plugs that penetrate at least through the active layer, the second bonding layer, and the first bonding layer, and the peripheral circuitry is at least partially coupled to the memory array through the contact plugs.

[0015] In some embodiments of this disclosure, the memory further includes: a plurality of word lines correspondingly coupled to the plurality of vertical transistors; a plurality of first connection plugs located between the plurality of word lines and the first bonding layer, respectively correspondingly coupled to the ends of the plurality of word lines; and at least one second connection plug located between the plurality of memory cells and the first bonding layer, coupled to the second end of the plurality of memory cells.

[0016] In some embodiments of this disclosure, the contact plug includes: a plurality of first contact plugs corresponding to and coupled to the plurality of first connecting plugs; at least one second contact plug corresponding to and coupled to the at least one second connecting plug; and a plurality of third contact plugs corresponding to and coupled to the middle portion of the plurality of bit lines.

[0017] In some embodiments of this disclosure, the storage unit includes one of a capacitor, a phase change storage unit, and a ferroelectric storage unit.

[0018] As can be seen from the above technical solutions, the transistor structure of this disclosure embodiment has at least one of the following advantages and positive effects:

[0019] In this embodiment of the present disclosure, a first semiconductor structure and a second semiconductor structure are bonded together using a first bonding layer and a second bonding layer. Then, peripheral circuits and interconnect structures are formed on the active layer of the second semiconductor structure to form a memory. Therefore, this embodiment of the present disclosure provides a new method for fabricating a three-dimensional memory to improve the density of the memory. Attached Figure Description

[0020] The above and other features and advantages of this disclosure will become more apparent from a detailed description of exemplary embodiments thereof with reference to the accompanying drawings.

[0021] Figure 1 The following is a flowchart illustrating a method for fabricating a memory according to some embodiments of this disclosure;

[0022] Figure 2 This is a top view schematic diagram illustrating a first substrate in some embodiments of this disclosure;

[0023] Figure 3 This is a top view schematic diagram illustrating the formation of an isolation layer in a first substrate according to some embodiments of this disclosure;

[0024] Figure 4 for Figure 3 Sectional view along the middle AA;

[0025] Figure 5 This is a top view schematic diagram illustrating the formation of word line trenches in a first substrate according to some embodiments of this disclosure;

[0026] Figure 6 for Figure 5 Sectional view along the middle AA;

[0027] Figure 7 This is a top view schematic diagram illustrating the formation of multiple character lines in some embodiments of this disclosure;

[0028] Figure 8 for Figure 7 Sectional view along the middle AA;

[0029] Figure 9 This is a cross-sectional schematic diagram showing, in some embodiments of the present disclosure, the doping of multiple active pillars after filling the word line trench with an isolation layer;

[0030] Figure 10 This is a schematic cross-sectional view illustrating the formation of a memory cell array according to some embodiments of this disclosure;

[0031] Figure 11 This is a schematic cross-sectional view of an inverted first semiconductor structure having a vertical transistor array and a memory cell array formed, as shown in some embodiments of this disclosure.

[0032] Figure 12 This is a schematic cross-sectional view showing the thinning of a first substrate to expose the second end of a vertical transistor and the doping of the second end, as illustrated in some embodiments of this disclosure.

[0033] Figure 13 This is a schematic cross-sectional view showing an insulating layer formed on the side of the second end of a vertical transistor away from the memory cell array, as illustrated in some embodiments of this disclosure.

[0034] Figure 14 This is a top view schematic diagram illustrating the formation of bit lines according to some embodiments of this disclosure;

[0035] Figure 15 For along Figure 14 Sectional view of AA;

[0036] Figure 16 In order to be in Figure 15 A cross-sectional schematic diagram of the first bonding layer formed on the basis of the above.

[0037] Figure 17 This is a simplified schematic diagram illustrating the distribution of internal word lines and bit lines in some embodiments of this disclosure;

[0038] Figure 18 For along Figure 17 A schematic diagram showing the unfolded section after the BB cross-section;

[0039] Figure 19 In order to be in Figure 18 A cross-sectional unfolded schematic diagram of the first bonding layer formed on the basis of the above.

[0040] Figure 20 This is a top view schematic diagram illustrating a second substrate according to some embodiments of the present disclosure;

[0041] Figure 21 For along Figure 20 A cross-sectional view of AA is shown, and a schematic diagram of the formation of a second bonding layer on the second substrate is also shown;

[0042] Figure 22 This is a schematic cross-sectional view illustrating the implantation of hydrogen ions into a second substrate to form a release layer, as shown in some embodiments of this disclosure.

[0043] Figure 23 This is a schematic cross-sectional view showing the bonding of a first semiconductor structure and a second semiconductor structure according to some embodiments of this disclosure;

[0044] Figure 24 This is a schematic cross-sectional view showing the separation of the release layer from the second substrate, as illustrated in some embodiments of this disclosure;

[0045] Figure 25 This is a simplified schematic diagram illustrating the distribution of bit lines and word lines after a third contact plug is formed on the bit line, as shown in some embodiments of this disclosure.

[0046] Figure 26 For along Figure 25 A schematic diagram showing the unfolded cross-section of the middle BB section.

[0047] Explanation of reference numerals in the attached figures:

[0048] 1. First substrate; 101. Isolation layer; 102. Active pillar; 2. Word line; 201. Word line trench; 3. Vertical transistor; 31. First terminal of vertical transistor; 32. Second terminal of vertical transistor; 33. Gate dielectric layer; 4. Memory cell; 401. First terminal of memory cell; 402. Second terminal of memory cell; 41. Upper electrode layer; 42. Capacitor dielectric layer; 43. Lower electrode layer; 44. Encapsulation layer; 5. Insulating layer; 6. Bit line ; 701, First connecting plug; 702, Second connecting plug; 8, First bonding layer; 9, Second substrate; 10, Second bonding layer; 11, Release layer; 12, Active layer; 13, Peripheral circuit; 14, Dielectric layer; 15, Interconnect structure; 151, First contact plug; 152, Second contact plug; 153, Third contact plug; 16, Via; 17, Spacer layer; X, First horizontal direction; Y, Second horizontal direction; Z, Vertical direction. Detailed Implementation

[0049] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, they are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and therefore their detailed description will be omitted.

[0050] In the following description of different exemplary embodiments of the present disclosure, reference is made to the accompanying drawings, which form part of the present disclosure and illustrate, by way of example, different exemplary structures that can implement various aspects of the present disclosure. It should be understood that other specific embodiments of components, structures, exemplary devices, systems, and steps may be used, and structural and functional modifications may be made without departing from the scope of the present disclosure. Furthermore, while the terms “above,” “between,” “within,” etc., may be used in this specification to describe different exemplary features and elements of the present disclosure, these terms are used herein only for convenience, such as according to the orientation of the examples in the drawings. Nothing in this specification should be construed as requiring a specific three-dimensional orientation of the structure to fall within the scope of the present disclosure. Moreover, the terms “first,” “second,” etc., in the claims are used only as illustrative marks and not as numerical limitations on the object.

[0051] The flowcharts shown in the accompanying drawings are merely illustrative and do not necessarily include all content and operations / steps, nor do they necessarily have to be performed in the described order. For example, some operations / steps can be broken down, while others can be combined or partially combined; therefore, the actual execution order may change depending on the specific circumstances.

[0052] In addition, in the description of this disclosure, "multiple" means at least two, such as two, three, etc., unless otherwise expressly and specifically limited.

[0053] like Figure 1 As shown, this disclosure provides a method for fabricating a memory, including the following steps S110 to S150.

[0054] S110: Form a first semiconductor structure, the first semiconductor structure including a memory array and a first bonding layer 8. The memory array includes a vertical transistor array, a memory cell array located on one side of the vertical transistor array, and multiple bit lines 6 located on the other side of the vertical transistor array. The first end 401 of multiple memory cells 4 in the memory cell array is correspondingly coupled to the first end 31 of multiple vertical transistors 3 in the vertical transistor array. The multiple bit lines 6 are correspondingly coupled to the second end 32 of multiple vertical transistors 3. The first bonding layer 8 is located on the side of the multiple bit lines 6 away from the vertical transistor array.

[0055] S120: Forming a second semiconductor structure, the second semiconductor structure including a second substrate 9, a second bonding layer 10 located on the second substrate 9, and a release layer 11 located within the second substrate 9.

[0056] S130: Bond the first bonding layer 8 and the second bonding layer 10 together to bond the first semiconductor structure and the second semiconductor structure.

[0057] S140: Separate the second substrate 9 in the release layer 11, and retain the portion of the second substrate 9 located between the release layer 11 and the second bonding layer 10 as the active layer 12.

[0058] S150: Form peripheral circuit 13 and interconnect structure 15. Peripheral circuit 13 is at least partially located in active layer 12. Interconnect structure 15 includes contact plugs that penetrate at least through active layer 12, second bonding layer 10 and first bonding layer 8. Peripheral circuit 13 is at least partially coupled to memory array through contact plugs.

[0059] In the above method of the present disclosure embodiments, the first semiconductor structure and the second semiconductor structure are bonded using the first bonding layer 8 and the second bonding layer 10, and then the peripheral circuit 13 and the interconnect structure 15 are formed on the active layer 12 of the second semiconductor structure to form a memory. Therefore, the present disclosure embodiments provide a new method for fabricating a three-dimensional memory to improve the density of the memory.

[0060] The method for fabricating the memory according to the embodiments of this disclosure will be described in detail below.

[0061] S110: Form a first semiconductor structure, the first semiconductor structure including a memory array and a first bonding layer 8. The memory array includes a vertical transistor array, a memory cell array located on one side of the vertical transistor array, and multiple bit lines 6 located on the other side of the vertical transistor array. The first end 401 of multiple memory cells 4 in the memory cell array is correspondingly coupled to the first end 31 of multiple vertical transistors 3 in the vertical transistor array. The multiple bit lines 6 are correspondingly coupled to the second end 32 of multiple vertical transistors 3. The first bonding layer 8 is located on the side of the multiple bit lines 6 away from the vertical transistor array.

[0062] In some embodiments, forming the first semiconductor structure includes the following contents A1 to A5.

[0063] A1: Provide a first substrate 1, and form a vertical transistor array on the first substrate 1.

[0064] For example, forming a vertical transistor array on the first substrate 1 includes the following contents A11 to A13.

[0065] A11: An active pillar array is formed in the first substrate 1.

[0066] like Figure 2 As shown, a first substrate 1 is provided, which is a semiconductor substrate. The substrate material can be silicon, silicon carbide, silicon-on-insulator, silicon-on-insulator, silicon-germanium-on-insulator, silicon-germanium-on-insulator, or germanium-on-insulator, etc. The substrate can also be implanted with certain dopant particles to change the electrical parameters according to design requirements. Those skilled in the art can choose according to the actual situation, and no limitation is made here.

[0067] A mask layer with an isolation layer pattern can be formed on a first substrate 1. The isolation layer pattern is transferred to the first substrate 1 to form trenches (not shown) of the isolation layer 101 in the first substrate 1. The trenches have a first trench portion extending along a first horizontal direction X and a second trench portion extending along a second horizontal direction Y to form an active pillar array including a plurality of active pillars 102. Figure 3 and Figure 4 As shown, an isolation layer 101 can be formed in the trench using a deposition process to insulate each active post 102 from other active posts 102.

[0068] In some embodiments, the material of the isolation layer 101 is an insulating material to insulate adjacent active pillars 102 from each other. The material of the isolation layer 101 may include at least one of silicon oxide, silicon nitride, and silicon oxynitride.

[0069] Wherein, the first horizontal direction X and the second horizontal direction Y are located in the same plane, and there is an angle between the first horizontal direction X and the second horizontal direction Y. The first horizontal direction X and the second horizontal direction Y may or may not be perpendicular to each other.

[0070] A12: Multiple word lines 2 are formed on the sidewalls of multiple active pillars 102 in the active pillar array, and each active pillar 102 includes a first end and a second end located on opposite sides of the corresponding word line 2.

[0071] In some embodiments, such as Figure 5 and Figure 6 As shown, word line trenches 201 can be etched in the isolation layer 101 using an etching process to form word lines 2. The depth of the word line trenches 201 is less than the height of the active pillar 102, i.e., as shown... Figure 7 and Figure 8 As shown, after word line 2 is formed in word line trench 201, word line 2 is located approximately at the center of active pillar 102 in the vertical direction Z, and is located around the active pillar 102 to form a fully encircling gate. After forming word line trench 201, the peripheral surfaces of source pillar 102 are exposed, as shown... Figure 7 and Figure 8As shown, a gate dielectric layer 33 is deposited on the surrounding surface of the active pillar 102, followed by the formation of word lines 2. After the word lines 2 are formed, in the vertical direction Z, as shown... Figure 9 As shown, an isolation layer 101 is then placed over the surface of the character line 2, such that the top surface of the isolation layer 101 is flush with the top surface of the active pillar 102. The vertical direction Z is perpendicular to both the first horizontal direction X and the second horizontal direction Y.

[0072] In some embodiments, the gate dielectric layer 33 may be made of at least one of silicon oxide, silicon nitride, and silicon oxynitride.

[0073] In some embodiments, in addition to forming the above-described all-around gate, a single-sided gate (i.e., word line 2 is located on one side of the active pillar 102) or a double-sided gate (i.e., word line 2 is located on both sides of the active pillar 102) can also be formed. Those skilled in the art can choose according to the actual situation, and will not be elaborated here.

[0074] A13: The first ends of the plurality of active pillars 102 are doped to form a first source-drain region, which serves as the first end 31 of the plurality of vertical transistors 3.

[0075] like Figure 9 As shown, the first end of the active pillar 102 is exposed. The first ends of multiple active pillars 102 are doped to form a first source / drain region. This first source / drain region can serve as either the source or drain of the vertical transistor 3. When the vertical transistor 3 is an N-type transistor, it can be doped with phosphorus (P) or arsenic (As); when it is a P-type transistor, it can be doped with boron (B) or gallium (Ga). The doping of the first end of the active pillar 102 can be performed using ion implantation or thermal diffusion processes; no specific method is used here. After the first source / drain region is formed, it can serve as the first end 31 of the vertical transistor 3.

[0076] In some embodiments, after the first source-drain region is formed, a metal silicide process can be performed on the first end 31 of the vertical transistor 3 to form a metal silicide layer on the first end 31 of the vertical transistor 3, so as to reduce the contact resistance between it and the memory cell 4 formed in subsequent processes.

[0077] A2: A memory cell array is formed on the side of the vertical transistor array away from the first substrate 1.

[0078] like Figure 10As shown, the memory cells in the memory cell array can be at least one of capacitors, phase-change memory cells, and ferroelectric memory cells. Taking a capacitor as an example, an upper electrode layer 41 can be formed on the surface of the side where the first end 31 of the vertical transistor 3 is located using a deposition process. The upper electrode layer 41 is the first end 401 of the memory cell 4 and is coupled to the first end 31 of the vertical transistor 3. A capacitor dielectric layer 42 is conformally formed on the upper electrode layer 41. Then, a lower electrode layer 43 is formed on the capacitor dielectric layer 42 and between adjacent capacitor dielectric layers 42. The lower electrode layer 43 is the second end 402 of the memory cell 4, thus forming a memory cell array. Each upper electrode layer 41, the capacitor dielectric layer 42 formed on the upper electrode layer 41, and the lower electrode layer 43 form a memory cell 4. Here, "conformally formed" can be understood as forming along the outer contour of the upper electrode layer 41.

[0079] In some embodiments, the deposition process can be at least one of chemical vapor deposition, physical vapor deposition, and atomic layer deposition.

[0080] A3: Thin the first substrate 1 from the side of the first substrate 1 away from the vertical transistor array until the second end 32 of the plurality of vertical transistors 3 is exposed.

[0081] After forming a memory cell array, such as Figure 10 As shown, the memory cell array can be encapsulated. For example, an encapsulation layer 44 can be formed on the surface of the memory cell 4. The material of the encapsulation layer 44 is an insulating material, which isolates the memory cell array from the outside world. In addition, after encapsulation, the encapsulation layer 44 can have a certain degree of rigidity to provide a certain degree of protection for the memory cell array.

[0082] After encapsulating storage unit 4, as follows Figure 11 As shown, the first semiconductor structure with a memory cell array and a vertical transistor array is inverted, such that the memory cell array is located below the vertical transistor 3. Figure 12 As shown, the first substrate 1 is thinned from the side away from the vertical transistor 3 or the memory cell array. For example, a chemical mechanical polishing process can be used to thin the first substrate 1, exposing the second ends of the multiple active pillars 102, which is equivalent to exposing the second ends 32 of the multiple vertical transistors 3. The second end 32 of the vertical transistor 3 is the end opposite to the first end 31 of the vertical transistor 3 in the vertical direction Z.

[0083] like Figure 12 As shown, after the second ends 32 of the plurality of vertical transistors 3 are exposed and before the plurality of bit lines 6 are formed, the second ends of the plurality of active pillars 102 are doped to form a second source-drain region, which serves as the second ends 32 of the plurality of vertical transistors 3.

[0084] The second source / drain region can serve as the other source or drain of the vertical transistor 3. Its doping process is the same as that of the first source / drain region, and will not be described again here.

[0085] A4: Multiple bit lines 6 are formed on the side of the second end 32 of multiple vertical transistors 3 away from the memory cell array.

[0086] like Figures 13 to 15 As shown, an insulating layer 5 can be formed on one side where the second end 32 of multiple vertical transistors 3 is located, and multiple bit lines 6 are formed in the insulating layer 5.

[0087] For example, such as Figure 13 As shown, an insulating layer 5 can be formed on one side of the second end 32 of multiple vertical transistors 3 using a deposition process. The material of the insulating layer 5 can be at least one of silicon oxide, silicon nitride, and silicon oxynitride. A mask layer with a bit line trench pattern is formed on the insulating layer 5, and the bit line trench pattern can be transferred to the insulating layer 5 using an etching process to form bit line trenches in the insulating layer 5. Figure 14 and Figure 15 As shown, bit lines 6 can be formed in bit line trenches using a deposition process. In some embodiments, the material of bit lines 6 may include at least one selected from tungsten, titanium, nickel, aluminum, and platinum.

[0088] In some embodiments, bit line 6 may extend along the second horizontal direction Y, and bit line 6 may be connected to the second end 32 of vertical transistor 3.

[0089] A5: A first bonding layer 8 is formed on the side of the multiple bit lines 6 away from the vertical transistor array.

[0090] For example, such as Figure 16 As shown, a first bonding layer 8 can be formed on the bit line 6 and the insulating layer 5 using a deposition process. The material of the first bonding layer 8 may include silicon oxide.

[0091] like Figure 17 and Figure 18 As shown, before forming the first bonding layer 8, a plurality of first connection plugs 701 and at least one second connection plug 702 are formed. The plurality of first connection plugs 701 are respectively coupled to the ends of a plurality of word lines 2, and the at least one second connection plug 702 is coupled to the second end 402 of a plurality of memory cells 4; as Figure 19 As shown, after the first bonding layer 8 is formed, a plurality of first connection plugs 701 are located between a plurality of word lines 2 and the first bonding layer 8, and at least one second connection plug 702 is located between a plurality of memory cells 4 and the first bonding layer 8.

[0092] in, Figure 18 For along Figure 17 The unfolded cross-section of BB in the diagram. Figure 19 Is Figure 18 The first bonding layer 8 formed on the basis of this cross-sectional unfolded view can more completely show the internal structure of the first semiconductor structure.

[0093] like Figure 17 As shown, the first connecting plugs 701 are formed at the ends of the plurality of word lines 2. To increase the spacing of the first connecting plugs 701 in the second horizontal direction Y and to avoid mutual interference between the first connecting plugs 701, the first connecting plugs 701 are formed at different ends of the plurality of word lines 2. For example... Figure 17 As shown, a first connecting plug 701 is formed on the end of the word line 2 on the same side of the odd-numbered sequence, and the first connecting plug 701 is formed on the end of the word line 2 on the other side of the even-numbered sequence.

[0094] S120: Forming a second semiconductor structure, the second semiconductor structure including a second substrate 9, a second bonding layer 10 located on the second substrate 9, and a release layer 11 located within the second substrate 9.

[0095] like Figures 20 to 22 As shown, S120 may include the following contents B1 to B3.

[0096] B1: Provides a second substrate 9.

[0097] like Figure 20 As shown, a second substrate 9 is provided. The second substrate 9 is a semiconductor substrate, and the material of the second substrate 9 can be the same as that of the first substrate 1, which will not be described in detail here.

[0098] B2: A second bonding layer 10 is formed on one side of the second substrate 9.

[0099] like Figure 21 As shown, a second bonding layer 10 can be formed on one side of the second substrate 9 using a deposition process. The material of the second bonding layer 10 may include silicon oxide. The material of the second bonding layer 10 can be the same as that of the first bonding layer 8, so that the material does not need to be changed during the process, simplifying the process. Moreover, the fact that the first bonding layer 8 and the second bonding layer 10 are made of the same material can promote more stable bonding between the two and increase the bonding strength.

[0100] In some embodiments, when the material of the second substrate 9 is silicon, a silicon oxide layer can also be formed on the silicon surface by thermal oxidation process, serving as the second bonding layer 10. The thickness of the formed silicon oxide layer can be controlled by adjusting parameters such as oxygen concentration, amount, and temperature. Regardless of the process used, as long as the second bonding layer 10 can be formed, no specific process is limited here.

[0101] The second bonding layer 10 is made of silicon oxide, which has a tetrahedral crystal structure, which is beneficial for the implantation of hydrogen ions in subsequent processes and improves the uniformity of implantation.

[0102] B3: Hydrogen ions are injected into the second substrate 9 from the side where the second bonding layer 10 is formed to form a release layer 11.

[0103] like Figure 22 As shown, hydrogen ions (H+) can be implanted into the side of the substrate 1 where the second bonding layer 10 is formed using an ion implantation process. + For example, by irradiating the second substrate 9 with a hydrogen ion beam, hydrogen ions are injected into the second substrate 9 through the second bonding layer 10 and are located at a certain depth to form a release layer 11.

[0104] S130: Bond the first bonding layer 8 and the second bonding layer 10 together to bond the first semiconductor structure and the second semiconductor structure.

[0105] like Figure 23 As shown, the second bonding layer 10 of the second semiconductor structure is oriented toward the first bonding layer 8 of the first semiconductor structure, and after heat treatment, the first bonding layer 8 and the second bonding layer 10 are bonded together.

[0106] After the first bonding layer 8 and the second bonding layer 10 are bonded together, a bonding interface is formed. It should be noted that the bonding interface is not just an interface that distinguishes the first bonding layer 8 and the second bonding layer 10. The bonding interface can have a certain thickness, and the first bonding layer 8 and the second bonding layer 10 are bonded at the bonding interface.

[0107] S140: Separate the second substrate 9 in the release layer 11, and retain the portion of the second substrate 9 located between the release layer 11 and the second bonding layer 10 as the active layer 12.

[0108] like Figure 24 As shown, separating the second substrate 9 in the release layer 11 includes heating the second substrate 9 so that the second substrate 9 is separated from the release layer 11.

[0109] For example, hydrogen ions are implanted into the second substrate 9 to form a release layer 11, and the release layer 11 is separated from the second substrate 9 by heating (or annealing).

[0110] After separating the release layer 11 from the second substrate 9, the portion of the second substrate 9 originally located between the release layer 11 and the second bonding layer 10 is retained. This retained portion of the second substrate 9 can serve as the active layer 12. The surface of the active layer 12 is polished to make it smooth and flat, which facilitates the subsequent formation of the peripheral circuit 13 and improves the electrical performance of the peripheral circuit 13.

[0111] S150: Form peripheral circuit 13 and interconnect structure 15. Peripheral circuit 13 is at least partially located in active layer 12. Interconnect structure 15 includes contact plugs that penetrate at least through active layer 12, second bonding layer 10 and first bonding layer 8. Peripheral circuit 13 is at least partially coupled to memory array through contact plugs.

[0112] For example, forming the peripheral circuit 13 and the interconnection structure 15 may include the following contents C1 to C3.

[0113] C1: External circuit 13 is formed on the active layer 12.

[0114] Peripheral circuitry 13 may include any suitable digital, analog, and / or mixed-signal circuitry for facilitating the operation of the memory cell array. For example, peripheral circuitry 13 may include one or more of the following: page buffers, decoders, sense amplifiers, drivers, input / output circuitry, charge pumps, voltage sources or generators, any portion (e.g., sub-circuits) of the aforementioned functional circuitry, or any active or passive component (e.g., transistors, diodes, resistors, or capacitors). Peripheral circuitry 13 may be implemented using complementary metal-oxide-semiconductor (CMOS) technology.

[0115] C2: Forms a dielectric layer 14 covering the active layer 12 and the peripheral circuit 13.

[0116] like Figure 26 As shown, a dielectric layer 14 can be formed between the active layer 12 and the peripheral circuit 13 using a deposition process. The dielectric layer 14 serves as an insulator, preventing short circuits in the multiple circuits within the peripheral circuit 13. In some embodiments, the material of the dielectric layer 14 may include at least one of silicon oxide, silicon nitride, and silicon oxynitride.

[0117] C3: Form an interconnect structure 15, the interconnect structure 15 includes contact plugs penetrating the dielectric layer 14, the active layer 12, the second bonding layer 10 and the first bonding layer 8, the contact plugs include a plurality of first contact plugs 151 corresponding to a plurality of first connection plugs 701, at least one second contact plug 152 corresponding to at least one second connection plug 702, and a plurality of third contact plugs 153 corresponding to a plurality of bit lines 6.

[0118] Before forming the interconnect structure 15, such as Figure 26 As shown, a via 16 can be formed that penetrates the dielectric layer 14, the active layer 12, the second bonding layer 10, and the first bonding layer 8. A spacer layer 17 is formed at least on the inner wall of the via 16 penetrating the active layer 12, and a contact plug is filled in the via 16. The spacer layer 17 is located at least between the inner wall of the via 16 of the active layer 12 and the contact plug.

[0119] For example, after forming via 16, a spacer layer 17 can be formed on the inner wall of via 16 using a deposition process. In some embodiments, the material of the spacer layer 17 can be at least one of silicon oxide, silicon nitride, and silicon oxynitride, i.e., the material of the spacer layer 17 is an insulating material, thereby preventing the contact plug from directly contacting the active layer 12 and causing a short circuit with other circuits. Alternatively, the spacer layer 17 can be formed only in the via 16 that penetrates the active layer 12 to save material.

[0120] like Figure 25 and Figure 26 As shown, contact plugs can be formed in vias 16 using a deposition process. The first contact plug 151 is coupled to the first connection plug 701, enabling electrical connection between the peripheral circuit 13 and multiple word lines 2. The second contact plug 152 is coupled to the second connection plug 702, enabling electrical connection between the peripheral circuit 13 and the memory cell 4. The third contact plug 153 is coupled to the bit line 6, enabling electrical connection between the peripheral circuit 13 and the bit line 6. In some embodiments, the third contact plug 153 is coupled to the middle of the bit line 6, which can improve the read / write performance of the memory cell.

[0121] In some embodiments, such as Figure 26 The first contact plug 151, the second contact plug 152, and the third contact plug 153 shown may be formed in segments. Figure 26 Taking the third contact plug 153 as an example, after forming the first bonding layer 8, a first via can be formed at a corresponding position of the first bonding layer 8, and a portion of the third contact plug 153 can be formed in the first via. After forming the second bonding layer 10 on the second substrate 9, a second via can be formed at the position of the second bonding layer 10 and the second substrate 9 corresponding to the first via, and another portion of the third contact plug 153 can be formed in the second via. After forming the dielectric layer 14, a third via corresponding to the second via is formed in the dielectric layer 14, and the remaining portion of the third contact plug 153 is formed in the third via. Of course, it is also possible that after the first semiconductor structure and the second semiconductor structure are bonded, and after the peripheral circuit 13 and the dielectric layer 14 are formed on the active layer 12 of the second semiconductor structure, a via can be directly drilled from the dielectric layer 14 into the first semiconductor structure, and then a conductive material is filled into the via to form the third contact plug 153. The first contact plug 151 and the second contact plug 152 can be formed in the same way as the third contact plug 153, that is, they can be formed in segments or formed by drilling and filling at one time. No special limitation is made here.

[0122] In summary, the embodiments of this disclosure utilize the first bonding layer 8 and the second bonding layer 10 to bond the first semiconductor structure and the second semiconductor structure, and then form the peripheral circuit 13 and the interconnect structure 15 on the active layer 12 of the second semiconductor structure to form a memory. Therefore, the embodiments of this disclosure provide a new method for fabricating a three-dimensional memory to improve the density of the memory.

[0123] This disclosure also provides a memory, such as... Figure 26 As shown, the memory includes a storage array, a first bonding layer 8, a second bonding layer 10, an active layer 12, peripheral circuitry 13, and an interconnect structure 15.

[0124] The memory array includes a vertical transistor array, a memory cell array on one side of the vertical transistor array, and multiple bit lines 6 on the other side of the vertical transistor array. The first end 401 of multiple memory cells 4 in the memory cell array is correspondingly coupled to the first end 31 of multiple vertical transistors 3 in the vertical transistor array, and the multiple bit lines 6 are correspondingly coupled to the second end 32 of multiple vertical transistors 3.

[0125] The first bonding layer 8 is located on the side of the multiple bit lines 6 away from the vertical transistor array. The second bonding layer 10 is located on the side of the first bonding layer 8 away from the multiple bit lines 6, and the first bonding layer 8 is bonded to the second bonding layer 10. That is, the first bonding layer 8 and the second bonding layer 10 are bonded together. The active layer 12 is located on the side of the second bonding layer 10 away from the first bonding layer 8. The peripheral circuitry 13 is at least partially located in the active layer 12, and the interconnect structure 15 includes contact plugs that penetrate at least through the active layer 12, the second bonding layer 10, and the first bonding layer 8. The peripheral circuitry 13 is coupled to the memory array through the interconnect structure 15.

[0126] In some embodiments, the memory further includes multiple word lines 2, multiple first connection plugs 701, and at least one second connection plug 702. The multiple word lines 2 are correspondingly coupled to multiple vertical transistors 3. The multiple first connection plugs 701 are located between the multiple word lines 2 and the first bonding layer 8, and are respectively coupled to the ends of the multiple word lines 2. The second connection plugs 702 are located between multiple memory cells 4 and the first bonding layer 8, and are coupled to the second ends 402 of the multiple memory cells 4.

[0127] In some embodiments, the contact plugs include a plurality of first contact plugs 151 and at least one second contact plug 152. The plurality of first contact plugs 151 are correspondingly coupled to a plurality of first connection plugs 701 to realize electrical connection between the peripheral circuit 13 and a plurality of word lines 2, and the at least one second contact plug 152 is correspondingly coupled to at least one second connection plug 702 to realize electrical connection between the peripheral circuit 13 and the memory cell 4.

[0128] In some embodiments, the storage unit 4 includes one of a capacitor, a phase change storage unit, and a ferroelectric storage unit.

[0129] The memory in this embodiment of the present disclosure can increase density and increase storage capacity.

[0130] It should be understood that this disclosure is not limited to the detailed structure and arrangement of the components presented in this specification. This disclosure is capable of other embodiments and can be implemented and performed in various ways. The foregoing variations and modifications fall within the scope of this disclosure. It should be understood that this disclosure, as disclosed and defined in this specification, extends to all alternative combinations of two or more individual features mentioned or apparent in the text and / or drawings. All these different combinations constitute multiple alternative aspects of this disclosure. The embodiments described in this specification illustrate the best known mode for implementing this disclosure and will enable those skilled in the art to adopt this disclosure.

Claims

1. A method for fabricating a memory, characterized in that, include: A first semiconductor structure is formed, the first semiconductor structure including a memory array and a first bonding layer. The memory array includes a vertical transistor array, a memory cell array located on one side of the vertical transistor array, and multiple bit lines located on the other side of the vertical transistor array. The first ends of multiple memory cells in the memory cell array are correspondingly coupled to the first ends of multiple vertical transistors in the vertical transistor array. The multiple bit lines are correspondingly coupled to the second ends of the multiple vertical transistors. The first bonding layer is located on the side of the multiple bit lines away from the vertical transistor array. A second semiconductor structure is formed, the second semiconductor structure including a second substrate, a second bonding layer located on the second substrate, and a release layer located within the second substrate; The first bonding layer and the second bonding layer are bonded together to bond the first semiconductor structure and the second semiconductor structure; The second substrate is separated in the release layer, and the portion of the second substrate located between the release layer and the second bonding layer is retained as an active layer; A peripheral circuit and interconnect structure are formed, wherein the peripheral circuit is at least partially located in the active layer, and the interconnect structure includes a contact plug that penetrates at least through the active layer, the second bonding layer and the first bonding layer, and the peripheral circuit is at least partially coupled to the memory array through the contact plug.

2. The method according to claim 1, characterized in that, Forming the first semiconductor structure includes: A first substrate is provided, and the vertical transistor array is formed on the first substrate; The memory cell array is formed on the side of the vertical transistor array away from the first substrate; The first substrate is thinned from the side of the first substrate away from the vertical transistor array until the second ends of the plurality of vertical transistors are exposed; The plurality of bit lines are formed on the side of the second end of the plurality of vertical transistors away from the memory cell array; The first bonding layer is formed on the side of the plurality of bit lines away from the vertical transistor array.

3. The method according to claim 2, characterized in that, Forming the vertical transistor array on the first substrate includes: An active pillar array is formed in the first substrate; Multiple word lines are formed on the sidewalls of multiple active columns in the active column array, and each active column includes a first end and a second end located on opposite sides of the corresponding word line; The first ends of the plurality of active pillars are doped to form a first source / drain region, the first source / drain region serving as the first end of the plurality of vertical transistors; and After exposing the second ends of the plurality of vertical transistors and before forming the plurality of bit lines, the second ends of the plurality of active pillars are doped to form a second source-drain region, which serves as the second end of the plurality of vertical transistors.

4. The method according to claim 3, characterized in that, Also includes: Before forming the first bonding layer, a plurality of first connection plugs and at least one second connection plug are formed. The plurality of first connection plugs are respectively coupled to the ends of the plurality of word lines, and the at least one second connection plug is coupled to the second end of the plurality of memory cells. Wherein, after the first bonding layer is formed, the plurality of first connection plugs are located between the plurality of word lines and the first bonding layer, and the at least one second connection plug is located between the plurality of memory cells and the first bonding layer.

5. The method according to claim 4, characterized in that, The formation of the peripheral circuit and the interconnection structure includes: The peripheral circuit is formed on the active layer; A dielectric layer is formed covering the active layer and the peripheral circuitry; The interconnect structure is formed, the interconnect structure includes contact plugs that penetrate the dielectric layer, the active layer, the second bonding layer and the first bonding layer, the contact plugs include a plurality of first contact plugs corresponding to the plurality of first connection plugs, at least one second contact plug corresponding to the at least one second connection plug, and a plurality of third contact plugs corresponding to the plurality of bit lines.

6. The method according to claim 5, characterized in that, Forming the interconnect structure includes: Before forming the contact plug, a via is formed through the dielectric layer, the active layer, the second bonding layer, and the first bonding layer; A spacer layer is formed at least on the inner wall of the via penetrating the active layer; The contact plug is filled in the via, and the spacer layer is located at least between the inner wall of the via of the active layer and the contact plug.

7. The method according to claim 2, characterized in that, The plurality of bit lines are formed on the side of the second end of the plurality of vertical transistors away from the memory cell array, including: An insulating layer is formed on one side where the second ends of the plurality of vertical transistors are located; The plurality of bit lines are formed in the insulating layer.

8. The method according to any one of claims 1 to 7, characterized in that, Forming the second semiconductor structure includes: Provide the second substrate; The second bonding layer is formed on one side of the second substrate; Hydrogen ions are injected into the second substrate from the side where the second bonding layer is formed to form the release layer; Separating the second substrate from the release layer includes: The second substrate is heated so that it separates from the release layer.

9. A memory, characterized in that, include: A memory array, comprising a vertical transistor array, a memory cell array located on one side of the vertical transistor array, and multiple bit lines located on the other side of the vertical transistor array, wherein the first ends of multiple memory cells in the memory cell array are correspondingly coupled to the first ends of multiple vertical transistors in the vertical transistor array, and the multiple bit lines are correspondingly coupled to the second ends of the multiple vertical transistors. The first bonding layer is located on the side of the multiple bit lines away from the vertical transistor array; The second bonding layer is located on the side of the first bonding layer away from the multiple bit lines and is bonded to the first bonding layer. The active layer is located on the side of the second bonding layer away from the first bonding layer; The peripheral circuitry and interconnect structure are at least partially located in the active layer, and the interconnect structure includes contact plugs that penetrate at least through the active layer, the second bonding layer, and the first bonding layer, and the peripheral circuitry is at least partially coupled to the memory array through the contact plugs.

10. The memory according to claim 9, characterized in that, Also includes: Multiple word lines are coupled to the multiple vertical transistors; Multiple first connection plugs are located between the multiple word lines and the first bonding layer, and are respectively coupled to the ends of the multiple word lines; At least one second connection plug is located between the plurality of memory cells and the first bonding layer and is coupled to a second end of the plurality of memory cells.

11. The memory according to claim 10, characterized in that, The contact plug includes: A plurality of first contact plugs are coupled to the plurality of first connecting plugs; At least one second contact plug is coupled to the at least one second connecting plug; Multiple third contact plugs are coupled to the middle of the multiple bit lines.

12. The memory according to claim 9, characterized in that, The storage unit includes one of a capacitor, a phase change storage unit, and a ferroelectric storage unit.

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