Display hot plug detection circuit, working method, integrated circuit and electronic device

Abstract

This application provides a display hot-plug detection circuit, operating method, integrated circuit, and electronic device, relating to the field of display interface technology. A display hot-plug detection circuit includes: a main control module, which receives a first control signal from the display, generates a first detection signal based on the first control signal, and outputs the first detection signal to the display interface; and a delay control module, which receives a second control signal from the display, generates a second detection signal based on the second control signal, sets the second detection signal to a high level, and outputs the second detection signal to the display interface. According to embodiments of this application, the software latency of the display can be effectively shortened, and the hot-plug detection signal can be set to a high level as early as possible.

Description

Technical Field

[0001] This application relates to the field of display interface technology, and more specifically, to a display hot-plug detection circuit, operating method, integrated circuit, and electronic device. Background Technology

[0002] Currently, the monitor's hot-plug detection circuitry controls the level of the Hot Plug Detect (HPD) signal to be high or low via a control signal. When the HPD signal is high, the monitor displays the Basic Input / Output System (BIOS) screen normally.

[0003] When the computer host and monitor share the same power system, after the computer host starts up, the BIOS needs to configure the graphics card output, but at this time the graphics card driver has not yet been loaded. At the DisplayPort monitor interface output interface, the BIOS cannot perform interrupt handling, and therefore cannot respond to changes in the monitor interface's status. The DisplayPort monitor interface also cannot immediately set the HPD signal to a high level, causing the computer host to fail to output the BIOS screen to the monitor.

[0004] Due to the different architectures of power supply systems and displays, there are hardware delays in the power supply system and software delays in the display. If these hardware and software delays are prolonged, the aforementioned problems will occur. Since there is limited room for improvement in the hardware delay of the power supply system, and the cost of improvement is high, the commonly used solution is to minimize the software delay of the display. This is generally achieved by optimizing the software initialization process and adjusting the timing control of submodules. However, these methods are cumbersome and require repeated verification. Summary of the Invention

[0005] This application provides a display hot-plug detection circuit, working method, integrated circuit and electronic device. By adding a delay control circuit to improve the HPD control circuit, the cumbersome software improvement in the prior art can be effectively avoided, and the HPD signal can be set to high level as early as possible to realize the normal display of the BIOS screen.

[0006] According to one aspect of this application, a display hot-plug detection circuit is provided, comprising: a main control module, which receives a first control signal from the display, generates a first detection signal based on the first control signal, and outputs the first detection signal to the display interface; and a delay control module, which receives a second control signal from the display, generates a second detection signal based on the second control signal, sets the second detection signal to a high level, and outputs the second detection signal to the display interface.

[0007] According to some embodiments, the first control signal and the second control signal are issued simultaneously after the display receives power; the first control signal and the second control signal are both at a low level before the first detection signal is set to a high level; the first control signal and the second control signal are both at a high level after the first detection signal is set to a high level; and the second control signal remains at a high level after the first detection signal is set to a high level.

[0008] According to some embodiments, the delay control module operates when both the first control signal and the second control signal are at a low level; the delay control module is turned off when both the first control signal and the second control signal are at a high level.

[0009] According to some embodiments, the main control module includes a first resistor, a third resistor, and a first access port, wherein the first access port is electrically connected to the HPD receive pin of the display interface through the third resistor and receives the first control signal; the first resistor is grounded, and the HPD receive pin of the display interface is grounded through the first resistor.

[0010] According to some embodiments, the delay control module includes a first switch submodule and a second switch submodule, wherein the first switch submodule and the second switch submodule are electrically connected.

[0011] According to some embodiments, the first switching submodule includes a power supply, a first MOS switch, a first switching transistor, a second resistor, a fifth resistor, a sixth resistor, and a second access port. The second access port is electrically connected to the base of the first switching transistor via the sixth resistor and receives the second control signal. The base of the first switching transistor serves as the control port of the first switching transistor and is grounded via the fifth resistor. The emitter of the first switching transistor serves as the input port of the first switching transistor and is electrically connected to the drain of the first MOS switch. The collector of the first switching transistor serves as the output port of the first switching transistor and is electrically connected to the display interface via the second resistor. The source of the first MOS switch is electrically connected to the power supply, and the gate of the first MOS switch is electrically connected to the collector of the second switching transistor of the second switching submodule.

[0012] According to some embodiments, the first MOS switch is in the off state, and the emitter of the first switch is reverse biased, so that the first switch is in the off state; the first MOS switch is in the saturated conduction state and the second control signal is low, the emitter of the first switch is forward biased, and the second resistor, the fifth resistor, and the sixth resistor are adjusted to make the first switch in the conduction state, so that the delay control module sets the second detection signal to high based on the second control signal; the first MOS switch is in the saturated conduction state and the second control signal is high, and the emitter of the first switch is reverse biased, so that the first switch is in the off state.

[0013] According to some embodiments, the second switching submodule includes a power supply, a fourth resistor, a seventh resistor, an eighth resistor, a second switching transistor, a first capacitor, and a second capacitor. The base of the second switching transistor is grounded through the first capacitor and the fourth resistor, respectively, and the base of the second switching transistor serves as its control port. The collector of the second switching transistor serves as its output port, and the collector of the second switching transistor is electrically connected to the gate of the first MOS switching transistor of the first switching submodule. The emitter of the second switching transistor is grounded and connected to the power supply and the source of the first MOS switching transistor of the first switching submodule through the second capacitor, respectively. The power supply is electrically connected to the collector of the second switching transistor through the eighth resistor and to the base of the second switching transistor through the seventh resistor.

[0014] According to some embodiments, the second switch is in the off state, causing the first MOS switch to be in the off state; the second switch is in the saturated conduction state, causing the first MOS switch to be in the conduction state; the conduction duration of the second switch is controlled by the control port of the second switch, and the working duration of the delay control module is controlled by the conduction duration of the second switch.

[0015] According to some embodiments, the operating duration of the delay control module includes: the time after the display receives power, during which the delay control module sets the second detection signal to a high level; and the time from when the second detection signal is set to a high level to when the first detection signal is set to a high level.

[0016] According to one aspect of this application, a method for operating a display hot-plug detection circuit is provided. The circuit includes a main control module and a delay control module, comprising: determining the operating state of the delay control module based on the level of a first control signal and / or a second control signal emitted by the display; when the delay control module is in the operating state, controlling the delay control module to generate a second detection signal based on the second control signal and output it; when the delay control module is in the off state, controlling the main control module to generate a first detection signal based on the first control signal and output it.

[0017] According to some embodiments, when the delay control module is in operation, the delay control module sets the level of the second detection signal to a high level; when the delay control module is off, the main control module sets the level of the first detection signal to a high level.

[0018] According to some embodiments, when the delay control module is in operation, controlling the delay control module to generate and output a second detection signal based on the second control signal emitted by the display includes: adjusting the resistance value of at least one resistor in the delay control module so that the delay control module is in a saturated conduction state; generating the second detection signal and outputting the second detection signal; and adjusting the capacitor in the delay control module to control the operating duration of the delay control module.

[0019] According to one aspect of this application, an integrated circuit is provided, including the hot-plug detection circuit as described above.

[0020] According to one aspect of this application, an electronic device is provided, including a hot-plug detection circuit as described above or an integrated circuit as described above.

[0021] According to the embodiments of this application, while ensuring effective communication between the computer host and the DisplayPort monitor, the monitor software latency can be shortened as much as possible, and the HPD signal can be set to high level as early as possible, effectively solving the problem of the BIOS screen not displaying properly.

[0022] It should be understood that the above general description and the following detailed description are merely exemplary and do not limit this application. Attached Figure Description

[0023] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application.

[0024] Figure 1 The timing diagram of the power signal and hot-plug detection signal in the prior art is shown.

[0025] Figure 2 A circuit diagram of a display hot-plug detection circuit according to a first embodiment of this application is shown.

[0026] Figure 3 A circuit diagram of a display hot-plug detection circuit according to a second embodiment of this application is shown.

[0027] Figure 4 A timing diagram of hot-plug detection signals according to an embodiment of this application is shown.

[0028] Figure 5 A flowchart illustrating the operation of a display hot-plug detection circuit according to an embodiment of this application is shown.

[0029] Figure 6 A block diagram of an electronic device according to an example embodiment of this application is shown. Detailed Implementation

[0030] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, they are provided so that this application will be thorough and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar parts, and therefore repeated descriptions of them will be omitted.

[0031] The described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. Numerous specific details are provided in the following description to give a full understanding of embodiments of this application. However, those skilled in the art will recognize that the technical solutions of this application can be practiced without one or more of these specific details, or other methods, components, materials, apparatus, or operations may be employed. In these cases, well-known structures, methods, apparatuses, implementations, materials, or operations will not be shown or described in detail.

[0032] The flowcharts shown in the accompanying drawings are merely illustrative and do not necessarily include all content and operations / steps, nor do they necessarily have to be performed in the described order. For example, some operations / steps can be broken down, while others can be combined or partially combined; therefore, the actual execution order may change depending on the specific circumstances.

[0033] The terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish different objects, not to describe a specific order. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or apparatuses.

[0034] This application provides a hot-plug detection circuit, operating method, integrated circuit, and electronic device for a display. It adds a hot-plug detection signal delay control circuit to a DisplayPort display, which can effectively adjust and shorten the display software delay, and set the hot-plug detection signal to a high level as early as possible, so that the BIOS screen can be displayed normally.

[0035] The following description, with reference to the accompanying drawings, details a display hot-plug detection circuit, operating method, integrated circuit, and electronic device according to embodiments of this application.

[0036] Figure 1 The timing diagram of the power signal and hot-plug detection signal in the prior art is shown.

[0037] like Figure 1 As shown, 10 represents the signal that the power system supplies power to the computer host, including the BIOS startup phase 11 and the operating system startup phase 12.

[0038] 20 is the power supply signal for the power system to supply power to the display using the DisplayPort interface, including the initialization period 21 for each display module and the timing control period 22 for each module.

[0039] 40 is the Display Hot-Plug Detection (HPD) signal.

[0040] T1 represents the hardware latency of the power supply system, including the time difference T between the computer host and the external power supply to the monitor providing output. EPS (External Power Supply, EPS), and the display AC / DC voltage conversion module perform AC / DC voltage conversion, and provide the converted DC voltage to the display control module within a time difference T. IPS (Internal Power Supply, IPS), i.e., the hardware delay of the power supply system T1 = T EPS +T IPS .

[0041] T2 is the display software delay, which is the time period during which the display completes the initialization of each module and the timing control of each module before the display control module drives the HPD signal.

[0042] After the computer host receives power from the power supply system, signal 10 becomes high. After the power supply system's hardware delay T1, the computer host starts the BIOS and outputs the BIOS screen. After the BIOS starts, the operating system starts and outputs the operating system screen.

[0043] After the display receives power from the power system, signal 20 becomes high after a hardware delay T1 in the power system. The display then begins to initialize and control the timing of each module in sequence, and the duration of this process is the display software delay T2.

[0044] The display control module outputs a control signal to control the HPD circuit to generate and output HPD signal 40. When the display starts initializing each module, the level of HPD signal 40 is the same as the level of the control signal, both being low.

[0045] After the monitor software delay T2, that is, after the monitor completes the initialization and timing control of each module, the HPD signal 40 is set to a high level by the control signal through the HPD line, and the monitor begins to receive and display the BIOS screen and operating system screen output by the computer host in sequence.

[0046] The presence of hardware delay T1 in the power supply system and software delay T2 in the monitor prevents the monitor from displaying the BIOS screen correctly.

[0047] Figure 2 A circuit diagram of a display hot-plug detection circuit according to a first embodiment of this application is shown.

[0048] like Figure 2 As shown, a display hot-plug detection circuit according to the first embodiment of this application includes a display interface (such as DisplayPort) 100, a main control module 200 and a delay control module 300, and the display interface 100, the main control module 200 and the delay control module 300 are all located on the display side.

[0049] The display interface 100 includes an HPD receive pin 18 for receiving a first detection signal output by the main control module 200 or a second detection signal output by the delay control module 300.

[0050] According to some embodiments, the display interface 100 receives a first detection signal or a second detection signal through the HPD receiving pin 18 and transmits the first detection signal or the second detection signal to the computer host. The computer host determines whether to output the BIOS screen to the display based on the level of the first detection signal or the second detection signal.

[0051] Generally, when the level of the first detection signal or the second detection signal is high, the monitor displays the BIOS screen; when the level of the first detection signal or the second detection signal is low, the monitor does not display the BIOS screen.

[0052] The main control module 200 includes resistors R1 and R3 and an access port for the first control signal.

[0053] The access port for the first control signal is electrically connected to the HPD receive pin 18 of the display interface 100 through resistor R3, and receives the first control signal.

[0054] One end of resistor R1 is electrically connected to HPD receiver pin 18, and the other end is grounded.

[0055] According to some embodiments, the first control signal is output by the display control module. When the level of the first control signal is high, the timing of the first detection signal generated and output by the main control module 100 is the same as that of the first control signal.

[0056] The delay control module 300 includes a first switch submodule and a second switch submodule, and the first switch submodule and the second switch submodule are electrically connected.

[0057] The first switch submodule includes a power supply (VDD_DP 3V3), a first MOS switch U1, a first switch Q1, resistors R2, R5, and R6, and an access port for the second control signal.

[0058] The second switching submodule includes a power supply (VDD_DP 3V3), a second switching transistor Q2, resistors R4, R7, and R8, and capacitors C1 and C2.

[0059] In the first switch submodule, the access port for the second control signal is connected to the base B of the first switch transistor Q1 through resistor R6, and is used to receive the second control signal.

[0060] According to some embodiments, both the first control signal and the second control signal are output by the display control module, and the level of the first control signal and the level of the second control signal are both low or high.

[0061] When both the first control signal and the second control signal are at a low level, the delay control module 300 operates, and the HPD receiving pin 18 receives the second detection signal output through the first switch submodule.

[0062] When the first control signal and the second control signal are both high, the delay control module 300 is turned off, and the HPD receiving pin 18 receives the first detection signal output by the main control module 200.

[0063] The base B of the first switching transistor Q1 serves as the control port of the first switching transistor Q1 and is grounded through resistor R5.

[0064] The emitter E of the first switch Q1 serves as the input port of the first switch Q1 and is connected to the drain D of the first MOS switch U1.

[0065] The collector C of the first switching transistor Q1 serves as the output port of the first switching transistor Q1 and is electrically connected to the HPD receiving pin 18 of the display interface 100 through resistor R2. The delay control module 300 outputs the second detection signal to the display interface 100 through the output port of the first switching transistor Q1.

[0066] The gate G of the first MOS switch U1 is electrically connected to the collector C of the second switch Q2.

[0067] The source S of the first MOS switch U1 is connected to the power supply, and is connected to the emitter E of the second switch Q2 through capacitor C2.

[0068] The drain D of the first MOS switch U1 is connected to the input port (i.e. the emitter E of the first MOS switch Q1).

[0069] According to some embodiments, the first MOS switch U1 is a P-channel MOS transistor, including a cutoff state and a saturated conduction state.

[0070] When the first MOS switch U1 is in the off state, the emitter of the first switch Q1 is reverse biased, so that the first switch Q1 is in the off state.

[0071] When the first MOS switch U1 is in saturation conduction state, the first switch Q1 is in conduction or cutoff state according to the low or high level of the second control signal.

[0072] When the first MOS switch U1 is in saturation and the level of the second control signal is low, the emitter of the first switch Q1 is forward biased. By adjusting the resistance values ​​of resistors R2, R5 and R6, the collector of the first switch Q1 is forward biased, and the first switch Q1 is in the conducting state, and the delay control module 300 works.

[0073] When the first MOS switch U1 is in a saturated conduction state and the level of the second control signal is high, the emitter of the first switch Q1 is reverse biased, causing the first switch Q1 to be in a cut-off state, and the delay control module 300 is turned off.

[0074] Furthermore, in the working state, the delay control module 300 sets the level of the second detection signal to a high level based on the second control signal.

[0075] For example, the emitter turn-on voltage U of the first switch Q1 BE(sat) The voltage is 0.7V, the DC amplification factor β = 100, and the saturation voltage U CE(sat) The voltage is 0.4V, resistors R2 = 10KΩ, R5 = 20KΩ, R6 = 1KΩ, R3 = 100Ω, R1 = 100KΩ, the power supply (VDD_DP3V3) voltage is 3.3V, and the saturation on-resistance of the first MOS switch U1 is R. DS(on) =80mΩ, because R DS(on) It is small and can be ignored.

[0076] The second control signal has a high level of +3.3V and a low level of 0V. When the level of the second control signal is high, the emitter of the first switch Q1 is reverse biased, so the first switch Q1 is turned off, and the main control module 200 line is not affected by the delay control module 300 line.

[0077] When the level of the second control signal is low, the base current of the first switching transistor Q1...

[0078] I B1 =(VDD_DP3V3-U BE(sat) ) / (R5 / / R6)≈(3.3-0.7) / 1000=2.6mA.

[0079] Assuming the first switch Q1 is in saturation, then

[0080] I C1 / β=(VDD_DP3V3-U CE(sat) ) / [(R2+R1 / / R3)β]≈(3.3-0.4) / (10Kx100)=2.9uA,I C1 / β B1 If the assumption is true, the first switch Q1 is in a saturated conduction state, the delay control module 300 is working, and the level of the second detection signal is set to a high level by the delay control module 300 line.

[0081] In the second switch submodule, the base B of the second switch transistor Q2 serves as the control port of the second switch transistor Q2. It is connected to the power supply through resistor R7 and grounded through capacitor C1 and resistor R4 respectively.

[0082] The emitter E of the second switch Q2 is grounded and connected to the power supply and the source S of the first MOS switch U1 in the first switch submodule through capacitor C2.

[0083] The collector C of the second switch Q2 serves as the output port of the second switch Q2 and is connected to the power supply through resistor R8. The collector C of the second switch Q2 is also electrically connected to the gate G of the first MOS switch U1 in the first switch submodule.​

[0084] According to some embodiments, the state of the second switch Q2 includes a cut-off state and a saturated conduction state.

[0085] When the second switch Q2 is in the off state, the output port (collector C) of the second switch Q2 controls the gate G of the first MOS switch U1, and the voltage U at the electrode of the first MOS switch U1... GS >U GSth The first MOS switch U1 is in the off state.

[0086] When the second switch Q2 is in saturation conduction state, the output port (collector C) of the second switch Q2 controls the gate G of the first MOS switch U1, and the voltage U at the electrode of the first MOS switch U1... GS GSth The first MOS switch U1 is in the on state.

[0087] Furthermore, the conduction duration of the second switch Q2 can be controlled by adjusting the control port of the second switch Q2, thereby controlling the working duration of the delay control module 300.

[0088] For example, the emitter turn-on voltage U of the second switch Q2 BE(sat) The voltage is 0.7V, the DC amplification factor β = 100, and the saturation voltage U CE(sat) The voltage is 0.4V, resistor R4 = 20KΩ, resistor R7 = 10KΩ, capacitor C1 = 10uF, resistor R8 = 100KΩ, capacitor C2 = 0.1uF, and the threshold voltage U of the first MOS switch U1 is 0.4V. GSth = -0.8V.

[0089] Let V0 be the initial voltage value of capacitor C1, and V1 be the final voltage value that capacitor C1 can be charged to. t Let be the voltage value of capacitor C1 at time t.

[0090] V0=0V, V1=VDD_DP3V3*R4 / (R4+R7)=3.3*20K / (20K+10K)=2.2V, V t =U BE(sat) =0.7V,

[0091] Therefore, t=(R4 / / R7)*C1*Ln[(V1-V0) / (V1-V t The base current of the second switching transistor Q2 is approximately 6.67K * 10uF * Ln[2.2 / (2.2-0.7)] ≈ 6.67K * 10uF * 0.39 = 26ms. This means that the emitter of Q2 turns on approximately 26ms later.

[0092] I B2 ​=(VDD_DP3V3-U BE(sat) ) / R7-U BE(sat) / R4=(3.3-0.7) / 10K-0.7 / 20K=0.26mA-0.035mA=0.225mA.

[0093] Assuming the second switch Q2 is in saturation conduction state, then

[0094] I C2 / β=(VDD_DP3V3-U CE(sat) ) / (R8*β)=(3.3-0.4) / (100K*100)=0.29uA, I C2 / β B2 If the assumption is true, the second switch Q2 is in a saturated conduction state.

[0095] When the second switch Q2 is in saturation conduction state, the U of the first MOS switch U1 GS =(0.4V-3.3V)=-2.9V GSth The first MOS switch U1 is in the on state.

[0096] According to an embodiment of this application, the value of capacitor C1 can be adjusted to change t, thereby changing the conduction time of the second switch Q2, and realizing the function of controlling the working time of the delay control module 300.

[0097] Figure 3 A circuit diagram of a display hot-plug detection circuit according to a second embodiment of this application is shown.

[0098] like Figure 3 As shown, a display hot-plug detection circuit according to a second embodiment of this application includes a display interface 100, a main control module 200, and a delay control module 300', and the display interface 100, the main control module 200, and the delay control module 300' are all located on the display side.

[0099] The display interface 100 and main control module 200 in the second embodiment have the same composition and connection method as those in the first embodiment, and will not be described again here.

[0100] The delay control module 300' in the second embodiment includes a third switch submodule and a fourth switch submodule, and the third switch submodule and the fourth switch submodule are electrically connected.

[0101] The third switch submodule includes a power supply (VDD_DP 3V3), a first MOS switch U1, a third MOS switch U3, resistors R10, R11, and R14, and an access port for the second control signal. ​​

[0102] The fourth switch submodule includes a power supply (VDD_DP 3V3), a second MOS switch U2, resistors R9, R12, and R13, and capacitors C3 and C4.

[0103] In the third switch submodule, the access port for the second control signal is connected to the gate G of the third MOS switch U3 through resistor R10, and is used to receive the second control signal.

[0104] The gate G of the third MOS switch U3 serves as the control port of the third MOS switch U3 and is grounded through resistor R11.

[0105] The source S of the third MOS switch U3 serves as the input port of the third MOS switch U3 and is connected to the drain D of the first MOS switch U1.

[0106] The drain D of the third MOS switch U3 serves as the output port of the third MOS switch U3. It is electrically connected to the HPD receiver pin 18 of the display interface 100 through resistor R14. The delay control module 300' outputs the second detection signal to the display interface 100 through the output port of the third MOS switch U3.

[0107] The gate G of the first MOS switch U1 is electrically connected to the drain D of the second MOS switch U2.

[0108] The source S of the first MOS switch U1 is connected to the power supply, and is connected to the source S of the second MOS switch U2 through capacitor C4.

[0109] The drain D of the first MOS switch U1 is connected to the input port (i.e., the source S of the third MOS switch U3).

[0110] In the fourth switch submodule, the gate G of the second MOS switch U2 serves as the control port of the second MOS switch U2. It is connected to the power supply through resistor R9 and grounded through capacitor C3 and resistor R12 respectively.

[0111] The source S of the second MOS switch U2 is grounded, and is connected to the power supply and the source S of the first MOS switch U1 through capacitor C4.

[0112] The drain D of the second MOS switch U2 serves as the output port of the second MOS switch U2 and is connected to the power supply through resistor R13. The drain D of the second MOS switch U2 is also electrically connected to the gate G of the first MOS switch U1.

[0113] According to the embodiments of this application, in the second embodiment, a P-channel MOS switch is used to replace the first switch in the first embodiment, and an N-channel MOS switch is used to replace the second switch in the first embodiment. By adjusting the resistors, capacitors and other components, the same effect as in the first embodiment can be achieved.

[0114] Figure 4 A timing diagram of hot-plug detection signals according to an embodiment of this application is shown.

[0115] like Figure 4 As shown, signal 10 is the power signal on the computer host side, signal 20 is the power signal on the monitor side, signal 30 is the first control signal, signal 40 is the first detection signal output by the main control module, signal 50 is the second control signal, and signal 60 is the second detection signal output by the delay control module.

[0116] Both the first and second control signals are control signals connected to the GPIO port of the display control module. They are set to high or low levels by the display control module and are activated simultaneously.

[0117] T1 represents the hardware delay of the power supply system, including the delay T of the computer host's AC power input and output. EPS The delay T between the AC input and DC output of the monitor power supply IPS .

[0118] T2 is the monitor software delay, which is the time from when the monitor motherboard receives power and initializes each module until the levels of the first control signal and the second control signal are high.

[0119] After T3 receives power from the display, the delay control module circuit of this application sets the HPD signal (i.e., the second detection signal) of the display interface to a high level for the specified time. <T2。

[0120] According to some embodiments, the value of T3 can be changed by adjusting the conduction time of the delay control module circuit.

[0121] After the computer host receives power from the power supply system, signal 10 becomes high. After the power supply system's hardware delay T1, the computer host starts the BIOS and outputs the BIOS screen.

[0122] After the display receives power from the power system, signal 20 becomes high after a hardware delay T1 in the power system, and the display begins to initialize and control the timing of each module in sequence.

[0123] The display control module outputs signals 30 and 50 simultaneously, and outputs signal 40 through the main control module. When the display starts initializing and timing control of each module, the level of signal 40 is the same as the level of signal 30 and signal 50, which is low. At this time, the delay control module starts working according to the level of signal 50.

[0124] After the T3 period, signal 60 is set to a high level by the delay control module based on signal 50. The display completes the initialization and timing control of each module and begins to display the BIOS screen.

[0125] like Figure 4 As shown, in the prior art, signal 30 (the control signal of the main control module, i.e., the first control signal) and signal 40 (the HPD signal of the display interface, i.e., the first detection signal) need to wait for a time T2 before they can be set from a low level or high impedance state to a high level state. Because the T2 time is relatively long, it affects the communication between the computer host and the monitor.

[0126] The delay control module circuit of this application embodiment works when signal 50 (the control signal of the delay control module, i.e., the second control signal) is in a low-level or high-impedance state. It only takes T3 time to set signal 60 (the HPD signal of the display interface, i.e., the second detection signal) to a high-level state, so that the display shows the BIOS screen of the computer host. Moreover, T3 is much smaller than T2, which greatly improves the speed of displaying the BIOS screen compared with the prior art.

[0127] When signal 50 (the control signal of the delay control module, i.e. the second control signal) remains at a high level after time T2, the delay control module circuit of this embodiment is closed to a high impedance state, so as not to affect the operation of the original circuit. Signal 40 (the HPD signal of the display interface, i.e. the first detection signal) is only controlled by signal 30 (the control signal of the main control module, i.e. the first control signal) of the original control circuit.

[0128] Figure 5 A flowchart illustrating the operation of a display hot-plug detection circuit according to an embodiment of this application is shown.

[0129] like Figure 5 As shown, in S501, the working state of the delay control module is determined based on the level of the first control signal and / or the second control signal emitted by the display.

[0130] According to some embodiments, the first control signal and the second control signal are output by the display control module and can be set to high level or low level by software.

[0131] The first control signal is connected to the main control module line through the first access port of the main control module; the second control signal is connected to the delay control module line through the second access port of the delay control module.

[0132] According to some embodiments, the delay control module operates when both the first control signal and the second control signal are at a low level; the delay control module is turned off when both the first control signal and the second control signal are at a high level.

[0133] In S503, the delay control module is in working state, and the delay control module generates a second detection signal according to the second control signal and outputs it.

[0134] According to the first embodiment of this application, the delay control module is in a working state, and the first switch Q1 in its circuit is in a saturated conduction state. According to the second control signal of the control port of the first switch Q1, the delay control module sets the level of the second detection signal to a high level and outputs it to the display interface through the output port of the first switch Q1.

[0135] In S505, the delay control module is in the off state, and the main control module generates and outputs the first detection signal based on the first control signal.

[0136] According to the first embodiment of this application, the delay control module is in a closed state, and the first switch Q1 in its circuit is in a cut-off state. The delay control module circuit will not affect the main control module circuit.

[0137] The main control module sets the level of the first detection signal to high level based on the first control signal received from the first access port and outputs it to the display interface.

[0138] According to some embodiments, the display sends a first detection signal or a second detection signal to the computer host, and displays the BIOS screen output by the computer host to the display when the level of the first detection signal or the second detection signal is high.

[0139] Figure 6 A block diagram of an electronic device according to an example embodiment of this application is shown.

[0140] like Figure 6 As shown, the electronic device 600 is merely an example and should not impose any limitations on the functionality and scope of use of the embodiments of this application.

[0141] like Figure 6As shown, the electronic device 600 is manifested in the form of a general-purpose computing device. The components of the electronic device 600 may include, but are not limited to: at least one processing unit 610, at least one storage unit 620, a bus 630 connecting different system components (including the storage unit 620 and the processing unit 610), a display unit 640, etc. The storage unit stores program code, which can be executed by the processing unit 610, causing the processing unit 610 to perform the methods described in this specification according to the various exemplary embodiments of this application. For example, the processing unit 610 can perform, for example... Figure 5 The method shown.

[0142] Storage unit 620 may include a readable medium in the form of a volatile storage unit, such as random access memory (RAM) 6201 and / or cache memory 6202, and may further include a read-only memory (ROM) 6203.

[0143] Storage unit 620 may also include a program / utility 6204 having a set (at least one) program module 6205, such program module 6205 including but not limited to: operating system, one or more application programs, other program modules and program data, each or some combination of these examples may include an implementation of a network environment.

[0144] Bus 630 can represent one or more of several types of bus structures, including a memory cell bus or memory cell controller, a peripheral bus, a graphics acceleration port, a processing unit, or a local bus using any of the various bus structures.

[0145] Electronic device 600 can also communicate with one or more external devices 700 (e.g., keyboard, pointing device, Bluetooth device, etc.), and with one or more devices that enable a user to interact with electronic device 600, and / or with any device that enables electronic device 600 to communicate with one or more other computing devices (e.g., router, modem, etc.). This communication can be performed via input / output (I / O) interface 650. Furthermore, electronic device 600 can also communicate with one or more networks (e.g., local area network (LAN), wide area network (WAN), and / or public networks, such as the Internet) via network adapter 660. Network adapter 660 can communicate with other modules of electronic device 600 via bus 630. It should be understood that, although not shown in the figures, other hardware and / or software modules can be used in conjunction with electronic device 600, including but not limited to: microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data backup storage systems.

[0146] Through the above description of the embodiments, those skilled in the art will readily understand that the exemplary embodiments described herein can be implemented by software or by combining software with necessary hardware. The technical solutions according to the embodiments of this application can be embodied in the form of a software product, which can be stored in a non-volatile storage medium (such as a CD-ROM, USB flash drive, external hard drive, etc.) or on a network, including several instructions to cause a computing device (such as a personal computer, server, mobile terminal, or network device, etc.) to execute the methods according to the embodiments of this application.

[0147] Software products may employ any combination of one or more readable media. A readable medium may be a readable signal medium or a readable storage medium. A readable storage medium may be, for example,, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples of readable storage media (a non-exhaustive list) include: electrical connections with one or more wires, portable disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof.

[0148] Computer-readable storage media may include data signals propagated in baseband or as part of a carrier wave, carrying readable program code. Such propagated data signals may take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. A readable storage medium may also be any readable medium other than a readable storage medium that can transmit, propagate, or transfer a program for use by or in connection with an instruction execution system, apparatus, or device. The program code contained on the readable storage medium may be transmitted using any suitable medium, including but not limited to wireless, wired, optical fiber, RF, etc., or any suitable combination thereof.

[0149] Program code for performing the operations of this application can be written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Java and C++, and conventional procedural programming languages ​​such as C or similar languages. The program code can execute entirely on the user's computing device, partially on the user's computing device, as a standalone software package, partially on the user's computing device and partially on a remote computing device, or entirely on a remote computing device or server. In cases involving remote computing devices, the remote computing device can be connected to the user's computing device via any type of network, including a local area network (LAN) or a wide area network (WAN), or it can be connected to an external computing device (e.g., via the Internet using an Internet service provider).

[0150] The aforementioned computer-readable medium carries one or more programs, which, when executed by a device, cause the computer-readable medium to perform the aforementioned functions.

[0151] Those skilled in the art will understand that the above modules can be distributed in the device as described in the embodiments, or they can be modified accordingly and placed in one or more devices that are unique to this embodiment. The modules in the above embodiments can be combined into one module, or they can be further divided into multiple sub-modules.

[0152] According to some embodiments of this application, the technical solution of this application improves the existing hardware circuitry by adding a hot-plug detection signal delay control circuit. Based on effective communication between the computer host and the monitor, the hot-plug detection signal is set to a high level as early as possible, thus solving the problem of the BIOS screen not displaying properly.

[0153] The embodiments of this application have been described in detail above. These descriptions are solely for the purpose of helping to understand the method and core ideas of this application. Furthermore, any changes or modifications made by those skilled in the art based on the ideas of this application, its specific implementation methods, and its application scope, are all within the scope of protection of this application. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. A display hot plug detection circuit, comprising: include: The main control module receives a first control signal from the display, generates a first detection signal based on the first control signal, and outputs the first detection signal to the display interface. The delay control module receives a second control signal from the display, generates a second detection signal based on the second control signal, sets the second detection signal to a high level, and outputs the second detection signal to the display interface. The delay control module operates when both the first control signal and the second control signal are at a low level. When both the first control signal and the second control signal are at a high level, the delay control module is turned off.

2. The circuit according to claim 1, characterized in that, include: The first control signal and the second control signal are issued simultaneously after the display receives power; The first control signal and the second control signal are both at a low level before the first detection signal is set to a high level; The first control signal and the second control signal are both high after the first detection signal is set to high; and The second control signal remains at a high level after the first detection signal is set to a high level.

3. The circuit according to claim 1, characterized in that, The main control module includes a first resistor, a third resistor, and a first access port, wherein, The first access port is electrically connected to the HPD receive pin of the display interface through the third resistor, and receives the first control signal; The first resistor is grounded, and the HPD receive pin of the display interface is grounded through the first resistor.

4. The circuit according to claim 1, characterized in that, The delay control module includes a first switch submodule and a second switch submodule, and the first switch submodule and the second switch submodule are electrically connected.

5. The circuit according to claim 4, characterized in that, The first switching submodule includes a power supply, a first MOS switch, a first switching transistor, a second resistor, a fifth resistor, a sixth resistor, and a second access port, wherein... The second access port is electrically connected to the base of the first switching transistor through the sixth resistor and receives the second control signal; The base of the first switching transistor serves as the control port of the first switching transistor and is grounded through the fifth resistor; The emitter of the first switching transistor serves as the input port of the first switching transistor and is electrically connected to the drain of the first MOS switching transistor. The collector of the first switching transistor serves as the output port of the first switching transistor and is electrically connected to the display interface through the second resistor; The source of the first MOS switch is electrically connected to the power supply, and the gate of the first MOS switch is electrically connected to the collector of the second switch of the second switch submodule.

6. The circuit according to claim 5, characterized in that, The first MOS switch is in the off state, and the emitter of the first switch is reverse biased, so that the first switch is in the off state. The first MOS switch is in a saturated conduction state and the second control signal is low level. The emitter of the first switch is forward biased. The second resistor, the fifth resistor, and the sixth resistor are adjusted so that the first switch is in a conduction state. The delay control module sets the second detection signal to a high level based on the second control signal. When the first MOS switch is in saturation and the second control signal is high, the emitter of the first switch is reverse biased, causing the first switch to be in the cutoff state.

7. The circuit according to claim 4, characterized in that, The second switching submodule includes a power supply, a fourth resistor, a seventh resistor, an eighth resistor, a second switching transistor, a first capacitor, and a second capacitor, wherein... The base of the second switching transistor is grounded through the first capacitor and the fourth resistor, respectively, and the base of the second switching transistor serves as the control port of the second switching transistor. The collector of the second switch serves as the output port of the second switch, and the collector of the second switch is electrically connected to the gate of the first MOS switch of the first switch submodule. The emitter of the second switch is grounded and connected to the power supply and the source of the first MOS switch of the first switch submodule through the second capacitor. The power supply is electrically connected to the collector of the second switching transistor through the eighth resistor, and electrically connected to the base of the second switching transistor through the seventh resistor.

8. The circuit according to claim 7, characterized in that, The second switch is in the off state, which causes the first MOS switch to be in the off state; The second switch is in a saturated conduction state, which causes the first MOS switch to be in a conduction state; The conduction duration of the second switch is controlled by the control port of the second switch, and the working duration of the delay control module is controlled by the conduction duration of the second switch.

9. The circuit according to claim 8, characterized in that, The operating time of the delay control module includes: After the display receives power, the delay control module sets the second detection signal to a high level for a specified period of time; and The time from when the second detection signal is set to a high level to when the first detection signal is set to a high level.

10. A method of operating the display hot-plug detection circuit according to claim 1, wherein the circuit includes a main control module and a delay control module, characterized in that, include: The operating state of the delay control module is determined based on the level of the first control signal and / or the second control signal emitted by the display. When the delay control module is in operation, it is controlled to generate and output a second detection signal based on the second control signal. When the delay control module is in the off state, it controls the main control module to generate and output a first detection signal based on the first control signal. The delay control module is in operation when both the first control signal and the second control signal are at a low level. When both the first control signal and the second control signal are at a high level, the delay control module is in a closed state.

11. The method according to claim 10, characterized in that, include: The delay control module operates by setting the level of the second detection signal to a high level. When the delay control module is turned off, the main control module sets the level of the first detection signal to high.

12. The method according to claim 10, characterized in that, When the delay control module is in operation, it is controlled to generate and output a second detection signal based on the second control signal emitted by the display, including: Adjust the resistance value of at least one resistor in the delay control module so that the delay control module is in a saturated conduction state; Generate the second detection signal and output the second detection signal; Adjust the capacitor in the delay control module to control the working duration of the delay control module.

13. An integrated circuit, characterized in that, Includes the hot-plug detection circuit as described in any one of claims 1-9.

14. An electronic device, characterized in that, Includes the hot-plug detection circuit as described in any one of claims 1-9 or the integrated circuit as described in claim 13.

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