Imaging device array

Abstract

A solid-state imager array (100) is provided that includes a plurality of solid-state imagers (102-1 to 102-4) arranged in an array, each solid-state imager (102-1 to 102-4) including one or more photodiode groups (110), one or more device lines (120, 122) disposed along at least one side of the photodiode groups (110), each device line including a gate and a doped region aligned in a straight line, and a device power supply (124, 126, 128), each device power supply disposed at a point at each end of the device lines (120, 122) and each end of the device lines (120, 122) of an adjacent solid-state imager (102-1 to 102-4), wherein the gate and the doped region function as a transistor device for operating the solid-state imager (102-1 to 102-4), wherein the device power supplies (124, 126, 128) are disposed at four corners of a boundary of the solid-state imager (102-1 to 102-4).

Description

Technical Field

[0001] This invention relates to an imaging device array. More specifically, this invention relates to a pixel configuration for reducing pixel fixed-pattern noise. Background Technology

[0002] As pixel sizes shrink, pixel-sharing techniques are frequently employed to maximize the numerical aperture of photodiodes. In this technique, sharing transistors among multiple pixels ensures sufficient photodiode area, minimizing the footprint of other components within the pixel unit. Pixel-sharing improves pixel characteristics such as the amount of saturation signal and photodiode sensitivity. Consequently, various pixel unit layouts have been proposed in the field of CMOS imaging sensors employing pixel-sharing techniques.

[0003] Because solid-state imaging devices essentially follow a constant voltage scaling law, the doping concentration within a pixel increases rapidly as the pixel size decreases. Even with device isolation achieved through non-shallow trench isolation (non-STI) or shallow trench isolation (STI), a pn junction region exists within the device domain of the pixel. This is because STI requires a p-type layer to cover the STI interface to reduce dark current. Therefore, the higher the doping concentration, the higher the electric field becomes within the pixel. This leads to higher dark current, which is observed as high pixel fixed-mode noise. Fixed-mode noise is a critical issue for image quality.

[0004] To address these issues, prior art (US Patent No. 11,031,421) proposes a configuration in which pixel devices are individually arranged in two rows to maintain the fill factor of the photodiode, such as... Figure 13 As shown. However, Figure 13 The solid-state imaging device array 1300 shown includes four strong pn nodes 1310. Each of these four pn nodes 1310 includes N+ source / drain (N+ S / D) and P-type device isolation. These result in a high electric field, and the device will suffer from high current leakage and high parasitic capacitance.

[0005] Prior art (US Patent Application Publication No. 2020 / 0,194,485) proposes a pixel configuration that does not include N+ S / D and P-type isolation regions, such as Figure 14 As shown. Figure 14The solid-state imaging device array 1400 shown includes two photodiode groups 1402-1 and 1402-2 and a device line 1404 along these two photodiode groups 1402-1 and 1402-2. Device line 1404 includes, in the following order: a first row select device 1406, a first source follower device 1408 (whose gate is coupled to a floating diffusion region of photodiode group 1402-1), a first reset device 1410, a second reset device 1412, a second source follower device 1414 (whose gate is coupled to a floating diffusion region of photodiode group 1402-2), and a second row select device 1416. However, this solid-state imaging device array 1400 does not include dual conversion gain devices, which are highly required in small-pixel applications. Furthermore, instead of two photodiode groups (each group including four photodiodes in a 4×2 configuration), the pixel-sharing configuration uses two photodiode groups, each group including two photodiodes in a 2×2 configuration. Therefore, the conversion gain becomes worse. Summary of the Invention

[0006] The problem to be solved by the present invention The object of this invention is to solve the above-mentioned problems. For example, even if pixels are further miniaturized, it remains preferable to provide a solid-state imaging device that allows for reduced characteristic variations (e.g., fixed-pattern noise and photoresponse inhomogeneity).

[0007] Problem-solving methods A first embodiment of the present invention provides an imaging device array including a plurality of imaging devices arranged in the array. Each imaging device includes: one or more photodiode groups; one or more device lines disposed along at least one side of the photodiode groups, each device line including a gate and a doped region aligned in a straight line; and device power supplies, each device power supply being disposed at a point coupled to each end of the device line to each end of the device line of an adjacent imaging device. The gate and doped region serve as transistor devices for operating the imaging devices. The device power supplies are disposed at the four vertices of the boundaries of the imaging devices. The first embodiment of the present invention can provide device isolation between the imaging devices without providing pn junctions, thereby reducing fixed-mode noise.

[0008] According to a first embodiment of the present invention, the device power supply of the imaging device can be shared with adjacent imaging devices. The device power supply between the adjacent imaging devices can provide device isolation between the imaging devices without providing a pn junction, thereby reducing fixed-mode noise.

[0009] According to a first embodiment of the present invention, the one or more device lines may include: a first device line disposed along a first side of the photodiode group; and a second device line disposed along a second side of the photodiode group adjacent to the first side. The device power supply may include: a first device power supply electrically coupled to one end of the first device line; a second device power supply electrically coupled to the other end of the first device line and one end of the second device line; and a third device power supply electrically coupled to the other end of the second device line. The photodiode group may include: at least one photodiode; a floating diffusion region; and a charge transport gate, each charge transport gate being disposed between each photodiode and the floating diffusion region. The transistor device in the first device line may include a reset device, a double-conversion gain device, and an overflow gate device line-coupled in the following order. The transistor device in the second device line may include a first source follower device, a first row select device, a second row select device, and a second source follower device line-coupled in the following order. The second device line may further include an output contact disposed between and electrically coupled to the sources of the first row select device and the second row select device, and the output contact is also coupled to the Vout line and the column output line. The drain of the reset device may be electrically coupled to the power supply of the first device. The sources of the dual-conversion gain device and the overflow gate device may be electrically coupled to the floating diffusion region. The drain of the first source follower device may be electrically coupled to the power supply of the second device. The drain of the second source follower device may be electrically coupled to the power supply of the third device. The gates of the first source follower device and the second source follower device may be electrically coupled to the floating diffusion region. Each imaging device may be configured such that the first device line of a first adjacent imaging device is disposed along the third side of the photodiode group opposite to the first side of the photodiode group of the imaging device, and the second device line of a second adjacent imaging device is disposed along the fourth side of the photodiode group opposite to the second side of the photodiode group of the imaging device. Each imaging device can be configured such that the first device power supply of the imaging device and the second device power supply of the second adjacent imaging device together form a first common device power supply, and that the third device power supply of the imaging device and the second device power supply of the first adjacent imaging device together form a second common device power supply. The device power supplies between the adjacent imaging devices can provide device isolation between the imaging devices without providing a pn junction, thus reducing fixed-mode noise.

[0010] According to a first embodiment of the present invention, the photodiode group may include: a first photodiode group; and a second photodiode group adjacent to the first photodiode group. The device line may be disposed along a first side of the first photodiode group and a first side of the second photodiode group. The device power supply may include: a first device power supply electrically coupled to one end of the device line; and a second device power supply electrically coupled to the other end of the device line. Each of the first photodiode group and the second photodiode group may include: at least one photodiode; a floating diffusion region; and a charge transport gate, each charge transport gate being disposed between each photodiode and the floating diffusion region. The transistor device of the device line may include, in the following order, a first overflow gate device, a first double-conversion gain device, a first reset device, a first source follower device, a first row select device, a second row select device, a second source follower device, a second reset device, a second double-conversion gain device, and a second overflow gate device, all electrically coupled in a line. The device line may further include: a third device power supply, the third device power supply being disposed between the drain of the first reset device and the drain of the first source follower device and electrically coupled to the two drains; an output contact, the output contact being disposed between the source of the first row select device and the source of the second row select device and electrically coupled to the two sources, the output contact also being electrically coupled to the Vout line and the column output line; and a fourth device power supply, the fourth device power supply being disposed between the drain of the second source follower device and the drain of the second reset device and electrically coupled to the two drains. The drain of the first overflow gate device may be electrically coupled to the first device power supply. The source of the first overflow gate device, the source of the first dual-conversion gain device, and the gate of the first source follower device may be electrically coupled to the floating diffusion region of the first photodiode group. The source of the second overflow gate device, the source of the second dual-conversion gain device, and the gate of the second source follower device may be electrically coupled to the floating diffusion region of the second photodiode group. The drain of the second overflow gate device may be electrically coupled to the second device power supply. Each imaging device can be configured such that the first device power supply of the imaging device and the second device power supply of the imaging device adjacent to the second side of the first photodiode group form a common device power supply, wherein the second side of the first photodiode group is adjacent to the first side of the first photodiode group. The device power supply between adjacent imaging devices can provide device isolation between the imaging devices without providing a pn junction, thereby reducing fixed-mode noise.

[0011] According to a first embodiment of the present invention, the photodiode group may include: a first photodiode group; and a second photodiode group adjacent to the first photodiode group. The device line may include: a first device line disposed along a first side of the first photodiode group and a first side of the second photodiode group; a second device line disposed between a second side of the first photodiode group adjacent to the first side of the first photodiode group and a fourth side of the second photodiode group adjacent to the first side of the second photodiode group; and a third device line disposed along a second side of the second photodiode group opposite to the fourth side of the second photodiode group. The device power supply may include: a first device power supply electrically coupled to one end of the first device line; a second device power supply electrically coupled to the other end of the first device line and one end of the third device line; and a third device power supply electrically coupled to the other end of the third device line. Each of the first photodiode group and the second photodiode group may include: at least one photodiode; a floating diffusion region; and a charge transport gate, each charge transport gate being disposed between each of the photodiodes and the floating diffusion region. The transistor devices of the first device line may include, in the following order, a first reset device, a first double-conversion gain device, a first overflow gate device, a second overflow gate device, a second double-conversion gain device, and a second reset device, all electrically coupled in line. The transistor devices of the second device line may include, in the following order, a first source follower device, a first row select device, a second row select device, and a second source follower device, all electrically coupled in line. The transistor devices of the third device line may include, in the following order, a third source follower device, a third row select device, a fourth row select device, and a fourth source follower device, all electrically coupled in line. The first device line may also include a fourth device power supply, disposed between the drain of the first overflow gate device and the drain of the second overflow gate device and electrically coupled to both drains. The second device line may also include: a first output contact, disposed between the source of the first row select device and the source of the second row select device and electrically coupled to both sources, the first output contact also electrically coupled to the Vout line and the column output line; and a fifth device power supply, electrically coupled to the drain of the second source follower device. The third device line may include a second output contact, which is disposed between the source of the third row select device and the source of the fourth row select device and electrically coupled to the two sources. The second output contact is also electrically coupled to the Vout line and the column output line. The drain of the first reset device may be electrically coupled to the first device power supply.The drain of the second reset device and the drain of the third source follower device can be electrically coupled to the power supply of the second device. The drain of the first source follower device can be electrically coupled to the power supply of the fourth device. The drain of the fourth source follower device can be electrically coupled to the power supply of the third device. The source of the first dual-conversion gain device and the source of the second overflow gate device can be electrically coupled to the floating diffusion region of the first photodiode group and the second photodiode group. The source of the second dual-conversion gain device and the source of the second overflow gate device can be electrically coupled to the floating diffusion region of the first photodiode group and the second photodiode group. The gates of the first source follower device to the fourth source follower device can be electrically coupled to the floating diffusion region of the first photodiode group and the second photodiode group. Each imaging device can be configured such that the first device line of the first adjacent imaging device is disposed along the third side of the first photodiode group and the second photodiode group opposite to the first side of the first photodiode group and the second photodiode group, and the second device line of the second adjacent imaging device is disposed along the fourth side of the first photodiode group opposite to the second side of the first photodiode group. Each imaging device can be configured such that the first device power supply of the imaging device and the second device power supply of the second adjacent imaging device together form a first common device power supply; the third device power supply of the imaging device and the second device power supply of the first adjacent imaging device together form a second common device power supply; and the fifth device power supply of the imaging device and the fourth device power supply of the first adjacent imaging device together form a third common device power supply. The device power supplies between adjacent imaging devices can provide device isolation between the imaging devices without providing a pn junction, thus reducing fixed-mode noise. Furthermore, the parallel arrangement of source follower devices can increase the source follower gm.

[0012] According to a first embodiment of the present invention, the photodiode group may include: a first photodiode group; and a second photodiode group adjacent to the first photodiode group. The device line may include: a first device line disposed along a first side of the first photodiode group; and a second device line disposed between a third side of the first photodiode group opposite to the first side of the first photodiode group and a first side of the second photodiode. The device power supply may include: a first device power supply electrically coupled to one end of the first device line; a second device power supply electrically coupled to the other end of the first device line; a third device power supply electrically coupled to one end of the second device line; and a fourth device power supply electrically coupled to the other end of the second device line. Each of the first photodiode group and the second photodiode group includes: at least one photodiode; a floating diffusion region; and a charge transport gate, each charge transport gate disposed between each photodiode and the floating diffusion region. The transistor device of the first device line may include an overflow gate device, a double-conversion gain device, and a reset device, wire-coupled in the following order. The transistor device of the second device line may include a first source follower device, a first row select device, a second row select device, and a second source follower device, wire-coupled in the following order. The second device line may further include an output contact, which is located between and electrically coupled to the sources of the first row select device and the second row select device, and is also electrically coupled to the Vout line and the column output line. The drain of the overflow gate device may be electrically coupled to the power supply of the first device. The drain of the reset device may be electrically coupled to the power supply of the second device. The drain of the first source follower device may be electrically coupled to the power supply of the third device. The drain of the second source follower device may be electrically coupled to the power supply of the fourth device. The source of the overflow gate device and the source of the dual-conversion gain device may be electrically coupled to the floating diffusion region of the first photodiode group and the second photodiode group. The gates of the first source follower device and the second source follower device are electrically coupled to the floating diffusion region of the first photodiode group and the second photodiode group. Each imaging device is configured such that the first device line of the first adjacent imaging device is disposed along the third side of the second photodiode group opposite to the first side of the second photodiode group.Each imaging device can be configured such that the first device power supply of the imaging device and the second device power supply of the second adjacent imaging device together form a first common device power supply, wherein the second adjacent imaging device is disposed facing the second side of the first photodiode group and the second photodiode group adjacent to the first side of the first photodiode group and the second photodiode group, and the third device power supply of the imaging device and the fourth device power supply of the second adjacent imaging device together form a second common device power supply. The device power supplies between the adjacent imaging devices can provide device isolation between the imaging devices without providing a pn junction, thus reducing fixed-mode noise. Furthermore, since the device power supply for SF is separate from the device power supply for RST, different voltages can be applied to SF and RST.

[0013] According to a first embodiment of the present invention, in each imaging device, each of the photodiode groups may include a plurality of photodiodes.

[0014] According to a first embodiment of the present invention, in each imaging device, the transistor devices of the device line can be symmetrically arranged. The symmetrical transistor devices of the device line can reduce photoresponse non-uniformity (PRNU) and dark signal non-uniformity (DSNU).

[0015] According to a first embodiment of the present invention, the size of the gate of the overflow gate device can be equal to the size of the gate of the reset device. The symmetry of the transistor device can be improved.

[0016] According to a first embodiment of the present invention, in each imaging device, the gate size of the dual-conversion gain device can be equal to the gate size of the overflow gate device and / or the gate size of the reset device. The symmetry of the transistor device can be improved.

[0017] According to a first embodiment of the present invention, in each imaging device, the length of the gate of the reset device may be greater than the length of the gate of the dual-conversion gain device and / or the length of the gate of the overflow gate device. A larger gate length of the reset device can increase the reset speed and the full-well capacity limited by the reset device.

[0018] According to a first embodiment of the present invention, in each imaging device, the source and drain regions of each transistor device included in the device line can be self-aligned with the gate of each transistor device. Manufacturing costs and process variations can be reduced.

[0019] According to a first embodiment of the present invention, in each imaging device, a trap pickup, serving as a pinned photodiode contact for the photodiode group, can be disposed between the photodiode group and the device line. The area of ​​the trap pickup can be limited, thus reducing the number of white pixels resulting from damage.

[0020] According to a first embodiment of the present invention, in each imaging device, the width of the gate of the source follower device can be greater than the length of the gate of the source follower device. A wider gate of the source follower device can increase the gm of the source follower.

[0021] According to a first embodiment of the present invention, in each imaging device, the charge transport device has an embedded portion in the substrate.

[0022] According to a first embodiment of the present invention, each imaging device may include physical device isolation achieved by shallow trench isolation surrounding at least a portion of the photodiode group, or electrical device isolation achieved by a PN junction surrounding at least a portion of the photodiode group.

[0023] A second embodiment of the present invention provides an electronic device including any one of the above-described imaging device arrays. Attached Figure Description

[0024] Figure 1 A plan view of a solid-state imaging device array provided in the first embodiment of the present invention is shown.

[0025] Figure 1 (A) shows Figure 1 A plan view of a solid-state imaging device in a solid-state imaging device.

[0026] Figure 2 (A) shows an imaging system with a solid-state imaging device array as a pixel array.

[0027] Figure 2 It shows Figure 1 The circuit diagram of the solid-state imaging device in the solid-state imaging device array is shown.

[0028] Figure 3 It shows Figure 1 A partial cross-sectional view of the solid-state imaging device array shown.

[0029] Figure 4 It shows Figure 1 The timing diagram shows the operation of the solid-state imaging devices in the solid-state imaging device array.

[0030] Figure 5 A plan view of a solid-state imaging device array provided in a second embodiment of the present invention is shown.

[0031] Figure 5 (A) shows Figure 5 A plan view of a solid-state imaging device in a solid-state imaging device.

[0032] Figure 6 A plan view of a solid-state imaging device array provided in a third embodiment of the present invention is shown.

[0033] Figure 6 (A) shows Figure 6 A plan view of a solid-state imaging device in a solid-state imaging device.

[0034] Figure 7 A plan view of a solid-state imaging device array provided in the fourth embodiment of the present invention is shown.

[0035] Figure 7 (A) shows Figure 7 A plan view of a solid-state imaging device in a solid-state imaging device.

[0036] Figure 8 A partial cross-sectional view of a solid-state imaging device array provided in some embodiments of the present invention is shown.

[0037] Figure 9 An oblique view of an image sensor including a solid-state imaging device array, provided by some embodiments of the present invention, is shown.

[0038] Figure 10 A block diagram of an image sensor is shown.

[0039] Figure 11 An application example of the solid-state imaging device array provided by the present invention is shown.

[0040] Figure 12 An application example of the solid-state imaging device array provided by the present invention is shown.

[0041] Figure 13 A conventional solid-state imaging device array is shown.

[0042] Figure 14 A conventional solid-state imaging device array is shown. Detailed Implementation

[0043] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. Specific examples of elements and arrangements are described below to simplify the invention. Of course, these are merely examples and are not intended to limit the invention. For example, in the following description, forming a first feature above or on a second feature may include embodiments in which other features may be formed between the first and second features, such that the first and second features do not need to be in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples. Such repetition is for simplicity and clarity and does not, in itself, define the relationship between the various embodiments and / or configurations discussed.

[0044] The term "electrical coupling" in this article does not preclude the placement of another component between coupled components, as long as such placement does not interfere with conductivity. For example, if a first device is electrically coupled to a second device, contacts, nodes, power terminals, etc., can be positioned between the first and second devices.

[0045] This invention provides a solid-state imaging device array, comprising a plurality of solid-state imaging devices arranged in the array. Each solid-state imaging device includes: one or more photodiode groups; one or more device lines disposed along at least one side of the photodiode groups, each device line including a gate and a doped region aligned in a straight line; and device power supplies, each device power supply being disposed at a point coupled to each end of the device line to each end of the device line of an adjacent solid-state imaging device. The gate and doped region can be used as transistor devices for operating the solid-state imaging device. The device power supplies can be disposed at the four vertices of the boundary of the solid-state imaging device. The device power supplies of the solid-state imaging devices can be shared with adjacent solid-state imaging devices. In the following, more detailed exemplary embodiments of the solid-state imaging device array provided by this invention will be explained with reference to the accompanying drawings.

[0046] Figure 1 A plan view of a solid-state imaging device array 100 provided in a first embodiment of the present invention is shown. Figure 1 (A) shows a plan view of the solid-state imaging device 102-1 of the solid-state imaging device array 100. Figure 2 (A) illustrates an imaging system having a solid-state imaging device array as a pixel array. The solid-state imaging device array 100 may include a plurality of solid-state imaging devices disposed in the array. Although Figure 1The first solid-state imaging device 102-1 to the fourth solid-state imaging device 102-4 are shown as examples, but the number of solid-state imaging devices is not limited to this example, and the array may include, for example, multiple solid-state imaging devices corresponding to a number of pixels. The first solid-state imaging device 102-1 to the fourth solid-state imaging device 102-4 may include the same configuration as each other. For example, the first solid-state imaging device 102-1 may include: a photodiode group 110 including a first side 112 to a fourth side 118; a first device line 120 disposed along the first side 112 of the photodiode group 110; a second device line 122 disposed along a second side 114 adjacent to the first side 112; a first device power supply 124 electrically coupled to one end of the first device line 120; a second device power supply 126 electrically coupled to the other end of the first device line 120 and one end of the second device line 122; and a third device power supply 128 electrically coupled to the other end of the second device line 122. The second solid-state imaging devices 102-2 to the fourth solid-state imaging device 102-4 may include the same configuration.

[0047] The photodiode group 110 may include at least one photodiode. Although Figure 1 The photodiode group 110 shown in the example includes fourth photodiodes 130-1 to 130-4, but the number of photodiodes is not limited to this example. Figure 1 In this embodiment, photodiode group 110 includes a floating diffusion region 132 between photodiodes 130-1 to 130-4. The floating diffusion region 132 may be shared by photodiodes 130-1 to 130-4. Photodiode group 110 may include charge transport gates 134-1 to 134-4 respectively between photodiodes 130-1 to 130-4 and the floating diffusion region 132.

[0048] The first device line 120 may include a plurality of gates arranged in a line and an N+ doped region between the plurality of gates. The gates and the N+ doped regions may each form a device (e.g., an NMOS transistor). Figure 3 An example of a cross-section of the first device line 120 is shown. Of course, a PMOS transistor with a reverse conductivity type can also be used. In this case, the source and drain can be reversed in the following description. In the following text, in addition to solid-state imaging devices, the terms "device" and "transistor device" may also refer to an NMOS transistor, which includes a gate and doped regions (source / drain, S / D) formed on the device line.

[0049] The first device line 120 may include a reset device (RST) 136, a dual conversion gain device (DCG) 138, and an overflow gate device (OFG) 140 in the following order: The drain of RST 136 may be electrically coupled to a first device power supply 124. The drain and source of DCG 138 may be electrically coupled to the source of RST 136 and to a floating diffusion region 132, respectively. The source and drain of OFG 140 may be electrically coupled to the source of DCG 138 and to a second device power supply 126, respectively. Therefore, the devices in the first device line 120 can be symmetrically arranged relative to the gate of DCG 138. Furthermore, the symmetry of the transistor devices can be improved by configuring the gate of OFG 140 to have the same dimensions as the gate of RST 136.

[0050] The second device line 122 may include a first source follower (first SF) 142, a first row select (first SEL) 144, an output contact 146, a second row select (second SEL) 152, and a second source follower (second SF) 154 in the following order: The drain and gate of the first SF 142 may be electrically coupled to the second device power supply 126 and the floating diffusion region 132, respectively. The drain and source of the first SEL 144 may be electrically coupled to the source of the first SF 142 and the output contact 146. The output contact 146 may be electrically coupled to the Vout line 148 and the column output line 150. The source of the second SEL 152 may be electrically coupled to the output contact 146. The source and gate of the second SF 154 may be electrically coupled to the drain of the second SEL 152 and the floating diffusion region 132. The drain of the second SF 154 may be electrically coupled to the third device power supply 128. Therefore, the devices in the second device line 122 can be arranged symmetrically with respect to the output contact 146.

[0051] In the solid-state imaging device array 100 having this configuration, solid-state imaging devices 102-1 to 102-4 are configured such that the first device line 120-2 of the second solid-state imaging device 102-2 (or the first adjacent solid-state imaging device) is arranged along the third side 116 of the photodiode group 110 opposite to the first side 112 of the photodiode group 110 of the first solid-state imaging device 102-1, and the second device line 122-3 of the third solid-state imaging device 102-3 (or the second adjacent solid-state imaging device) is arranged along the fourth side 118 of the photodiode group 110 opposite to the second side 114 of the photodiode group 110 of the solid-state imaging device 102-1.

[0052] The first device power supply 124 of the first solid-state imaging device 102-1 and the second device power supply 126-3 of the third solid-state imaging device 102-3 can form a first common device power supply 156. Specifically, the first device power supply 124 of the first solid-state imaging device 102-1 and the second device power supply 126-3 of the third solid-state imaging device 102-3 can share a contact and be connected to a device power line (not shown). The third device power supply 128 of the first solid-state imaging device 102-1 and the second device power supply 126-2 of the second solid-state imaging device 102-2 can form a second common device power supply 158. Specifically, the third device power supply 128 of the first solid-state imaging device 102-1 and the second device power supply 126-2 of the second solid-state imaging device 102-2 can share a contact and be connected to a device power line (not shown).

[0053] In the solid-state imaging device array 100 with this configuration, the device power supply is located on both sides of the device line of the solid-state imaging device. Therefore, each device line of the solid-state imaging device shares the device power supply with the device lines of adjacent solid-state imaging devices. Thus, the device power supply can be used as device isolation between the N+ S / D of adjacent device lines, and isolation between device lines is not required via shallow trench isolation (STI) or non-STI providing a pn junction. Reducing pn junction leakage and parasitic capacitance suppresses the increase in dark current caused by the pn junction and reduces pixel fixed pattern noise (FPN), even when pixels are miniaturized and doped. Furthermore, the reduction in parasitic capacitance improves conversion gain. Since STI fabrication processes are not required, manufacturing costs can be reduced.

[0054] Furthermore, the symmetrical first device line 120 and second device line 122 provide electrical and optical symmetry, which enables the reduction of photo response non-uniformity (PRNU) and dark signal non-uniformity (DSNU).

[0055] Furthermore, to ensure the symmetry of the second device line 122, the first SF 142 and the second SF 154 are connected in parallel. This improves the source follower gm, enabling high frame rate imaging. The gate widths of the first SF 142 and the second SF 154 can be greater than their gate lengths, respectively. This configuration allows the first SF 142 and the second SF 154 to operate at higher speeds.

[0056] The gate length of RST 136 can be greater than that of DCG 138 and / or OFG 140. In this case, although the symmetry of the device lines decreases, the reset speed and the full-well capacity limited by the reset device can be increased.

[0057] The S / D region of each device line can be self-aligned because the initially formed gate is used as a mask during the doping process. Self-alignment eliminates alignment errors between the gate and the S / D region, thus improving manufacturing yield.

[0058] A well pickup, used as a pinned photodiode contact, can be disposed between the photodiode group 110 and the first device line 120. The area of ​​the well pickup can be reduced by being masked by the gate and spacers of the S / D sidewalls of the adjacent device line. Since the well pickup is a P+ doped region, it can be damaged due to doping. Therefore, when the area of ​​the well pickup is limited, the number of white pixels resulting from damage can be reduced.

[0059] Solid-state imaging devices 102-1 to 102-4 may include physical device isolation achieved by an STI surrounding at least a portion of the photodiode group 110, or electrical device isolation achieved by a pn junction surrounding at least a portion of the photodiode group 110.

[0060] Figure 2 (A) illustrates that the solid-state imaging device array 100 can be implemented as a pixel array 209 in the imaging system 201. The imaging system 201 may further include control circuitry 205 for controlling the pixel array 209, bit lines 204 for each column output line 150 coupled to the solid-state imaging device array 100, readout circuitry 210 coupled to the bit lines 204, and signal processing circuitry 206 coupled to the output of the readout circuitry 210. As described above, the signal generated by light impacting the solid-state imaging device array 100 is read out by the readout circuitry via the bit lines 204. Therefore, the control circuitry 205 can perform a readout scan for each row, and the signal processing circuitry 206 can process the readout signal to obtain a two-dimensional image.

[0061] Refer to the circuit diagram showing the solid-state imaging device 100. Figure 2 And showing the timing diagram Figure 4 To explain the operation of the solid-state imaging device array 100 with this configuration. Figure 4 In the diagram, SEL indicates the first row device 144 and the second row device 152, RST is the reset device 136, DCG is the dual-conversion gain device 138, OFG is the overflow gate device 140, and TX is the charge transport gate. For example... Figure 2 The charge transport gate 134-1 indicated by TX1 is shown.

[0062] In some embodiments, OFG 140 is turned on during shutter timing and low conversion gain reset timing, such as Figure 4 As shown in (A).

[0063] The first SEL 144 and the second SEL 152 remain off during shutter timing 400. RST 136, DCG 138, OFG 140 and charge transport gate 134-1 are turned on to reset photodiode 130-1 and floating diffusion region 132. Subsequently, these devices are all turned off.

[0064] During exposure timing 402, the devices remain in the off state for a predetermined time period. As a result of photoelectric conversion via electromagnetic wave projection onto photodiode 130-1, photocharge is stored in the photodiode.

[0065] Then, readout timing 404 is performed. The readout timing includes low conversion gain reset timing 404-2, high conversion gain reset timing 404-4, high conversion signal timing 404-6, and low conversion gain signal timing 404-8. The signal is obtained by performing correlated double sampling (CDS), which uses the difference between the reset level and the signal level.

[0066] In the low conversion gain reset timing 404-2, the first SEL 144, the second SEL 152, RST 136, DCG 138, and OFG 140 are turned on. Subsequently, RST 136 and OFG 140 are turned off.

[0067] During high conversion gain reset timing 404-4, DCG 138 is turned off. Since the floating diffusion region 132 is reset by the device power supply during low conversion gain reset timing 404-2 and high conversion gain reset timing 404-4, the gates of the first SF 142 and the second SF 154 are in a high state, and therefore current flows to the column output line 150.

[0068] In the high conversion gain signal timing 404-6, the charge transfer gate 134-1 is turned on for a predetermined time period to transfer the photocharge (electrons in this embodiment) stored in the photodiode 130-1 to the floating diffusion region 132. The voltage applied to the gates of the first SF 142 and the second SF 154 coupled to the floating diffusion region 132 decreases in response to the amount of photocharge transferred. The current output to the column output line 150 decreases, and the voltage of the Vout line 148 changes. In other words, the first SF 142 and the second SF 154 acquire the photocharge resulting from photoelectric conversion and output it to the Vout line 148. Since the DCG 138 is in the off state in the high conversion gain signal timing 404-6, the floating diffusion region 132 saturates if the amount of photocharge transferred is large. Therefore, the output in the high conversion gain signal timing 404-6 is advantageous when the amount of photocharge transferred is small.

[0069] During low conversion gain signal timing 404-8, DCG 138 is turned on, and charge transfer gate 134-1 is turned on for a predetermined time period. If there is untransferred photocharge due to saturation of floating diffusion region 132 during high conversion gain signal timing 404-6, this photocharge is transferred to floating diffusion region 132, obtained by first SF 142 and second SF 154, and output to Vout line 148. Imaging can be performed even if the amount of projected electromagnetic wave is large and therefore the amount of photocharge is large. Finally, first SEL 144, second SEL 152 and DCG 138 are turned off, and readout timing 404 ends.

[0070] Figure 4 (B) illustrates an alternative example of operating a solid-state imaging device. (Compared to) Figure 4 (A) Different, in Figure 4 In (B), OFG140 is in the on state during shutter timing 400, exposure timing 402 and low conversion gain reset timing 404-2.

[0071] Figure 4 (C) illustrates another alternative example of operating a solid-state imaging device. Figure 4 In (C), OFG 140 is off during all periods.

[0072] Figure 4 (D) illustrates another alternative example of operating a solid-state imaging device. Figure 4 In (D), OFG 140 is turned on only during shutter timing.

[0073] You can choose appropriately based on your purpose. Figure 4 (A) to Figure 4 The operation method shown in (D) is as follows.

[0074] Figure 5 A plan view of a solid-state imaging device array 500 provided in a second embodiment of the present invention is shown. Figure 5 (A) shows a plan view of solid-state imaging device 502-1 in a solid-state imaging device array 500. The solid-state imaging device array 500 may include multiple solid-state imaging devices disposed in the array. Although Figure 5 A first solid-state imaging device 502-1 and a second solid-state imaging device 502-2 are shown as examples, but the number of solid-state devices is not limited to this example, and the array may include, for example, multiple solid-state imaging devices corresponding to a number of pixels. The first solid-state imaging device 502-1 and the second solid-state imaging device 502-2 may include the same configuration as each other. For example, the first solid-state imaging device 502-1 includes: a first photodiode group 510-1, which includes a first side 512-1 to a fourth side 518-1; a second photodiode group 510-2, which includes a first side 512-2 to a fourth side 518-2; a device line 520 disposed along the first side 512-1 of the first photodiode group 510-1 and the first side 512-2 of the second photodiode group 510-2; a first device power supply 524 electrically coupled to one end of the device line 520; and a second device power supply 526 electrically coupled to the other end of the device line 520. The second solid-state imaging device 502-2 may include the same configuration.

[0075] Each of the first photodiode group 510-1 and the second photodiode group 510-2 may include at least one photodiode. Figure 5 In the example shown, the first diode group 510-1 includes four photodiodes 530-1 to 530-4. However, the number of photodiodes is not limited to four. Figure 5 In this configuration, the first photodiode group 510-1 includes a floating diffusion region 532-1 between photodiodes 530-1 to 530-4. The floating diffusion region 532-1 may be shared by photodiodes 530-1 to 530-4. The first photodiode group 510-1 may include charge transport gates 534-1 to 534-4, respectively, between photodiodes 530-1 to 530-4 and the floating diffusion region 532-1. The second photodiode group 510-2 may include the same configuration.

[0076] Configuration of device line 520 and Figures 1 to 3The solid-state imaging device array 100 shown has the same device line configuration, only the arrangement of transistor devices differs. Device line 520 may include, in the following order: first OFG 540-1, first DCG 538-1, first RST 536-1, third device power supply 560, first SF 542, first SEL 544, output contact 546, second SEL 552, second SF 554, fourth device power supply 562, second RST 536-2, second DCG 538-2, and second OFG 540-2. The drain and source of the first OFG 540-1 are electrically coupled to the first device power supply 524 and the floating diffusion region 532-1 of the first photodiode group 510-1, respectively. The source of the first DCG 538-1 is electrically coupled to the source of the first OFG 540-1. The source and drain of the first RST 536-1 are electrically coupled to the drain of the first DCG 538-1 and the third device power supply 560, respectively. The drain and gate of the first SF 542 are electrically coupled to the third device power supply 560 and the floating diffusion region 532-1 of the first photodiode group 510-1. The drain of the first SEL 544 is electrically coupled to the source of the first SF 542. The output contact 546 is electrically coupled to the source of the first SEL 544, the Vout line 548, and the column output line 550. The source of the second SEL 552 is electrically coupled to the output contact 546. The source, gate, and drain of the second SF 544 are electrically coupled to the drain of the second SEL 552, the floating diffusion region 532-2 of the second photodiode group 510-2, and the fourth device power supply 562, respectively. The drain of the second RST 536-2 is electrically coupled to the fourth device power supply 562. The source of the second DCG 538-2 is electrically coupled to the floating diffusion region 532-2 of the second photodiode group 510-2. The source and drain of the second OFG 540-2 are electrically coupled to the floating diffusion region 532-2 of the second photodiode group 510-2 and the second device power supply 526, respectively. Therefore, the transistor devices in the device line 520 can be symmetrically arranged with respect to the output contact 546.

[0077] In the solid-state imaging device array 500, the first device power supply 524 of the first solid-state imaging device 502-1 and the second device power supply 526 of the second solid-state imaging device 502-2 can form a common device power supply 556, wherein the second solid-state imaging device is adjacent to the second side 512-2 of the first photodiode group 510-1 of the first solid-state imaging device 502-1, and the second side 512-2 is adjacent to the first side 512-1. Specifically, the first device power supply 524 of the first solid-state imaging device 502-1 and the second device power supply 526 of the second solid-state imaging device 502-2 can share a contact and be connected to a device power line (not shown).

[0078] Therefore, in the solid-state imaging device array 500 with this configuration, the device power supply is used as device isolation between N+ S / D of adjacent device lines, and there is no need for isolation between device lines via STI or non-STI.

[0079] Furthermore, the variations and effects of the explanation regarding solid-state imaging device array 100 can be applied to solid-state imaging device array 500, provided that the configurations are compatible. (Reference) Figure 4 The method explained for operating the solid-state imaging device array 100 can also be applied to the solid-state imaging device array 500.

[0080] Figure 6 A plan view of a solid-state imaging device array 600 provided in a third embodiment of the present invention is shown. Figure 6 (A) shows a plan view of solid-state imaging device 602-1 in a solid-state imaging device array 600. The solid-state imaging device array 600 may include multiple solid-state imaging devices disposed in the array. Although Figure 6 The first solid-state imaging device 602-1 to the fourth solid-state imaging device 602-4 are shown as examples, but the number of solid-state imaging devices is not limited to this example, and the array may include, for example, multiple solid-state imaging devices corresponding to a number of pixels. The first solid-state imaging device 602-1 to the fourth solid-state imaging device 602-4 may include the same configuration as each other. For example, the first solid-state imaging device 602-1 may include: a first photodiode group 610-1, which includes a first side 612-1 to a fourth side 618-1; a second photodiode group 610-2, which includes a first side 612-2 to a fourth side 618-2; a first device line 620, which is disposed along the first side 612-1 of the first photodiode group 610-1 and the first side 612-2 of the second photodiode group 610-2; and a second device line 622, which is disposed adjacent to the first side 612-1 of the first photodiode group 612-1. Between the second side 614-1 and the fourth side 618-2 adjacent to the first side 612-2 of the second photodiode group 610-2; a third device line 670, which is disposed along the second side 614-2 opposite to the fourth side 618-2 of the second photodiode group 610-2; a first device power supply 624, which is electrically coupled to one end of the first device line 620; a second device power supply 626, which is electrically coupled to the other end of the first device line 620 and one end of the third device line 670; and a third device power supply 660, which is electrically coupled to the other end of the third device line 670. The second solid-state imaging devices 602-2 to the fourth solid-state imaging devices 602-4 may include the same configuration.

[0081] The first photodiode group 610-1 and the second photodiode group 610-2 may each include at least one photodiode. Figure 6In the example shown, the first photodiode group 610-1 includes four photodiodes 630-1 to 630-4. However, the number of photodiodes is not limited to four. Figure 6 In this configuration, the first photodiode group 610-1 includes a floating diffusion region 632-1 between photodiodes 630-1 to 630-4. The floating diffusion region 632-1 may be shared by photodiodes 630-1 to 630-4. The first photodiode group 610-1 may include charge transport gates 634-1 to 634-4 between photodiodes 630-1 to 630-4 and the floating diffusion region 632-1. The second photodiode group 610-2 may include the same configuration.

[0082] The configuration of the first device line to the third device lines 620, 622, and 670 and Figures 1 to 3 The solid-state imaging device array 100 shown has the same device line configuration, only the device arrangement is different. The first device line 620 may include a first RST 636-1, a first DCG 638-1, a first OFG 640-1, a fourth device power supply 662, a second OFG 640-2, a second DCG 638-2, and a second RST 636-2 in the following order. The drain of the first RST 636-1 is electrically coupled to the first device power supply 624. The drain and source of the first DCG 638-1 are electrically coupled to the source of the first RST 636-1 and the floating diffusion regions 632-1 and 632-2 of the first photodiode group 610-1 and the second photodiode group 610-2, respectively. The source and drain of the first OFG 640-1 are electrically coupled to the source of the first DCG 638-1 and the fourth device power supply 662, respectively. The drain and source of the second OFG 640-2 are electrically coupled to the fourth device power supply 662 and the source of the first OFG 640-1. The drain of the second DCG 638-2 is electrically coupled to the source of the second OFG 640-2. The source and drain of the second RST 636-2 are electrically coupled to the drain of the second DCG 638-2 and the second device power supply 626. Therefore, the devices in the first device line 620 can be arranged symmetrically with respect to the fourth device power supply 662.

[0083] The second device line 622 may include a first SF 642-1, a first SEL 644-1, a first output contact 646-1, a second SEL 652-1, a second SF 654-1, and a fifth device power supply 664 in the following order. The drain of the first SF 642-1 is electrically coupled to the fourth device power supply 662. The gate of the first SF 642-1 is electrically coupled to the floating diffusion regions 632-1 and 632-2 of the first photodiode group 610-1 and the second photodiode group 610-2. The drain of the first SEL 644-1 is electrically coupled to the source of the first SF 642-1. The first output contact 646-1 is electrically coupled to the source of the first SEL 644-1, the Vout line 648, and the column output line 650. The source of the second SEL 652-1 is electrically coupled to the first output contact 646-1. The source of the second SF 654-1 is electrically coupled to the drain of the second SEL 652-1. The gate of the second SF 654-1 is electrically coupled to the floating diffusion regions 632-1 and 632-2 of the first photodiode group 610-1 and the second photodiode group 610-2. The drain of the second SF 654-1 is electrically coupled to the fifth device power supply 664. Therefore, the devices in the second device line 622 can be symmetrically arranged with respect to the first output contact 646-1.

[0084] The third device line 670 may include, in the following order: a third SF 642-2, a third SEL 644-2, a second output contact 646-2, a fourth SEL 652-2, a fourth SF 654-2, and a sixth device power supply 666. The drain of the third SF 642-2 is electrically coupled to the second device power supply 626. The gate of the third SF 642-2 is electrically coupled to the floating diffusion regions 632-1 and 632-2 of the first photodiode group 610-1 and the second photodiode group 610-2. The drain of the third SEL 644-2 is electrically coupled to the source of the third SF 642-2. The second output contact 646-2 is electrically coupled to the source of the third SEL 644-2, the Vout line 648, and the column output line 650. The source of the fourth SEL 652-2 is electrically coupled to the second output contact 646-2. The source and drain of the fourth SF 654-2 are electrically coupled to the drain of the fourth SEL 652-2 and the third device power supply 660. The gate of the fourth SF 654-2 is electrically coupled to the floating diffusion regions 632-1 and 632-2 of the first photodiode group 610-1 and the second photodiode group 610-2. Therefore, the devices in the third device line 670 can be symmetrically arranged with respect to the second output contact 646-2.

[0085] In the solid-state imaging device array 600 with this configuration, the first device power supply 624 of the first solid-state imaging device 602-1 and the second device power supply 626 of the second solid-state imaging device 602-2 can form a common device power supply 672, wherein the second solid-state imaging device is adjacent to the fourth side 618-1 of the first photodiode group 610-1 opposite to the second side 614-1. Specifically, the first device power supply 624 of the first solid-state imaging device 602-1 and the second device power supply 626 of the second solid-state imaging device 602-2 can share a contact and be connected to a device power line (not shown). The fifth device power supply 664 of the first solid-state imaging device 602-1 and the fourth device power supply 662 of the third solid-state imaging device 602-3 can form a common device power supply 674, wherein the third solid-state imaging device is adjacent to the third side 616-1 of the first photodiode group 610-1 opposite to the first side 612-1 and to the third side 616-2 of the second photodiode group 610-2 opposite to the first side 612-2. Specifically, the fifth device power supply 664 of the first solid-state imaging device 602-1 and the fourth device power supply 662 of the third solid-state imaging device 602-3 can share a contact and be connected to a device power line (not shown). The third device power supply 660 of the first solid-state imaging device 601-1 and the second device power supply 626 of the third solid-state imaging device 601-3 can form a common device power supply 676. Specifically, the third device power supply 660 of the first solid-state imaging device 601-1 and the second device power supply 626 of the third solid-state imaging device 601-3 can share a contact and be connected to a device power line (not shown).

[0086] Therefore, in the solid-state imaging device array 600 with this configuration, the device power supply is used as device isolation between N+ S / D between adjacent device lines, and the device lines do not need to be isolated by STI or non-STI, similar to the solid-state imaging device array 100.

[0087] The solid-state imaging device array 600 includes four SF 642-1, SF 654-1, SF 642-2, and SF654-2 arranged in parallel. Therefore, the source follower gm further improves and enables higher frame rate imaging.

[0088] Furthermore, the variations and effects of the explanation regarding solid-state imaging device array 100 can be applied to solid-state imaging device array 600, provided that the configurations are compatible. (Reference) Figure 4 The method of operating the solid-state imaging device array 100 explained can also be applied to the solid-state imaging device array 600.

[0089] Figure 7 A plan view of a solid-state imaging device array 700 provided in the fourth embodiment of the present invention is shown. Figure 7 (A) shows a plan view of the solid-state imaging device 102-1 in the solid-state imaging device array 700. The solid-state imaging device array 700 may include multiple solid-state imaging devices disposed in the array. Although Figure 7 A first solid-state imaging device 702-1 and a second solid-state imaging device 702-2 are shown as examples, but the number of solid-state imaging devices is not limited to this example, and the array may include, for example, multiple solid-state imaging devices corresponding to a number of pixels. The first solid-state imaging device 702-1 and the second solid-state imaging device 702-2 may include the same configuration as each other. For example, the first solid-state imaging device 702-1 may include: a first photodiode group 710-1, including a first side 712-1 to a fourth side 718-1; a second photodiode group 710-2, including a first side 712-2 to a fourth side 718-2; a first device line 720 disposed along the first side 712-1 of the first photodiode group 710-1; a second device line 722 disposed between a third side 716-1 of the first photodiode group 710-1 opposite to the first side 712-1 and the first side 712-2 of the second photodiode group 710-2; a first device power supply 724 electrically coupled to one end of the first device line 720; a second device power supply 726 electrically coupled to the other end of the first device line 720; a third device power supply 760 electrically coupled to one end of the second device line 722; and a fourth device power supply 762 electrically coupled to the other end of the second device line 722. The second solid-state imaging device 702-2 may include the same configuration.

[0090] The first photodiode group 710-1 and the second photodiode group 710-2 may each include at least one photodiode. Figure 7 In the example shown, the first photodiode group 710-1 includes four photodiodes 730-1 to 730-4. However, the number of photodiodes is not limited to this example. Figure 7 In this configuration, the first photodiode group 710-1 may include a floating diffusion region 732-1 between photodiodes 730-1 to 730-4. The floating diffusion region 732-1 may be shared by photodiodes 730-1 to 730-4. The first photodiode group 710-1 may include charge transport gates 734-1 to 734-4, respectively, between photodiodes 730-1 to 730-4 and the floating diffusion region 732-1. The second photodiode group 710-2 may include the same configuration.

[0091] The configuration of the first device line 720 and the second device line 722 Figures 1 to 3The solid-state imaging device array 100 shown has the same device line configuration, only the device arrangement differs. The first device line 720 may include OFG 740, DCG 738, and RST 736 in the following order: The drain of OFG 740 is electrically coupled to the first device power supply 724. The source of OFG 740 is electrically coupled to the floating diffusion regions 732-1 and 732-2 of the first photodiode group 710-1 and the second photodiode group 710-2. The source of DCG 738 is electrically coupled to the source of OFG 740. The source and drain of RST 736 are electrically coupled to the source of DCG 738 and the second device power supply 726. Therefore, the devices in the first device line 720 can be arranged symmetrically with respect to DCG 738.

[0092] The second device line 722 may include a first SF 742, a first SEL 744, an output contact 746, a second SEL 752, and a second SF 754 in the following order. The drain of the first SF 742 is electrically coupled to a third device power supply 760. The gate of the first SF 742 is electrically coupled to the floating diffusion regions 732-1 and 732-2 of the first photodiode group 710-1 and the second photodiode group 710-2. The drain of the first SEL 744 is electrically coupled to the source of the first SF 742. The output contact 746 is electrically coupled to the source of the first SEL 744, the Vout line 748, and the column output line 750. The source of the second SEL 752 is electrically coupled to the output contact 746. The source and drain of the second source follower device 754 are electrically coupled to the drain of the second SEL 752 and a fourth device power supply 762. Therefore, the devices of the second device line 722 can be arranged symmetrically with respect to the output contact 746.

[0093] In the solid-state imaging device array 700 with this configuration, the first device power supply 724 of the first solid-state imaging device 702-1 and the second device power supply 726 of the second solid-state imaging device 702-2 can form a common device power supply 772, wherein the second solid-state imaging device is adjacent to the second sides 714-1, 714-2 of the first photodiode group 710-1 and the second photodiode group 701-2, and the second sides are adjacent to the first sides 712-1, 712-2. The third device power supply 760 of the first solid-state imaging device 702-1 and the fourth device power supply 762 of the second solid-state imaging device 702-2 can form a common device power supply 774. Specifically, the first device power supply 724 of the first solid-state imaging device 702-1 and the second device power supply 726 of the second solid-state imaging device 702-2 can share a contact and be connected to a device power line (not shown). The third device power supply 760 of the first solid-state imaging device 702-1 and the fourth device power supply 762 of the second solid-state imaging device 702-2 can share a contact and be connected to a device power line (not shown).

[0094] Therefore, in the solid-state imaging device array 700 with this configuration, the device power supply is used as device isolation between N+ S / D between adjacent device lines, and there is no need for isolation between device lines via ST or non-STI.

[0095] Because the device power supply for SF is separate from that for RST, different voltages can be applied to SF and RST.

[0096] Furthermore, the variations and effects of the explanation regarding solid-state imaging device array 100 can be applied to solid-state imaging device array 700, provided that the configurations are compatible. (Reference) Figure 4 The method explained for operating the solid-state imaging device array 100 can also be applied to the solid-state imaging device array 700.

[0097] Figure 8 A partial cross-sectional view of a solid-state imaging device array including multiple solid-state imaging devices 1, provided by some embodiments of the present invention, is shown. The second side 6 of the substrate 2 of the solid-state imaging device 1 can be coupled to an integrated circuit chip 1801 for controlling the solid-state imaging device 1 and processing signals from the solid-state imaging device 1.

[0098] Figure 9 A perspective view of image sensors 1901 to 1905, including solid-state imaging device arrays, provided in some embodiments of the present invention is shown.

[0099] exist Figure 9 In (A), the image sensor 1901 may include a pixel array 1911, a control circuit 1921, and a logic circuit 1931 integrated on a single chip.

[0100] exist Figure 9 In (B), the image sensor 1902 may include a first chip on which a pixel array 1912 and control circuitry 1922 are integrated, and a second chip stacked on the first chip and including logic circuitry 1932.

[0101] exist Figure 9 In (C), the image sensor 1903 may include a first chip with a pixel array 1913 and a second chip stacked on the first chip and having control circuitry 1923 and logic circuitry 1933 integrated thereon.

[0102] exist Figure 9 In (D), the image sensor 1904 may include a first chip with a pixel array 1914, a second chip with a memory circuit 1944, and a third chip with a control circuit 1924 and a logic circuit 1934 integrated thereon. The first chip, the second chip, and the third chip may be stacked.

[0103] exist Figure 9 In (E), the image sensor 1905 may include a first chip with a pixel array 1915, a second chip with pixel circuitry 1955, and a third chip with control circuitry 1925 and logic circuitry 1935 integrated thereon. The first chip, the second chip, and the third chip may be stacked.

[0104] Figure 10 An image sensor 2000 (e.g.) is shown. Figure 9 The image sensor 2000 is shown in the block diagram. The image sensor 2000 may include: a lens 2002; a solid-state imaging device array 2009; a shutter 2003 disposed between the lens 2002 and the solid-state imaging device array 2009; a control circuit 2005 for controlling the solid-state imaging device array 2009 and the shutter 2003; a signal processing circuit 2006 for processing output signals from the solid-state imaging device array 2009; a monitor 2007 for displaying the image processed and output by the signal processing circuit 2006; and a memory 2008 for storing the image processed and output by the signal processing circuit 2006.

[0105] The aforementioned solid-state imaging devices can be applied in various fields, including sports, beauty and personal care, security, home appliances, agriculture, entertainment, transportation, as well as medical, therapeutic, and healthcare applications, such as... Figure 11 As shown. The aforementioned solid-state imaging device can be used as an external monitoring sensor for vehicles, such as... Figure 12 As shown.

[0106] Although embodiments of the present invention have been described illustratively, those skilled in the art will readily understand that various modifications and changes can be made without departing from the spirit and scope of the invention, such as... Figure 12 As shown.

Claims

1. An imaging device array, characterized in that, It includes multiple imaging devices arranged in an array, each imaging device comprising: One or more photodiode groups, each of the photodiode groups including at least one photodiode, a floating diffusion region and a charge transport gate, wherein each charge transport gate is disposed between each photodiode and the floating diffusion region; One or more device lines are arranged along at least one side of the photodiode group, wherein each device line includes a gate and a doped region aligned in a straight line to form a transistor device; Device power supplies are located at points at each end of the device line and at each end of the device line of the adjacent imaging device. The power supply for the device is located at the four vertices of the boundary of the imaging device.

2. The imaging device array according to claim 1, characterized in that, The power supply of the imaging device is shared with adjacent imaging devices.

3. The imaging device array according to claim 1, characterized in that, The one or more device lines include: A first device line is disposed along the first side of the photodiode group; A second device line is disposed along the second side of the photodiode group adjacent to the first side. The power supply for the device includes: The first device power supply is electrically coupled to one end of the first device line; A second device power supply electrically coupled to the other end of the first device line and one end of the second device line; The power supply of the third device is electrically coupled to the other end of the second device line. Each imaging device is configured such that a first device line of a first adjacent imaging device is disposed along a third side of the photodiode group opposite to a first side of the photodiode group of the imaging device, and a second device line of a second adjacent imaging device is disposed along a fourth side of the photodiode group opposite to a second side of the photodiode group of the imaging device. Each imaging device is configured such that the first device power supply of the imaging device and the second device power supply of the second adjacent imaging device together form a first common device power supply, and the third device power supply of the imaging device and the second device power supply of the first adjacent imaging device together form a second common device power supply.

4. The imaging device array according to claim 1, characterized in that, The photodiode group includes: First photodiode group; The second photodiode group is adjacent to the first photodiode group. The device lines are arranged along the first side of the first photodiode group and the first side of the second photodiode group; The power supply for the device includes: A first device power supply electrically coupled to one end of the device line; A second device power supply is electrically coupled to the other end of the device line. Each imaging device is configured such that the first device power supply of the imaging device and the second device power supply of the imaging device adjacent to the second side of the first photodiode group together form a common device power supply, wherein the second side of the first photodiode group is adjacent to the first side of the first photodiode group.

5. The imaging device array according to claim 1, characterized in that, The photodiode group includes: First photodiode group; The second photodiode group is adjacent to the first photodiode group. The device line includes: A first device line is disposed along a first side of the first photodiode group and a first side of the second photodiode group; The second device line is disposed between the second side of the first photodiode group adjacent to the first side of the first photodiode group and the fourth side of the second photodiode group adjacent to the first side of the second photodiode group. A third device line is disposed along the second side of the second photodiode group, which is opposite to the fourth side of the second photodiode group. The power supply for the device includes: The first device power supply is electrically coupled to one end of the first device line; A second device power supply electrically coupled to the other end of the first device line and one end of the third device line; The third device power supply is electrically coupled to the other end of the third device line. Each imaging device is configured such that a first device line of a first adjacent imaging device is disposed along a third side of the first photodiode group and the second photodiode group opposite to the first side of the first photodiode group and the second photodiode group, and a second device line of a second adjacent imaging device is disposed along a fourth side of the first photodiode group opposite to the second side of the first photodiode group. Each imaging device is configured such that the first device power supply of the imaging device and the second device power supply of the second adjacent imaging device together form a first common device power supply, the third device power supply of the imaging device and the second device power supply of the first adjacent imaging device together form a second common device power supply, and the fifth device power supply of the imaging device and the fourth device power supply of the first adjacent imaging device together form a third common device power supply.

6. The imaging device array according to claim 1, characterized in that, The photodiode group includes: First photodiode group; The second photodiode group is adjacent to the first photodiode group. The device line includes: A first device line is disposed along a first side of the first photodiode group; The second device line is disposed between the third side of the first photodiode group and the first side of the second photodiode, which is opposite to the first side of the first photodiode group. The power supply for the device includes: The first device power supply is electrically coupled to one end of the first device line; A second device power supply electrically coupled to the other end of the first device line; A third device power supply electrically coupled to one end of the second device line; The power supply of the fourth device is electrically coupled to the other end of the second device line. Each imaging device is configured such that the first device line of an adjacent imaging device is disposed along the third side of the second photodiode group opposite to the first side of the second photodiode group; Each imaging device is configured such that the first device power supply of the imaging device and the second device power supply of the adjacent imaging device together form a first common device power supply, and the third device power supply of the imaging device and the fourth device power supply of the adjacent imaging device together form a second common device power supply.

7. The imaging device array according to any one of claims 1 to 6, characterized in that, In each imaging device, each of the photodiode groups includes a plurality of photodiodes.

8. The imaging device array according to any one of claims 1 to 6, characterized in that, In each imaging device, the transistor devices of the device line are arranged symmetrically.

9. The imaging device array according to any one of claims 3 to 6, characterized in that, The transistor devices in the first device line include a reset device, a double-conversion gain device, and an overflow gate device, wherein the gate size of the overflow gate device is equal to the gate size of the reset device.

10. The imaging device array according to claim 9, characterized in that, In each imaging device, the size of the gate of the dual-conversion gain device is equal to the size of the gate of the overflow gate device and / or the size of the gate of the reset device.

11. The imaging device array according to any one of claims 3 to 6, characterized in that, The transistor devices in the first device line include a reset device, a dual-conversion gain device, and an overflow gate device. In each imaging device, the length of the gate of the reset device is greater than the length of the gate of the dual-conversion gain device and / or the length of the gate of the overflow gate device.

12. The imaging device array according to any one of claims 1 to 6, characterized in that, In each imaging device, the source and drain regions of each transistor device included in the device line are self-aligned with the gate of each transistor device.

13. The imaging device array according to any one of claims 1 to 6, characterized in that, In each imaging device, a trap pickup, which serves as a pinned photodiode contact for the photodiode group, is disposed between the photodiode group and the device line.

14. The imaging device array according to any one of claims 3 to 6, characterized in that, The transistor devices in the second device line include source follower devices, and in each imaging device, the width of the gate of the source follower device is greater than the length of the gate of the source follower device.

15. The imaging device array according to any one of claims 1 to 6, characterized in that, The charge transport gate has an embedded portion in the substrate.

16. The imaging device array according to any one of claims 1 to 6, characterized in that, Each imaging device includes physical device isolation achieved by shallow trench isolation surrounding at least a portion of the photodiode group, or electrical device isolation achieved by a PN junction surrounding at least a portion of the photodiode group.

17. An electronic device, characterized in that, Includes an imaging device array according to any one of claims 1 to 6.

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