Silicon carbide semiconductor device

Abstract

A silicon carbide semiconductor device (50) includes: an n-type silicon carbide semiconductor substrate (1); an n-type first semiconductor layer (2, 6) having a lower impurity concentration than the silicon carbide semiconductor substrate (1); an n-type first JFET region (6b) provided in a surface layer of the first semiconductor layer and having a higher effective donor concentration than the first semiconductor layer; a p-type second semiconductor layer (3) provided in a surface of the first semiconductor layer on the side opposite to the silicon carbide semiconductor substrate (1); an n-type first semiconductor region (7) selectively provided in a surface layer of the second semiconductor layer; and a trench (16) penetrating the first semiconductor region (7), the second semiconductor layer, and the first JFET region (6b). The first JFET region (6b) is doped with a donor composed of either one of nitrogen and phosphorus and aluminum.

Description

Technical Field

[0001] This invention relates to a silicon carbide semiconductor device. Background Technology

[0002] Silicon (Si) single crystals have traditionally been used as materials for power semiconductor devices that control high voltage and high current. There are several types of silicon power semiconductor devices, currently differentiated according to their applications. For example, PiN diodes (P-intrinsic-N diodes), bipolar transistors, and IGBTs (Insulated Gate Bipolar Transistors) are so-called bipolar devices. While these devices achieve higher current densities, they cannot perform high-speed switching; for example, the operating limit of bipolar transistors is several kHz, and the operating limit of IGBTs is around 20 kHz. On the other hand, power MOSFETs (Metal Oxide Semiconductor Field Effect Transistors), as unipolar devices, cannot achieve high currents but can be used at speeds up to several MHz. However, there is a strong market demand for power devices that combine high current and high speed, leading to efforts to improve silicon IGBTs, power MOSFETs, etc., and current development progress is almost at the physical limits of silicon materials.

[0003] In addition, new material research has been conducted on power semiconductor devices. Silicon carbide (SiC) is expected to be a promising material for next-generation power semiconductor devices, exhibiting low on-state voltage and excellent high-speed / high-temperature characteristics, and has recently attracted particular attention. This is because SiC is a chemically very stable material with a wide bandgap of up to 3 eV, maintaining extreme stability as a semiconductor even at high temperatures. Furthermore, its maximum electric field strength is more than an order of magnitude greater than that of silicon. SiC has the potential to surpass the material limits of silicon, therefore, its future development in power semiconductor applications is highly anticipated.

[0004] As silicon carbide semiconductor devices, products manufactured to date include Schottky Barrier Diodes (SBDs), planar gate structures, and trench gate structures of vertical MOSFETs (Metal Oxide Semiconductor Field Effect Transistors).

[0005] A planar gate structure is a MOS gate structure in which the MOS gate is arranged in a planar shape on the front side of a semiconductor substrate. A trench gate structure is a MOS gate structure in which the MOS gate is buried in a trench formed on the front side of the semiconductor substrate (semiconductor chip), and a channel (inversion layer) is formed along the sidewalls of the trench in a direction orthogonal to the front side of the semiconductor substrate. Therefore, compared to a planar gate structure where the channel is formed along the front side of the semiconductor substrate, it is possible to increase the unit cell (structural unit of the element) density per unit area and the current density per unit area, thus offering an advantage in terms of cost.

[0006] In this trench gate structure, to prevent the electric field from concentrating on the bottom surface of the trench, p+ type base regions are selectively provided at the bottom of the trench and between the trenches. In a 1.2kV trench gate MOSFET formed on a 4H-SiC substrate, the n-type region (JFET region) between the sidewall of the trench and the p+ type base region between the trenches is divided by a factor of 1×10. 17 / cm 3 The impurity concentration was such that only nitrogen (N) was implanted in the form of ions to form a layer.

[0007] In addition, the following technology is proposed: by forming a region with different carrier concentrations (channel resistance adjustment region) on the surface of the well region, the saturation current is suppressed and the short-circuit withstand capability is improved compared with a semiconductor device in which the carrier concentration in the channel is uniform and the on-resistance is the same (for example, see Patent Document 1 below).

[0008] In addition, the following technique was proposed: by setting the length of the JFET region to less than 3 μm, and setting the impurity density Nd of the JFET region to be greater than or equal to the impurity density of the drift layer, i.e., 1 × 10⁻⁶. 16 cm -3 In this way, the on-resistance is reduced, and the overcurrent during a short circuit is reduced (for example, see Patent Document 2 below).

[0009] Existing technical documents

[0010] Patent Document 1: International Publication No. 2015 / 198468

[0011] Patent Document 2: Japanese Patent Application Publication No. 2011-159797 Summary of the Invention

[0012] Technical issues

[0013] In a MOSFET, during a load short-circuit fault, if a short circuit occurs between the drain and source, a high voltage is applied to the device in the on-state, resulting in a large instantaneous current flow and a rapid rise in the internal junction temperature to around 1000K. As the internal junction temperature rises, the device resistance increases, the current decreases, but the device temperature continues to rise, sometimes leading to thermal damage due to electrode melting. Therefore, it is desirable for the MOSFET to remain undamaged for at least 10μs before the gate-cutting protection circuit detects a short circuit and activates. Consequently, a small short-circuit current and minimal heat loss are required.

[0014] However, generally speaking, there is a trade-off between on-resistance and short-circuit withstand capability. In the case of low-resistance devices such as trench-gate MOSFETs with increased channel density, a large current flows during a short circuit, resulting in a lower short-circuit withstand capability compared to planar gate structures (see Reference 1). Due to the low short-circuit withstand capability of trench-type silicon carbide semiconductor devices, thermal damage can sometimes occur to the device within the time (approximately 10 μs) before the protection circuit activates.

[0015] Reference 1: R. Green, Mat. Sci. Forum 924 (2018) pp. 715

[0016] The purpose of this invention is to eliminate the problems of the prior art described above and to provide a silicon carbide semiconductor device that can improve short-circuit withstand capability while maintaining the on-resistance of the element.

[0017] Technical solution

[0018] To solve the above problems and achieve the objective of this invention, the silicon carbide semiconductor device of this invention has the following features: An n-type first semiconductor layer with an impurity concentration lower than that of the silicon carbide semiconductor substrate is disposed on the front side of an n-type silicon carbide semiconductor substrate. An n-type first JFET region with an effective donor concentration higher than that of the first semiconductor layer is disposed on the surface layer of the first semiconductor layer. A p-type second semiconductor layer is disposed on the surface of the first semiconductor layer opposite to the silicon carbide semiconductor substrate. The n-type first semiconductor region is selectively disposed on the surface layer of the second semiconductor layer. A trench is disposed penetrating the first semiconductor region, the second semiconductor layer, and the first JFET region. A gate electrode is disposed inside the trench, separated by a gate insulating film. An interlayer insulating film is disposed on the gate electrode. A first electrode is disposed in contact with the first semiconductor region and the second semiconductor layer. A second electrode is disposed on the back side of the silicon carbide semiconductor substrate. The first JFET region is doped with a donor composed of either nitrogen or phosphorus and aluminum, wherein the doping concentration of the donor is greater than the doping concentration of the aluminum.

[0019] Furthermore, the silicon carbide semiconductor device of the present invention is characterized in that, in the above-described invention, the donor concentration is 7 × 10⁻⁶. 16 / cm 3 Above and 7×10 17 / cm 3 Hereinafter, the concentration of aluminum is 10% or more but less than 100% of the concentration of the donor.

[0020] Furthermore, the silicon carbide semiconductor device of the present invention is characterized in that, in the above-described invention, the concentration of the donor ( / cm³) 3 Let X be a constant between 0.1 and 0.99, and let the concentration of aluminum ( / cm³) be... 3 When denoted as aX, the donor concentration X satisfies the following relationship:

[0021] X≥(7×10 16 ) / (1-a)

[0022] X≤(7×10 17 ) / (1-a).

[0023] Furthermore, the silicon carbide semiconductor device of the present invention is characterized in that, in the above-described invention, the effective donor concentration of the first JFET region is 7 × 10⁻⁶. 16 / cm 3 Above and 7×10 17 / cm 3 the following.

[0024] Furthermore, the silicon carbide semiconductor device of the present invention is characterized in that, in the above-described invention, the effective donor concentration of 7 × 10⁻⁶ is satisfied within the actual operating temperature range of the element, 245K to 524K. 16 / cm 3 Above and 7×10 17 / cm 3 The following range.

[0025] Furthermore, the silicon carbide semiconductor device of the present invention is characterized in that, in the above-described invention, the effective donor concentration of 7 × 10⁻⁶ is satisfied within the actual operating temperature range of the element, which is 300 K to 448 K. 16 / cm 3 Above and 7×10 17 / cm 3 The following range.

[0026] Furthermore, the silicon carbide semiconductor device of the present invention is characterized in that, in the above invention, the first semiconductor layer includes: a drift layer having the same impurity concentration as the first semiconductor layer; and an n-type second JFET region disposed between the first JFET region and the drift layer, wherein the effective donor concentration is higher than the effective donor concentration of the drift layer.

[0027] Furthermore, the silicon carbide semiconductor device of the present invention is characterized in that, in the above invention, the second JFET region is doped with the donor and the aluminum, wherein the doping concentration of the donor is greater than the doping concentration of the aluminum.

[0028] Furthermore, the silicon carbide semiconductor device of the present invention is characterized in that, in the above-described invention, the silicon carbide semiconductor device further comprises: a p-type first base region, which is located inside the first semiconductor layer, between a plurality of periodically disposed trenches, to separate the first JFET and is grounded to the second semiconductor layer; and a p-type second base region, which is located inside the first semiconductor layer at a position opposite to the bottom of the trenches in the depth direction.

[0029] According to the invention described above, a donor composed of either N or P and Al are simultaneously doped in the JFET1 region (the first semiconductor layer between the trench and the first base region). Taking advantage of the temperature-dependent ionization of Al, the n-type concentration in the JFET1 region is reduced at high temperatures, thereby increasing the JFET resistance when short-circuited and reaching high temperatures, thus suppressing short-circuit current. Therefore, the short-circuit current can be reduced while maintaining the on-resistance of the device, improving short-circuit withstand capability.

[0030] Invention Effects

[0031] The silicon carbide semiconductor device according to the present invention has the effect of improving short-circuit withstand capability while maintaining the on-resistance of the element. Attached Figure Description

[0032] Figure 1 This illustrates the structure of a silicon carbide semiconductor device according to an embodiment. Figure 2 A-A' cross-sectional view.

[0033] Figure 2 This illustrates the structure of a silicon carbide semiconductor device according to an embodiment. Figure 1 The top view of B-B'.

[0034] Figure 3 This illustrates the structure of a silicon carbide semiconductor device according to an embodiment. Figure 1 The top view of C-C'.

[0035] Figure 4This is a graph showing the temperature dependence of Al ionization rate.

[0036] Figure 5 This is a graph showing the temperature dependence of the effective donor concentration Nd-Na during N+Al co-doping.

[0037] Figure 6 This is a graph showing the relationship between the effective donor concentration and the short-circuit current in the JFET1 region.

[0038] Figure 7 It is a graph showing the relationship between the effective donor concentration in the JFET1 region and the short-circuit current, as well as the relationship between the effective donor concentration in the JFET1 region and the device temperature.

[0039] Figure 8 It is a graph showing the relationship between the effective donor concentration and the on-resistance (RonA) of the JFET1 region, and the relationship between the effective donor concentration and the withstand voltage of the JFET1 region.

[0040] Figure 9 This is a cross-sectional view showing the electric field when the silicon carbide semiconductor device is turned off.

[0041] Figure 10 It is shown Figure 9 The graph shows the relationship between the maximum electric field of the oxide film and the effective donor concentration in the JFET1 region.

[0042] Figure 11 This is a cross-sectional view (one of the embodiments) schematically showing the state of the manufacturing process of the silicon carbide semiconductor device.

[0043] Figure 12 This is a cross-sectional view (second one) schematically showing the state of the manufacturing process of the silicon carbide semiconductor device according to the embodiment.

[0044] Figure 13 This is a cross-sectional view (third one) schematically showing the state of the manufacturing process of the silicon carbide semiconductor device according to the embodiment.

[0045] Figure 14 This is a cross-sectional view (fourth one) schematically showing the state of the manufacturing process of the silicon carbide semiconductor device according to the embodiment.

[0046] Figure 15 This is a cross-sectional view (fifth) schematically showing the state of the manufacturing process of the silicon carbide semiconductor device according to the embodiment.

[0047] Figure 16 This is a cross-sectional view (sixth) schematically showing the state of the manufacturing process of the silicon carbide semiconductor device according to the embodiment.

[0048] Figure 17 This is a cross-sectional view (seventh) schematically showing the state of the manufacturing process of the silicon carbide semiconductor device according to the embodiment.

[0049] Figure 18 This is a cross-sectional view (eighth) schematically showing the state of the manufacturing process of the silicon carbide semiconductor device according to the embodiment.

[0050] Symbol Explanation

[0051] 1: n+ type silicon carbide substrate

[0052] 2: n-type silicon carbide epitaxial layer

[0053] 2a: First n-type silicon carbide epitaxial layer

[0054] 2b: Second n-type silicon carbide epitaxial layer

[0055] 3: P-type base layer

[0056] 4: First p+ type base region

[0057] 4a: First p+ type region

[0058] 4b: Second p+ type region

[0059] 5: Second p+ type base region

[0060] 6: n-type high concentration area

[0061] 6a: First n-type region

[0062] 6b: Second n-type region

[0063] 7: n+ type source region

[0064] 8: p++ type contact area

[0065] 9: Gate insulating film

[0066] 10: Gate electrode

[0067] 11: Interlayer insulating film

[0068] 12: Ohmic electrode

[0069] 13: Drain electrode

[0070] 14: Source Electrode

[0071] 15: Blocking metal

[0072] 16: Trench

[0073] 21: JFET1 region (first JFET region)

[0074] 22: JFET2 region (second JFET region)

[0075] 23: Mask

[0076] 50: Trench MOSFET Detailed Implementation

[0077] Hereinafter, preferred embodiments of the silicon carbide semiconductor device of the present invention will be described in detail with reference to the accompanying drawings. In this specification and the drawings, layers and regions prefixed with n or p respectively indicate that electrons or holes are the majority carriers. Furthermore, the + and - symbols for n and p respectively indicate high and low impurity concentrations compared to layers and regions without + and - symbols. When the n and p symbols containing + and - are the same, they represent similar concentrations, but the concentrations are not limited to being equal. Impurity concentrations are generally expressed in terms of 3 × 10⁻⁶. 17 / cm 3 This is the format shown, but in this specification, abbreviated forms such as 3e17, 3E17, and 3E+17 are also used. Where the numerical value clearly indicates the concentration, the unit of concentration ( / cm³) is omitted. 3 It should be noted that in the following description and drawings of the embodiments, the same reference numerals are used to refer to the same structures, and repeated descriptions are omitted. Furthermore, considering manufacturing variations, it is preferable that identical or equivalent descriptions be included within 5%.

[0078] (Implementation Method)

[0079] The semiconductor device of the present invention is constructed using a wide-bandgap semiconductor. In an embodiment, a silicon carbide semiconductor device, which is made (manufactured) using silicon carbide (SiC) as a wide-bandgap semiconductor, will be described using a MOSFET as an example. Figure 1 This illustrates the structure of a silicon carbide semiconductor device according to an embodiment. Figure 2 A-A' cross-sectional view. Figure 2 This illustrates the structure of a silicon carbide semiconductor device according to an embodiment. Figure 1 The top view of B-B'. Figure 3 This illustrates the structure of a silicon carbide semiconductor device according to an embodiment. Figure 1 The top view of C-C'. Figures 1-3 An example of a trench MOSFET50 is shown.

[0080] like Figure 1 As shown, in the embodiment, an n-type silicon carbide epitaxial layer 2 is deposited on the first main surface (front side) of an n+ type silicon carbide substrate (n-type silicon carbide semiconductor substrate) 1, such as the (0001) surface (Si surface).

[0081] The n+ type silicon carbide substrate 1 is a single-crystal silicon carbide substrate. The n- type silicon carbide epitaxial layer 2 is, for example, a low-concentration n-type drift layer with an impurity concentration lower than that of the n+ type silicon carbide substrate 1. An n-type high-concentration region 6 is provided on the surface of the n-type silicon carbide epitaxial layer 2 opposite to the n+ type silicon carbide substrate 1. The n-type high-concentration region 6 is a high-concentration n-type drift layer with an impurity concentration lower than that of the n+ type silicon carbide substrate 1 and higher than that of the n-type silicon carbide epitaxial layer 2. More specifically, the n-type high-concentration region 6 is composed of a first n-type region 6a and a second n-type region 6b. As a functional name for the MOSFET structure, the first n-type region 6a can also be called JFET2 region 22 (second JFET region), and the second n-type region 6b can also be called JFET1 region 21 (first JFET region). Here, as will be described in detail later, in region 21 of JFET1, both nitrogen (N) and aluminum (Al) are intentionally doped (co-doped), with the N doping concentration being greater than the Al doping concentration. On the other hand, region 22 of JFET2 is at least doped with N, and may also be intentionally doped with Al. If Al is intentionally doped in region 22 of JFET2 for co-doping, the breakdown voltage may decrease depending on the amount, so it is preferable to have less Al doping than in region 21 of JFET1. The n-type carrier concentrations of regions 21 of JFET1 and 22 of JFET2 are set to be lower than the n-type carrier concentration of the n+ type silicon carbide substrate 1 and higher than the n-type carrier concentration of the n-type silicon carbide epitaxial layer 2. If the carrier concentration of region 22 of JFET2 is reduced to the same level as the carrier concentration of the n-type silicon carbide epitaxial layer 2, the device resistance increases, so the carrier concentration is increased. It should be noted that phosphorus can also be used instead of nitrogen as a donor.

[0082] A p-type substrate (a p-type second semiconductor layer) 3 is provided on the surface side of the n-type high-concentration region 6 opposite to the n+ type silicon carbide substrate 1. Hereinafter, the n+ type silicon carbide substrate 1, the n-type silicon carbide epitaxial layer 2, and the p-type substrate 3 are collectively referred to as the silicon carbide semiconductor substrate.

[0083] A drain electrode 13, serving as a back electrode, is provided on the second main surface (back side, i.e., the back side of the silicon carbide semiconductor substrate) of the n+ type silicon carbide substrate 1. The drain electrode 13 is provided, for example, by sequentially stacking titanium, nickel, and gold. Molybdenum can also be used instead of titanium.

[0084] A trench structure is formed on the first main surface side (p-type substrate 3 side) of the silicon carbide semiconductor substrate. Specifically, the trench 16 extends from the surface of the p-type substrate 3, opposite to the n+ type silicon carbide substrate 1 side (the first main surface side of the silicon carbide semiconductor substrate), through the p-type substrate 3 to the n-type high-concentration region 6. Furthermore, the trench 16 is striped. A gate insulating film 9 is formed along the inner wall of the trench 16 at the bottom and sidewalls, and a gate electrode 10 is formed inside the gate insulating film 9 within the trench 16. The gate electrode 10 is insulated from the n-type high-concentration region 6 and the p-type substrate 3 through the gate insulating film 9. A portion of the gate electrode 10 may also protrude from above the trench 16 (on the side where the source electrode 14, described later, is located) toward the source electrode 14 side. The gate electrode 10 is covered by an interlayer insulating film 11. The interlayer insulating film 11 is covered by a barrier metal 15 composed of titanium or titanium and titanium nitride. The p-type substrate 3 is connected to the first p+ type base region 4. Inside the p-type substrate 3, an n+ type source region (n-type first semiconductor region) 7 is provided on the first main surface side of the substrate. Alternatively, a p++ type contact region 8 may be selectively provided. In this case, the n+ type source region 7 and the p++ type contact region 8 are connected to each other. The n+ type source region 7 and the p++ type contact region 8 are connected to the source electrode 14 via an ohmic electrode 12 made of nickel or the like that forming silicide. The source electrode 14 is made of aluminum or an aluminum alloy containing silicon and is connected to an external circuit using bonding wires made of aluminum or the like. Alternatively, a nickel / phosphorus-based plating may be formed on the surface of the source electrode 14 and wiring conductors may be connected to an external circuit by soldering.

[0085] A first p+ type base region (a first p-type base region) 4 is selectively disposed on the side of the n-type high-concentration region 6 opposite to the n+ type silicon carbide substrate 1 side (the first main surface side of the silicon carbide semiconductor substrate). The first p+ type base region is disposed at least on the surface layer of the n-type high-concentration region 6 on the side opposite to the n+ type silicon carbide substrate 1 side (the first main surface side of the silicon carbide semiconductor substrate). The first p+ type base region 4 is separated from the trench 16 and reaches a position deeper towards the drain side than the bottom of the trench 16. With the first p+ type base region (a first p-type base region) 4 disposed, the JFET 1 region 21 is divided by the first p+ type base region 4 among the plurality of trenches 16.

[0086] A second p+ type base region (p-type second base region) 5 is provided at a position opposite to the bottom of the trench 16 in the depth direction. The width of the second p+ type base region 5 is the same as or wider than the width of the trench 16. The bottom of the trench 16 can reach the second p+ type base region 5, or it can be located within an n-type high-concentration region 6 sandwiched between the p-type base layer 3 and the second p+ type base region 5. The first p+ type base region 4 and the second p+ type base region 5 are doped with, for example, aluminum (Al). If sufficient protection can be provided in the event of avalanche breakdown, only the second p+ type base region 5 at the bottom of the trench 16 can be retained, while the first p+ type base region 4 can be omitted.

[0087] Alternatively, it can be a structure in which a portion of the first p+ type base region 4 extends toward the trench side and connects with the second p+ type base region 5. For example... Figure 2 As shown, a portion of the first p+ type base region 4a, which is closer to the drain side than the bottom of the trench 16, can extend in a direction perpendicular to the extension direction of the trench and connect with the second p+ type base region 5. Since the first p+ type region 4a and the second p+ type base region 5 are formed and connected simultaneously, they form a lattice structure in the plane. Furthermore, Figure 1 The second p+ type region 4b, which is located further from the source side than the bottom of trench 16 in the first p+ type base region 4, is as follows: Figure 3 The stripes shown are striped and formed in a direction parallel to the extension direction of the grooves. Furthermore, as... Figure 1 As shown, the second p+ type region 4b is connected to the first p+ type region 4a and the p-type base layer 3. Alternatively, a portion of the second p+ type region 4b can extend perpendicularly to the trench extension direction and connect to the second p+ type base region 5. By connecting the first p+ type region 4a, the second p+ type region 4b, the second p+ type base region 5, and the p-type base layer 3, holes generated during avalanche breakdown at the junction of the second p+ type base region 5 and the n-type high-concentration region 6 are efficiently repelled to the source electrode 14, thereby reducing the burden on the gate insulating film 9 and improving reliability. Figure 1 The middle figure shows the location where the first p+ type base region 4 and the second p+ type base region 5 are separately configured. Figure 2 and Figure 3 The A-A' section. Regarding the above... Figure 1 The component structure, broadly speaking, can be understood as a structure in which a first semiconductor layer and a second semiconductor layer are disposed on an n+ type silicon carbide substrate 1. Here, the first semiconductor layer is a layer obtained by combining an n- type silicon carbide epitaxial layer 2, a first p+ type base region 4, a second p+ type base region 5, and an n-type high-concentration region 6. Furthermore, the second semiconductor layer is a layer obtained by combining an n+ type source region 7 and a p-type base layer 3 containing p++ type contact regions 8.

[0088] Here, Figure 4 This is a graph showing the calculated temperature dependence of Al ionization rate. Figure 4 In the diagram, the vertical axis represents the Al ionization rate, expressed as a percentage (%). The horizontal axis represents the temperature, expressed in Kelvin (K). The damage temperature of components during a short circuit is generally known to be around 1000 K, therefore it is recorded up to 1000 K. For example... Figure 4As shown, Al has a deep energy level, therefore its ionization rate is around 10-20% near room temperature, but it approaches 100% at higher temperatures (above 800K). It can be assumed that within the intended operating temperature range of semiconductor devices (above 233K and below 448K), for example, at Al concentrations of 7.5e16, 5.0e16, and 2.5e16 / cm³, ionization can be achieved. 3 Under these conditions, the Al ionization rate varied within the ranges of 3%–62%, 4%–68%, and 5%–78%, respectively.

[0089] in addition, Figure 5 This is a graph showing the calculated temperature dependence of the effective donor concentration Nd-Na in N+Al co-doping. The effective donor concentration Nd-Na is the effective ionized donor concentration obtained by subtracting the acceptor concentration (e.g., the ionized Al concentration) from the donor concentration Nd (e.g., the ionized N concentration). Figure 5 In the middle, the vertical axis shows the effective donor concentration Nd-Na, in units of / cm³. 3 The horizontal axis represents temperature, in Kelvin (K). Figure 5 The study presents the temperature dependence for three cases where the ratio of N concentration to Al concentration is changed. For example, Figure 5 The N / Al ratio of 5.3e17 / 5e17 indicates a N concentration of 5.3 × 10⁻⁶. 17 / cm 3 Al concentration is 5×10 17 / cm 3 An example is given when the Al / N ratio is 0.94 (94%). N is also ionized 100% near room temperature, whereas the ionization rate of Al depends on temperature. Figure 4 Therefore, the effective donor concentration of Nd-Na varies with temperature. Figure 5 With an N / Al ratio of 5.3e17 / 5e17, the effective donor concentrations of Nd-Na at room temperature (approximately 300 K), 400 K, 600 K, and 800 K are 5e17, 4e17, 2e17, and 8e16, respectively. The effective donor concentration of Nd-Na decreases with increasing temperature. That is, at room temperature (approximately 300 K), the effective donor concentration of Nd-Na is roughly dominated by the N concentration. Conversely, as the temperature rises and Al ionization occurs, carrier compensation occurs, leading to a decrease in effective Nd-Na.

[0090] in addition, Figure 6 This is a graph showing the simulation results of the relationship between the doping concentration and short-circuit current in the JFET1 region. Figure 6In the diagram, the vertical axis represents the drain current in amperes (A). The horizontal axis represents the load short-circuit time in seconds (s). JFET1 region 21 is the portion of the second n-type region 6b sandwiched between the sidewall of trench 16 and the second p+ type region 4b. JFET2 region 22 is the portion of the first n-type region 6a sandwiched between the second p+ type base region 5 and the first p+ type region 4a (see reference). Figures 1-3 The doping concentrations shown in Figure 2.5E+17 to 3.3E+16 are the effective donor concentrations Nd-Na set at room temperature (300K). In this simulation, if a short circuit occurs at time 0, the drain current increases sharply, but reaches a maximum at approximately 1 μs and then decreases. This is due to the increased resistance caused by device heating, which limits the current. In the case of co-doping of the JFET1 region, the effective donor concentration decreases with increasing device temperature; however, this simulation does not consider the temperature variation of Al ionization in the JFET1 region. Figure 4 The effective donor concentration at any point on the horizontal axis is set to the same initial value as the room temperature shown in the figure. Therefore, in the simulated waveforms shown from 2.5E+17 to 3.3E+16, in Figure 6 The drain current behavior, which takes into account the decrease in effective donor concentration caused by time changes (temperature rise), changes from a high-concentration waveform to a low-concentration waveform over time (temperature rise).

[0091] in addition, Figure 7 This is a graph showing the simulation results of the relationship between the effective donor concentration in region 1 of the JFET and the short-circuit current, and the relationship between the effective donor concentration in region 1 of the JFET and the device temperature. Figure 7 In the diagram, the left vertical axis represents the short-circuit current (Isc max), in A, and the right vertical axis represents the component temperature (Tj max), in K. For example... Figure 6 The calculations show that the short-circuit current (Isc max) is the maximum value of the drain current over time, and the element temperature (Tj max) is the highest junction temperature of the element during the short circuit. The horizontal axis represents the effective donor concentration Nd-Na in region 21 of JFET1, in units of / cm². 3 .like Figure 6 and Figure 7 As shown, if the Nd-Na in region 21 of JFET1 is reduced, the short-circuit current during short circuit is significantly reduced.

[0092] in addition, Figure 8 This is a graph showing the relationship between the effective donor concentration and on-resistance (RonA) of the JFET1 region and the relationship between the effective donor concentration and breakdown voltage (BV) of the JFET1 region. Figure 8 In the diagram, the left vertical axis represents the on-resistance (RonA), with units equal to the effective donor concentration of 1.0 × 10⁻⁶ in region 21 of JFET1.17 / cm 3 The time is set to a relative unit of 1. The right vertical axis represents the withstand voltage (BV), in V. The horizontal axis represents the effective donor concentration Nd-Na in region 21 of JFET1, in / cm². 3 .

[0093] like Figure 8 As shown, the on-resistance increases when the effective donor concentration Nd-Na in region 21 of JFET1 is reduced. Therefore, in this embodiment, a predetermined amount of Al+N is co-doped (co-implanted) into region 21 of JFET1 to make region 21 of JFET1 above the range where the on-resistance does not increase (e.g., 7.0 × 10⁻⁶). 16 / cm 3 (Above), thereby making the impurity concentration in region 21 of JFET1 higher near room temperature and lower at high temperature, thereby suppressing the increase of on-resistance and suppressing short-circuit current.

[0094] in addition, Figure 9 This is a cross-sectional view near the bottom of the trench, showing the results of a simulation of the electric field when the silicon carbide semiconductor device is turned off. The electric field intensity is indicated by contour lines. It can be seen that the electric field intensity in the oxide film is the largest in the part where the oxide film on the trench side meets the JFET1 region 21. Figure 10 It is shown Figure 9 The graph shows the relationship between the maximum electric field of the oxide film and the effective donor concentration in region 21 of JFET1. Figure 9 The data shows a drain voltage Vd of 600V, a gate voltage Vg of -5V, and an effective donor concentration of Nd-Na of region 21 in JFET1 of 6.0 × 10⁻⁶. 17 / cm 3 The electric field of a silicon carbide semiconductor device when it is turned off. Figure 10 In the diagram, the vertical axis represents the maximum electric field of the oxide film (Max Eox), in V / cm, and the horizontal axis represents the effective donor concentration Nd-Na in region 21 of JFET1, in / cm². 3 .

[0095] like Figure 10 As shown, increasing the effective donor concentration Nd-Na in region 21 of JFET1 increases the oxide film electric field at turn-off. If the value of the oxide film electric field, 3 MV / cm, is set as the limit for maintaining long-term reliability (refer to reference 2 below), then 7 × 10⁻⁶... 17 / cm 3 This becomes the upper limit of the effective donor concentration Nd-Na in JFET1 region 21.

[0096] (Reference 2) Sumi Krishnaswami, et al., Mat. Sci. Forum 527-529 (2006) pp. 1313

[0097] Thus, the upper limit of the N concentration is determined by the upper limit of the oxide film electric field at turn-off, and the lower limit is determined by the limit of the increase in on-resistance. Furthermore, the upper limit of the Al concentration is set below the N concentration to prevent JFET1 region 21 from becoming p-type. Additionally, the lower limit is preferably 10% or more of the N concentration, as it allows for a significant change in Nd-Na concentration. Therefore, for JFET1 region 21, N is preferably set to 7 × 10⁻⁶. 16 / cm 3 Above and 7×10 17 / cm 3 The following concentrations are provided, where Al is 10% or more of the N concentration and less than the N concentration (i.e., less than 100% of the N concentration). Furthermore, for intentional Al doping, it is more preferable to set the Al concentration to 30% or more of the N concentration. Additionally, a predetermined amount of Al+N may be co-doped in the JFET2 region 22. Thus, by maintaining a high impurity concentration in the JFET2 region 22 near room temperature and decreasing it at high temperatures, the increase in on-resistance and short-circuit current can be suppressed.

[0098] In addition, when the nitrogen concentration ( / cm) 3 Let X be the value of aluminum, a be a constant between 0.1 and 0.99, and let the concentration of aluminum ( / cm³) be the value of aluminum. 3 When denoted as aX, the nitrogen concentration X can be set to satisfy the following relationship:

[0099] X≥(7×10 16 ) / (1-a)····Equation (1)

[0100] X≤(7×10 17 ) / (1-a)····Equation (2)

[0101] That is, a represents the Al / N ratio, equation (1) becomes the lower limit Xmin of N concentration, and equation (2) becomes the upper limit Xmax of N concentration. The estimation results of this relationship are shown in Table 1.

[0102] Table 1

[0103] 0.1 7.8E+16 7.8E+17 0.2 8.8E+16 8.8E+17 0.3 1.0E+17 1.0E+18 0.4 1.2E+17 1.2E+18 0.5 1.4E+17 1.4E+18 0.6 1.8E+17 1.8E+18 0.7 2.3E+17 2.3E+18 0.8 3.5E+17 3.5E+18 0.9 7.0E+17 7.0E+18 0.95 1.4E+18 1.4E+19 0.99 7.0E+18 7.0E+19

[0104] The p-type substrate 3 is connected to the first p+ type base region 4. Inside the p-type substrate 3, an n+ type source region (n-type first semiconductor region) 7 is provided on the first main surface side of the substrate. Alternatively, a p++ type contact region 8 may be selectively provided. In this case, the n+ type source region 7 and the p++ type contact region 8 are connected to each other.

[0105] An n-type high-concentration region 6 can be formed in the region of the surface layer on the first main surface side of the n-type silicon carbide epitaxial layer 2 that is sandwiched between the first p+ type base region 4 and the second p+ type base region 5, and in the region sandwiched between the p-type base region 3 and the second p+ type base region 5. This n-type high-concentration region 6 is formed at a deeper location than the first p+ type base region 4 and the second p+ type base region 5. Therefore, the depth (thickness) of the n-type high-concentration region 6 is greater than the depth (thickness) of the first p+ type base region 4 and the second p+ type base region 5. Alternatively, the first p+ type base region 4 and the second p+ type base region 5 can be formed at the same depth. Furthermore, the n-type high-concentration region 6 can be formed on the drain side of the first p+ type base region 4 and the second p+ type base region 5 in a manner that surrounds them.

[0106] exist Figure 1 In the diagram, half of the structure of a trench MOS structure is shown on each side. However, more trench structures of MOS gate (insulating gate composed of metal-oxide-semiconductor) structures can also be arranged side by side and periodically.

[0107] An interlayer insulating film 11 is provided on the entire surface of the first main surface of the silicon carbide semiconductor substrate, covering the gate electrode 10 buried in the trench. An ohmic electrode 12, in contact with the n+ type source region 7 and the p-type substrate 3, and a source electrode (first electrode) 14 covering the ohmic electrode 12 are provided via contact holes opening in the interlayer insulating film 11. When a p++ type contact region 8 is provided, the ohmic electrode 12 is in contact with both the n+ type source region 7 and the p++ type contact region 8. The ohmic electrode 12 is electrically insulated from the gate electrode 10 by the interlayer insulating film 11.

[0108] (Method for manufacturing a silicon carbide semiconductor device according to the embodiments)

[0109] Next, the manufacturing method of the silicon carbide semiconductor device according to the embodiment will be described. Figures 11-17 This is a cross-sectional view schematically illustrating the state of the manufacturing process of the silicon carbide semiconductor device according to an embodiment.

[0110] First, such as Figure 11 As shown, an n+ type silicon carbide substrate 1 made of n-type silicon carbide is prepared. Then, on the first main surface of the n+ type silicon carbide substrate 1, while doping with n-type impurities, such as nitrogen atoms, a first n- type silicon carbide epitaxial layer 2a made of silicon carbide is epitaxially grown to a thickness of, for example, about 30 μm. This first n- type silicon carbide epitaxial layer 2a becomes the n- type silicon carbide epitaxial layer 2. Assuming a withstand voltage of 600V to 6.5kV, the impurity concentration of the n+ type silicon carbide substrate 1 is, for example, 8e18 / cm³. 3 Left and right, but it can also be set to 1e18 / cm 3 ~1e19 / cm3 The impurity concentration of the first n-type silicon carbide epitaxial layer 2a is, for example, about 3e15, but it can also be set to 1e15 / cm. 3 ~2e16 / cm 3 .

[0111] Next, on the surface of the first n-type silicon carbide epitaxial layer 2a, a mask 23 with the desired opening is formed from an oxide film using photolithography. Then, using this oxide film as the mask 23, p-type impurities, such as aluminum atoms, are implanted via ion implantation. Thus, as... Figure 11 As shown, in a portion of the surface region of the first n-type silicon carbide epitaxial layer 2a, a first p+ type region 4a and a second p+ type base region 5 are formed, for example, with a depth of approximately 0.5 μm, such that the distance between adjacent first p+ type regions 4a and second p+ type base regions 5 is approximately 1.5 μm. The Al dosage used during ion implantation to form the first p+ type regions 4a and second p+ type base regions 5 is set such that the impurity concentration of the first p+ type regions 4a and second p+ type base regions 5 is, for example, 3e18 / cm³. 3 Left and right, but it can also be set to 1e18 / cm 3 ~6e18 / cm 3 The range. The state up to this point is as follows: Figure 11 As shown.

[0112] Next, as Figure 12 As shown, the mask 23 used during ion implantation to form the first p+ type region 4a and the second p+ type base region 5 is removed. Then, n-type impurities, such as nitrogen atoms, can be ion implanted using ion implantation. Thus, as... Figure 12 As shown, a first n-type region 6a is formed between the first p+ type region 4a and the second p+ type base region 5 on the surface layer of the first n-type silicon carbide epitaxial layer 2a, at a depth of 0.2 to 0.5 μm deeper than the first p+ type region 4a and the second p+ type base region 5. Here, the first n-type region 6a is formed to surround the lower side (n+ type silicon carbide substrate 1 side) of the first p+ type region 4a and the second p+ type base region 5. The ion implantation dose used to form the first n-type region 6a can also be set to, for example, an impurity concentration of 5 × 10⁻⁶. 16 / cm 3 The first p+ type region 4a and the second p+ type base region 5 are set to, for example, Al of approximately 3e18. This region is also implanted with nitrogen via ions, but the nitrogen impurity concentration is about two orders of magnitude lower, having almost no effect. Therefore, the mask is omitted in this process. Alternatively, it could be assumed that, even if there were concerns about the impact, the first p+ type region 4a and the second p+ type base region 5 could be covered with a mask. The state up to this point is as follows... Figure 12 As shown.

[0113] Next, as Figure 13 As shown, while doping the surface of the first n-type silicon carbide epitaxial layer 2a with an n-type impurity such as nitrogen atoms, a second n-type silicon carbide epitaxial layer 2b is epitaxially grown to a thickness of, for example, about 0.5 μm. The layer consisting of this second n-type silicon carbide epitaxial layer 2b, the first n-type silicon carbide epitaxial layer 2a, and the n-type silicon carbide epitaxial layer 2b constitutes the first semiconductor layer. The epitaxial growth conditions used to form the second n-type silicon carbide epitaxial layer 2b can be set, for example, to make the impurity concentration of the second n-type silicon carbide epitaxial layer 2b 3 × 10⁻⁶. 15 / cm 3 Left and right. The current state is as follows: Figure 13 As shown.

[0114] Next, as Figure 14 As shown, a mask 23 with desired openings is formed on the surface of the n-type silicon carbide epitaxial layer 2 using photolithography, for example, an oxide film. Then, using this oxide film as the mask 23, p-type impurities, such as aluminum atoms, are ion implanted via ion implantation. Thus, as... Figure 14 As shown, a second p+ type region 4b, with a depth of approximately 0.5 μm, is formed in a portion of the surface region of the n-type silicon carbide epitaxial layer 2, overlapping, for example, the upper part of the first p+ type region 4a. This second p+ type region 4b and the first p+ type region 4a together form the first p+ type base region 4. The state up to this point is as follows... Figure 14 As shown.

[0115] Next, as Figure 15 As shown, the mask 23 used during ion implantation to form the second p+ type region 4b is removed. Then, an n-type impurity, such as nitrogen atoms, and a p-type impurity, such as aluminum atoms, are co-implanted to the same location using ion implantation. Thus, as... Figure 15 As shown, a second n-type region 6b with a depth of approximately 0.5 μm is formed in a portion of the surface layer of the second n-type silicon carbide epitaxial layer 2b, in a manner that connects to the first p+ type region 4a, the second p+ type base region 5, and the first n-type region 6a. This second n-type region 6b and the first n-type region 6a together form the n-type high-concentration region 6. Thus, the second n-type region 6b becomes the JFET1 region 21. The first p+ type base regions 4 (4a, 4b), the second p+ type base region 5, and the n-type high-concentration regions 6 (6a, 6b) are formed as part of the first semiconductor layer. In the conventional ion implantation of n-type impurities for concentration adjustment of the JFET region, by co-doping with p-type impurities, such as Al, the effective donor concentration Nd-Na of the JFET1 region 21 can be set to 7 × 10⁻⁶. 16 / cm 3 ~7×10 17 / cm 3The concentration of Al is greater than or equal to 10% of the N concentration but less than the N concentration. The second p+ region 4b is set to, for example, an Al concentration of approximately 3e18. Nitrogen and Al are also ion-implanted in this region, but there is no effect if the concentration difference between the implanted nitrogen and Al is more than two orders of magnitude smaller than the concentration of the second p+ region 4b. If the concentration difference is larger, to suppress the effect, the Al concentration of the second p+ region 4b can be pre-set to be high, or the second p+ region 4b can be covered with a mask during implantation. The state up to this point is as follows: Figure 15 As shown.

[0116] Next, as Figure 16 As shown, on the surface of the n-type silicon carbide epitaxial layer 2 (i.e., the surface of the first p+ type base region 4 and the second n-type region 6b), p-type impurities such as aluminum atoms are doped while the p-type base region 3 is epitaxially grown to a thickness of, for example, about 1.3 μm. The epitaxial growth conditions used to form the p-type base layer 3 can be set, for example, to a 4 × 10⁻⁶ lower impurity concentration than that of the first p+ type base region 4. 17 / cm 3 Left and right. Through the processes up to this point, a silicon carbide semiconductor substrate is formed by stacking an n-type silicon carbide epitaxial layer 2 and a p-type base layer 3 on an n+ type silicon carbide substrate 1. The state up to this point is as follows. Figure 16 As shown.

[0117] Next, as Figure 17 As shown, on the surface of the p-type substrate 3, a mask (not shown) with desired openings is formed using photolithography, for example, as an oxide film. Then, using this oxide film as a mask, n-type impurities, such as N or phosphorus (P), are implanted in an ion-like manner via ion implantation. Thus, as... Figure 17 As shown, an n+ type source region 7 is formed in a portion of the surface layer of the p-type base layer 3.

[0118] Next, the mask used during ion implantation to form the n+ source region 7 is removed. Then, on the exposed surface of the p-type substrate 3, a mask (not shown) with the desired opening is formed using photolithography, for example, an oxide film. Using this oxide film as a mask, p-type impurities, such as aluminum, are ion-implanted onto the surface of the p-type substrate 3. This forms a p++ type contact region 8 on a portion of the surface region of the p-type substrate 3. The ion implantation dose used to form the p++ type contact region 8 can be set to, for example, a higher impurity concentration than the impurity concentration of the second p+ base region 4. The order of ion implantation for forming the n+ source region 7 and for forming the p++ type contact region 8 can be changed. The state up to this point is as follows: Figure 17 As shown.

[0119] Next, after separating the components by removing the p-type base layer 3 on the outer periphery of the chip through dry etching, a breakdown structure such as JTE (Junction Termination Extension) (not shown) is formed on the outer periphery by Al ion implantation.

[0120] Next, heat treatment (annealing) is performed to activate, for example, the first p+ type region 4a, the second p+ type region 4b, the n+ type source region 7, and the p++ type contact region 8. The heat treatment temperature can be, for example, around 1700°C. The heat treatment time can be, for example, around 2 minutes. It should be noted that each ion-implanted region can be activated simultaneously through a single heat treatment as described above, or it can be activated by heat treatment during each ion implantation.

[0121] Next, as Figure 18 As shown, on the surface of the p-type substrate 3 (i.e., the surface of the n+ type source region 7 and the p++ type contact region 8), a mask (not shown) with the desired opening is formed using photolithography, for example, by forming an oxide film. Then, using this oxide film as a mask, a trench 16 is formed through the n+ type source region 7 and the p-type substrate 3, reaching the n-type high-concentration region 6, by dry etching or the like. The bottom of the trench 16 can reach the second p+ type base region 5, or it can be located within the n-type high-concentration region 6 sandwiched between the p-type substrate 3 and the second p+ type base region 5. Next, the mask used to form the trench 16 is removed. The state up to this point is as follows... Figure 18 As shown.

[0122] Next, after depositing a field oxide film (not shown) on the outer periphery of the chip, a gate insulating film 9 is formed along the surface of the n+ source region 7 and the p++ contact region 8, as well as the bottom and sidewalls of the trench 16. This gate insulating film 9 can also be formed by thermal oxidation through heat treatment at a temperature of approximately 1000°C in an oxygen atmosphere. Alternatively, this gate insulating film 9 can also be formed by deposition using a chemical reaction such as high-temperature oxidation (HTO).

[0123] Next, a polysilicon layer doped with, for example, phosphorus atoms is formed on the gate insulating film 9. This polysilicon layer is formed in a manner that fills the trench 16. The gate electrode 10 is formed by patterning the polysilicon layer and leaving it inside the trench 16. A portion of the gate electrode 10 may also protrude from the top of the trench 16 toward the source electrode 14.

[0124] Next, an interlayer insulating film 11 is formed by depositing phosphor glass to a thickness of approximately 1 μm, for example, to cover the gate insulating film 9 and the gate electrode 10. Contact holes are formed by patterning the interlayer insulating film 11 and the gate insulating film 9 and selectively removing them, exposing the n+ type source region 7 and the p++ type contact region 8. A barrier metal 15, such as titanium or titanium nitride, is formed on the surface of the interlayer insulating film 11.

[0125] Next, for example, an ohmic electrode 12 is formed in contact with the n+ type source region 7 and the p++ type contact region 8 by sputtering. Then, heat treatment (sintering) is performed to form the alloy layer. Next, for example, an aluminum film is formed by sputtering to cover the ohmic electrode 12 and the barrier metal 15 on the interlayer insulating film 11, with a thickness of, for example, about 5 μm. Then, the aluminum film is selectively removed, leaving a residue that covers the active portion of the entire device, thereby forming the source electrode 14 and the gate electrode pad (not shown).

[0126] Next, as a surface passivation film, polyimide is applied, for example, by spin coating, patterned using photolithography, and then heat-treated (cured). Following this, titanium (Ti), nickel (Ni), and gold (Au) are sequentially deposited on the second main surface of the n+ type silicon carbide substrate 1 using, for example, vapor deposition, to form the drain electrode 13. As described above, the process is complete. Figures 1-3 The semiconductor device shown.

[0127] As explained above, according to the embodiment, N and Al are simultaneously doped in the JFET1 region. Taking advantage of the fact that the ionization rate of Al changes with temperature, the concentration in the JFET1 region is reduced at high temperatures, thereby increasing the JFET resistance when a short circuit occurs and the temperature becomes high, thus suppressing the short-circuit current. Therefore, the short-circuit current can be reduced while maintaining the on-resistance of the device, improving short-circuit withstand capability. Furthermore, in this embodiment, the actual operating temperature is described as 300K to 448K, but it is not limited to this; for example, 233K to 524K can also be set as the actual operating temperature. In aluminum-doped p-type SiC, the resistance increases at negative temperatures. This is because the ionization rate of aluminum decreases at low temperatures, resulting in a decrease in the free carrier density. In this embodiment, a predetermined amount of nitrogen and aluminum is used, which can be considered as a nitrogen-only concentration at low temperatures, thus being effective even at negative temperatures (e.g., 233K).

[0128] It should be noted that regarding the doping of N and Al in the JFET1 region, if predetermined impurity concentrations are set, doping is not performed simultaneously. For example, during the epitaxial growth stage, nitrogen can be used as a dopant to form an n-type epitaxial layer, followed by ion implantation of aluminum; alternatively, aluminum can be used as a dopant to form a p-type epitaxial layer, followed by ion implantation of nitrogen. Furthermore, nitrogen and aluminum can be used as dopants during epitaxial growth. An example of using nitrogen as an n-type dopant has been given, but it is not limited to this; phosphorus can also be used instead of nitrogen to dope aluminum. Since either nitrogen or phosphorus can be used as an n-type dopant, these n-type impurities can also be referred to as donors.

[0129] As described above, the present invention can be modified in various ways without departing from the spirit of the invention. In the above embodiments, for example, the size of each part, the concentration of impurities, etc., can be set in various ways according to the required specifications.

[0130] Industrial availability

[0131] As described above, the silicon carbide semiconductor device of the present invention is useful for power semiconductor devices used in power conversion devices such as inverters, power supply devices for various industrial machinery, inverters for electric vehicles, and the like.

Claims

1. A silicon carbide semiconductor device, characterized in that, have: n-type silicon carbide semiconductor substrate; The first semiconductor layer of type n is disposed on the front side of the silicon carbide semiconductor substrate and has an impurity concentration lower than that of the silicon carbide semiconductor substrate. The first JFET region of the n-type is disposed on the surface layer of the first semiconductor layer, and the effective donor concentration is higher than the effective donor concentration of the first semiconductor layer; A p-type second semiconductor layer is disposed on the surface of the first semiconductor layer on the side opposite to the silicon carbide semiconductor substrate; The first semiconductor region of type n is selectively disposed on the surface layer of the second semiconductor layer; The trench extends through the first semiconductor region, the second semiconductor layer, and the first JFET region; A gate electrode is disposed inside the trench, separated by a gate insulating film; An interlayer insulating film is disposed on the gate electrode; The first electrode is in contact with the first semiconductor region and the second semiconductor layer; as well as The second electrode is disposed on the back side of the silicon carbide semiconductor substrate. The first JFET region is doped with a donor composed of either nitrogen or phosphorus and aluminum, wherein the doping concentration of the donor is greater than the doping concentration of the aluminum.

2. The silicon carbide semiconductor device according to claim 1, characterized in that, The donor concentration was 7 × 10⁻⁶. 16 / cm 3 Above and 7×10 17 / cm 3 the following, The concentration of aluminum is more than 10% and less than 100% of the donor's concentration.

3. The silicon carbide semiconductor device according to claim 1, characterized in that, The concentration of the donor ( / cm) 3 Let X be a constant between 0.1 and 0.99, and let the concentration of aluminum ( / cm³) be... 3 When denoted as aX, the donor concentration X satisfies the following relationship: X≥(7×10 16 ) / (1-a) X≤(7×10 17 ) / (1-a)。 4. The silicon carbide semiconductor device according to claim 1, characterized in that, The effective donor concentration in the first JFET region is 7 × 10⁻⁶. 16 / cm 3 Above and 7×10 17 / cm 3 the following.

5. The silicon carbide semiconductor device according to claim 4, characterized in that, Within the actual operating temperature range of the element, 245K to 524K, the effective donor concentration of 7×10⁻⁶ is satisfied. 16 / cm 3 Above and 7×10 17 / cm 3 The following range.

6. The silicon carbide semiconductor device according to claim 4, characterized in that, Within the actual operating temperature range of the element (300K~448K), the effective donor concentration is satisfied at 7×10⁻⁶. 16 / cm 3 Above and 7×10 17 / cm 3 The following range.

7. The silicon carbide semiconductor device according to any one of claims 1 to 6, characterized in that, The first semiconductor layer includes: A drift layer having the same impurity concentration as the first semiconductor layer; and The second JFET region of type n is disposed between the first JFET region and the drift layer, and the effective donor concentration is higher than that of the drift layer.

8. The silicon carbide semiconductor device according to claim 7, characterized in that, The second JFET region is doped with the donor and the aluminum, wherein the doping concentration of the donor is greater than the doping concentration of the aluminum.

9. The silicon carbide semiconductor device according to any one of claims 1 to 6, characterized in that, The silicon carbide semiconductor device further comprises: The first base region of the p-type is located inside the first semiconductor layer, between a plurality of periodically arranged trenches, which separates the first JFET and is grounded to the second semiconductor layer; as well as The second base region of the p-type is disposed inside the first semiconductor layer at a position opposite to the bottom of the trench in the depth direction.

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