Display substrate and display device

Abstract

This invention belongs to the field of displays and relates to a display substrate and a display device. The display substrate includes a driving substrate, an anode layer, a pixel defining layer, a light-emitting functional layer, a cathode layer, and an encapsulation layer. The driving circuit includes at least one transistor, the transistor including a semiconductor layer, the semiconductor layer being at least partially located inside the substrate. The anode layer includes multiple anodes, and the display substrate includes multiple pixel openings located on the side of the multiple anodes away from the driving substrate. The multiple pixel openings are configured to at least overlap with the multiple anodes. Each anode includes a main body portion and a protrusion portion, the protrusion portion being connected to the main body portion, and the dimension of the protrusion portion in a direction perpendicular to the driving substrate being larger than the dimension of the main body portion in the same direction. The light-emitting functional layer includes multiple light-emitting portions, the multiple light-emitting portions being contacted and disposed with the main bodies of the multiple anodes. Therefore, this display substrate can reduce and avoid crosstalk between adjacent sub-pixels.

Description

[0001] This application claims priority to Chinese Patent Application No. 202210423991.9, filed on April 22, 2022, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] Embodiments of this disclosure relate to a display substrate and a display device. Background Technology

[0003] With the continuous development of display technology, micro organic light-emitting diode (Micro-OLED) display devices are a new type of OLED display device using a silicon substrate, also known as silicon-based organic light-emitting diode (silicon-based OLED) display devices. Silicon-based OLED display devices have advantages such as small size and high resolution. They are fabricated using CMOS integrated circuit technology, enabling active pixel addressing. Furthermore, various functional circuits, including TCON (timing control) circuits and OCP (operation control) circuits, can be fabricated on the silicon substrate, achieving lightweight design.

[0004] Micro OLED displays have excellent display characteristics, such as high resolution, high brightness, rich colors, low driving voltage, fast response speed, and low power consumption, and have broad development prospects. Summary of the Invention

[0005] This disclosure provides a display substrate and a display device. The display substrate includes a driving substrate, an anode layer, a pixel defining layer, a light-emitting functional layer, a cathode layer, and an encapsulation layer. The driving substrate includes a substrate and a driving circuit. The anode layer is located on the driving substrate. The pixel defining layer is located on the side of the anode layer away from the driving substrate. The light-emitting functional layer is located on the side of the anode layer away from the driving substrate. The cathode layer is located on the side of the light-emitting functional layer away from the driving substrate. The encapsulation layer is located on the side of the cathode layer away from the driving substrate. The driving circuit includes at least one transistor, the transistor includes a semiconductor layer, and the semiconductor layer is at least partially located inside the substrate. The anode layer includes a plurality of anodes. The display substrate includes a plurality of pixel openings, which are located within the pixel defining layer and on the side of the plurality of anodes away from the driving substrate. The plurality of pixel openings are configured to at least overlap with the plurality of anodes. Each anode includes a main body portion and a protrusion portion. The protrusion portion is disposed around the periphery of the main body portion, and the size of the protrusion portion in a direction perpendicular to the driving substrate is larger than the size of the main body portion in the same direction. The light-emitting functional layer includes a plurality of light-emitting portions, which are located within the plurality of pixel openings and are in contact with the main body portions of the plurality of anodes. Therefore, this display substrate can effectively avoid leakage and crosstalk between adjacent sub-pixels.

[0006] At least one embodiment of this disclosure provides a display substrate comprising: a driving substrate including a substrate and a driving circuit; a first planarization layer located on the driving circuit; an anode layer located on a side of the first planarization layer away from the driving substrate; a pixel defining layer located on a side of the anode layer away from the driving substrate; a light-emitting functional layer located on a side of the anode layer away from the driving substrate; a cathode layer located on a side of the light-emitting functional layer away from the driving substrate; and an encapsulation layer located on a side of the cathode layer away from the driving substrate; the driving circuit includes at least one transistor, the transistor including a semiconductor layer at least partially located inside the substrate; the anode layer including a plurality of anodes; and the display substrate including a plurality of pixel openings located on a side of the plurality of anodes away from the driving substrate. The plurality of pixel openings are configured to at least overlap with the plurality of anodes; each anode includes a main body and a protrusion, the protrusion being connected to the main body, the size of the protrusion in a first direction being larger than the size of the main body in the first direction; the light-emitting functional layer includes a plurality of light-emitting portions, the plurality of light-emitting portions being in contact with the main body of the plurality of anodes; the distance between the surface of the first flat layer away from the substrate at the location of the main body and the substrate is equal to the distance between the surface of the first flat layer away from the substrate at the location of the protrusion and the substrate; the distance between the surface of the main body away from the substrate and the surface of the first flat layer away from the substrate is less than the distance between the surface of the protrusion away from the substrate and the surface of the first flat layer away from the substrate.

[0007] For example, in a display substrate provided in one embodiment of this disclosure, the protrusion is disposed around the periphery of the main body.

[0008] For example, in a display substrate provided in one embodiment of this disclosure, the orthographic projection of the pixel defining layer on the driving substrate overlaps with the orthographic projection of the protrusion on the driving substrate.

[0009] For example, in a display substrate provided in one embodiment of this disclosure, the pixel defining layer includes a pixel defining portion, the pixel defining portion including: a pixel defining flat portion located between two adjacent anodes; and protrusion structures located on the side of the protrusions of the two adjacent anodes away from the driving substrate, the pixel defining flat portion connecting the protrusion structures.

[0010] For example, in a display substrate provided in one embodiment of this disclosure, the pixel defining portion is symmetrically arranged about the center of the spacing region between two adjacent anodes.

[0011] For example, in a display substrate provided in one embodiment of this disclosure, each of the protrusion structures includes: a first sidewall located on the side of the protrusion structure near the center of the main body; and a second sidewall connected to the first sidewall, wherein the second sidewall is further away from the driving substrate relative to the first sidewall; and the slope angle of the first sidewall is greater than the slope angle of the second sidewall.

[0012] For example, in a display substrate provided in one embodiment of this disclosure, the slope angle of the first sidewall ranges from 75 to 89 degrees, and the slope angle of the second sidewall ranges from 15 to 45 degrees.

[0013] For example, in a display substrate provided in one embodiment of this disclosure, each of the protrusion structures further includes: a third sidewall located on the side of the protrusion structure near the pixel-defined flat portion, wherein the slope angle of the third sidewall is greater than the slope angle of the second sidewall and less than the slope angle of the first sidewall.

[0014] For example, in a display substrate provided in one embodiment of this disclosure, each of the protrusion structures further includes: a third sidewall located on the side of the protrusion structure near the pixel-defined flat portion, wherein the slope angle of the first sidewall is α, the slope angle of the second sidewall is β, and the slope angle of the third sidewall is γ, and satisfies the following formula: β < γ < α.

[0015] For example, in a display substrate provided in one embodiment of this disclosure, the difference between the slope angle of the first sidewall and the slope angle of the second sidewall is equal to i times the slope angle of the third sidewall, where i ranges from 0.8 to 1.2.

[0016] For example, in a display substrate provided in one embodiment of this disclosure, the slope angle α of the first sidewall, the slope angle β of the second sidewall, and the slope angle γ of the third sidewall satisfy the following formula: (α-β)=i*γ, where the value of i ranges from 0.8 to 1.2.

[0017] For example, in a display substrate provided in one embodiment of this disclosure, the difference between the slope angle of the first sidewall and the slope angle of the second sidewall is equal to j times the difference between the slope angle of the second sidewall and the slope angle of the third sidewall, where j ranges from 1.5 to 3.

[0018] For example, in a display substrate provided in one embodiment of this disclosure, the slope angle α of the first sidewall, the slope angle β of the second sidewall, and the slope angle γ of the third sidewall satisfy the following formula: (α-β)=j*(γ-β), where the value of j ranges from 1.5 to 3.

[0019] For example, in a display substrate provided in one embodiment of this disclosure, the sum of the slope angle of the first sidewall and the slope angle of the second sidewall is equal to k times the slope angle of the third sidewall, where k ranges from 2 to 3.

[0020] For example, in a display substrate provided in one embodiment of this disclosure, the slope angle of the third sidewall is in the range of 45-60 degrees.

[0021] For example, in a display substrate provided in one embodiment of this disclosure, the orthographic projection of the third sidewall onto the driving substrate in the second direction is larger than the orthographic projection of the second sidewall onto the driving substrate in the second direction, and the orthographic projection of the second sidewall onto the driving substrate in the second direction is larger than the orthographic projection of the first sidewall onto the driving substrate in the second direction. The second direction is either from the protrusion to the main body or from the main body to the protrusion, and the second direction is parallel to the surface of the driving substrate away from the anode layer.

[0022] For example, in a display substrate provided in one embodiment of this disclosure, the dimension of the first sidewall in the first direction is H1, the dimension of the second sidewall in the first direction is H2, and the dimension of the third sidewall in the first direction is H3, wherein H1, H2, and H3 satisfy the following formula:

[0023] H3*cosγ>H2*cosβ>H1*cosα.

[0024] For example, in a display substrate provided in one embodiment of this disclosure, the protrusion of each anode includes a fourth sidewall located on the side of the protrusion near the center of the main body. The slope angle of the fourth sidewall is greater than that of the second sidewall and less than that of the first sidewall.

[0025] For example, in a display substrate provided in one embodiment of this disclosure, the protrusion of each anode includes a fourth sidewall located on the side of the protrusion near the center of the main body, and the slope angle of the fourth sidewall is δ, and satisfies the following formula: β<δ<α.

[0026] For example, in a display substrate provided in one embodiment of this disclosure, the protrusion of each anode includes: a first sub-anode layer located on the side of the driving circuit away from the substrate; a second sub-anode layer located on the side of the first sub-anode layer away from the driving substrate; and a third sub-anode layer located on the side of the second sub-anode layer away from the driving substrate.

[0027] For example, in a display substrate provided in one embodiment of this disclosure, the dimension of the first sub-anode layer in the second direction is greater than the dimension of the third sub-anode layer in the second direction, and the dimension of the third sub-anode layer in the second direction is greater than the dimension of the second sub-anode layer in the second direction. The second direction is either from the protrusion to the main body or from the main body to the protrusion, and the second direction is parallel to the surface of the driving substrate away from the anode layer.

[0028] For example, in a display substrate provided in one embodiment of this disclosure, the end of the first sub-anode layer away from the main body includes a raised portion, and the thickness of the raised portion in the first direction is greater than the average thickness of the first sub-anode layer in the first direction.

[0029] For example, in a display substrate provided in one embodiment of this disclosure, the end of the third sub-anode layer away from the main body is bent toward the first sub-anode layer.

[0030] For example, in a display substrate provided in one embodiment of this disclosure, the protrusion of each anode further includes: a fourth sub-anode layer located between the second sub-anode layer and the third sub-anode layer, wherein the dimension of the fourth sub-anode layer in the second direction is smaller than the dimension of the second sub-anode layer in the second direction.

[0031] For example, in a display substrate provided in one embodiment of this disclosure, the dimension of the third sub-anode layer extending beyond the fourth sub-anode layer in the second direction is smaller than the dimension of the overlapping area of ​​the orthographic projection of the pixel defining layer on the driving substrate and the orthographic projection of the protrusion on the driving substrate in the second direction.

[0032] For example, in a display substrate provided in one embodiment of this disclosure, the second sub-anode layer includes a fifth sidewall located on the side of the second sub-anode layer away from the main body, and the fourth sub-anode layer includes a sixth sidewall located on the side of the fourth sub-anode layer away from the main body. The slope angle of the fifth sidewall is greater than that of the fourth sidewall, the slope angle of the sixth sidewall is greater than that of the fourth sidewall, and the slope angle of the fifth sidewall is greater than that of the sixth sidewall.

[0033] For example, in a display substrate provided in one embodiment of this disclosure, the ratio of the thickness of the first sub-anode layer in the first direction to the thickness of the second sub-anode layer in the first direction is in the range of 1 / 15 to 1 / 5.

[0034] For example, in a display substrate provided in one embodiment of this disclosure, the ratio of the thickness of the first sub-anode layer in the first direction to the thickness of the third sub-anode layer in the first direction is in the range of 1 / 3 to 4 / 5.

[0035] For example, in a display substrate provided in one embodiment of this disclosure, the ratio of the thickness of the first sub-anode layer in the first direction to the thickness of the fourth sub-anode layer in the first direction is in the range of 1 / 24 to 1 / 8.

[0036] For example, in a display substrate provided in one embodiment of this disclosure, the ratio of the distance between two adjacent anodes to the length of the orthographic projection of the anode protrusion onto the driving substrate is in the range of 2-4.

[0037] For example, in a display substrate provided in one embodiment of this disclosure, the ratio of the distance between two adjacent anodes to the length of the orthographic projection of the anode protrusion on the driving substrate is in the range of 2.5-3.5.

[0038] For example, in a display substrate provided in one embodiment of this disclosure, the protrusion is disposed around the main body portion.

[0039] For example, in a display substrate provided in one embodiment of this disclosure, the shape of the orthographic projection of the anode onto the driving substrate includes a hexagon.

[0040] For example, a display substrate provided in one embodiment of this disclosure further includes: a reflective electrode layer located on the side of the first planarization layer near the anode layer; and a second planarization layer located on the side of the reflective electrode layer near the anode layer.

[0041] For example, in a display substrate provided in one embodiment of this disclosure, the reflective electrode layer is continuously disposed in the pixel opening.

[0042] For example, in a display substrate provided in one embodiment of this disclosure, there is a first aperture between the light-emitting functional layer and the main body, and at least one second aperture between the light-emitting functional layer and the pixel defining layer, wherein the space occupied by the first aperture is greater than the space occupied by the second aperture.

[0043] For example, in a display substrate provided in one embodiment of this disclosure, the encapsulation layer includes an inorganic encapsulation layer located on the side of the cathode layer away from the driving substrate, and the inorganic encapsulation layer includes a plurality of sub-inorganic encapsulation layers.

[0044] For example, in a display substrate provided in one embodiment of this disclosure, at least two adjacent sub-inorganic encapsulation layers are made of different materials, and at least two adjacent sub-inorganic encapsulation layers are made of the same material.

[0045] For example, in a display substrate provided in one embodiment of this disclosure, the refractive index of the plurality of sub-inorganic encapsulation layers first increases and then decreases in the direction away from the driving substrate.

[0046] For example, in a display substrate provided in one embodiment of this disclosure, the thickness of the plurality of sub-inorganic encapsulation layers gradually decreases in the first direction in the direction away from the driving substrate.

[0047] For example, in a display substrate provided in one embodiment of this disclosure, each of the sub-inorganic encapsulation layers includes: an alternately arranged flat region and a double-arched spacer region, a first arched region located on the side of the flat region away from the double-arched spacer region, a second arched region located between the flat region and the double-arched spacer region, and a third arched region located on the flat region away from the second arched region, wherein the first arched region and the second arched region are symmetrically arranged about the center of the flat region.

[0048] For example, in a display substrate provided in one embodiment of this disclosure, the flat area has a dimension L in the second direction, the distance between the center of the second arched area and the center of the third arched area in the second direction is a first distance D1, the distance between the center of the first arched area and the center of the second arched area in the second direction is a second distance D2, and the radii of curvature of the first arched area, the second arched area, and the third arched area are all R.

[0049] The first distance D1 satisfies the following formula:

[0050] D2≤(L+D1)<(L+R),

[0051] The second direction is either from the protrusion to the main body or from the main body to the protrusion, and the second direction is parallel to the surface of the driving substrate away from the anode layer.

[0052] For example, in a display substrate provided in one embodiment of this disclosure, the flat area has a dimension L in the second direction, the distance between the center of the second arched area and the center of the third arched area in the second direction is a first distance D1, the distance between the center of the first arched area and the center of the second arched area in the second direction is a second distance D2, and the radii of curvature of the first arched area, the second arched area, and the third arched area are all R.

[0053] The first distance D1 satisfies the following formula:

[0054] (L+D1)≤D2<(L+R),

[0055] The second direction is either from the protrusion to the main body or from the main body to the protrusion, and the second direction is parallel to the surface of the driving substrate away from the anode layer.

[0056] For example, in a display substrate provided in one embodiment of this disclosure, the orthographic projection of the first arched region, the second arched region, or the third arched region on the driving substrate overlaps with the orthographic projection of the protrusion on the driving substrate, the orthographic projection of the flat region on the driving substrate overlaps with the orthographic projection of the main body on the driving substrate, and the distance between the surface of the first arched region, the second arched region, or the third arched region away from the driving substrate and the driving substrate is greater than the distance between the surface of the flat region away from the driving substrate and the driving substrate.

[0057] For example, in a display substrate provided in one embodiment of this disclosure, the orthographic projection of the double-arched spacing region on the driving substrate overlaps with the orthographic projection of the spacing region between two adjacent anodes on the driving substrate.

[0058] For example, in a display substrate provided in one embodiment of this disclosure, the plurality of sub-inorganic encapsulation layers include: a first sub-inorganic encapsulation layer located on the side of the cathode layer away from the driving substrate; a second sub-inorganic encapsulation layer located on the side of the first sub-inorganic encapsulation layer away from the driving substrate; a third sub-inorganic encapsulation layer located on the side of the second sub-inorganic encapsulation layer away from the driving substrate; and a fourth sub-inorganic encapsulation layer located on the side of the third sub-inorganic encapsulation layer away from the driving substrate.

[0059] For example, in a display substrate provided in one embodiment of this disclosure, the refractive index of the first sub-inorganic encapsulation layer is less than the refractive index of the second sub-inorganic encapsulation layer, and the refractive index of the fourth sub-inorganic encapsulation layer is less than the refractive index of the third sub-inorganic encapsulation layer.

[0060] For example, in a display substrate provided in one embodiment of this disclosure, the refractive index of the second sub-inorganic encapsulation layer is equal to the refractive index of the third sub-inorganic encapsulation layer.

[0061] For example, in a display substrate provided in an embodiment of this disclosure, the flat area of ​​the first sub-inorganic encapsulation layer has a first width in the second direction, the flat area of ​​the second sub-inorganic encapsulation layer has a second width in the second direction, the flat area of ​​the third sub-inorganic encapsulation layer has a third width in the second direction, and the flat area of ​​the fourth sub-inorganic encapsulation layer has a fourth width in the second direction, wherein the first width is greater than the second width, the second width is greater than the third width, and the third width is greater than the fourth width.

[0062] For example, in a display substrate provided in one embodiment of this disclosure, the angle between the first line connecting the edge of the flat area of ​​the first sub-inorganic encapsulation layer near the first arched area, the edge of the flat area of ​​the second sub-inorganic encapsulation layer near the first arched area, the edge of the flat area of ​​the third sub-inorganic encapsulation layer near the first arched area, and the edge of the flat area of ​​the fourth sub-inorganic encapsulation layer near the first arched area, and the surface of the driving substrate away from the anode layer is a first angle; the angle between the second line connecting the apex of the first arched area of ​​the first sub-inorganic encapsulation layer, the apex of the first arched area of ​​the second sub-inorganic encapsulation layer, the apex of the first arched area of ​​the third sub-inorganic encapsulation layer, and the apex of the first arched area of ​​the fourth sub-inorganic encapsulation layer, and the surface of the driving substrate away from the anode layer is a second angle; and the first angle is smaller than the second angle.

[0063] For example, in a display substrate provided in one embodiment of this disclosure, the first included angle ranges from 60 to 85 degrees, and the second included angle ranges from 85 to 89 degrees.

[0064] For example, in a display substrate provided in one embodiment of this disclosure, the intersection of the first connection line and the second connection line is located within the driving substrate.

[0065] For example, in a display substrate provided in one embodiment of this disclosure, the driving circuit includes: a semiconductor layer located in the substrate; a first conductive layer located on the semiconductor layer; a second conductive layer located on the side of the first conductive layer away from the substrate; a third conductive layer located on the side of the second conductive layer away from the substrate; and a fourth conductive layer located on the side of the third conductive layer away from the substrate.

[0066] For example, in a display substrate provided in one embodiment of this disclosure, the intersection of the first line and the second line is located between the upper surface of the third conductive layer away from the substrate and the anode layer.

[0067] For example, in a display substrate provided in one embodiment of this disclosure, the distance between the intersection of the first line and the second line and the vertex of the protrusion structure of the pixel defining layer away from the upper surface of the substrate is greater than the thickness of the first sub-inorganic encapsulation layer in the first direction.

[0068] For example, in a display substrate provided in one embodiment of this disclosure, the distance between the intersection of the first line and the second line and the vertex of the protrusion structure of the pixel defining layer away from the upper surface of the substrate is less than the sum of the thickness of the first sub-inorganic encapsulation layer in the first direction and the thickness of the second sub-inorganic encapsulation layer in the first direction.

[0069] For example, in a display substrate provided in one embodiment of this disclosure, the angle between the third line connecting the edge of the second arched region of the first sub-inorganic encapsulation layer near the double arched interval region, the edge of the second arched region of the second sub-inorganic encapsulation layer near the double arched interval region, the edge of the second arched region of the third sub-inorganic encapsulation layer near the double arched interval region, and the edge of the second arched region of the fourth sub-inorganic encapsulation layer near the double arched interval region, and the surface of the driving substrate away from the anode layer is a third angle, and the third angle is smaller than the second angle.

[0070] For example, in a display substrate provided in one embodiment of this disclosure, the intersection of the first connecting line and the three connecting lines is located between the upper surface of the second conductive layer away from the substrate and the lower surface of the third conductive layer near the substrate.

[0071] For example, in a display substrate provided in one embodiment of this disclosure, the intersection of the second line and the third line is located between the lower surface of the first conductive layer near the substrate and the lower surface of the substrate away from the first conductive layer.

[0072] For example, in a display substrate provided in one embodiment of this disclosure, the angle between the fourth line connecting the edge of the third arched region of the first sub-inorganic encapsulation layer away from the double arched interval region, the edge of the third arched region of the second sub-inorganic encapsulation layer away from the double arched interval region, the edge of the third arched region of the third sub-inorganic encapsulation layer away from the double arched interval region, and the edge of the third arched region of the fourth sub-inorganic encapsulation layer away from the double arched interval region, and the surface of the driving substrate away from the anode layer is a fourth angle, which is smaller than the second angle.

[0073] For example, in a display substrate provided in one embodiment of this disclosure, the intersection of the first line and the fourth line is located on the side of the substrate away from the first conductive layer.

[0074] For example, in a display substrate provided in one embodiment of this disclosure, the intersection of the third line and the fourth line is located on the side of the substrate away from the first conductive layer.

[0075] For example, in a display substrate provided in one embodiment of this disclosure, the first arched region of the first sub-inorganic encapsulation layer has a first radius of curvature away from the upper surface of the substrate, the first arched region of the second sub-inorganic encapsulation layer has a second radius of curvature away from the upper surface of the substrate, the first arched region of the third sub-inorganic encapsulation layer has a third radius of curvature away from the upper surface of the substrate, and the first arched region of the fourth sub-inorganic encapsulation layer has a fourth radius of curvature away from the upper surface of the substrate. The first radius of curvature is smaller than the second radius of curvature, the second radius of curvature is smaller than the third radius of curvature, and the third radius of curvature is smaller than the fourth radius of curvature.

[0076] For example, in a display substrate provided in one embodiment of this disclosure, the illusory center of the first arched region of the fourth sub-inorganic encapsulation layer is located between the upper surface of the first sub-inorganic encapsulation layer away from the substrate and the lower surface of the fourth sub-inorganic encapsulation layer near the substrate.

[0077] For example, in a display substrate provided in one embodiment of this disclosure, the first sub-inorganic encapsulation layer has a first thickness in the first direction, the second sub-inorganic encapsulation layer has a second thickness in the first direction, the third sub-inorganic encapsulation layer has a third thickness in the first direction, and the fourth sub-inorganic encapsulation layer has a fourth thickness in the first direction, wherein the first thickness is greater than the second thickness, the second thickness is greater than the third thickness, and the third thickness is greater than the fourth thickness.

[0078] For example, in a display substrate provided in one embodiment of this disclosure, the ratio of the difference between the first thickness and the second thickness to the difference between the third thickness and the fourth thickness is in the range of 1.5 to 2 times.

[0079] For example, in a display substrate provided in one embodiment of this disclosure, the ratio of the sum of the second thickness and the third thickness to the first thickness is in the range of 0.8-1.2.

[0080] For example, in a display substrate provided in one embodiment of this disclosure, the first thickness ranges from 1000 to 1200 nanometers, the second thickness ranges from 500 to 660 nanometers, the third thickness ranges from 480 to 560 nanometers, and the fourth thickness ranges from 180 to 260 nanometers.

[0081] For example, in a display substrate provided in one embodiment of this disclosure, the material of the first sub-inorganic encapsulation layer includes silicon oxide and silicon oxynitride, the material of the second sub-inorganic encapsulation layer includes silicon nitride, the material of the third sub-inorganic encapsulation layer includes silicon nitride, and the material of the fourth sub-inorganic encapsulation layer includes silicon oxide.

[0082] For example, in a display substrate provided in one embodiment of this disclosure, the encapsulation layer further includes: an organic encapsulation layer located on the side of the inorganic encapsulation layer away from the driving substrate, the organic encapsulation layer including a first region, a second region and a third region, the average thickness of the first region being less than the average thickness of the second region, and the average thickness of the second region being less than the average thickness of the third region.

[0083] For example, a display substrate provided in one embodiment of this disclosure further includes a color filter layer located on the side of the encapsulation layer away from the driving substrate, the color filter layer including a first color filter, a second color filter and a third color filter.

[0084] For example, in a display substrate provided in one embodiment of this disclosure, the first color filter and the second color filter have a first overlapping area, the second color filter and the third color filter have a second overlapping area, and the third color filter and the first color filter have a third overlapping area.

[0085] For example, in a display substrate provided in one embodiment of this disclosure, the orthographic projections of the first overlapping area, the second overlapping area, and the third overlapping area on the driving substrate overlap with the orthographic projection of the protrusion on the driving substrate.

[0086] For example, in a display substrate provided in one embodiment of this disclosure, the orthographic projections of the first overlapping region, the second overlapping region, and the third overlapping region on the driving substrate overlap with the orthographic projections of the spacing region between two adjacent anodes on the driving substrate.

[0087] For example, in a display substrate provided in one embodiment of this disclosure, the size of the first overlapping region in the second direction is larger than the size of the second overlapping region in the second direction, and the size of the second overlapping region in the second direction is larger than the size of the third overlapping region in the second direction.

[0088] For example, in a display substrate provided in one embodiment of this disclosure, the size range of the first overlapping region in the second direction is 400-600 nanometers, the size range of the second overlapping region in the second direction is 250-350 nanometers, and the size range of the third overlapping region in the second direction is 100-200 nanometers.

[0089] For example, in a display substrate provided in one embodiment of this disclosure, the average size of the first color filter in the first direction is greater than the average size of the second color filter in the first direction, and smaller than the average size of the third color filter in the first direction.

[0090] For example, in a display substrate provided in one embodiment of this disclosure, the average size of the first color filter in the first direction ranges from 2.3 to 2.6 micrometers, the average size of the second color filter in the first direction ranges from 1.7 to 1.95 micrometers, and the average size of the third color filter in the first direction ranges from 2.3 to 2.7 micrometers.

[0091] For example, in a display substrate provided in one embodiment of this disclosure, the ratio of the difference between the average size of the first color filter in the first direction and the average size of the second color filter in the first direction and the difference between the average size of the first color filter in the first direction and the average size of the third color filter in the first direction is in the range of 2-3.

[0092] For example, in a display substrate provided in one embodiment of this disclosure, the first color filter includes a first edge portion, a second edge portion, and an intermediate portion located between the first edge portion and the second edge portion, wherein the average size of the intermediate portion in the first direction is smaller than the average size of the first edge portion in the first direction and the average size of the second edge portion in the first direction.

[0093] For example, in a display substrate provided in one embodiment of this disclosure, the first color filter includes a first contact surface that contacts the second color filter, the second color filter includes a second contact surface that contacts the third color filter, and the third color filter includes a third contact surface that contacts the first color filter. The size of the first contact surface in a first direction perpendicular to the driving substrate is equal to the size of the second contact surface in the first direction, and smaller than the size of the third contact surface in the first direction.

[0094] For example, in a display substrate provided in one embodiment of this disclosure, the distance between the first color filter and the surface of the driving substrate away from the anode layer is greater than the distance between the third color filter and the surface of the driving substrate away from the anode layer, and less than the distance between the second color filter and the surface of the driving substrate away from the anode layer.

[0095] For example, in a display substrate provided in one embodiment of this disclosure, the first color filter is a red filter, the second color filter is a green filter, and the third color filter is a blue filter.

[0096] For example, in a display substrate provided in one embodiment of this disclosure, the material of the color filter layer includes a desiccant.

[0097] For example, in a display substrate provided in one embodiment of this disclosure, the color filter layer includes aluminum.

[0098] For example, a display substrate provided in one embodiment of this disclosure further includes a protective layer located on the side of the color filter layer away from the driving substrate.

[0099] For example, in a display substrate provided in one embodiment of this disclosure, the color filter layer further includes a black matrix located between any two adjacent colors among the first color filter, the second color filter, and the third color filter.

[0100] For example, a display substrate provided in one embodiment of this disclosure further includes a glass cover plate located on the side of the color filter layer away from the driving substrate.

[0101] At least one embodiment of this disclosure also provides a display device comprising the display substrate described in any of the preceding claims.

[0102] At least one embodiment of this disclosure also provides another display device comprising the display substrate described in any of the preceding claims.

[0103] For example, a display device provided in one embodiment of this disclosure further includes: a counter substrate disposed opposite to the display substrate, the counter substrate including a glass cover plate and a color filter layer located on the glass cover plate, the color filter layer including a first color filter, a second color filter and a third color filter.

[0104] For example, in a display device provided in one embodiment of this disclosure, the first color filter and the second color filter have a first overlapping area, the second color filter and the third color filter have a second overlapping area, and the third color filter and the first color filter have a third overlapping area.

[0105] For example, in a display device provided in one embodiment of this disclosure, the orthographic projections of the first overlapping area, the second overlapping area, and the third overlapping area on the driving substrate overlap with the orthographic projection of the protrusion on the driving substrate.

[0106] For example, in a display device provided in one embodiment of this disclosure, the orthographic projections of the first overlapping area, the second overlapping area, and the third overlapping area on the driving substrate overlap with the orthographic projections of the spacing area between two adjacent anodes on the driving substrate.

[0107] For example, in a display device provided in one embodiment of this disclosure, the size of the first overlapping area in the second direction is larger than the size of the second overlapping area in the second direction, and the size of the second overlapping area in the second direction is larger than the size of the third overlapping area in the second direction.

[0108] For example, in a display device provided in one embodiment of this disclosure, the size range of the first overlapping region in the second direction is 400-600 nanometers, the size range of the second overlapping region in the second direction is 250-350 nanometers, and the size range of the third overlapping region in the second direction is 100-200 nanometers.

[0109] For example, in a display device provided in one embodiment of this disclosure, the average size of the first color filter in the first direction is greater than the average size of the second color filter in the first direction, and smaller than the average size of the third color filter in the first direction.

[0110] For example, in a display device provided in one embodiment of this disclosure, the average size of the first color filter in the first direction ranges from 2.3 to 2.6 micrometers, the average size of the second color filter in the first direction ranges from 1.7 to 1.95 micrometers, and the average size of the third color filter in the first direction ranges from 2.3 to 2.7 micrometers.

[0111] For example, in a display device provided in one embodiment of this disclosure, the ratio of the difference between the average size of the first color filter in the first direction and the average size of the second color filter in the first direction and the difference between the average size of the first color filter in the first direction and the average size of the third color filter in the first direction is in the range of 2-3.

[0112] For example, in a display device provided in one embodiment of this disclosure, the first color filter includes a first edge portion, a second edge portion, and an intermediate portion located between the first edge portion and the second edge portion, wherein the average size of the intermediate portion in the first direction is smaller than the average size of the first edge portion in the first direction and the average size of the second edge portion in the first direction.

[0113] For example, in a display device provided in one embodiment of this disclosure, the first color filter includes a first contact surface that contacts the second color filter, the second color filter includes a second contact surface that contacts the third color filter, and the third color filter includes a third contact surface that contacts the first color filter. The dimension of the first contact surface in a second direction perpendicular to the driving substrate is equal to the dimension of the second contact surface in the second direction, and smaller than the dimension of the third contact surface in the second direction.

[0114] For example, in a display device provided in one embodiment of this disclosure, the distance between the first color filter and the surface of the driving substrate away from the anode layer is greater than the distance between the third color filter and the surface of the driving substrate away from the anode layer, and less than the distance between the second color filter and the surface of the driving substrate away from the anode layer.

[0115] For example, in a display device provided in one embodiment of this disclosure, the first color filter is a red filter, the second color filter is a green filter, and the third color filter is a blue filter.

[0116] For example, in a display device provided in one embodiment of this disclosure, the material of the color filter layer includes a desiccant.

[0117] For example, in a display device provided in one embodiment of this disclosure, the color filter layer includes aluminum.

[0118] For example, in a display device provided in one embodiment of this disclosure, the color filter layer further includes a black matrix located between any two adjacent colors among the first color filter, the second color filter, and the third color filter. Attached Figure Description

[0119] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly described below. Obviously, the drawings described below only relate to some embodiments of this disclosure and are not intended to limit this disclosure.

[0120] Figure 1 This is a planar schematic diagram of a display substrate provided in an embodiment of the present disclosure.

[0121] Figure 2 This is a partial structural schematic diagram of another display substrate provided in an embodiment of the present disclosure.

[0122] Figure 3 This is a partial structural schematic diagram of another display substrate provided in an embodiment of the present disclosure.

[0123] Figure 4AThis is a partial structural schematic diagram of another display substrate provided in an embodiment of the present disclosure.

[0124] Figure 4B This is a partial structural schematic diagram of another display substrate provided in an embodiment of the present disclosure.

[0125] Figure 5 This is a planar schematic diagram of a display substrate provided in an embodiment of the present disclosure.

[0126] Figure 6 This is a partial structural schematic diagram of another display substrate provided in an embodiment of the present disclosure.

[0127] Figure 7 This is a partial structural schematic diagram of another display substrate provided in an embodiment of the present disclosure.

[0128] Figure 8 This is a partial structural schematic diagram of another display substrate provided in an embodiment of the present disclosure.

[0129] Figure 9 This is a schematic diagram of a first color filter in a display substrate provided in an embodiment of the present disclosure.

[0130] Figure 10 This is a partial structural schematic diagram of another display substrate provided in an embodiment of the present disclosure.

[0131] Figure 11 This is a schematic diagram of the structure of a driving substrate provided in an embodiment of the present disclosure.

[0132] Figure 12 This is a partial structural schematic diagram of another display substrate provided in an embodiment of the present disclosure.

[0133] Figure 13 This is a schematic diagram of a display device provided according to an embodiment of the present disclosure.

[0134] Figure 14 This is a plan view of a display device provided in an embodiment of the present disclosure.

[0135] Figure 15 This is a schematic diagram of another display device provided according to an embodiment of the present disclosure.

[0136] Figure 16 This is a planar schematic diagram of a display substrate provided in an embodiment of the present disclosure.

[0137] Figure 17 This is a partial cross-sectional schematic diagram of a display substrate provided in an embodiment of the present disclosure.

[0138] Figure 18 This is an equivalent schematic diagram of a driving circuit in a display substrate according to an embodiment of the present disclosure.

[0139] Figure 19 This is a planar schematic diagram of a driving circuit in a display substrate according to an embodiment of the present disclosure.

[0140] Figures 20A-20E They are shown respectively Figure 19 The diagram shows a plan view of the layer layout of the display substrate.

[0141] Figure 21 This is a schematic diagram of a display substrate for setting a storage capacitor area according to an embodiment of the present disclosure.

[0142] Figure 22 This is a layout diagram of storage capacitors in a display substrate provided in an embodiment of the present disclosure.

[0143] Figures 23A-23D for Figure 22 Floor plan of each level.

[0144] Figure 23E This is a cross-sectional schematic diagram of a storage capacitor in a display substrate provided in an embodiment of the present disclosure.

[0145] Figure 24A This is a block diagram of a display substrate provided in one embodiment of the present disclosure.

[0146] Figure 24B This is a schematic diagram of a pixel circuit provided in one embodiment of the present disclosure.

[0147] Figure 24C A schematic diagram showing the latch-up effect formed by the pixel circuit is shown.

[0148] Figure 25A This is a schematic diagram of another pixel circuit provided in an embodiment of the present disclosure.

[0149] Figure 25B for Figure 24A The diagram shows a specific implementation example of the pixel circuit.

[0150] Figure 25C It shows Figure 25B The signal timing diagram of the pixel circuit shown is shown.

[0151] Figure 26A This is a schematic diagram of another display substrate provided in an embodiment of the present disclosure.

[0152] Figure 26B for Figure 26A A sectional view along section line I-I'.

[0153] Figure 27A This is a schematic diagram of another display substrate provided in an embodiment of the present disclosure.

[0154] Figure 27B This is a schematic diagram of another display substrate provided in an embodiment of the present disclosure.

[0155] Figures 28A-28E for Figure 27A The formation process of the substrate structure shown.

[0156] Figures 29A-29C This is a schematic diagram illustrating the formation process of a display substrate according to an embodiment of the present disclosure.

[0157] Figure 30A This is a schematic diagram of a second conductive layer in a display substrate according to an embodiment of the present disclosure.

[0158] Figure 30B This disclosure provides a schematic diagram of a first conductive layer and a second conductive layer in a display substrate according to an embodiment.

[0159] Figure 31A This is a schematic diagram of a third conductive layer in a display substrate according to an embodiment of the present disclosure.

[0160] Figure 31B This is a schematic diagram of a second conductive layer and a third conductive layer in a display substrate according to an embodiment of the present disclosure. Detailed Implementation

[0161] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0162] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that an element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as “connected” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect.

[0163] Traditional large-size organic light-emitting diode (OLED) displays reduce leakage current and crosstalk by isolating the anode. However, in micro-OLED displays, although the same method can reduce leakage current and crosstalk, the pixel confinement layer is thinner and the pixel density is higher, so the same method cannot completely isolate the light-emitting layer, and leakage current and crosstalk still exist.

[0164] This disclosure provides a display substrate and a display device. The display substrate includes a driving substrate, an anode layer, a pixel defining layer, a light-emitting functional layer, a cathode layer, and an encapsulation layer. The driving substrate includes a substrate and a driving circuit. The anode layer is located on the driving substrate. The pixel defining layer is located on the side of the anode layer away from the driving substrate. The light-emitting functional layer is located on the side of the anode layer away from the driving substrate. The cathode layer is located on the side of the light-emitting functional layer away from the driving substrate. The encapsulation layer is located on the side of the cathode layer away from the driving substrate. The driving circuit includes at least one transistor, the transistor including a semiconductor layer, the semiconductor layer being at least partially located inside the substrate. The anode layer includes multiple anodes, and the display substrate includes multiple pixel openings located on the side of the multiple anodes away from the driving substrate. The multiple pixel openings are configured to at least overlap with the multiple anodes. The light-emitting functional layer includes multiple light-emitting portions, the multiple light-emitting portions being in contact with the exposed portions of the multiple anodes. Each anode includes a main body portion and a protrusion portion, the protrusion portion being connected to the main body portion, and the size of the protrusion portion in a first direction perpendicular to the driving substrate is larger than the size of the main body portion in the first direction perpendicular to the driving substrate. Therefore, this display substrate can provide a miniature display substrate that can use a silicon-based circuit board as a driving substrate to drive the light-emitting functional layer to emit light and display, and can also reduce and avoid crosstalk between adjacent sub-pixels.

[0165] The display substrate and display device provided in the embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.

[0166] One embodiment of this disclosure provides a display substrate. Figure 1 This is a plan view of a display substrate provided according to an embodiment of the present disclosure; Figure 2 This is a partial structural schematic diagram of another display substrate provided in an embodiment of the present disclosure.

[0167] like Figure 1 and Figure 2As shown, the display substrate 500 includes a driving substrate 510, an anode layer 520, a pixel defining layer 530, a light-emitting functional layer 540, a cathode layer 550, and an encapsulation layer 560. The driving substrate 510 includes a substrate 512 and a driving circuit 514. The anode layer 520 is located on the driving substrate 510. The pixel defining layer 530 is located on the side of the anode layer 520 away from the driving substrate 510. The light-emitting functional layer 540 is located on the side of the anode layer 520 away from the driving substrate 510. The cathode layer 550 is located on the side of the light-emitting functional layer 540 away from the driving substrate 510. The encapsulation layer 560 is located on the side of the cathode layer 550 away from the driving substrate 510. The driving circuit 514 includes at least one transistor T, and the transistor T includes a semiconductor layer 102, which is at least partially located inside the substrate 512. That is, a portion of the substrate 512 can serve as a semiconductor layer. It should be noted that... Figure 1 and Figure 2 The complete structure of the driving circuit is not shown in the figure. The driving circuit may include transistors, storage capacitors, current control resistors, voltage divider resistors, etc. The specific circuit structure of the driving circuit can be set according to actual needs, and the embodiments of this disclosure do not limit it.

[0168] For example, the driving substrate 510 can be a silicon-based circuit board. Since silicon-based circuit boards utilize mature semiconductor manufacturing processes, have stable performance, and possess small size and precision, they are advantageous for fabricating micro-display devices. Of course, embodiments of this disclosure include, but are not limited to, other types of driving substrates may also be used.

[0169] In some examples, such as Figure 1 and Figure 2 As shown, the anode layer 520 includes a plurality of anodes 525, and the display substrate 500 includes a plurality of pixel openings 535. The plurality of pixel openings 535 are located in the film layer containing the pixel defining layer 530 and are surrounded by the pixel defining layer 530. The plurality of pixel openings 535 are located on the side of the plurality of anodes 525 away from the driving substrate 510, and the plurality of pixel openings 535 are configured to at least overlap with the plurality of anodes 525. The light-emitting functional layer 540 includes a plurality of light-emitting portions 545. The plurality of light-emitting portions 545 are at least partially located within the plurality of pixel openings 535 and are in contact with the exposed portions of the plurality of anodes 525. Thus, the plurality of anodes can drive the plurality of light-emitting portions to emit light for display.

[0170] In the display substrate provided in this embodiment, the driving substrate can be fabricated using semiconductor manufacturing processes, thereby integrating the pixel driving circuits used to drive each pixel to emit light and display light within the driving substrate. Therefore, this display substrate provides a miniature display substrate with advantages such as high resolution, high brightness, rich colors, low driving voltage, fast response speed, and low power consumption.

[0171] In some examples, such as Figure 1 and Figure 2 As shown, a plurality of anodes 525 are configured one-to-one with a plurality of pixel openings 535, and a plurality of pixel openings 535 are configured one-to-one with a plurality of light-emitting parts 545. It should be noted that the aforementioned "one-to-one correspondence" means that one pixel opening is provided on one anode, one light-emitting part is provided in one pixel opening, and the orthographic projection of the anode on the driving substrate at least partially overlaps with the orthographic projection of the corresponding pixel opening on the driving substrate, and the orthographic projection of the pixel opening on the driving substrate at least partially overlaps with the orthographic projection of the light-emitting part on the driving substrate. Of course, embodiments of this disclosure include, but are not limited to, this.

[0172] In some examples, such as Figure 2 As shown, the display substrate 100 further includes: a first planarization layer 591, a second planarization layer 592, and a reflective electrode layer 593; the first planarization layer 591 is located between the driving circuit 514 and the anode layer 520; the reflective electrode layer 593 is located on the side of the first planarization layer 591 near the anode layer 520; and the second planarization layer 592 is located on the side of the reflective electrode layer 593 near the anode layer 520.

[0173] In some examples, such as Figure 2 As shown, the reflective electrode layer 593 is continuously disposed in the pixel opening 535.

[0174] In some examples, such as Figure 1 and Figure 2 As shown, the display substrate also includes a color filter layer 570, located on the side of the encapsulation layer 560 away from the driving substrate 510. When the light-emitting functional layer is configured to emit white light, the color filter layer may include multiple color filters to achieve color display. Of course, embodiments of this disclosure include, but are not limited to, the light-emitting functional layer may also be configured to directly emit light of different colors.

[0175] In some examples, such as Figure 1 and Figure 2 As shown, the display substrate 500 also includes a protective layer 580 located on the side of the color filter layer 570 away from the driving substrate 510. The protective layer 580 can protect the color filter layer 570, so that the light filtering performance of the color filter layer 570 remains stable during long-term use, thereby improving the display quality of the display substrate.

[0176] In some examples, such as Figure 1 and Figure 2 As shown, the display substrate 500 also includes a glass cover plate 590 located on the side of the color filter layer 570 away from the driving substrate 510.

[0177] Figure 3 This is a partial structural schematic diagram of another display substrate provided in an embodiment of the present disclosure. Figure 4AThis is a partial structural schematic diagram of another display substrate provided in an embodiment of the present disclosure. For example... Figure 3 and Figure 4A As shown, Figure 3 The display substrate shown does not show a light-emitting layer. Figure 4A The display substrate shown contains a light-emitting functional layer.

[0178] like Figure 3 and Figure 4A As shown, each anode 525 includes a main body portion 525A and a protrusion portion 525B. The protrusion portion 525B is connected to the main body portion 525A, and the dimension of the protrusion portion 525B in the first direction is larger than the dimension of the main body portion 525A in the first direction; that is, the thickness of the protrusion portion 525B is greater than the thickness of the main body portion 525A. The distance between the surface of the first planarization layer 591 away from the substrate 512 at the location of the main body portion 525A and the substrate 512 is equal to the distance between the surface of the first planarization layer 591 away from the substrate 512 at the location of the protrusion portion 525B and the surface of the first planarization layer 591 away from the substrate 512. The distance between the surface of the main body portion 525A away from the substrate 512 and the surface of the first planarization layer 591 away from the substrate 512 is less than the distance between the surface of the protrusion portion 525B away from the substrate 512 and the surface of the first planarization layer 591 away from the substrate 512. It should be noted that the first direction can be a direction perpendicular to the driving substrate.

[0179] In the display substrate provided in this example, since the size of the protrusion 525B in the direction perpendicular to the driving substrate 510 is larger than the size of the main body 525A in the direction perpendicular to the driving substrate 510, the pixel defining layer 530 located between the two anodes 525 and overlapping with the edge portions of the anodes 525 can form a protrusion structure 532 corresponding to the protrusion 525. Therefore, when forming the light-emitting functional layer 540, at least some sub-functional layers (e.g., charge-generating layers) in the light-emitting functional layer 540 can be better disconnected at the location of the protrusion structure 532, that is, at least some sub-functional layers in the light-emitting portions 545 corresponding to the two adjacent anodes 525 are not connected, thereby effectively avoiding leakage and crosstalk between adjacent sub-pixels. On the other hand, the height of the protrusion structure 532 of the pixel defining layer 530 is also higher at this time, thereby better fulfilling the function of pixel defining and optically reducing and avoiding crosstalk between adjacent sub-pixels.

[0180] In some examples, such as Figure 3 and Figure 4A As shown, each anode 525 includes a main body portion 525A and a protrusion portion 525B. The protrusion portion 525B is disposed around the main body portion 525A, thereby enabling at least a portion of the functional layer in the light-emitting functional layer 540 to be disconnected at the edge of the main body portion 525A.

[0181] In some examples, such as Figure 3and Figure 4A As shown, the orthographic projection of the pixel limiting layer 530 on the driving substrate 510 overlaps with the orthographic projection of the protrusion 525B on the driving substrate 510. Thus, the pixel limiting layer 530 can form a protrusion structure 532 corresponding to the protrusion 525 and located on the side of the protrusion 525 away from the driving substrate 510.

[0182] In some examples, such as Figure 3 and Figure 4A As shown, the pixel defining layer 530 includes a pixel defining portion 530A, which includes a pixel defining flat portion 534 and two protrusion structures 532 on both sides of the pixel defining flat portion 534. The pixel defining flat portion 534 is located between two adjacent anodes 525, and the two protrusion structures 532 are located on the side of the two protrusions 525B of the two adjacent anodes 525 away from the driving substrate 510, respectively. The pixel defining flat portion 534 connects the two protrusion structures 532. That is, the pixel defining portion 530A includes both the portion located between two adjacent anodes 525 and the portion overlapping with the two anodes 525. Since the area between the two adjacent anodes 525 is relatively flat, and the edge portion of the anode 525 is provided with the aforementioned protrusions 525B, the portion located between the two adjacent anodes 525 is formed as the aforementioned pixel defining flat portion 534, while the portion overlapping with the two anodes 525 is formed as the aforementioned protrusion structure 532.

[0183] In the display substrate provided in this example, during the formation of the light-emitting functional layer 540, due to the presence of the pixel defining portion 530A, at least some sub-functional layers (e.g., charge generation layers) in the light-emitting functional layer 540 can be better disconnected at the location of the protrusion structure 532. That is, at least some sub-functional layers in the light-emitting portions 545 corresponding to two adjacent anodes 525 are not connected, thereby effectively avoiding leakage and crosstalk between adjacent sub-pixels. On the other hand, the height of the protrusion structure 532 is also higher at this time, thereby better fulfilling the function of pixel definition and optically reducing and avoiding crosstalk between adjacent sub-pixels.

[0184] In some examples, such as Figure 3 and Figure 4A As shown, the pixel defining portion 530A is symmetrically arranged about the center of the gap region 522 between two adjacent anodes 525. It should be noted that due to process errors, the two parts of the actual pixel defining portion on both sides of the center of the gap region may differ. Therefore, the above-mentioned case where the pixel defining portion is symmetrically arranged about the center of the gap region between two adjacent anodes includes the case where the overlap rate of the two parts of the pixel defining portion on both sides of the center of the gap region reaches 80%.

[0185] In some examples, such as Figure 3 and Figure 4AAs shown, each protrusion structure 532 includes a first sidewall 532A and a second sidewall 532B. The first sidewall 532A is located on the side of the protrusion structure 532 near the center of the main body 525A of the anode 525. The second sidewall 532B is connected to the first sidewall 532A and is located on the side of the first sidewall 532A away from the driving substrate 510. That is, the second sidewall 532B is further away from the driving substrate 510 than the first sidewall 532A. The slope angle of the first sidewall 532A is greater than the slope angle of the second sidewall 532B. It should be noted that since the first sidewall or the second sidewall may not be a standard plane in the actual process, the above-mentioned slope angle can be the slope angle of the line connecting the two endpoints of the first sidewall or the second sidewall.

[0186] In the display substrate provided in this example, during the formation of the light-emitting functional layer, the first sidewall has a steeper slope angle because its slope angle is greater than that of the second sidewall. This allows for better separation of at least some sub-functional layers (e.g., charge generation layers) within the light-emitting functional layer at the location of the first sidewall. Conversely, the second sidewall has a gentler slope angle than the first sidewall, forming a smoother platform. The second sidewall guides the material of the light-emitting functional layer, preventing poor contact areas from forming in the portion of the light-emitting functional layer exposed by the pixel opening and adjacent to the protrusion structure. This reduces the luminous intensity of the light-emitting functional layer in these areas. Therefore, the display substrate provided in this example can further reduce crosstalk between adjacent sub-pixels.

[0187] In some examples, such as Figure 4A As shown, a first aperture 5471 exists between the light-emitting functional layer 540 and the main body 525A, and at least one second aperture 5472 exists between the light-emitting functional layer 540 and the pixel defining layer 530. The space occupied by the first aperture 5471 is larger than the space occupied by the second aperture 5472. Thus, the first aperture 5471 and the second aperture 5472 form a weak conduction region for lateral carrier transfer in a common layer, which is beneficial for reducing lateral crosstalk of light. Of course, embodiments of this disclosure include, but are not limited to, the light-emitting functional layer and the pixel defining layer may not form the aforementioned second aperture.

[0188] Figure 4B This is a partial structural schematic diagram of another display substrate provided in an embodiment of the present disclosure. For example... Figure 4B As shown, the light-emitting functional layer 540 and the pixel limiting layer 530 are tightly bonded together.

[0189] In some examples, such as Figure 3 and Figure 4AAs shown, the protrusion structure 532 also includes a third sidewall 532C, located on the side of the protrusion structure 532 away from the main body 525A. The slope angle of the third sidewall 532C is greater than that of the second sidewall 532B, but less than that of the first sidewall 532A. Therefore, the slope angle of the third sidewall is relatively gentle, which reduces or even avoids the formation of pores in the light-emitting functional layer subsequently formed on the third sidewall, thereby preventing the formation of channels for water and oxygen intrusion. On the other hand, because the slope angle of the third sidewall is relatively gentle, it also facilitates the formation of a complete integrated structure for the pixel defining portion, avoiding peeling phenomena on the third sidewall.

[0190] In some examples, such as Figure 3 and Figure 4A As shown, each protruding structure 532 also includes a third sidewall 532C, which is located on the side of the protruding structure 532 away from the main body 525A. At this time, the slope angle of the first sidewall 532A is α, the slope angle of the second sidewall 532B is β, and the slope angle of the third sidewall 532C is γ, satisfying the following formula:

[0191] β < γ < α. In the display substrate provided in this example, the slope angle γ of the third sidewall 532C is gentler than the slope angle α of the first sidewall 532A, thereby reducing or even avoiding the formation of pores in the light-emitting functional layer subsequently formed on the third sidewall 532C, and thus preventing the formation of channels for water and oxygen intrusion. On the other hand, since the slope angle γ of the third sidewall 532C is gentler, it is also easier to form a complete integral structure for the pixel defining portion, avoiding peeling on the third sidewall. On the other hand, since the slope angle γ of the third sidewall 532C is greater than the slope angle β of the second sidewall 532B, it is possible to avoid the protruding structure occupying a large area, thus avoiding affecting the aperture ratio.

[0192] In some examples, such as Figure 3 and Figure 4A As shown, the difference between the slope angle of the first sidewall 532A and the slope angle of the second sidewall 532B is equal to i times the slope angle of the third sidewall, where i ranges from 0.8 to 1.2. Therefore, this protruding structure can effectively achieve the aforementioned effects of preventing crosstalk between adjacent sub-pixels, avoiding water and oxygen intrusion, and preventing the pixel definition portion from detaching.

[0193] In some examples, such as Figure 3 and Figure 4A As shown, the slope angle α of the first sidewall, the slope angle β of the second sidewall, and the slope angle γ of the third sidewall satisfy the following formula:

[0194] (α-β)=i*γ,

[0195] The value of i ranges from 0.8 to 1.2.

[0196] In the display substrate provided in this example, since the slope angle α of the first sidewall, the slope angle β of the second sidewall, and the slope angle γ of the third sidewall satisfy the size relationship defined by the above formula, the protrusion structure can better achieve the above-mentioned effects of preventing crosstalk between adjacent sub-pixels, avoiding water and oxygen intrusion, and preventing the pixel limiting part from falling off.

[0197] In some examples, such as Figure 3 and Figure 4A As shown, the difference between the slope angle of the first sidewall 532A and the slope angle of the second sidewall 532B is equal to j times the difference between the slope angle of the second sidewall 532B and the slope angle of the third sidewall 532C, where j ranges from 1.5 to 3. Therefore, this protruding structure can effectively achieve the aforementioned effects of preventing crosstalk between adjacent sub-pixels, avoiding water and oxygen intrusion, and preventing the pixel definition portion from detaching.

[0198] In some examples, such as Figure 3 and Figure 4A As shown, the slope angle α of the first sidewall, the slope angle β of the second sidewall, and the slope angle γ of the third sidewall satisfy the following formula:

[0199] (α-β)=j*(γ-β),

[0200] The value of j ranges from 1.5 to 3.

[0201] In the display substrate provided in this example, since the slope angle α of the first sidewall, the slope angle β of the second sidewall, and the slope angle γ of the third sidewall satisfy the size relationship defined by the above formula, the protrusion structure can better achieve the above-mentioned effects of preventing crosstalk between adjacent sub-pixels, avoiding water and oxygen intrusion, and preventing the pixel limiting part from falling off.

[0202] In some examples, such as Figure 3 and Figure 4A As shown, the sum of the slope angles of the first sidewall 532A and the second sidewall 532B is equal to k times the slope angle of the third sidewall 532C, where k ranges from 2 to 3. Therefore, this protruding structure effectively achieves the aforementioned effects of preventing crosstalk between adjacent sub-pixels, avoiding water and oxygen intrusion, and preventing the pixel definition portion from detaching.

[0203] In some examples, such as Figure 3 and Figure 4A As shown, the slope angle α of the first sidewall, the slope angle β of the second sidewall, and the slope angle γ of the third sidewall satisfy the following formula:

[0204] (α+β)=k*γ-β,

[0205] The value of k ranges from 2 to 3.

[0206] In the display substrate provided in this example, since the slope angle α of the first sidewall, the slope angle β of the second sidewall, and the slope angle γ of the third sidewall satisfy the size relationship defined by the above formula, the protrusion structure can better achieve the above-mentioned effects of preventing crosstalk between adjacent sub-pixels, avoiding water and oxygen intrusion, and preventing the pixel limiting part from falling off.

[0207] In some examples, such as Figure 3 and Figure 4A As shown, the slope angle of the first sidewall 532A can range from 75 to 89 degrees; the slope angle of the second sidewall 532B can range from 15 to 45 degrees; and the slope angle of the third sidewall 532C can range from 45 to 60 degrees.

[0208] In some examples, such as Figure 3 and Figure 4A As shown, the slope angle of the first sidewall 532A can range from 75 to 89 degrees; the slope angle of the second sidewall 532B can range from 25 to 35 degrees; and the slope angle of the third sidewall 532C can range from 45 to 55 degrees.

[0209] In some examples, such as Figure 3 and Figure 4A As shown, the orthographic projection of the second sidewall 532B onto the driving substrate 510 in the second direction is larger than the orthographic projection of the first sidewall 532A onto the driving substrate 510 in the second direction. Therefore, this protruding structure can better facilitate the disconnection of the charge generation layer in the light-emitting functional layer at the location of the first sidewall.

[0210] In some examples, such as Figure 3 and Figure 4A As shown, the orthographic projection of the third sidewall 532C onto the driving substrate 510 in the second direction is larger than the orthographic projection of the second sidewall 532B onto the driving substrate 510 in the second direction. Therefore, this protruding structure can reduce or even prevent the formation of pores in the light-emitting functional layer subsequently formed on the third sidewall 532C, thereby preventing the formation of channels for water and oxygen intrusion. On the other hand, since the slope angle γ of the third sidewall 532C is relatively gentle, it is also convenient for the pixel defining portion to form a complete integral structure, avoiding peeling phenomena on the third sidewall.

[0211] In some examples, such as Figure 3 and Figure 4A As shown, the first sidewall 532A has a dimension of H1 in the first direction, the second sidewall 532B has a dimension of H2 in the first direction, and the third sidewall 532C has a dimension of H3 in the first direction. H1, H2, and H3 satisfy the following formula:

[0212] H3*cosγ>H2*cosβ>H1*cosα.

[0213] Therefore, the protrusion structure can better facilitate the disconnection of the charge generation layer in the light-emitting functional layer at the location of the first sidewall; at the same time, the protrusion structure can reduce or even avoid the formation of pores in the light-emitting functional layer subsequently formed on the third sidewall, thereby avoiding the formation of channels for water and oxygen intrusion.

[0214] In some examples, such as Figure 3 and Figure 4A As shown, the protrusion 525B of each anode 525 also includes a fourth sidewall 525D, located on the side of the protrusion 525B near the center of the main body 525A. The slope angle of the fourth sidewall 525D is greater than the slope angle of the second sidewall 532B and less than the slope angle of the first sidewall 532A.

[0215] In some examples, such as Figure 3 and Figure 4A As shown, the protrusion 525B of the anode 525 includes a fourth sidewall 525D, located on the side of the protrusion 525B near the center of the main body 525A. The slope angle of the fourth sidewall is δ, and it satisfies the following formula:

[0216] β < δ < α.

[0217] In some examples, such as Figure 3 and Figure 4A As shown, the protrusion 525B of each anode 525 includes: a first sub-anode layer 5251, a second sub-anode layer 5252, and a third sub-anode layer 5253; the first sub-anode layer 5251 is located on the side of the drive circuit 514 away from the substrate 512; the second sub-anode layer 5252 is located on the side of the first sub-anode layer 5251 away from the drive substrate 510; and the third sub-anode layer 5253 is located on the side of the second sub-anode layer 5252 away from the drive substrate 510.

[0218] In some examples, such as Figure 3 and Figure 4AAs shown, the dimension of the first sub-anode layer 5251 in the second direction is larger than that of the third sub-anode layer 5253 in the second direction, and the dimension of the third sub-anode layer 5253 in the second direction is larger than that of the second sub-anode layer 5252 in the second direction. Therefore, since the dimension of the third sub-anode layer in the second direction is larger than that of the second sub-anode layer, the edge of the third sub-anode layer lacks support. This allows the third sub-anode layer 5253 to form a bent structure 5253S that bends towards the driving substrate 510, effectively preventing the pixel defining portion from peeling off during subsequent pixel defining portion formation. It should be noted that since the pixel defining portion is usually made of inorganic material, if the edge of the protrusion is too steep, peeling can easily occur.

[0219] On the other hand, the third sub-anode layer can be made of a material with poor conductivity, such as indium tin oxide. In this case, since the size of the third sub-anode layer in the second direction is larger than that of the second sub-anode layer in the second direction, the edge of the third sub-anode layer lacks support. Therefore, the third sub-anode layer can form a bent structure that bends towards the driving substrate, which can play a certain role in wrapping the edge of the protrusion. This can prevent the edge of the protrusion from contacting the light-emitting functional layer when there is a defect in the pixel limiting part, and can also avoid phenomena such as tip discharge.

[0220] For example, the second direction described above is either from the protrusion 525B to the main body 525A or from the main body 525A to the protrusion 525B, and the second direction is parallel to the surface of the driving substrate 510 away from the anode layer 520.

[0221] For example, the conductivity of the third sub-anode layer is lower than that of the first and second sub-anode layers, which allows for better matching with the work function of the light-emitting functional layer.

[0222] In some examples, such as Figure 3 and Figure 4A As shown, the dimension of the third sub-anode layer 5253 extending beyond the second sub-anode layer 5252 in the second direction is smaller than the dimension of the overlapping area in the second direction of the orthographic projection of the pixel limiting layer 530 on the driving substrate 510 and the orthographic projection of the protrusion 525B on the driving substrate 510.

[0223] In some examples, such as Figure 3 and Figure 4A As shown, the dimension of the third sub-anode layer 5253 extending beyond the second sub-anode layer 5252 in the second direction is less than 1 / 4 of the dimension of the overlapping area of ​​the orthographic projection of the pixel limiting layer 530 on the driving substrate 510 and the orthographic projection of the protrusion 525B on the driving substrate 510 in the second direction.

[0224] In some examples, such as Figure 3 and Figure 4A As shown, the end of the third sub-anode layer 5253 away from the main body 525A is bent toward the first sub-anode layer 5251, so that the third sub-anode layer can, to a certain extent, wrap the edge of the protrusion, thereby preventing the edge of the protrusion from contacting the light-emitting functional layer when a defect occurs in the pixel limiting part, and also avoiding phenomena such as tip discharge.

[0225] In some examples, such as Figure 3 and Figure 4A As shown, each anode 525's protrusion 525B also includes a fourth sub-anode layer 5254, located between the second sub-anode layer 5252 and the third sub-anode layer 5253. Thus, by retaining the fourth sub-anode layer located on the protrusion of the anode while etching away the fourth sub-anode layer located on the main body of the anode, the aforementioned main body and protrusion with height differences can be formed.

[0226] In some examples, such as Figure 3 and Figure 4A As shown, the dimension of the fourth sub-anode layer 5254 in the second direction is smaller than the dimension of the second sub-anode layer 5252 in the second direction. Therefore, the third sub-anode layer 5253 formed on the fourth sub-anode layer 5254 can better form a curved structure 5253S, thereby effectively preventing the pixel defining portion from peeling off during subsequent pixel defining portion formation.

[0227] In some examples, such as Figure 3 and Figure 4A As shown, the dimension of the third sub-anode layer 5253 extending beyond the fourth sub-anode layer 5254 in the second direction is smaller than the dimension of the overlapping area in the second direction of the orthographic projection of the pixel limiting layer 530 on the driving substrate 510 and the orthographic projection of the protrusion 525B on the driving substrate 510.

[0228] In some examples, such as Figure 3 and Figure 4A As shown, the second sub-anode layer 5252 includes a fifth sidewall 525E located on the side of the second sub-anode layer 525E away from the main body 525A, and the fourth sub-anode layer 5254 includes a sixth sidewall 525F located on the side of the fourth sub-anode layer 5254 away from the main body 525A. The slope angle of the fifth sidewall 525E is greater than the slope angle of the fourth sidewall 525D, the slope angle of the sixth sidewall 525F is greater than the slope angle of the fourth sidewall 525D, and the slope angle of the fifth sidewall 525E is greater than the slope angle of the sixth sidewall 525F, thereby preventing the formation of a pointed structure between the second and third sub-anode layers. This can suppress the pointed discharge phenomenon to a certain extent, thereby improving the product yield and service life.

[0229] In some examples, such as Figure 3 and Figure 4A As shown, the end of the first sub-anode layer 5251 away from the main body portion 525A includes a raised portion 5251A. The thickness of the raised portion 5251A in the direction perpendicular to the driving substrate 510 is greater than the average thickness of the first sub-anode layer 5251 in the direction perpendicular to the driving substrate 510. Therefore, the raised portion 5251A can also, to a certain extent, wrap around the edge of the protrusion, thereby preventing the edge of the protrusion from contacting the light-emitting functional layer when defects occur in the pixel limiting portion, and also avoiding phenomena such as tip discharge.

[0230] In some examples, such as Figure 3 and Figure 4A As shown, when the raised portion 5251A of the first sub-anode layer 5251 and the curved structure 5253S of the third sub-anode layer 5253 coexist, the raised portion 5251A and the curved structure 5253S can wrap the edge of the raised portion from both the top and bottom directions. This can better prevent the edge of the raised portion from contacting the light-emitting functional layer when defects occur in the pixel limiting portion, and can also avoid phenomena such as tip discharge. It should be noted that the embodiments of this disclosure include, but are not limited to, the raised portion 5251A of the first sub-anode layer 5251 or the curved structure 5253S of the third sub-anode layer 5253, when existing alone, can also wrap the edge of the raised portion to a certain extent.

[0231] In some examples, the ratio of the thickness of the first sub-anode layer 5251 in the direction perpendicular to the driving substrate 510 to the thickness of the second sub-anode layer 5252 in the direction perpendicular to the driving substrate 510 ranges from 1 / 15 to 1 / 5.

[0232] In some examples, the ratio of the thickness of the first sub-anode layer 5251 in the direction perpendicular to the driving substrate 510 to the thickness of the third sub-anode layer 5253 in the direction perpendicular to the driving substrate 510 ranges from 1 / 3 to 4 / 5.

[0233] In some examples, the ratio of the thickness of the first sub-anode layer 5251 in the direction perpendicular to the driving substrate 510 to the thickness of the fourth sub-anode layer 5254 in the direction perpendicular to the driving substrate 510 ranges from 1 / 24 to 1 / 8.

[0234] In some examples, the thickness of the first sub-anode layer 5251 in the direction perpendicular to the driving substrate 510 ranges from 1 to 4 nanometers; the thickness of the second sub-anode layer 5252 in the direction perpendicular to the driving substrate 510 ranges from 15 to 22 nanometers; the thickness of the fourth sub-anode layer 5254 in the direction perpendicular to the driving substrate 510 ranges from 24 to 32 nanometers; and the thickness of the third sub-anode layer 5253 in the direction perpendicular to the driving substrate 510 ranges from 3 to 5 nanometers.

[0235] In some examples, the thickness of the first sub-anode layer 5251 in the direction perpendicular to the driving substrate 510 ranges from 2 to 3 nanometers; the thickness of the second sub-anode layer 5252 in the direction perpendicular to the driving substrate 510 ranges from 17 to 20 nanometers; the thickness of the fourth sub-anode layer 5254 in the direction perpendicular to the driving substrate 510 ranges from 26 to 30 nanometers; and the thickness of the third sub-anode layer 5253 in the direction perpendicular to the driving substrate 510 ranges from 4 nanometers.

[0236] In some examples, the ratio of the distance between two adjacent anodes 525 to the length of the orthographic projection of the protrusion 525B of the anode 525 onto the driving substrate 510 ranges from 2 to 4. That is, the ratio of the distance between two adjacent anodes 525 to the length of the anode 525 in the second direction ranges from 2 to 4. As a result, the display substrate can better avoid crosstalk between adjacent sub-pixels.

[0237] In some examples, the ratio of the distance between two adjacent anodes 525 to the length of the orthographic projection of the protrusion 525B of the anode 525 onto the driving substrate 510 ranges from 2.5 to 3.5. That is, the ratio of the distance between two adjacent anodes 525 to the length of the anode 525 in the second direction ranges from 2.5 to 3.5. Therefore, the display substrate can better avoid crosstalk between adjacent sub-pixels.

[0238] In some examples, the distance between two adjacent anodes 525 ranges from 0.6 to 1 micrometer. That is, the width of the spacer region 522 can range from 0.6 to 1 micrometer. Of course, embodiments of this disclosure include, but are not limited to, this, and the width range of the spacer region can be set according to actual conditions.

[0239] In some examples, the distance between two adjacent anodes 525 ranges from 0.7 to 0.9 micrometers. Of course, embodiments of this disclosure include, but are not limited to, this, and the width range of the spacing region can be set according to actual conditions.

[0240] Figure 5 This is a planar schematic diagram of a display substrate provided according to an embodiment of the present disclosure. For example... Figure 5As shown, the protrusion 525B is provided around the main body 525A. Therefore, this display substrate can effectively avoid crosstalk between adjacent sub-pixels in any direction, thereby allowing the display substrate to adapt to different pixel arrangement structures.

[0241] In some examples, such as Figure 5 As shown, the orthographic projection of the anode 525 onto the driving substrate 510 has a hexagonal shape. Of course, embodiments of this disclosure include, but are not limited to, other suitable shapes for the orthographic projection of the anode 525 onto the driving substrate 510. It should be noted that the pixel opening is correspondingly disposed to the anode; therefore, the shape of the orthographic projection of the pixel opening onto the driving substrate is similar to the shape of the orthographic projection of the anode onto the driving substrate.

[0242] In some examples, such as Figure 5 As shown, multiple anodes 525 are arranged in an array on the driving substrate 510 to form anode rows 610; in each anode row 610, multiple anodes 525 are arranged sequentially along the direction.

[0243] In some examples, such as Figure 5 As shown, the second direction can be the row direction. In this case, the ratio of the size of the orthographic projection of each anode 525 onto the driving substrate 510 in the second direction to the distance between two adjacent anodes 525 is in the range of 4-6. Therefore, the display substrate can achieve a large aperture ratio and effectively avoid crosstalk between adjacent sub-pixels.

[0244] In some examples, such as Figure 5 As shown, the size of the orthographic projection of each anode 525 onto the driving substrate 510 in the second direction can be 4-5 micrometers.

[0245] Figure 6 This is a partial structural schematic diagram of another display substrate provided in an embodiment of the present disclosure. For example... Figure 6 As shown, Figure 6 As shown, the protrusion 525B of each anode 525 includes a first sub-anode layer 5251, a second sub-anode layer 5252, and a third sub-anode layer 5253; the first sub-anode layer 5251 is located on the side of the driving circuit 514 away from the substrate 512; the second sub-anode layer 5252 is located on the side of the first sub-anode layer 5251 away from the driving substrate 510; and the third sub-anode layer 5253 is located on the side of the second sub-anode layer 5252 away from the driving substrate 510. Figure 3 and Figure 4A The difference between the display substrate shown is that... Figure 6 The display substrate shown does not include the fourth sub-anode layer.

[0246] In some examples, such as Figure 6As shown, the main body 525A and the protrusion 525B of the anode 525 can have the same layer structure, that is, include the same number of multiple film layers and the same stacking relationship, but it is not limited that the thickness of each film layer is the same. In this case, the second sub-anode layer of the anode protrusion can be retained by etching the second sub-anode layer of the anode main body, thereby forming a main body and a protrusion with different heights.

[0247] In some examples, such as Figure 6 As shown, the dimension of the first sub-anode layer 5251 in the second direction is larger than that of the third sub-anode layer 5253 in the second direction, and the dimension of the third sub-anode layer 5253 in the second direction is larger than that of the second sub-anode layer 5252 in the second direction. The aforementioned second direction is either from the protrusion 525B to the main body 525A or from the main body 525A to the protrusion 525B, and the second direction is parallel to the direction of the driving substrate 510 away from the surface of the anode layer 520. Therefore, since the dimension of the third sub-anode layer in the second direction is larger than that of the second sub-anode layer in the second direction, the edge of the third sub-anode layer lacks support. This allows the third sub-anode layer 5253 to form a bent structure 5253S that bends towards the driving substrate 510, effectively preventing the pixel defining portion from peeling off during subsequent pixel defining portion formation. It should be noted that since the pixel defining portion is usually made of inorganic material, if the edge of the protrusion is too steep, peeling can easily occur.

[0248] On the other hand, the third sub-anode layer can be made of a material with poor conductivity, such as indium tin oxide. In this case, since the size of the third sub-anode layer in the second direction is larger than that of the second sub-anode layer in the second direction, the edge of the third sub-anode layer lacks support. Therefore, the third sub-anode layer can form a bent structure that bends towards the driving substrate, which can play a certain role in wrapping the edge of the protrusion. This can prevent the edge of the protrusion from contacting the light-emitting functional layer when there is a defect in the pixel limiting part, and can also avoid phenomena such as tip discharge.

[0249] For example, the conductivity of the third sub-anode layer is less than that of the first sub-anode layer and the second sub-anode layer.

[0250] In some examples, such as Figure 6 As shown, the end of the third sub-anode layer 5253 away from the main body 525A is bent toward the first sub-anode layer 5251, so that the third sub-anode layer can, to a certain extent, wrap the edge of the protrusion, thereby preventing the edge of the protrusion from contacting the light-emitting functional layer when a defect occurs in the pixel limiting part, and also avoiding phenomena such as tip discharge.

[0251] In some examples, such as Figure 6As shown, the second sub-anode layer 5252 includes a fifth sidewall 525E and a sixth sidewall 525F. The sixth sidewall 525F is located on the side of the fifth sidewall 525E that is farther from the driving substrate 510, meaning the sixth sidewall 525F is farther from the driving substrate 510 than the fifth sidewall 525E. The slope angle of the fifth sidewall 525E is greater than that of the fourth sidewall 525D, and the slope angle of the sixth sidewall 525F is greater than that of the fourth sidewall 525D. The slope angle of the fifth sidewall 525E is greater than that of the sixth sidewall 525F, thereby preventing the formation of a sharp structure in the second sub-anode layer. This can suppress sharp discharge phenomena to a certain extent, thereby improving product yield and lifespan. Furthermore, by forming a stepped structure including the fifth and sixth sidewalls at the edge of the second sub-anode layer 5252, a smoother curved structure can be formed in the third sub-anode layer located on the second sub-anode layer, thereby better preventing the pixel defining portion from detaching.

[0252] In some examples, such as Figure 6 As shown, the end of the first sub-anode layer 5251 away from the main body portion 525A includes a raised portion 5251A. The thickness of the raised portion 5251A in the direction perpendicular to the driving substrate 510 is greater than the average thickness of the first sub-anode layer 5251 in the direction perpendicular to the driving substrate 510. Therefore, the raised portion 5251A can also, to a certain extent, wrap around the edge of the protrusion, thereby preventing the edge of the protrusion from contacting the light-emitting functional layer when defects occur in the pixel limiting portion, and also avoiding phenomena such as tip discharge.

[0253] In some examples, such as Figure 6 As shown, when the raised portion 5251A of the first sub-anode layer 5251 and the curved structure 5253S of the third sub-anode layer 5253 coexist, the raised portion 5251A and the curved structure 5253S can wrap the edge of the raised portion from both the top and bottom directions. This can better prevent the edge of the raised portion from contacting the light-emitting functional layer when defects occur in the pixel limiting portion, and can also avoid phenomena such as tip discharge. It should be noted that the embodiments of this disclosure include, but are not limited to, the raised portion 5251A of the first sub-anode layer 5251 or the curved structure 5253S of the third sub-anode layer 5253, when existing alone, can also wrap the edge of the raised portion to a certain extent.

[0254] Figure 7 This is a partial structural schematic diagram of another display substrate provided in an embodiment of the present disclosure. For example... Figure 7 As shown, Figure 7As shown, the protrusion 525B of each anode 525 includes a first sub-anode layer 5251, a second sub-anode layer 5252, a third sub-anode layer 5253, and a fourth sub-anode layer 5254; the first sub-anode layer 5251 is located on the side of the driving circuit 514 away from the substrate 512; the second sub-anode layer 5252 is located on the side of the first sub-anode layer 5251 away from the driving substrate 510; the third sub-anode layer 5253 is located on the side of the second sub-anode layer 5252 away from the driving substrate 510; and the fourth sub-anode layer 5254 is located between the second sub-anode layer 5252 and the third sub-anode layer 5253.

[0255] In some examples, such as Figure 7 As shown, the main body 525A and the protrusion 525B of the anode 525 can have the same layer structure, that is, include the same number of multiple film layers and the same stacking relationship, but the thickness of each film layer is not limited to be the same. In this case, the main body 525A of the anode 525 also includes a first sub-anode layer 5251, a second sub-anode layer 5252, a third sub-anode layer 5253, and a fourth sub-anode layer 5254; the first sub-anode layer 5251 is located on the side of the drive circuit 514 away from the substrate 512; the second sub-anode layer 5252 is located on the side of the first sub-anode layer 5251 away from the drive substrate 510; the third sub-anode layer 5253 is located on the side of the second sub-anode layer 5252 away from the drive substrate 510; and the fourth sub-anode layer 5254 is located between the second sub-anode layer 5252 and the third sub-anode layer 5253. In this case, by etching the second sub-anode layer portion located in the main body of the anode, the second sub-anode layer of the protrusion of the anode can be retained, thereby forming a main body and a protrusion with different heights.

[0256] For example, such as Figure 7 As shown, the thickness of the first sub-anode layer 5251 of the main body portion 525A of the anode 525 in the direction perpendicular to the driving substrate 510 is the same as the thickness of the first sub-anode layer 5251 of the protrusion portion 525B of the anode 525 in the direction perpendicular to the driving substrate 510.

[0257] For example, such as Figure 7 As shown, the thickness of the third sub-anode layer 5253 of the main body portion 525A of the anode 525 in the direction perpendicular to the drive substrate 510 is the same as the thickness of the third sub-anode layer 5253 of the protrusion portion 525B of the anode 525 in the direction perpendicular to the drive substrate 510.

[0258] For example, such as Figure 7 As shown, the thickness of the fourth sub-anode layer 5254 of the main body portion 525A of the anode 525 in the direction perpendicular to the drive substrate 510 is the same as the thickness of the fourth sub-anode layer 5254 of the protrusion portion 525B of the anode 525 in the direction perpendicular to the drive substrate 510.

[0259] In some examples, such as Figure 7 As shown, the dimension of the first sub-anode layer 5251 in the second direction is larger than that of the third sub-anode layer 5253 in the second direction, and the dimension of the third sub-anode layer 5253 in the second direction is larger than that of the second sub-anode layer 5252 in the second direction; the dimension of the fourth sub-anode layer 5254 in the second direction is smaller than that of the second sub-anode layer 5252 in the second direction. The aforementioned second direction is either from the protrusion 525B to the main body 525A or from the main body 525A to the protrusion 525B, and the second direction is parallel to the direction of the driving substrate 510 away from the surface of the anode layer 520. Therefore, the third sub-anode layer 5253 formed on the fourth sub-anode layer 5254 can better form a curved structure 5253S, thereby effectively preventing the pixel defining portion from peeling off during subsequent pixel defining portion formation.

[0260] On the other hand, the third sub-anode layer can be made of a material with poor conductivity, such as indium tin oxide. In this case, since the size of the third sub-anode layer in the second direction is larger than that of the second sub-anode layer in the second direction, the edge of the third sub-anode layer lacks support. Therefore, the third sub-anode layer can form a bent structure that bends towards the driving substrate, which can play a certain role in wrapping the edge of the protrusion. This can prevent the edge of the protrusion from contacting the light-emitting functional layer when there is a defect in the pixel limiting part, and can also avoid phenomena such as tip discharge.

[0261] For example, the conductivity of the third sub-anode layer is less than that of the first sub-anode layer and the second sub-anode layer.

[0262] In some examples, such as Figure 7 As shown, the end of the third sub-anode layer 5253 away from the main body 525A is bent toward the first sub-anode layer 5251, so that the third sub-anode layer can, to a certain extent, wrap the edge of the protrusion, thereby preventing the edge of the protrusion from contacting the light-emitting functional layer when a defect occurs in the pixel limiting part, and also avoiding phenomena such as tip discharge.

[0263] In some examples, such as Figure 7As shown, the second sub-anode layer 5252 includes a fifth sidewall 525E located on the side of the second sub-anode layer 525E away from the main body 525A, and the fourth sub-anode layer 5254 includes a sixth sidewall 525F located on the side of the fourth sub-anode layer 5254 away from the main body 525A. The slope angle of the fifth sidewall 525E is greater than the slope angle of the fourth sidewall 525D, the slope angle of the sixth sidewall 525F is greater than the slope angle of the fourth sidewall 525D, and the slope angle of the fifth sidewall 525E is greater than the slope angle of the sixth sidewall 525F, thereby preventing the formation of a pointed structure between the second and third sub-anode layers. This can suppress the pointed discharge phenomenon to a certain extent, thereby improving the product yield and service life.

[0264] In some examples, such as Figure 7 As shown, the end of the first sub-anode layer 5251 away from the main body portion 525A includes a raised portion 5251A. The thickness of the raised portion 5251A in the direction perpendicular to the driving substrate 510 is greater than the average thickness of the first sub-anode layer 5251 in the direction perpendicular to the driving substrate 510. Therefore, the raised portion 5251A can also, to a certain extent, wrap around the edge of the protrusion, thereby preventing the edge of the protrusion from contacting the light-emitting functional layer when defects occur in the pixel limiting portion, and also avoiding phenomena such as tip discharge.

[0265] In some examples, such as Figure 7 As shown, when the raised portion 5251A of the first sub-anode layer 5251 and the curved structure 5253S of the third sub-anode layer 5253 coexist, the raised portion 5251A and the curved structure 5253S can wrap the edge of the raised portion from both the top and bottom directions. This can better prevent the edge of the raised portion from contacting the light-emitting functional layer when defects occur in the pixel limiting portion, and can also avoid phenomena such as tip discharge. It should be noted that the embodiments of this disclosure include, but are not limited to, the raised portion 5251A of the first sub-anode layer 5251 or the curved structure 5253S of the third sub-anode layer 5253, when existing alone, can also wrap the edge of the raised portion to a certain extent.

[0266] Figure 8 This is a partial structural schematic diagram of another display substrate provided in an embodiment of the present disclosure. For example... Figure 8 As shown, the encapsulation layer 560 includes an inorganic encapsulation layer 710; the inorganic encapsulation layer 710 is located on the side of the cathode layer 550 away from the driving substrate 510.

[0267] In some examples, such as Figure 8As shown, the inorganic encapsulation layer 710 includes a plurality of sub-inorganic encapsulation layers 7100. At least two adjacent sub-inorganic encapsulation layers 7100 are made of different materials, and at least two adjacent sub-inorganic encapsulation layers 7100 are made of the same material. By providing at least two adjacent sub-inorganic encapsulation layers 7100 made of different materials and at least two adjacent sub-inorganic encapsulation layers 7100 made of the same material between the plurality of sub-inorganic encapsulation layers 7100, the inorganic encapsulation layer can form a denser film layer, thereby better preventing water and oxygen intrusion and thus improving the service life of the display device.

[0268] For example, the material of each sub-inorganic encapsulation layer 7100 may be selected from at least one of silicon nitride, silicon oxide, and silicon oxynitride.

[0269] In some examples, such as Figure 8 As shown, in the direction away from the driving substrate 510, the refraction of the multiple sub-inorganic encapsulation layers 7100 first increases and then decreases. When the emitted light from the light-emitting functional layer 540 enters the sub-inorganic encapsulation layer with a lower refractive index from the sub-inorganic encapsulation layer with a higher refractive index, the emitted light is refracted at the interface between them, thereby reducing the emitted light diffusion angle and thus reducing or avoiding crosstalk between adjacent sub-pixels within the display substrate. Then, the emitted light enters the sub-inorganic encapsulation layer with a lower refractive index from the sub-inorganic encapsulation layer with a higher refractive index and is refracted at the interface between them. At this time, the diffusion angle of the emitted light increases, but since the emitted light is already close to the light-emitting surface of the display substrate, it will not cause crosstalk to adjacent sub-pixels.

[0270] In some examples, such as Figure 8 As shown, each sub-inorganic encapsulation layer 7100 includes an alternately arranged flat region PTQ and double-arched spacer region JGQ, a first arched region GX1 located on the side of the flat region PTQ away from the double-arched spacer region JGQ, a second arched region GX2 located between the flat region PTQ and the double-arched spacer region JGQ, and a third arched region GX3 located on the flat region PTQ away from the second arched region GX2. The first arched region GX1 and the second arched region GX2 are symmetrically arranged about the center of the flat region PTQ.

[0271] In some examples, such as Figure 8As shown, the orthographic projections of the first arched region GX1, the second arched region GX2, or the third arched region GX3 on the driving substrate 510 overlap with the orthographic projections of the protrusions 525B on the driving substrate 510, and the orthographic projection of the flat region PTQ on the driving substrate 510 overlaps with the orthographic projection of the main body 525A on the driving substrate 510. In other words, the orthographic projections of the first arched region GX1, the second arched region GX2, or the third arched region GX3 of each sub-inorganic encapsulation layer 7100 on the driving substrate 510 overlap with the orthographic projections of the protrusions 525B on the driving substrate 510, and the orthographic projections of the flat region PTQ of each sub-inorganic encapsulation layer 7100 on the driving substrate 510 overlap with the orthographic projections of the main body 525A on the driving substrate 510; furthermore, the first arched region GX1, the second arched region GX2, and the third arched region GX3 of each sub-inorganic encapsulation layer 7100 overlap with the protrusions 525B of different anodes 525. Therefore, light from the edges of each sub-pixel can be refracted through the first, second, or third arched regions and converge onto the black matrix, thus avoiding crosstalk between adjacent sub-pixels. It should be noted that the aforementioned black matrix can be a typical black matrix or a structure with low light transmittance formed by overlapping at least two color filters, serving the function of a black matrix.

[0272] In some examples, such as Figure 8 As shown, the flat region PTQ has a dimension L in the second direction. The distance between the center of the second arched region GX2 and the center of the third arched region GX3 in the second direction is the first distance D1. The distance between the center of the first arched region GX1 and the center of the second arched region GX2 in the second direction is the second distance D2. The radii of curvature of the first arched region GX1, the second arched region GX2, and the third arched region GX3 are all R. The first distance D1 satisfies the following formula:

[0273] D2≤(L+D1)<(L+R).

[0274] In the display substrate provided in this example, by ensuring that the first distance D1 satisfies the above formula, the pixel density or aperture ratio can be increased while reducing crosstalk between adjacent sub-pixels, thereby achieving a better display effect. It should be noted that the aforementioned radius of curvature is the average radius of curvature, i.e., the reciprocal of the average curvature of the corresponding arc. For example, the aforementioned second direction is either the direction from the protrusion to the main body or the direction from the main body to the protrusion, and the second direction is parallel to the surface of the driving substrate away from the anode layer.

[0275] In some examples, such as Figure 8As shown, the flat region PTQ has a dimension L in the second direction. The distance between the center of the second arched region GX2 and the center of the third arched region GX3 in the second direction is the first distance D1. The distance between the center of the first arched region GX1 and the center of the second arched region GX2 in the second direction is the second distance D2. The radii of curvature of the first arched region GX1, the second arched region GX2, and the third arched region GX3 are all R. The first distance D1 satisfies the following formula:

[0276] (L+D1)≤D2<(L+R).

[0277] In the display substrate provided in this example, by making the first distance D1 satisfy the above formula, the crosstalk between adjacent sub-pixels can be reduced while increasing the pixel density or aperture ratio, thereby obtaining a better display effect.

[0278] For example, the second direction mentioned above is either from the protrusion to the main body or from the main body to the protrusion, and the second direction is parallel to the surface of the driving substrate away from the anode layer.

[0279] In some examples, such as Figure 8 As shown, in each sub-inorganic packaging layer 7100, the distance between the surface of the first arched region GX1, the second arched region GX2, or the third arched region GX3 away from the driving substrate 510 and the driving substrate 510 is greater than the distance between the surface of the flat region PTQ away from the driving substrate 510 and the driving substrate 510. Therefore, the first arched region GX1, the second arched region GX2, or the third arched region GX3 has an upwardly arched structure.

[0280] In some examples, such as Figure 8 As shown, the orthographic projection of the double-arched spacer region JGQ on the driving substrate 510 overlaps with the orthographic projection of the spacer region 522 between two adjacent anodes 525 on the driving substrate 510.

[0281] In some examples, such as Figure 8 As shown, the plurality of sub-inorganic packaging layers 7100 include: a first sub-inorganic packaging layer 711, a second sub-inorganic packaging layer 712, a third sub-inorganic packaging layer 713, and a fourth sub-inorganic packaging layer 714; the first sub-inorganic packaging layer 711 is located on the side of the cathode layer 550 away from the driving substrate 510; the second sub-inorganic packaging layer 712 is located on the side of the first sub-inorganic packaging layer 711 away from the driving substrate 510; the third sub-inorganic packaging layer 713 is located on the side of the second sub-inorganic packaging layer 711 away from the driving substrate 510; and the fourth sub-inorganic packaging layer 714 is located on the side of the third sub-inorganic packaging layer 713 away from the driving substrate 510.

[0282] In some examples, such as Figure 8As shown, the refractive index of the first sub-inorganic encapsulation layer 711 is less than that of the second sub-inorganic encapsulation layer 712, and the refractive index of the fourth sub-inorganic encapsulation layer 714 is less than that of the third sub-inorganic encapsulation layer 713. Therefore, when the emitted light from the light-emitting functional layer 540 enters the second sub-inorganic encapsulation layer 712 (which has a higher refractive index) from the first sub-inorganic encapsulation layer 711, the emitted light is refracted at the interface between the first and second sub-inorganic encapsulation layers 711 and 712, thereby reducing the emitted light diffusion angle and reducing or avoiding crosstalk between adjacent sub-pixels within the display substrate. Then, the emitted light enters the fourth sub-inorganic encapsulation layer 714 (which has a lower refractive index) from the third sub-inorganic encapsulation layer 713 (which has a higher refractive index) and is refracted at the interface between them. At this time, the diffusion angle of the emitted light increases, but since the emitted light is already close to the light-emitting surface of the display substrate, it will not cause crosstalk to adjacent sub-pixels.

[0283] In some examples, such as Figure 8 As shown, the refractive index of the second sub-inorganic encapsulation layer 712 is equal to that of the third sub-inorganic encapsulation layer 713. In this case, the second sub-inorganic encapsulation layer 712 and the third sub-inorganic encapsulation layer 713 can be made of the same material. Of course, embodiments of this disclosure include, but are not limited to, the refractive indices of the second and third sub-inorganic encapsulation layers may also be unequal.

[0284] In some examples, such as Figure 8 As shown, the first sub-inorganic encapsulation layer 711 and the second sub-inorganic encapsulation layer 712 are made of different materials; the fourth sub-inorganic encapsulation layer 714 and the third sub-inorganic encapsulation layer 713 can be made of different materials.

[0285] For example, the first sub-inorganic encapsulation layer 711 is made of silicon oxide or silicon oxynitride, the second sub-inorganic encapsulation layer 712 is made of silicon nitride, the fourth sub-inorganic encapsulation layer 714 is made of silicon oxide, and the third sub-inorganic encapsulation layer 713 is made of silicon nitride.

[0286] In some examples, such as Figure 8 As shown, the first sub-inorganic encapsulation layer 711 and the fourth sub-inorganic encapsulation layer 714 can be made of the same material or different materials.

[0287] For example, both the first sub-inorganic encapsulation layer 711 and the fourth sub-inorganic encapsulation layer 714 are made of silicon oxide material; or, the first sub-inorganic encapsulation layer 711 is made of silicon oxynitride material and the fourth sub-inorganic encapsulation layer 714 is made of silicon oxide material.

[0288] In some examples, such as Figure 8As shown, the first arched region GX1 of the first sub-inorganic encapsulation layer 711 has a first radius of curvature on its upper surface away from the substrate 512; the first arched region GX1 of the second sub-inorganic encapsulation layer 712 has a second radius of curvature on its upper surface away from the substrate 512; the first arched region GX1 of the third sub-inorganic encapsulation layer 713 has a third radius of curvature on its upper surface away from the substrate 512; and the first arched region GX1 of the fourth sub-inorganic encapsulation layer 714 has a fourth radius of curvature on its upper surface away from the substrate 512. The first radius of curvature is smaller than the second radius of curvature, the second radius of curvature is smaller than the third radius of curvature, and the third radius of curvature is smaller than the fourth radius of curvature. In other words, in the direction away from the driving substrate 510, the radius of curvature of the first arched region of each sub-inorganic encapsulation layer gradually increases.

[0289] In some examples, such as Figure 8 As shown, similar to the relationship satisfied by the radius of curvature of the first arched region of each sub-inorganic packaging layer away from the substrate, the radius of curvature of the second arched region of each sub-inorganic packaging layer away from the substrate also gradually increases in the direction away from the driving substrate.

[0290] In some examples, such as Figure 8 As shown, similar to the relationship satisfied by the radius of curvature of the first arched region of each sub-inorganic packaging layer away from the substrate, the radius of curvature of the third arched region of each sub-inorganic packaging layer away from the substrate also gradually increases in the direction away from the driving substrate.

[0291] In some examples, such as Figure 8 As shown, the first arched region GX1, the second arched region GX2, and the third arched region GX3 of the first sub-inorganic encapsulation layer 711 have the same shape; the first arched region GX1, the second arched region GX2, and the third arched region GX3 of the second sub-inorganic encapsulation layer 712 have the same shape; the first arched region GX1, the second arched region GX2, and the third arched region GX3 of the third sub-inorganic encapsulation layer 713 have the same shape; and the first arched region GX1, the second arched region GX2, and the third arched region GX3 of the fourth sub-inorganic encapsulation layer 714 have the same shape.

[0292] In some examples, such as Figure 8 As shown, the illusory center of the first arched region of the fourth sub-inorganic packaging layer 714 is located between the upper surface of the first sub-inorganic packaging layer 711 away from the substrate 512 and the lower surface of the fourth sub-inorganic packaging layer 714 near the substrate 512. It should be noted that the aforementioned illusory center refers to the center of a virtual circle drawn with the arc of the upper surface of the first arched region away from the substrate.

[0293] In some examples, such as Figure 8As shown, the first sub-inorganic encapsulation layer 711 has a first thickness TH1 in the direction perpendicular to the driving substrate 510, the second sub-inorganic encapsulation layer 712 has a second thickness TH2 in the direction perpendicular to the driving substrate 510, the third sub-inorganic encapsulation layer 713 has a third thickness TH3 in the direction perpendicular to the driving substrate 510, and the fourth sub-inorganic encapsulation layer 714 has a fourth thickness TH4 in the direction perpendicular to the driving substrate 510. The first thickness TH1 is greater than the second thickness TH2, the second thickness TH2 is greater than the third thickness TH3, and the third thickness TH3 is greater than the fourth thickness TH4. That is, the thickness of each sub-inorganic encapsulation layer gradually decreases in the direction away from the driving substrate 510.

[0294] In some examples, such as Figure 8 As shown, the ratio of the difference between the first thickness TH1 and the second thickness TH2, and the ratio of the difference between the third thickness TH3 and the fourth thickness TH4, ranges from 1.5 to 2 times; that is, the first thickness TH1, the second thickness TH2, the third thickness TH3, and the fourth thickness TH4 satisfy the following formula: TH1 - TH2 = m * (TH3 - TH4), where the value of m ranges from 1.2 to 2. Therefore, this display substrate can better avoid crosstalk between adjacent sub-pixels.

[0295] In some examples, such as Figure 8 As shown, the ratio of the sum of the second thickness TH2 and the third thickness TH3 to the first thickness TH1 ranges from 0.8 to 1.2; that is, the first thickness TH1, the second thickness TH2, and the third thickness TH3 satisfy the following formula: (TH2 + TH3) = n * TH1, where n ranges from 0.8 to 1.2. Therefore, this display substrate can better avoid crosstalk between adjacent sub-pixels.

[0296] In some examples, such as Figure 8 As shown, the first thickness ranges from 1000 to 1200 nanometers, the second thickness ranges from 500 to 660 nanometers, the third thickness ranges from 480 to 560 nanometers, and the fourth thickness ranges from 180 to 260 nanometers.

[0297] In some examples, the material of the first sub-inorganic encapsulation layer includes silicon oxide or silicon oxynitride, the material of the second sub-inorganic encapsulation layer includes silicon nitride, the material of the third sub-inorganic encapsulation layer includes silicon nitride, and the material of the fourth sub-inorganic encapsulation layer includes silicon oxide. Of course, embodiments of this disclosure are not limited to these, and the material of each sub-inorganic encapsulation layer may also be other suitable materials.

[0298] In some examples, the first thickness is 1100 nanometers, the second thickness ranges from 580 nanometers, the third thickness ranges from 520 nanometers, and the fourth thickness ranges from 220 nanometers. Of course, embodiments of this disclosure include, but are not limited to, the thickness of each sub-inorganic encapsulation layer may also be other values.

[0299] In some examples, such as Figure 8 As shown, the encapsulation layer 560 further includes an organic encapsulation layer 720, which is located on the side of the inorganic encapsulation layer 710 away from the driving substrate 510. The organic encapsulation layer 720 includes a first region 7201, a second region 7202, and a third region 7203. The average thickness of the first region 7201 is less than the average thickness of the second region 7202, and the average thickness of the second region 7202 is less than the average thickness of the third region 7203. Therefore, this organic encapsulation layer can better match the subsequently formed color filters with different thicknesses.

[0300] In some examples, such as Figure 8 As shown, the display substrate 500 also includes a color filter layer 570, which is located on the side of the encapsulation layer 560 away from the driving substrate 510; the color filter layer 570 includes a first color filter 571, a second color filter 572 and a third color filter 573.

[0301] For example, the first color filter 571, the second color filter 572, and the third color filter 573 can be color filters of different colors.

[0302] For example, the first color filter 571, the second color filter 572, and the third color filter 573 may each have different thicknesses. Of course, embodiments of this disclosure include, but are not limited to, these.

[0303] In some examples, such as Figure 8 As shown, the first color filter 571 and the second color filter 572 have a first overlapping area OP1, the second color filter 572 and the third color filter 573 have a second overlapping area OP2, and the third color filter 573 and the first color filter 571 have a third overlapping area OP3. When two filters of different colors overlap, the light transmittance of the overlapping area is low, so it can be used as a black matrix. Therefore, the first overlapping area, the second overlapping area, and the third overlapping area of ​​the display substrate can all be used as a black matrix to achieve a light-shielding effect. Of course, the embodiments of this disclosure include, but are not limited to, that adjacent color filters may not overlap, and an additional black matrix may be formed between adjacent color filters.

[0304] In some examples, such as Figure 8As shown, the orthographic projections of the first overlapping region OP1, the second overlapping region OP2, and the third overlapping region OP3 on the driving substrate 510 overlap with the orthographic projections of the spacing region 522 between two adjacent anodes 525 on the driving substrate 510, thus serving as a black matrix to achieve a light-shielding effect. It should be noted that... Figure 8 The display substrate shown uses only two color filters to form an overlapping area equivalent to a black matrix. However, the display substrate provided in this embodiment can also use three color filters to form an overlapping area equivalent to a black matrix.

[0305] In some examples, such as Figure 8 As shown, the orthographic projections of the first overlapping region OP1, the second overlapping region OP2, and the third overlapping region OP3 on the driving substrate 510 overlap with the orthographic projection of the protrusion 525B on the driving substrate 510.

[0306] In some examples, such as Figure 8 As shown, the size of the first overlapping region OP1 in the second direction is larger than the size of the second overlapping region OP2 in the second direction, and the size of the second overlapping region OP2 in the second direction is larger than the size of the third overlapping region OP3 in the second direction.

[0307] In some examples, such as Figure 8 As shown, the size range of the first overlapping region OP1 in the second direction is 400-600 nanometers, the size range of the second overlapping region OP2 in the second direction is 250-350 nanometers, and the size range of the third overlapping region OP3 in the second direction is 100-200 nanometers.

[0308] In some examples, such as Figure 8 As shown, the average size of the first color filter 571 in the direction perpendicular to the driving substrate 510 is larger than the average size of the second color filter 572 in the direction perpendicular to the driving substrate 510, and smaller than the average size of the third color filter 573 in the direction perpendicular to the driving substrate 510. It should be noted that the aforementioned average size refers to the arithmetic mean of the dimensions of each part of the color filter in the direction perpendicular to the driving substrate.

[0309] In some examples, such as Figure 8 As shown, the average size of the first color filter 571 in the direction perpendicular to the driving substrate 510 ranges from 2.3 to 2.6 micrometers, the average size of the second color filter 572 in the direction perpendicular to the driving substrate 510 ranges from 1.7 to 1.95 micrometers, and the average size of the third color filter 573 in the direction perpendicular to the driving substrate 510 ranges from 2.3 to 2.7 micrometers.

[0310] In some examples, such as Figure 8 As shown, the ratio of the difference between the average size of the first color filter 571 in the direction perpendicular to the driving substrate 510 and the average size of the second color filter 572 in the direction perpendicular to the driving substrate 510, and the difference between the average size of the first color filter 571 in the direction perpendicular to the driving substrate 510 and the average size of the third color filter 573 in the direction perpendicular to the driving substrate 510, is in the range of 2-3.

[0311] Figure 9 This is a schematic diagram of a first color filter in a display substrate according to an embodiment of the present disclosure. Figure 8 and Figure 9 As shown, the first color filter 571 includes a first edge portion 571A, a second edge portion 571B, and an intermediate portion 571C located between the first edge portion 571A and the second edge portion 571B. The average size of the intermediate portion 571C in the direction perpendicular to the driving substrate 510 is smaller than the average size of the first edge portion 571A in the direction perpendicular to the driving substrate 510 and the average size of the second edge portion 571B in the direction perpendicular to the driving substrate 510.

[0312] In some examples, such as Figure 8 As shown, the first color filter 571 includes a first contact surface 571C that contacts the second color filter 572, the second color filter 572 includes a second contact surface 572C that contacts the third color filter 573, and the third color filter 573 includes a third contact surface 573C that contacts the first color filter 571. The size of the first contact surface 571C in a first direction perpendicular to the driving substrate 510 is equal to the size of the second contact surface 572C in the first direction, and smaller than the size of the third contact surface 573C in the first direction.

[0313] In some examples, such as Figure 8 As shown, the distance between the first color filter 571 and the surface of the driving substrate 510 away from the anode layer 520 is greater than the distance between the third color filter 573 and the surface of the driving substrate 510 away from the anode layer 520, and less than the distance between the second color filter 572 and the surface of the driving substrate 510 away from the anode layer 520.

[0314] In some examples, such as Figure 8 As shown, the first color filter is a red filter, the second color filter is a green filter, and the third color filter is a blue filter. Of course, the embodiments disclosed herein are not limited to this; the first, second, and third color filters may also be color filters of other colors.

[0315] In some examples, the material of the color filter layer 570 includes a desiccant, which can prevent external water and oxygen from entering the film layer below the color filter layer.

[0316] In some examples, color filter layer 570 includes aluminum.

[0317] In some examples, such as Figure 8 As shown, the display substrate 500 also includes a protective layer 580 located on the side of the color filter layer 570 away from the driving substrate 510. The protective layer 580 can protect the color filter layer 570, so that the light filtering performance of the color filter layer 570 remains stable during long-term use, thereby improving the display quality of the display substrate.

[0318] In some examples, such as Figure 8 As shown, the display substrate 500 also includes a glass cover plate 590 located on the side of the color filter layer 570 away from the driving substrate 510.

[0319] In some examples, such as Figure 8 As shown, the flat region PTQ of the first sub-inorganic encapsulation layer 711 has a first width in the second direction, the flat region PTQ of the second sub-inorganic encapsulation layer 712 has a second width in the second direction, the flat region PTQ of the third sub-inorganic encapsulation layer 713 has a third width in the second direction, and the flat region PTQ of the fourth sub-inorganic encapsulation layer 714 has a fourth width in the second direction. The first width is greater than the second width, the second width is greater than the third width, and the third width is greater than the fourth width. That is, the first width, the second width, the third width, and the fourth width gradually decrease.

[0320] Figure 10 This is a partial structural schematic diagram of another display substrate provided in an embodiment of the present disclosure. For example... Figure 8 and Figure 10 As shown, the first angle between the first line L1 connecting the flat area PTQ of the first sub-inorganic encapsulation layer 711 near the edge of the second arched area GX2, the flat area PTQ of the second sub-inorganic encapsulation layer 712 near the edge of the second arched area GX2, the flat area PTQ of the third sub-inorganic encapsulation layer 713 near the edge of the second arched area GX2, and the flat area PTQ of the fourth sub-inorganic encapsulation layer 714 near the edge of the second arched area GX2, and the surface of the driving substrate 510 away from the anode layer 520 is the first angle; the second angle between the second line L2 connecting the apex of the second arched area GX2 of the first sub-inorganic encapsulation layer 711, the apex of the first arched area GX1 of the second sub-inorganic encapsulation layer 712, the apex of the second arched area GX2 of the third sub-inorganic encapsulation layer 713, and the apex of the second arched area GX2 of the fourth sub-inorganic encapsulation layer 714, and the surface of the driving substrate 510 away from the anode layer 520, and the first angle is smaller than the second angle.

[0321] In some examples, such as Figure 8 and Figure 10 As shown, the first included angle ranges from 60 to 85 degrees, and the second included angle ranges from 85 to 89 degrees.

[0322] In some examples, such as Figure 8 and Figure 10 As shown, the intersection of the first line L1 and the second line L2 is located within the drive substrate 510.

[0323] Figure 11 This is a schematic diagram of a driving substrate provided in one embodiment of the present disclosure. Figure 11 As shown, the driving circuit 514 includes a semiconductor layer 102, a first conductive layer 301, a second conductive layer 302, a third conductive layer 303, and a fourth conductive layer 304; the semiconductor layer 102 is located within the substrate 512; the first conductive layer 301 is located on the semiconductor layer 102; the second conductive layer 302 is located on the side of the first conductive layer 301 away from the substrate 512; the third conductive layer 303 is located on the side of the second conductive layer 302 away from the substrate 512; and the fourth conductive layer 304 is located on the side of the third conductive layer 303 away from the substrate 512.

[0324] In some examples, such as Figure 11 As shown, the intersection of the first line L1 and the second line L2 is located between the upper surface of the third conductive layer 303 away from the substrate 512 and the anode layer 520.

[0325] In some examples, such as Figure 11 As shown, the distance between the intersection of the first line L1 and the second line L2 and the vertex of the protrusion structure 535 of the pixel limiting layer 530 away from the upper surface of the substrate 512 is greater than the thickness of the first sub-inorganic encapsulation layer 711 in the first direction.

[0326] In some examples, such as Figure 11 As shown, the distance between the intersection of the first line L1 and the second line L2 and the vertex of the protrusion structure 535 of the pixel limiting layer 530 away from the upper surface of the substrate 512 is less than the sum of the thickness of the first sub-inorganic encapsulation layer 711 in the first direction and the thickness of the second sub-inorganic encapsulation layer 712 in the first direction.

[0327] In some examples, such as Figure 11As shown, the angle between the third line L3 connecting the second arched region GX2 of the first sub-inorganic encapsulation layer 711 near the edge of the double arched spacer region JGQ, the second arched region GX2 of the second sub-inorganic encapsulation layer 712 near the edge of the double arched spacer region JGQ, the second arched region GX2 of the third sub-inorganic encapsulation layer 713 near the edge of the double arched spacer region JGQ, and the second arched region GX2 of the fourth sub-inorganic encapsulation layer 714 near the edge of the double arched spacer region JGQ, and the surface of the driving substrate 510 away from the anode layer 520 is the third angle, which is smaller than the second angle.

[0328] In some examples, such as Figure 11 As shown, the intersection of the first line L1 and the third line L3 is located between the upper surface of the second conductive layer 302 away from the substrate 512 and the lower surface of the third conductive layer 303 near the substrate 512.

[0329] In some examples, such as Figure 11 As shown, the intersection of the second line L2 and the third line L3 is located between the lower surface of the first conductive layer 301 near the substrate 512 and the lower surface of the substrate 512 away from the first conductive layer 301.

[0330] In some examples, such as Figure 11 As shown, the fourth line L4 connecting the edge of the third arched region GX3 of the first sub-inorganic encapsulation layer 711 away from the edge of the double arched spacer region JGQ, the edge of the third arched region GX3 of the second sub-inorganic encapsulation layer 712 away from the edge of the double arched spacer region JGQ, the edge of the third arched region GX3 of the third sub-inorganic encapsulation layer 713 away from the edge of the double arched spacer region JGQ, and the edge of the third arched region GX3 of the fourth sub-inorganic encapsulation layer 714 away from the edge of the double arched spacer region JGQ, and the surface of the driving substrate 510 away from the anode layer 520 is the fourth included angle, which is smaller than the second included angle.

[0331] In some examples, such as Figure 11 As shown, the intersection of the first line L1 and the fourth line L4 is located on the side of the substrate 512 away from the first conductive layer 301.

[0332] In some examples, such as Figure 11 As shown, the intersection of the third line L3 and the fourth line L4 is located between the upper surface of the second conductive layer 302 away from the substrate 512 and the lower surface of the third conductive layer 303 near the substrate 512.

[0333] Figure 12 This is a partial structural schematic diagram of a display substrate provided in one embodiment of the present disclosure. Figure 12 As shown, the color filter layer 570 also includes a black matrix 574, located between any two adjacent colors among the first color filter 571, the second color filter 572, and the third color filter 573.

[0334] In some examples, such as Figure 12 As shown, the orthographic projection of the black matrix 574 on the driving substrate 510 overlaps with the orthographic projection of the spacing region 522 between two adjacent anodes 525 on the driving substrate 510.

[0335] In some examples, such as Figure 12 As shown, the display substrate 500 also includes a protective layer 580 located on the side of the color filter layer 570 away from the driving substrate 510. The protective layer 580 can protect the color filter layer 570, so that the light filtering performance of the color filter layer 570 remains stable during long-term use, thereby improving the display quality of the display substrate.

[0336] In some examples, such as Figure 12 As shown, the display substrate 500 also includes a glass cover plate 590 located on the side of the color filter layer 570 away from the driving substrate 510.

[0337] An embodiment of this disclosure also provides a display device, including the display substrate described in any of the above claims. Figure 13 This is a schematic diagram of a display device provided according to an embodiment of the present disclosure. Figure 13 As shown, the display device 900 includes the aforementioned display substrate 500. Therefore, the display device has technical effects corresponding to the beneficial technical effects of the display substrate.

[0338] For example, in this display substrate, since the anode includes a main body and a protrusion, and the size of the protrusion in the direction perpendicular to the driving substrate is larger than the size of the main body in the same direction, the pixel defining layer located between the two anodes and overlapping with the edge portion of the anode can form a protrusion structure corresponding to the protrusion. When forming the light-emitting functional layer, at least some sub-functional layers (e.g., charge-generating layers) in the light-emitting functional layer can be better disconnected at the location of the protrusion structure; that is, at least some sub-functional layers in the light-emitting portions corresponding to adjacent anodes are not connected, thereby effectively avoiding leakage and crosstalk between adjacent sub-pixels. On the other hand, the height of the protrusion structure of the pixel defining layer is also higher, thus better fulfilling the pixel defining function and optically reducing and avoiding crosstalk between adjacent sub-pixels. Therefore, this display substrate can also reduce or even avoid crosstalk between adjacent sub-pixels, resulting in better display quality.

[0339] For example, since the driving substrate in the display substrate can be fabricated using semiconductor manufacturing processes, the pixel driving circuits used to drive each pixel to emit light and display can be integrated into the driving substrate. Therefore, this display device can provide a miniature display device with advantages such as high resolution, high brightness, rich colors, low driving voltage, fast response speed, and low power consumption.

[0340] For example, the display device 900 can be a wearable display device, such as a smartwatch or smart glasses. Of course, the embodiments disclosed herein include, but are not limited to, other electronic products with display functions, such as mobile phones, televisions, navigators, electronic photo albums, electronic picture frames, and computer monitors.

[0341] Figure 14 This is a plan view of a display device provided according to an embodiment of the present disclosure. Figure 14 As shown, the display device 900 includes a display area 910 and a peripheral area 920 surrounding the display area 910; the peripheral area 920 of the display device 900 includes a wiring area 930. The display area 910 can be used for luminous display, while the wiring area 930 can be used to lead out various drive lines or signal lines from the display area 910.

[0342] Figure 15 This is a schematic diagram of another display device provided according to an embodiment of the present disclosure. Figure 15 As shown, the display device 900 includes a display substrate 500 that does not include a color filter layer. In this case, the display device 900 also includes a counter substrate 800, which is disposed opposite to the display substrate 500. The counter substrate 800 includes a glass cover plate 810 and a color filter layer 570 located on the glass cover plate 810. The color filter layer 570 includes a first color filter 571, a second color filter 572, and a third color filter 573. Therefore, the display substrate and the counter substrate can be fabricated separately first, and then aligned to form the aforementioned display device. Furthermore, this display device has technical effects corresponding to the beneficial technical effects of the display substrate.

[0343] For example, in this display substrate, since the anode includes a main body and a protrusion, and the size of the protrusion in the direction perpendicular to the driving substrate is larger than the size of the main body in the same direction, the pixel defining layer located between the two anodes and overlapping with the edge portion of the anode can form a protrusion structure corresponding to the protrusion. When forming the light-emitting functional layer, at least some sub-functional layers (e.g., charge-generating layers) in the light-emitting functional layer can be better disconnected at the location of the protrusion structure; that is, at least some sub-functional layers in the light-emitting portions corresponding to adjacent anodes are not connected, thereby effectively avoiding leakage and crosstalk between adjacent sub-pixels. On the other hand, the height of the protrusion structure of the pixel defining layer is also higher, thus better fulfilling the pixel defining function and optically reducing and avoiding crosstalk between adjacent sub-pixels. Therefore, this display substrate can also reduce or even avoid crosstalk between adjacent sub-pixels, resulting in better display quality.

[0344] For example, since the driving substrate in the display substrate can be fabricated using semiconductor manufacturing processes, the pixel driving circuits used to drive each pixel to emit light and display can be integrated into the driving substrate. Therefore, this display device can provide a miniature display device with advantages such as high resolution, high brightness, rich colors, low driving voltage, fast response speed, and low power consumption.

[0345] For example, the display device 900 can be a wearable display device, such as a smartwatch or smart glasses. Of course, the embodiments disclosed herein include, but are not limited to, other electronic products with display functions, such as mobile phones, televisions, navigators, electronic photo albums, electronic picture frames, and computer monitors.

[0346] In some examples, such as Figure 15 As shown, the first color filter 571 and the second color filter 572 have a first overlapping area OP1, the second color filter 572 and the third color filter 573 have a second overlapping area OP2, and the third color filter 573 and the first color filter 571 have a third overlapping area OP3. When two filters of different colors overlap, the light transmittance of the overlapping area is low, so it can be used as a black matrix. Therefore, the first overlapping area, the second overlapping area, and the third overlapping area of ​​the display substrate can all be used as a black matrix to achieve a light-shielding effect. Of course, the embodiments of this disclosure include, but are not limited to, that adjacent color filters may not overlap, and an additional black matrix may be formed between adjacent color filters.

[0347] In some examples, such as Figure 15 As shown, the orthographic projections of the first overlapping region OP1, the second overlapping region OP2, and the third overlapping region OP3 on the driving substrate 510 overlap with the orthographic projections of the spacing region 522 between two adjacent anodes 525 on the driving substrate 510. It should be noted that... Figure 14 The display substrate shown uses only two color filters to form an overlapping area equivalent to a black matrix. However, the display substrate provided in this embodiment can also use three color filters to form an overlapping area equivalent to a black matrix.

[0348] In some examples, such as Figure 15 As shown, the size of the first overlapping region OP1 in the second direction is larger than the size of the second overlapping region OP2 in the second direction, and the size of the second overlapping region OP2 in the second direction is larger than the size of the third overlapping region OP3 in the second direction.

[0349] In some examples, such as Figure 15As shown, the size range of the first overlapping region OP1 in the second direction is 400-600 nanometers, the size range of the second overlapping region OP2 in the second direction is 250-350 nanometers, and the size range of the third overlapping region OP3 in the second direction is 100-200 nanometers.

[0350] In some examples, such as Figure 15 As shown, the average size of the first color filter 571 in the direction perpendicular to the driving substrate 510 is greater than the average size of the second color filter 572 in the direction perpendicular to the driving substrate 510, and smaller than the average size of the third color filter 573 in the direction perpendicular to the driving substrate 510.

[0351] In some examples, such as Figure 15 As shown, the average size of the first color filter 571 in the direction perpendicular to the driving substrate 510 ranges from 2.3 to 2.6 micrometers, the average size of the second color filter 572 in the direction perpendicular to the driving substrate 510 ranges from 1.7 to 1.95 micrometers, and the average size of the third color filter 573 in the direction perpendicular to the driving substrate 510 ranges from 2.3 to 2.7 micrometers.

[0352] In some examples, such as Figure 15 As shown, the ratio of the difference between the average size of the first color filter 571 in the direction perpendicular to the driving substrate 510 and the average size of the second color filter 572 in the direction perpendicular to the driving substrate 510, and the difference between the average size of the first color filter 571 in the direction perpendicular to the driving substrate 510 and the average size of the third color filter 573 in the direction perpendicular to the driving substrate 510, is in the range of 2-3.

[0353] In some examples, such as Figure 10 and Figure 15 As shown, the first color filter 571 includes a first edge portion 571A, a second edge portion 571B, and a middle portion 571M located between the first edge portion 571A and the second edge portion 571B. The average size of the middle portion 571M in the direction perpendicular to the driving substrate 510 is smaller than the average size of the first edge portion 571A in the direction perpendicular to the driving substrate 510 and the average size of the second edge portion 571B in the direction perpendicular to the driving substrate 510.

[0354] In some examples, such as Figure 15As shown, the first color filter 571 includes a first contact surface 571C that contacts the second color filter 572, the second color filter 572 includes a second contact surface 572C that contacts the third color filter 573, and the third color filter 573 includes a third contact surface 573C that contacts the first color filter 571. The size of the first contact surface in a first direction perpendicular to the driving substrate 510 is equal to the size of the second contact surface in the first direction, and smaller than the size of the third contact surface in the first direction.

[0355] In some examples, such as Figure 15 As shown, the distance between the first color filter 571 and the surface of the driving substrate 510 away from the anode layer 520 is greater than the distance between the third color filter 573 and the surface of the driving substrate 510 away from the anode layer 520, and less than the distance between the second color filter 572 and the surface of the driving substrate 510 away from the anode layer 520.

[0356] In some examples, such as Figure 15 As shown, the first color filter is a red filter, the second color filter is a green filter, and the third color filter is a blue filter. Of course, the embodiments disclosed herein are not limited to this; the first, second, and third color filters may also be color filters of other colors.

[0357] In some examples, the material of the color filter layer 570 includes a desiccant, which can prevent external water and oxygen from entering the film layer below the color filter layer.

[0358] In some examples, color filter layer 570 includes aluminum.

[0359] At least one embodiment of this disclosure also provides a display substrate. Figure 16 This is a planar schematic diagram of a display substrate provided according to an embodiment of the present disclosure. For example... Figure 16 As shown, the display device 900 includes a plurality of pixel units PU arranged in an array in the display area 910. For example, at least one of the plurality of pixel units PU may include the aforementioned driving circuit and the aforementioned anode.

[0360] For example, such as Figure 16 As shown, the display device 900 also includes a row driving circuit 200 fabricated in a substrate. The row driving circuit 200 is configured to provide a first scan signal SCAN1, a second scan signal SCAN2, and a light emission control signal EN to the driving circuits in a plurality of pixel units PU in the display device 900. For example, the row driving circuit 200 is disposed in a peripheral region 920 surrounding the display area 910.

[0361] At least one embodiment of this disclosure also provides a display substrate. Figure 17 This is a partial cross-sectional schematic diagram of a display substrate provided in one embodiment of this disclosure. Figure 17 As shown, the display substrate 500 includes a driving substrate 510, which includes a driving circuit 514. The driving circuit 514 is electrically connected to an anode 525 to emit light from the light-emitting functional layer 540, which is in contact with the anode 525. It should be noted that... Figure 17 The structures of the anode, light-emitting functional layer, and encapsulation layer in the display substrate shown can adopt the relevant designs in the display substrate provided in the above embodiments.

[0362] For example, such as Figure 17 As shown, the driving substrate 510 includes a transistor T, which includes a gate electrode G, a source electrode S, and a drain electrode D. The three electrodes correspond to three electrode connection portions. For example, the gate electrode G is electrically connected to the gate electrode connection portion 610g, the source electrode S is electrically connected to the source electrode connection portion 610s, and the drain electrode D is electrically connected to the drain electrode connection portion 610d. Alternatively, all three electrodes may be electrically connected to the corresponding electrode connection portions via tungsten vias 605.

[0363] For example, such as Figure 17 As shown, the source electrode connection portion 610s is electrically connected to the anode 525 through a tungsten via. For example, the source electrode connection portion 610s is electrically connected to the metal reflective layer 593 through a tungsten via, while the anode 525 is electrically connected to the metal reflective layer 593 through a via 624a in the inorganic insulating layer 624. When the transistor T is in the on state, the electrical signal provided by the power line can be transmitted to the anode 525 through the source electrode S, the source electrode connection portion 610s, and the metal reflective layer 593 of the transistor T. Due to the voltage difference between the anode 525 and the cathode 550, an electric field is formed between them, and holes and electrons are injected into the light-emitting functional layer 540, which emits light under the action of this electric field. It can be understood that the positions of the source electrode S and the drain electrode D in the transistor T can be interchanged (correspondingly, the positions of the source electrode connection portion 610s and the drain electrode connection portion 610d can also be interchanged).

[0364] For example, the materials of the gate electrode connection portion 610g, the source electrode connection portion 610s, and the drain electrode connection portion 610d may include metallic materials. For example, such as... Figure 17 As shown, an anti-oxidation layer 607 can be provided on at least one side (e.g., the upper side and / or the lower side) of each of the gate electrode connection portion 610g, the source electrode connection portion 610s and the drain electrode connection portion 610d, which can effectively prevent these electrode connections from being oxidized and improve their conductivity.

[0365] For example, such as Figure 17As shown, the display substrate 500 also includes a pixel defining layer 530 for defining the light-emitting functional layer 540. The pixel defining layer 530 defines the organic light-emitting functional layer 540 in its pixel opening 535 to avoid crosstalk between adjacent sub-pixels.

[0366] It should be noted that, in Figure 17 In the display substrate 500 shown, the via 624a in the inorganic insulating layer 624 can be disposed between the edge region of the anode 525 and the metal reflective layer 593. For example, in some examples, the orthographic projection of the light-emitting functional layer 540 on the driving substrate 510 and the orthographic projection of the via 624a on the driving substrate 510 are both located within the orthographic projection of the metal reflective layer 593 on the driving substrate 510. At the same time, there is no overlap between the orthographic projection of the light-emitting functional layer 540 on the driving substrate 510 and the orthographic projection of the via 624a on the driving substrate 510. Therefore, when the metal reflective layer reflects the light emitted by the light-emitting functional layer 540, the via 624a has virtually no effect on the reflection process.

[0367] Figure 18 This is an equivalent schematic diagram of a driving circuit in a display substrate provided in an embodiment of the present disclosure;

[0368] Figure 19 This is a planar schematic diagram of a driving circuit in a display substrate according to an embodiment of this disclosure. Figure 18 and Figure 19 As shown, the driving circuit 514 includes a driving transistor 140, a first transistor 110, a second transistor 120, and a third transistor 130. It should be noted that in some embodiments, the driving circuit may not include the third transistor 130, and the embodiments disclosed herein do not limit this.

[0369] For example, the driving transistor 140 includes a control electrode 143, a first electrode 141, and a second electrode 142. The driving transistor 140 is configured to control the driving current flowing through the first electrode 141 and the second electrode 142 of the driving transistor 140 for driving the light-emitting element LE to emit light, based on the voltage of the control electrode 143. The light-emitting element LE can emit light of different intensities depending on the magnitude of the driving current.

[0370] It should be noted that the source and drain of the transistors used in the embodiments of this disclosure can be structurally symmetrical, so their source and drain can be structurally indistinguishable. In the embodiments of this disclosure, to distinguish the two terminals of the transistor other than the gate, one terminal is directly described as the first terminal and the other as the second terminal. Therefore, the first and second terminals of all or some of the transistors in the embodiments of this disclosure can be interchanged as needed. For example, the first terminal of the transistor described in the embodiments of this disclosure can be the source and the second terminal can be the drain; or, the first terminal of the transistor is the drain and the second terminal is the source. The following embodiments use the example of a transistor with the first terminal as the drain and the second terminal as the source for illustration, and will not be repeated.

[0371] For example, the first transistor 110 is connected to the control electrode 143 of the driving transistor 140 and is configured to write the data signal DATA to the control electrode 143 of the driving transistor 140 in response to the first scan signal SCAN1.

[0372] For example, the second transistor 120 is connected to the control electrode 143 of the driving transistor 140 and is configured to write the data signal DATA to the control electrode 143 of the driving transistor 140 in response to the second scan signal SCAN2.

[0373] For example, the third transistor 130 is connected to the first terminal 141 of the driving transistor 140 and is configured to apply a first power supply voltage ELVDD to the first terminal 141 of the driving transistor 140 in response to the light emission control signal EN. For example, in embodiments of this disclosure, the first power supply voltage ELVDD is a high-level voltage, such as 5V.

[0374] like Figure 18 As shown, in some embodiments, the first electrode 111 (e.g., drain) of the first transistor 110 and the first electrode 121 (e.g., drain) of the second transistor 120 are connected to form a common electrode, and are connected to the control electrode 143 of the driving transistor 140 through the common electrode.

[0375] In the above embodiments, a first scan signal line SL1, a second scan signal line SL2, a data line DL, a first power supply voltage line VL1, and a light emission control line EL are also provided to provide corresponding electrical signals. The control electrode 113 of the first transistor 110 is configured to receive a first scan signal SCAN1 from the first scan signal line SL1, and the second electrode 112 (e.g., the source) of the first transistor 110 is configured to receive a data signal DATA from the data line DL. The control electrode 123 of the second transistor 120 is configured to receive a second scan signal SCAN2 from the second scan signal line SL2, and the second electrode 122 (e.g., the source) of the second transistor 120 is configured to receive a data signal DATA from the data line DL. The control electrode 133 of the third transistor 130 is configured to receive the light emission control signal EN from the light emission control line EL, the first electrode 131 (e.g., drain) of the third transistor 130 is configured to receive the first power supply voltage ELVDD from the first power supply voltage line VL1, and the second electrode 132 (e.g., source) of the third transistor 130 is connected to the first electrode 141 (e.g., drain) of the driving transistor 140.

[0376] The second terminal 142 (e.g., the source) of the driving transistor 140 is configured to be connected to the first terminal of the light-emitting element LE. For example, when the light-emitting element LE is an OLED, the second terminal 142 of the driving transistor 140 can be connected to the anode of the OLED. For example, the second terminal of the light-emitting element LE is configured to receive a fourth power supply voltage VCOM. For example, in embodiments of this disclosure, the fourth power supply voltage VCOM is a low-level voltage.

[0377] For example, in the embodiments of this disclosure, the light-emitting element LE can be an OLED. When multiple pixel units constitute a pixel array in a display panel, the second electrodes (e.g., cathodes) of multiple light-emitting elements OLED in multiple pixel units can be electrically connected together, for example, respectively connected to the same electrode or integrally formed, to receive a fourth power supply voltage VCOM. That is, the multiple light-emitting elements OLED in multiple pixel units adopt a common cathode connection method.

[0378] For example, the light-emitting element OLED can be of various types, such as top-emitting, bottom-emitting, etc., and can emit red light, green light, blue light or white light, etc. The embodiments disclosed herein do not limit this.

[0379] For example, such as Figure 18As shown, the driving circuit also includes a storage capacitor CST to store the data signal DATA written to the control terminal 143 of the driving transistor 140, thereby enabling the driving transistor 140 to control the driving current of the light-emitting element LE according to the voltage of the stored data signal DATA. The first terminal of the storage capacitor CST is connected to the control terminal 143 of the driving transistor 140, and the second terminal of the storage capacitor CST is configured to receive a third power supply voltage AVSS. For example, in the embodiments of this disclosure, the third power supply voltage AVSS is a low-level voltage. It should be noted that in the embodiments of this disclosure, the third power supply voltage AVSS can be the same as the fourth power supply voltage VCOM; for example, the third power supply voltage AVSS and the fourth power supply voltage VCOM can both be grounded. Embodiments of this disclosure include, but are not limited to, this.

[0380] like Figure 18 As shown, in some embodiments of this disclosure, the first transistor 110 may be a P-type MOS transistor, and the second transistor 120, the third transistor 130 and the driving transistor 140 may be N-type MOS transistors. For example, the first transistor 110, the second transistor 120, the third transistor 130 and the driving transistor 140 are formed in a substrate.

[0381] For example, such as Figure 18 As shown, the third stage of the first transistor 110 is configured to receive the second power supply voltage VDD. For example, the third stage of the first transistor 110 is connected to the second power supply voltage line VL2 to receive the second power supply voltage VDD.

[0382] For example, the third terminal of the second transistor 120, the third transistor 130, and the driving transistor 140 is configured to ground (GND). It should be noted that in the embodiments of this disclosure, the third terminal of a transistor is the terminal opposite to the control terminal (gate) 113 of the transistor, and the following embodiments are the same and will not be described again.

[0383] In embodiments of this disclosure, since the first transistor 110 and the second transistor 120 employ MOS transistors with opposite semiconductor types, they can constitute a transmission gate switch with complementary characteristics. In this case, for example, the first scan signal SCAN1 provided to the first transistor 110 and the second scan signal SCAN2 provided to the second transistor 120 can be inversely related signals. This ensures that one of the first transistor 110 and the second transistor 120 is always on at any given time, allowing the data signal DATA to be transmitted to the storage capacitor CST without voltage loss, thereby improving the reliability and stability of the drive circuit.

[0384] like Figure 19As shown in the embodiments of this disclosure, the direction along the first electrode 111 to the second electrode 112 of the first transistor 110 is referred to as the first direction D1, the direction along the first electrode 121 to the second electrode 122 of the second transistor 120 is referred to as the second direction D2, the direction along the first electrode 131 to the second electrode 132 of the third transistor 130 is referred to as the third direction D3, and the direction along the first electrode 141 to the second electrode 142 of the driving transistor 140 is referred to as the fourth direction D4. It should be noted that... Figures 1-15 The first direction in this embodiment is different from the first direction provided in this embodiment. Figures 1-15 The second direction in this embodiment may be the same as or different from the second direction provided in this embodiment.

[0385] For example, at least one of the first direction D1 and the second direction D2 intersects with the fourth direction D4. For example, in the case where the drive circuit includes a third transistor 130, at least one of the first direction D1, the second direction D2, and the third direction D3 intersects with the fourth direction D4. For example, the fourth direction D4 is... Figure 19 The horizontal direction from left to right in the middle.

[0386] In the driving circuit, since the size of the driving transistor 140 is generally larger than that of other switching transistors (e.g., the first transistor 110, the second transistor 120, and the third transistor 130), when arranging the position of the transistor, the driving transistor 140 can be arranged along the fourth direction D4, while at least one of the first direction D1, the second direction D2, and the third direction D3 intersects with the fourth direction D4. This makes the layout of the four transistors more compact, thereby reducing the layout area occupied by the display substrate 500, and making it easier for the display substrate 500 to achieve a high PPI.

[0387] In some embodiments of this disclosure, the first direction D1 and the second direction D2 can both intersect the fourth direction D4; or, for example, the first direction D1, the second direction D2, and the third direction D3 can all intersect the fourth direction D4. For example, as... Figure 19 As shown, the fourth direction D4 is the lateral direction, while the first direction D1, the second direction D2, and the third direction D3 are all lateral directions. Figure 3 The longitudinal direction that is perpendicular to the horizontal direction.

[0388] For example, in some embodiments of this disclosure, the first direction D1 and the second direction D2 are both perpendicular to the fourth direction D4; or, for example, the first direction D1, the second direction D2, and the third direction D3 are all perpendicular to the fourth direction D4. When multiple pixel units in the display area of ​​a display device are arranged in a multi-row, multi-column manner, this arrangement makes the layout of the display substrate 500 more compact, thereby further reducing the layout area occupied by the display substrate 500, and thus making it easier for the display substrate 500 to achieve a high PPI.

[0389] For example, such as Figure 19 As shown, the first transistor 110 includes a first active region 114 extending along a first direction D1. The first active region 114 includes a first electrode 111 of the first transistor 110, a second electrode 112 of the first transistor 110, and a channel region formed between the first electrode 111 and the second electrode 112 of the first transistor 110.

[0390] The second transistor 120 includes a second active region 124 extending along the second direction D2. The second active region 124 includes a first electrode 121 of the second transistor 120, a second electrode 122 of the second transistor 120, and a channel region formed between the first electrode 121 and the second electrode 122 of the second transistor 120.

[0391] The third transistor 130 includes a third active region 134 extending along the third direction D3. The third active region 134 includes a first electrode 131 of the third transistor 130, a second electrode 132 of the third transistor 130, and a channel region formed between the first electrode 131 and the second electrode 132 of the third transistor 130.

[0392] The driving transistor 140 includes a fourth active region 144 extending along a fourth direction D4. The fourth active region 144 includes a first electrode 141 of the fourth transistor 140, a second electrode 142 of the fourth transistor 140, and a channel region formed between the first electrode 141 and the second electrode 142 of the fourth transistor 140.

[0393] For example, the substrate in the display substrate 500 provided in the embodiments of this disclosure is a silicon-based substrate. The first active region 114, the second active region 124, the third active region 134 and the fourth active region 144 are all doped regions in the silicon-based substrate. These doped regions are obtained, for example, by ion implantation or ion diffusion. For amorphous silicon, P-type doping can be achieved by doping boron (B), and N-type doping can be achieved by doping phosphorus (P) or arsenic (As). The embodiments of this disclosure do not limit this.

[0394] For example, in some embodiments of this disclosure, the doping types of the first active region 114 and the second active region 124 are opposite. For example, the first active region 114 is doped with P-type, and the second active region 124 is doped with N-type.

[0395] like Figure 19 As shown, the two ends of the first active region 114 and the two ends of the second active region 124 are aligned with each other in the fourth direction D4, and for example, the two ends of the first active region 114 and the second active region 124 are arranged adjacent to each other. This arrangement simplifies the layout design of the display substrate 500.

[0396] The line connecting one edge of the first active region 114 along the first direction D1 and one edge of the second active region 124 along the second direction D2 is parallel to the fourth direction D4; the line connecting the other edge of the first active region 114 along the first direction D1 and the other edge of the second active region 124 along the second direction D2 is parallel to the fourth direction D4. This method simplifies the layout design of the display substrate 500.

[0397] Compared to silicon-based analog CMOS circuits used for non-display applications, the driving current for the light-emitting element (LE) in the display substrate 500 provided in the embodiments of this disclosure is one to two orders of magnitude smaller. The current characteristics of the driving transistor 140 in saturation state are as follows:

[0398]

[0399] Among them, I D The drive current provided for driving transistor 140, W / L is the width-to-length ratio of driving transistor 140, K is a constant value, and V GS4 To drive the voltage difference between the gate and source of transistor 140, V th The threshold voltage for driving transistor 140.

[0400] As can be seen from the formula above, in order to achieve a lower driving current, the L value of the driving transistor 140 must be increased during the size design, which is not conducive to reducing the layout area of ​​the display substrate 500 that uses the driving transistor 140.

[0401] The driving circuit 514 provided in some embodiments of this disclosure can improve or avoid the above-mentioned problems by adjusting the relative relationship between the doping concentrations of the first active region 114, the second active region 124, the third active region 134 and the fourth active region 144.

[0402] For example, the doping concentration of the fourth active region 144 is less than the doping concentration of the third active region 134. For example, the doping concentration of the third active region 134 is approximately 10. 17 cm -3The doping concentration of the fourth active region 144 is approximately 10. 13 cm -3 The doping concentration of the fourth active region 144 is four orders of magnitude smaller than that of the third active region 134. By reducing the doping concentration of the fourth active region 144, embodiments of this disclosure, without changing the size of the driving transistor 140 (e.g., the width-to-length ratio W / L remains constant), can enable the driving transistor 140 to output a smaller driving current, and the change in the output driving current is more gradual. This results in better uniformity of grayscale values ​​when the driving circuit using this driving transistor 140 drives a light-emitting element (LE) (e.g., an OLED) to emit light.

[0403] For example, in some embodiments of the present disclosure, the doping concentration of at least one of the first active region 114 and the second active region 124 is greater than the doping concentration of the third active region 134.

[0404] For example, the doping concentrations of the first active region 114 and the second active region 124 are both greater than the doping concentration of the third active region. For example, the doping concentrations of the first active region 114 and the second active region 124 are approximately 10. 20 cm -3 In this case, the doping concentration of the first active region 114 and the second active region 124 is three orders of magnitude greater than the doping concentration of the third active region 134.

[0405] like Figure 18 As shown, the first transistor 110 and the second transistor 120 are used as switching transistors in the driving circuit, so they need to have good switching characteristics. When the doping concentration of the first active region 114 and / or the second active region 124 is large, a larger driving current can be obtained and the driving current changes more rapidly, thereby giving the first transistor 110 and / or the second transistor 120 better switching characteristics.

[0406] For example, in embodiments of this disclosure, the first transistor 110 is a first semiconductor type MOS transistor, and the second transistor, the third transistor, and the driving transistor are all second semiconductor type MOS transistors, with the first semiconductor type and the second semiconductor type being opposite. For example, the first semiconductor type is P-type, and the second semiconductor type is N-type; embodiments of this disclosure include, but are not limited to, these.

[0407] like Figure 19 As shown, the display substrate 500 provided in some embodiments of this disclosure further includes a first scan signal line SL1 for transmitting a first scan signal SCAN1 and a second scan signal line SL2 for transmitting a second scan signal SCAN2, wherein the first scan signal line SL1 and the second scan signal line SL2 are arranged in parallel.

[0408] For example, the first scan signal line SL1 is connected to the control electrode 113 of the first transistor 110 to provide the first scan signal SCAN1, and the second scan signal line SL2 is connected to the control electrode 123 of the second transistor 120 to provide the second scan signal SCAN2.

[0409] For example, the extension directions of both the first scan signal line SL1 and the second scan signal line SL2 are parallel to the fourth direction D4. The orthographic projection of the first scan signal line SL1 onto the substrate is parallel to the orthographic projection of the second scan signal line SL2 onto the substrate, for example, both are parallel to the fourth direction D4.

[0410] For example, the area where the driving circuit 514 is projected onto the substrate 512 is the pixel area, and the first scan signal line SL1 and the second scan signal line SL2 are located side by side on one side of the pixel area.

[0411] like Figure 19 As shown, some embodiments of this disclosure provide a display substrate 500 that further includes a data line DL for transmitting a data signal DATA, wherein the orthographic projection of the second scan signal line SL2 onto the substrate at least partially overlaps with the orthographic projection of the data line DL onto the substrate. For example, the second scan signal line SL2 overlaps with the data line DL in a direction perpendicular to the substrate. For example, as... Figure 19 As shown, it can be used to... Figure 19 If the plane containing the substrate is considered the same as the plane containing the substrate, then perpendicular to the substrate is perpendicular to the plane containing the substrate. Figure 19 The plane in which it is located. By making the second scan signal line SL2 overlap with the data line DT in a direction perpendicular to the substrate, the data line DL can be made to not occupy additional layout area, thereby further reducing the layout area occupied by the display substrate 500 and making it more conducive to achieving high PPI.

[0412] like Figure 19 As shown, the display substrate 500 provided in some embodiments of this disclosure further includes a first power supply voltage line VL1 for transmitting a first power supply voltage ELVDD and a light emission control line EL for transmitting a light emission control signal EN.

[0413] For example, the extension directions of the first power supply voltage line VL1 and the light emission control line EL are parallel to the fourth direction D4, and the first scan signal line SL1, the second scan signal line SL2, the first power supply voltage line VL1 and the light emission control line EL are arranged sequentially along the direction perpendicular to the fourth direction D4 when projected onto the substrate.

[0414] It should be noted that, in some embodiments of the display substrate 500 provided in this disclosure, such as Figure 19As shown, the orthographic projection of the first power supply voltage line VL1 onto the substrate is positioned between the orthographic projection of the second scan signal line SL2 onto the substrate and the orthographic projection of the light emission control line EL onto the substrate. Since the first power supply voltage ELVDD transmitted by the first power supply voltage line VL1 is a DC signal, and the second scan signal SCAN2 transmitted by the second scan signal line SL2 and the light emission control signal EN transmitted by the light emission control line EL are both transition signals, the above arrangement can effectively shield the mutual interference between the second scan signal SCAN2 and the light emission control signal EN.

[0415] like Figure 19 As shown, some embodiments of this disclosure provide a display substrate 500 that further includes a second power supply voltage line VL2 for transmitting a second power supply voltage VDD. The third terminal of the first transistor 110 is electrically connected to the second power supply voltage line VL2 to receive the second power supply voltage VDD. For example, in embodiments of this disclosure, the second power supply voltage VDD is a high-level voltage, such as 5V.

[0416] For example, the first transistor 110 is a P-type MOS transistor, and its channel region is P-type doped. Figure 19 As shown, the third terminal opposite to the control electrode (gate) 113 of the first transistor 110 receives the second power supply voltage VDD. For example, the second transistor 120, the third transistor 130, and the driving transistor 140 are all N-type MOS transistors with N-type doped channel regions, and the third terminals of the second transistor 120, the third transistor 130, and the driving transistor 140 are all configured to be grounded (GND).

[0417] For example, the orthographic projection of the second power supply voltage line VL2 onto the substrate is located between the orthographic projection of the first power supply voltage line VL1 onto the substrate and the orthographic projection of the light emission control line EL onto the substrate, and part of the extension direction of the second power supply voltage line VL2 is parallel to the fourth direction D4.

[0418] like Figure 19 As shown, the second power supply voltage line VL2 has a bend when extending along the fourth direction D4; additionally, the light-emitting control line EL also has a bend when extending along the fourth direction D4, and the bend directions of the second power supply voltage line VL2 and the light-emitting control line EL are different. This routing method, for example, can provide layout space for the first adapter electrode AE1 described below.

[0419] For example, such as Figure 19 As shown, the first transistor 110 and the second transistor 120 are both disposed between the second scan signal line SL2 and the light emission control line EL. The first transistor 110 intersects with the first power supply voltage line VL1 and the second power supply voltage line VL2, and the second transistor 120 intersects with the first power supply voltage line VL1 and the second power supply voltage line VL2.

[0420] For example, the orthographic projection of the first active region 114 of the first transistor 110 onto the substrate and the orthographic projection of the second active region 124 of the second transistor 120 onto the substrate are both located between the orthographic projection of the second scan signal line SL2 onto the substrate and the orthographic projection of the light emission control line EL onto the substrate.

[0421] The orthographic projection of the first active region 114 of the first transistor 110 onto the substrate intersects with the orthographic projection of the first power supply voltage line VL1 onto the substrate, and the orthographic projection of the first active region 114 of the first transistor 110 onto the substrate intersects with the orthographic projection of the second power supply voltage line VL2 onto the substrate.

[0422] The orthographic projection of the second active region 124 of the second transistor 120 onto the substrate intersects with the orthographic projection of the first power supply voltage line VL1 onto the substrate, and the orthographic projection of the second active region 124 of the second transistor 120 onto the substrate intersects with the orthographic projection of the second power supply voltage line VL2 onto the substrate.

[0423] like Figure 19 As shown, some embodiments of the present disclosure provide a display substrate 500 that further includes a first transfer electrode AE1 disposed on a first side of the light emission control line EL, and a second transfer electrode AE2 extending from the first side of the light emission control line EL to a second side of the light emission control line EL.

[0424] For example, the orthographic projection of the second transfer electrode AE2 onto the substrate intersects with the orthographic projection of the light-emitting control line EL onto the substrate. The two ends of the first transfer electrode AE1 are electrically connected to the first electrode 111 of the first transistor 110 and the first electrode 121 of the second transistor 120, respectively. The first transfer electrode AE1 and the second transfer electrode AE2 are electrically connected, and the second transfer electrode AE2 is electrically connected to the control electrode 143 of the driving transistor 140.

[0425] For example, the extension direction of the second transfer electrode AE2 is perpendicular to the extension direction of the first transfer electrode AE1, and is also perpendicular to the fourth direction D4.

[0426] Since the second transition electrode AE2 is connected to the storage capacitor CST, the voltage level on the second transition electrode AE2 may fluctuate significantly during operation of the driving circuit. This fluctuation may cause crosstalk to the first power supply voltage line VL1, generating noise. In the display substrate 500 provided in the embodiments of this disclosure, the first power supply voltage line VL1 and the second transition electrode AE2 are separated by the second power supply voltage line VL2, thereby reducing the crosstalk caused by the voltage level fluctuation on the second transition electrode AE2 to the first power supply voltage line VL1 and isolating noise.

[0427] In addition, some embodiments of this disclosure provide a display substrate 500 that extends the first active region 114 of the first transistor 110 and the second active region 124 of the second transistor 120 to provide a wiring channel for the second power supply voltage line VL2.

[0428] For example, the layout dimensions of the driving circuit (rectangular shape) provided in the embodiments of this disclosure are approximately 4.5µm × 2.9µm.

[0429] Figures 20A-20E They are shown respectively Figure 19 The plan view of the layer layout of the display substrate 500 shown.

[0430] Figure 20A The diagram shows a first active region 114 of a first transistor 110, a second active region 124 of a second transistor 120, a third active region 134 of a third transistor 130, and a fourth active region 144 of a driving transistor 140, which can... Figure 4A The layer shown is called the Active Display (AA) layer.

[0431] Figure 20B The control electrode 113 of the first transistor 110, the control electrode 123 of the second transistor 120, the control electrode 133 of the third transistor 130, and the control electrode 143 of the drive transistor 140 are shown. The layer shown in 4B can be referred to as the first conductive layer, which will be further described below. For example, the material of the first conductive layer can be polycrystalline silicon.

[0432] Figure 20C The diagram shows the first power supply voltage line VL1, the second power supply voltage line VL2, the light control line EL, the data line DL, the ground line GND, and the first adapter electrode AE1. It can be used to... Figure 20C The layer shown is called the first metal layer (metal1).

[0433] Figure 20D The diagram shows the second transfer electrode AE2, the electrode connecting the first scan signal line SL1 to the first transistor 110, and the electrode connecting the second scan signal line SL2 to the second transistor 120. This allows for... Figure 20D The layer shown is called the second metal layer (metal2).

[0434] Figure 20E The first scan signal line SL1 and the second scan signal line SL2 are shown, which can... Figure 20E The layer shown is called the third metal layer (metal3).

[0435] It should be noted that, in the embodiments of this disclosure, for the sake of clarity, Figure 19 The storage capacitor CST is not shown in the diagram. Below, we will refer to... Figures 21-23Eright Figure 18 The storage capacitor CST shown in the figure will be further described.

[0436] like Figure 21 As shown, Figure 21 The area 850 shown is the area where the storage capacitor CST is set. It should be noted that, for clarity, Figure 21 The table does not show the corresponding markers for all structures; the omitted parts can be found in the reference table. Figure 19 The corresponding marker in.

[0437] Figure 22 This is a layout diagram of the storage capacitor CST. Figures 23A-23D For the corresponding Figure 22 Floor plans showing the layout of each level. Figure 23E This is a schematic diagram of the cross-section of the storage capacitor CST.

[0438] Figure 22 The diagram shows a four-layer structure: a third metal layer (metal3), a fourth metal layer (metal4), an auxiliary metal layer (metal4'), and a fifth metal layer (metal5). It also shows a first via (V1) and a second via (V2), which will be described in detail below with reference to the cross-sectional diagram. Further details will not be provided here.

[0439] For example, Figure 23A A third metal layer, metal3, is shown, for example, this third metal layer and Figure 20E The layers shown are the same layer. For example... Figure 23A As shown, the third metal layer metal3 comprises two parts: an electrode 811 that serves as the first terminal of the first capacitor C1 and an electrode 812 that serves as the second terminal of the first capacitor C1. For example, electrode 811 is configured to receive a third power supply voltage AVSS; electrode 812 is electrically connected to electrode 840 in the fifth metal layer metal5 through a second via V2, thereby achieving electrical connection with the control terminal 143 of the driving transistor 140.

[0440] Electrode 811 includes multiple strip electrodes, and electrode 812 includes multiple strip electrodes. The multiple strip electrodes of electrode 811 and electrode 812 are arranged alternately, and electrodes 811 and 812, as well as the intervals between them, form a first capacitor C1. For example, the first capacitor C1 is part of a storage capacitor CST. For example, the first capacitor C1 and the second capacitor C2 (described below) are connected in parallel to form the storage capacitor CST.

[0441] For example, Figure 23B An electrode 820 located in the fourth metal layer metal4 is shown. For example, electrode 820 is a planar electrode that acts as the first electrode of the second capacitor C2.

[0442] For example, Figure 23C An electrode 830 located in the auxiliary metal layer metal4' is shown. For example, electrode 830 is a planar electrode that acts as the second electrode of the second capacitor C2.

[0443] For example, Figure 23D The electrode 840 located in the fifth metal layer metal5 is shown, as well as the first via V1 and the second via V2.

[0444] Figure 23E A cross-sectional schematic diagram of a portion of the aforementioned storage capacitor CST structure is shown, as follows: Figure 23E As shown, electrode 840 located in the fifth metal layer (metal5) is electrically connected to electrode 830 located in the auxiliary metal layer (metal4') through a first via V1; additionally, electrode 840 located in the fifth metal layer (metal5) is electrically connected to electrode 812 located in the third metal layer (metal3) through a second via V2. It should be noted that the second via V2 penetrates the fourth metal layer (metal4). Figure 23E Not shown in the image.

[0445] like Figure 23E As shown, the electrode 820 located in the fourth metal layer metal4 and the electrode 830 located in the auxiliary metal layer metal4', and the space between them form the second capacitor C2; for example, the first capacitor C1 mentioned above and the second capacitor C2 are connected in parallel to form the storage capacitor CST.

[0446] In embodiments of this disclosure, such as Figure 23E As shown, an auxiliary metal layer metal4' is provided between the fourth metal layer metal4 and the fifth metal layer metal5, so that the spacing between the fourth metal layer metal4 and the auxiliary metal layer metal4' is, for example, about 1 / 10 of the spacing between the fourth metal layer metal4 and the fifth metal layer metal5, thereby effectively increasing the capacitance value per unit area of ​​the second capacitor C2.

[0447] like Figure 18 and Figure 19 As shown, embodiments of this disclosure also provide a display substrate 500, including a substrate and at least one driving circuit formed on the substrate. The driving circuit includes a driving transistor 140, a first transistor 110, a second transistor 120, and a third crystal 130.

[0448] The driving transistor 140 includes a control electrode 143, a first electrode 141, and a second electrode 142, and is configured to control the driving current flowing through the first electrode 141 and the second electrode 142 of the driving transistor 140 for driving the light-emitting element LE to emit light, based on the voltage of the control electrode 143 of the driving transistor 140.

[0449] The first transistor 110 is connected to the control terminal 143 of the driving transistor 140 and is configured to write the data signal DATA to the control terminal 143 of the driving transistor 140 in response to the first scan signal SCAN1. The second transistor 120 is connected to the control terminal 143 of the driving transistor 140 and is configured to write the data signal DATA to the control terminal 143 of the driving transistor 140 in response to the second scan signal SCAN2. The third transistor 130 is connected to the first terminal 141 of the driving transistor 140 and is configured to apply the first power supply voltage ELVDD to the first terminal 141 of the driving transistor 140 in response to the light emission control signal EN.

[0450] The display substrate 500 also includes a first scan signal line SL1 for transmitting a first scan signal SCAN1 and a second scan signal line SL2 for transmitting a second scan signal SCAN2, a first power supply voltage line VL1 for transmitting a first power supply voltage ELVDD and a light emission control line EL for transmitting a light emission control signal EN; the first scan signal line SL1, the second scan signal line SL2, the first power supply voltage line VL1 and the light emission control line EL are arranged sequentially along the direction perpendicular to the fourth direction D4 when projected onto the substrate.

[0451] For example, the direction along the first electrode 111 to the second electrode 112 of the first transistor 110 is the first direction D1; the direction along the first electrode 121 to the second electrode 122 of the second transistor 120 is the second direction D2; the direction along the first electrode 131 to the second electrode 132 of the third transistor 130 is the third direction D3; and the direction along the first electrode 141 to the second electrode 142 of the driving transistor 140 is the fourth direction D4. The first direction D1, the second direction D2, and the third direction D3 all intersect with the fourth direction D4. For example, the first direction D1, the second direction D2, and the third direction D3 are all perpendicular to the fourth direction D4.

[0452] The display substrate provided in at least one embodiment of this disclosure, through optimized layout and wiring design, can achieve a subpixel area of ​​5.45um × 13.6um, thereby achieving high resolution (PPI) and optimized arrangement of pixel circuit array, and has a better display effect.

[0453] Figure 24AThis is a block diagram of a display substrate provided in at least one embodiment of this disclosure. For example... Figure 24A As shown, the display substrate 10 includes a plurality of sub-pixels 100 arranged in an array, a plurality of scan lines 11, and a plurality of data lines 12. Each sub-pixel 100 includes a light-emitting element and a pixel circuit for driving the light-emitting element. The plurality of scan lines 11 and the plurality of data lines 12 intersect each other in the display area to define a plurality of pixel regions arranged in an array, and a pixel circuit of a sub-pixel 100 is disposed in each pixel region. The pixel circuit is, for example, a conventional pixel circuit, such as a 2T1C (i.e., two transistors and one capacitor) pixel circuit, a 4T2C, a 5T1C, a 7T1C, etc. nTmC (n, m are positive integers) pixel circuit, and in different embodiments, the pixel circuit may further include a compensation sub-circuit, which may include an internal compensation sub-circuit or an external compensation sub-circuit, and the compensation sub-circuit may include transistors, capacitors, etc. For example, as needed, the pixel circuit may further include a reset circuit, a light-emitting control sub-circuit, a detection circuit, etc. For example, the display substrate may also include a gate driving sub-circuit 13 and a data driving sub-circuit 14 located in the non-display area. The gate driving sub-circuit 13 is connected to the pixel circuit via scan line 11 to provide various scan signals, and the data driving sub-circuit 14 is connected to the pixel circuit via data line 12 to provide data signals. Figure 24A The positional relationship of the gate drive sub-circuit 13 and data drive sub-circuit 14, scan line 11 and data line 12 in the display substrate shown is only an example. The actual arrangement can be designed as needed.

[0454] For example, the display substrate 10 may also include control circuitry (not shown). This control circuitry may be configured to control the data driving sub-circuit 14 to apply the data signal and to control the gate driving sub-circuit to apply the scan signal. An example of this control circuitry is a timing control circuit (T-con). The control circuitry can take various forms, such as including a processor and a memory, the memory containing executable code, which the processor runs to perform the detection method described above.

[0455] For example, the processor can be a central processing unit (CPU) or other forms of processing device with data processing and / or instruction execution capabilities, such as a microprocessor, a programmable logic controller (PLC), etc.

[0456] For example, a storage device may include one or more computer program products, which may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. Volatile memory may include, for example, random access memory (RAM) and / or cache memory. Non-volatile memory may include, for example, read-only memory (ROM), hard disk, flash memory, etc. One or more computer program instructions may be stored on the computer-readable storage medium, and a processor may execute the functions expected by the program instructions. Various application programs and various data may also be stored in the computer-readable storage medium.

[0457] The pixel circuit may include, as needed, a driving sub-circuit, a data writing sub-circuit, a compensation sub-circuit, and a storage sub-circuit. It may also include, as needed, a light emission control sub-circuit, a reset circuit, etc.

[0458] Figure 24B A schematic diagram of a pixel circuit is shown. (For example...) Figure 24B As shown, the pixel circuit includes a data writing sub-circuit 111, a driving sub-circuit 112, and a storage sub-circuit 113.

[0459] The data writing sub-circuit 111 is electrically connected to the first terminal of the storage sub-circuit 113 and is configured to transmit the data signal Vd to the first terminal of the storage sub-circuit 113 in response to a control signal (first control signal SEL). The second terminal of the storage sub-circuit 113 is configured, for example, to receive a second power supply voltage VSS.

[0460] The driving sub-circuit 112 includes a control electrode 150, a first electrode 151, and a second electrode 152. The control electrode 150 of the driving sub-circuit is electrically connected to a first terminal of the storage sub-circuit. The first electrode 151 of the driving sub-circuit 112 is configured to receive a first power supply voltage VDD. The second electrode 152 of the driving sub-circuit 112 is electrically connected to a first node S and connected to the first electrode 121 of the light-emitting element 120. The driving sub-circuit 112 is configured to drive the light-emitting element 120 to emit light in response to the voltage at the first terminal of the storage sub-circuit. The second electrode 122 of the light-emitting element 120 is configured, for example, to receive a first common voltage Vcom1.

[0461] In at least some embodiments of this disclosure, such as Figure 24BAs shown, the pixel circuit also includes a bias sub-circuit 114. The bias sub-circuit 114 includes a control terminal, a first terminal, and a second terminal. The control terminal of the bias sub-circuit 114 is configured to receive a bias signal; the first terminal of the bias sub-circuit 114 is configured, for example, to receive a second power supply voltage VSS; and the second terminal of the bias sub-circuit 114 is electrically connected to the first node S. For example, the bias signal is a second common voltage Vcom2. For example, the bias signal Vcom2 is a constant voltage signal, such as 0.8V-1V. Under the action of the bias signal, the bias sub-circuit 114 is normally open and configured to provide a constant current, thereby making the voltage applied to the light-emitting element 120 linearly related to the data signal, which helps to achieve fine control of grayscale and thus improve the display effect. This will be further explained later with reference to a specific circuit.

[0462] For example, when the data signal (voltage) Vd changes from high to low, the grayscale voltage written to the first electrode 121 of the light-emitting element 120 needs to change rapidly. The bias sub-circuit 114 can also allow the first electrode 121 of the light-emitting element 120 to release charge quickly, thereby achieving better dynamic contrast.

[0463] The transistors used in the embodiments of this disclosure can all be thin-film transistors, field-effect transistors, or other switching devices with the same characteristics. The embodiments of this disclosure use metal-oxide-semiconductor field-effect transistors as an example for illustration. The source and drain of the transistors used here can be structurally symmetrical, so their structures can be indistinguishable. In the embodiments of this disclosure, to distinguish the two terminals of the transistor other than the gate, one terminal is directly described as the first terminal and the other as the second terminal. Furthermore, transistors can be classified into N-type and P-type transistors according to their characteristics. When the transistor is a P-type transistor, the turn-on voltage is a low-level voltage (e.g., 0V, -5V, -10V, or other suitable voltage), and the turn-off voltage is a high-level voltage (e.g., 5V, 10V, or other suitable voltage); when the transistor is an N-type transistor, the turn-on voltage is a high-level voltage (e.g., 5V, 10V, or other suitable voltage), and the turn-off voltage is a low-level voltage (e.g., 0V, -5V, -10V, or other suitable voltage).

[0464] The display substrate provided in this disclosure can be a rigid substrate, such as a glass substrate or a silicon substrate, or it can be formed from a flexible material with excellent heat resistance and durability, such as polyimide (PI), polycarbonate (PC), polyethylene terephthalate (PET), polyethylene, polyacrylate, polyaryl compounds, polyetherimide, polyethersulfone, polyethylene glycol terephthalate (PET), polyethylene (PE), polypropylene (PP), polysulfone (PSF), polymethyl methacrylate (PMMA), cellulose triacetate (TAC), cyclic olefin polymers (COP), and cyclic olefin copolymers (COC). The embodiments in this disclosure are all described using a silicon substrate as an example, that is, the pixel structure is fabricated on a silicon substrate; however, this disclosure does not limit the scope of the embodiments.

[0465] For example, the pixel circuit includes a complementary metal-oxide-semiconductor (CMOS) circuit, meaning the pixel circuit is fabricated on a single-crystal silicon substrate. Thanks to mature CMOS integrated circuit technology, silicon-based processes can achieve high precision (e.g., PPI can reach 6500 or even over 10,000).

[0466] For example, if the first electrode 121 and the second electrode 122 of the light-emitting element 120 in the sub-pixel are short-circuited due to process fluctuations in the display substrate, the voltage of the first electrode 121 of the light-emitting element 120 may be too high (e.g., the first common voltage Vcom1 is at a high potential) or too low (e.g., the first common voltage Vcom1 is at a low potential), thereby triggering a latch-up effect at the first node S, causing the CMOS circuit to fail, resulting in defects such as dark lines on the display substrate.

[0467] In some examples, for instance, the data writing sub-circuit includes a first data writing transistor P1, and the driving sub-circuit includes a driving transistor N2; for example, the first data writing transistor is a P-type metal-oxide-semiconductor field-effect transistor (PMOS), and the driving transistor N2 is an N-type metal-oxide-semiconductor field-effect transistor (NMOS). The gate, first electrode, and second electrode of the driving transistor N2 serve as the control electrode 150, the first electrode 151, and the second electrode 152 of the driving sub-circuit 112, respectively. In this case, for example, when the first common voltage Vcom1 supplied to the second electrode 122 of the light-emitting element 120 is low, and a short circuit occurs between the first electrode 121 and the second electrode 122 of the light-emitting element 120, the potential of the second electrode of the driving transistor directly connected to the first electrode 121 will be too low.

[0468] Figure 24CThe diagram illustrates the latch-up effect formed by the pixel circuit. The N-type active region (e.g., the second electrode) of the driving transistor N2, the P-type silicon substrate, the N-type well region where the first data writing transistor P1 is located, and the P-type active region (e.g., the first electrode) of the first data writing transistor P1 form two parasitic transistors Q1 and Q2 that are interconnected, constituting an NPNP structure. When the potential of the second terminal (i.e., at the first node S) of the driving transistor N2 is too low, the PN junction (emitter junction) between the second terminal (N-type heavily doped region) of the driving transistor N2 and the P-type substrate becomes forward biased. Q1 turns on, providing a sufficiently large current to turn on the parasitic transistor Q2, which in turn feeds current back to the parasitic transistor Q1, forming a vicious cycle. In the end, most of the current flows directly from VDD through the parasitic transistor to VSS, without being controlled by the transistor gate voltage, causing the CMOS pixel circuit to fail. Furthermore, this latch-up effect causes the parasitic transistor Q2 to continuously draw current from the emitter, i.e., from the data line, thereby causing a row of sub-pixels connected to the data line to fail, resulting in defects such as dark lines on the display substrate, which greatly affects the display effect.

[0469] In at least some embodiments of this disclosure, at least one sub-pixel further includes a resistor connected between the second electrode 152 of the driving sub-circuit 112 and the first electrode 121 of the light-emitting element 120. The resistor can increase or decrease the S potential of the first node, thereby alleviating or avoiding latch-up effects, improving circuit reliability, and enhancing display performance.

[0470] Figure 25A This is a schematic diagram of a pixel circuit provided in at least one embodiment of the present disclosure. Figure 25A As shown, the pixel circuit also includes a resistor 130. The first end 131 of the resistor 130 is electrically connected to the second electrode 152 of the driving sub-circuit 112, and the second end 132 is electrically connected to the first electrode 121 of the light-emitting element 120. That is, the second electrode 152 of the driving sub-circuit 112 is electrically connected to the first electrode 121 of the light-emitting element 120 through the resistor 130.

[0471] For example, the resistor 130 can be a constant resistor or a variable resistor, or it can be an equivalent resistor formed by other devices (such as transistors).

[0472] For example, the resistor 130 is insulated from the control electrode 150 of the drive sub-circuit 112 in the same layer, and the resistivity of the resistor is higher than that of the control electrode of the drive sub-circuit. For example, the resistivity of the resistor is more than ten times that of the control electrode.

[0473] It should be noted that, in this disclosure, "co-layered configuration" refers to a structure formed by two (or more) structures through the same deposition process and patterned through the same patterning process, and their materials may be the same or different. For example, the precursors forming multiple co-layered configurations may be made of the same material, while the final materials may be the same or different. "Integral structure" in this disclosure refers to a structure formed by two (or more) structures through the same deposition process and patterned through the same patterning process, and their materials may be the same or different.

[0474] This setup allows the control electrodes and resistors of the drive sub-circuit to be formed in the same patterning process, thus saving process time.

[0475] For example, both the resistor and the control electrode of the driving sub-circuit are made of polycrystalline silicon, and the doping concentration of the resistor is lower than that of the control electrode, thus the resistor has a higher resistivity than the control electrode. For example, the resistor can be intrinsic polycrystalline silicon or lightly doped polycrystalline silicon, and the control electrode can be heavily doped polycrystalline silicon.

[0476] In other examples, the materials of the control electrode and the resistor can be different. For example, the materials of the control electrode and the resistor can each include a metal and a corresponding metal oxide. For example, the metal can include gold (Au), silver (Ag), copper (Cu), aluminum (Al), molybdenum (Mo), magnesium (Mg), tungsten (W), and alloys of the above metals.

[0477] In at least one embodiment of this disclosure, the data writing sub-circuit 111 may include a transmission gate circuit consisting of two complementary transistors connected in parallel; the control signals include two inverted control signals. The transmission gate structure employed in the data writing sub-circuit 111 can facilitate lossless transmission of data signals to the first terminal of the storage sub-circuit 113.

[0478] For example, the data writing sub-circuit includes a first control electrode, a second control electrode, a first terminal, and a second terminal. The first and second control electrodes of the data writing sub-circuit are respectively configured to receive a first control signal and a second control signal. The first terminal of the data writing sub-circuit is configured to receive a data signal. The second terminal of the data writing sub-circuit is electrically connected to the first terminal of the storage sub-circuit and is configured to transmit the data signal to the first terminal of the storage sub-circuit in response to the first control signal and the second control signal.

[0479] It should be noted that in the description of the embodiments of this disclosure, the first node S does not necessarily represent an actual existing component, but rather represents the junction point of related circuit connections in the circuit diagram.

[0480] It should be noted that, in the description of the embodiments of this disclosure, the symbol Vd can represent both a data signal terminal and the level of a data signal; similarly, the symbol SEL can represent both a control signal and a control signal terminal; the symbols Vcom1 and Vcom2 can represent both a first common voltage and a second common voltage, or both a first common voltage terminal and a second common voltage terminal; the symbol VDD can represent both a first voltage terminal and a first power supply voltage; and the symbol VSS can represent both a second voltage terminal and a second power supply voltage. The following embodiments are the same and will not be described again.

[0481] Figure 25B It shows Figure 24A The circuit diagram shows a specific implementation example of the pixel circuit. For example... Figure 25B As shown, the data writing sub-circuit 111 includes a first data writing transistor P1 and a second data writing transistor N1 connected in parallel. The first data writing transistor P1 and the second data writing transistor N1 are a P-type metal-oxide-semiconductor field-effect transistor (PMOS) and an N-type metal-oxide-semiconductor field-effect transistor (NMOS), respectively. The control signals include a first control signal SEL and a second control signal SEL_B that are inversely related. The gate of the first data writing transistor P1 serves as the first control electrode of the data writing sub-circuit and is configured to receive the first control signal SEL. The gate of the second data writing transistor N1 serves as the second control electrode of the data writing sub-circuit and is configured to receive the second control signal SEL_B. The first terminal of the second data writing transistor N1 is electrically connected to the first terminal of the first data writing transistor P1, serving as the first terminal of the data writing sub-circuit and configured to receive the data signal Vd. The second terminal of the second data writing transistor N1 is electrically connected to the second terminal of the first data writing transistor P1, serving as the second terminal of the data writing sub-circuit and is electrically connected to the control electrode 150 of the driving sub-circuit 112.

[0482] For example, the first data write transistor P1 and the second data write transistor N1 are the same size and have the same channel width-to-length ratio.

[0483] The data writing sub-circuit 111 utilizes the complementary electrical characteristics of transistors, and has a low on-state resistance regardless of whether it transmits a high level or a low level, thus having the advantage of electrical signal transmission integrity, and can transmit the data signal Vd to the first terminal of the storage sub-circuit 113 without loss.

[0484] For example, such as Figure 25B As shown, the driving sub-circuit 112 includes a driving transistor N2, for example, the driving transistor N2 is an NMOS. The gate, first electrode, and second electrode of the driving transistor N2 serve as the control electrode, first electrode, and second electrode of the driving sub-circuit 112, respectively.

[0485] For example, the storage sub-circuit 113 includes a storage capacitor Cst, which includes a first capacitor electrode 141 and a second capacitor electrode 142. The first capacitor electrode 141 and the second capacitor electrode 142 serve as the first terminal and the second terminal of the storage sub-circuit 113, respectively.

[0486] For example, resistor 130 includes a resistor R. For example, a PN junction is formed between the second electrode 152 of the driving sub-circuit 112 and the substrate. The resistance of resistor 130 is configured such that the PN junction is turned off when the driving transistor N2 operates in the saturation region, that is, when the pixel circuit operates to drive the light-emitting element 120 to emit light. In this case, even if a short circuit occurs between the two electrodes of the light-emitting element 120, the voltage drop across resistor 130 can protect the potential of the second electrode 152, thereby preventing latch-up.

[0487] For example, the light-emitting element 120 is specifically implemented as an organic light-emitting diode (OLED). For example, the light-emitting element 120 can be a top-emitting OLED, emitting red, green, blue, or white light, etc. For example, the light-emitting element 120 is a micro OLED. The embodiments of this disclosure do not limit the specific structure of the light-emitting element. For example, the first electrode 121 of the light-emitting element 120 is the anode of the OLED, and the second electrode 122 is the cathode of the OLED, that is, the pixel circuit is a common cathode structure. However, the embodiments of this disclosure do not limit this, and the pixel circuit can also be a common anode structure depending on the change in circuit structure.

[0488] For example, the bias sub-circuit 114 includes a bias transistor N3, the gate, first terminal, and second terminal of which serve as the control terminal, first terminal, and second terminal of the bias sub-circuit 114, respectively.

[0489] Figure 25C It shows Figure 25B The signal timing diagram of the pixel circuit shown below will be combined with the following. Figure 25B The signal timing diagram shown is for Figure 25C The working principle of the pixel circuit shown will be explained. For example, the second data writing transistor, the driving transistor, and the bias transistor are all N-type transistors, and the first data writing transistor is a P-type transistor; however, this embodiment of the present disclosure does not limit this.

[0490] Figure 25C The waveforms of each signal are shown in two consecutive display cycles T1 and T2. For example, the data signal Vd is a high grayscale voltage in display cycle T1 and a low grayscale voltage in display cycle T2.

[0491] For example, such as Figure 25CAs shown, the display process of each frame of the image includes a data writing stage 1 and a light emission stage 2. One operating process of the pixel circuit includes: in the data writing stage 1, both the first control signal SEL and the second control signal SEL_B are on, the first data writing transistor P1 and the second data writing transistor N1 are turned on, and the data signal Vd is transmitted to the gate of the driving transistor N2 via the first data writing transistor P1 and the second data writing transistor N1; in the light emission stage 2, both the first control signal SEL and the second control signal SEL_B are off. Due to the bootstrap effect of the storage capacitor Cst, the voltage across the storage capacitor Cst remains constant, the driving transistor N2 operates in saturation and the current remains constant, driving the light-emitting element 120 to emit light. When the pixel circuit transitions from display cycle T1 to display cycle T2, the data signal Vd changes from a high grayscale voltage to a low grayscale voltage. Under the control of the second common voltage Vcom2, the bias transistor N3 generates a stable drain current. This drain current can quickly discharge the charge stored in the OLED anode when the grayscale of the OLED display needs to change rapidly. For example, the discharge process occurs during the data writing phase 1 of display cycle T2. Therefore, during the light emission phase 2 of display cycle T2, the voltage of the OLED anode drops rapidly, thereby achieving better dynamic contrast and improving the display effect.

[0492] For example, when the first node S is directly electrically connected to the light-emitting element 120, the voltage V0 is directly applied to the first electrode 121 of the light-emitting element 120, such as the anode voltage of the OLED; when the first node S is electrically connected to the light-emitting element 120 through the resistor 130, since the current flowing through the light-emitting element 120 is extremely small, the voltage of the first node S can be approximately equal to the voltage of the first electrode 121 of the light-emitting element 120; that is, the voltage of the first electrode 121 of the light-emitting element 120 is linearly related to the data signal (data voltage) Vd, thereby enabling fine control of grayscale and improving the display effect.

[0493] For example, the first control signal SEL and the second control signal SEL_B are differential complementary signals with the same amplitude but opposite phase. This helps improve the circuit's anti-interference performance. For example, the first control signal SEL and the second control signal SEL_B can be output from the same gate drive circuit unit (such as the GOA unit), thereby simplifying the circuit.

[0494] For example, such as Figure 24AAs shown, the display substrate 10 may further include a data driving circuit 13 and a scan driving circuit 14. The data driving circuit 13 is configured to output data signals as needed (e.g., an image signal from the input display device), such as the aforementioned data signal Vd. The scan driving circuit 14 is configured to output various scan signals, such as the aforementioned first control signal SEL and second control signal SEL_B, which may be, for example, an integrated circuit chip (IC) or a gate drive circuit (GOA) directly fabricated on the display substrate.

[0495] For example, the display substrate uses a silicon substrate as the substrate 101, and the pixel circuit, data driving circuit 13, and scan driving circuit 14 can all be integrated on the silicon substrate. In this case, since silicon-based circuits can achieve higher precision, the data driving circuit 13 and scan driving circuit 14 can, for example, be formed in the area corresponding to the display area of ​​the display substrate, and are not necessarily located in the non-display area.

[0496] For example, the display substrate 10 also includes a control circuit (not shown). This control circuit is configured to control the data driving circuit 13 to apply the data signal Vd, and to control the gate driving circuit 13 to apply various scan signals. An example of this control circuit is a timing control circuit (T-con). The control circuit can take various forms, such as including a processor and a memory, the memory containing executable code, which the processor runs to perform the detection method described above.

[0497] For example, the processor can be a central processing unit (CPU) or other forms of processing device with data processing and / or instruction execution capabilities, such as a microprocessor, a programmable logic controller (PLC), etc.

[0498] For example, the storage device may include one or more computer program products, which may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. Volatile memory may include, for example, random access memory (RAM) and / or cache memory. Non-volatile memory may include, for example, read-only memory (ROM), hard disk, flash memory, etc. One or more computer program instructions may be stored on the computer-readable storage medium, and the processor 121 may execute the functions expected by the program instructions. Various application programs and various data, such as electrical characteristic parameters acquired in the above-described detection method, may also be stored in the computer-readable storage medium.

[0499] The following adopts Figure 25B The pixel circuit shown is used as an example to illustrate the display substrate provided in at least one embodiment of the present disclosure; however, the embodiments of the present disclosure are not limited thereto.

[0500] Figure 26A This is a schematic diagram of a display substrate 10 provided for at least one embodiment of the present disclosure. For example, such as... Figure 26A As shown, the display substrate 10 includes a substrate 101, and a plurality of sub-pixels 100 are located on the substrate 101. The plurality of sub-pixels 100 are arranged in a sub-pixel array, the row direction of the sub-pixel array is a first direction D1, the column direction is a second direction D2, and the first direction D1 and the second direction D2 intersect, for example, orthogonal. Figure 26A The example shows two rows and six columns of subpixels, namely two pixel rows 20 and six pixel columns 30, and the areas of three pixel columns spaced apart from each other are shown with dashed boxes.

[0501] For example, the substrate 101 can be a rigid substrate, such as a glass substrate or a silicon substrate, or it can be formed of a flexible material with excellent heat resistance and durability, such as polyimide (PI), polycarbonate (PC), polyethylene terephthalate (PET), polyethylene, polyacrylate, polyaryl compounds, polyetherimide, polyethersulfone, polyethylene glycol terephthalate (PET), polyethylene (PE), polypropylene (PP), polysulfone (PSF), polymethyl methacrylate (PMMA), cellulose triacetate (TAC), cyclic olefin polymers (COP), and cyclic olefin copolymers (COC). The embodiments in this disclosure are all described using a silicon substrate as an example; however, the embodiments in this disclosure are not limited to this.

[0502] For example, the substrate 101 includes monocrystalline silicon or high-purity silicon. The pixel circuit is formed on the substrate 101 using CMOS semiconductor processes. For instance, the active regions of transistors (including the channel region, first electrode, and second electrode) are formed in the substrate 101 through a doping process, and insulating layers are formed through silicon oxidation or chemical vapor deposition (CVD), and multiple conductive layers are formed through sputtering to form a wiring structure. The active regions of each transistor are located inside the substrate 101.

[0503] Figure 26B It shows Figure 26A A sectional view along section line I-I'. For clarity, Figure 26B Some traces or electrode structures that are not directly connected have been omitted.

[0504] For example, such as Figure 26BAs shown, the display substrate 10 includes a substrate 101, a first insulating layer 201, a polysilicon layer 102, a second insulating layer 202, a first conductive layer 301, a third insulating layer 203, a second conductive layer 302, a fourth insulating layer 204, a third conductive layer 303, a fifth insulating layer 205, and a fourth conductive layer 304, sequentially located on the substrate 101. The structure of this display substrate 10 will be described layer by layer below. Figure 26B This will be used as a reference and explained together.

[0505] For clarity and ease of explanation, Figure 27A The portion of the display substrate 10 below the first conductive layer 301 is shown, namely the substrate 101 and the first insulating layer 201 and polysilicon layer 102 thereon, including each transistor (P1, N1-N3), storage capacitor Cst and resistor 130. Figure 27B It shows Figure 27A A magnified illustration of a subpixel 100; for clarity, in Figure 27A The text also shows corresponding examples. Figure 26A Mid-section line I-I'. Figures 28A-28E It shows Figure 27A The formation process of the substrate structure shown.

[0506] like Figure 27B As shown, for example, in a direction parallel to the surface of the substrate 101, the first data writing transistor P1 and the driving transistor N2 are located on opposite sides of the storage capacitor Cst, for example, on opposite sides of the storage capacitor Cst in the second direction D2.

[0507] Reference Figure 24C This setup helps to increase the distance between the first data write transistor P1 and the drive transistor N2, thereby increasing the resistance of the parasitic circuit and further reducing the risk of latch-up in the CMOS circuit.

[0508] For example, the material of the second capacitor electrode 142 of the storage capacitor 140 is a conductor or a semiconductor. For example, combined with Figure 26B and Figure 27B As shown, the second capacitor electrode 142 of the storage capacitor 140 is the first region 401 of the substrate 101; for example, the substrate 101 is a P-type silicon substrate, and the material of the second capacitor electrode 142 is P-type single crystal silicon. When a voltage is applied to the first capacitor electrode 141, the semiconductor-type first region 401 located below the first capacitor electrode 141 in the substrate 101 forms an inversion region and becomes a conductor, thereby connecting with the contact hole regions (such as...) on both sides of the first region 401. Figure 4B The contact hole regions 145a and 145b shown form an electrical connection. In this case, no additional doping or other treatment is applied to the first region 401.

[0509] In another example, the first region 401 is, for example, a conductor region in the substrate 101, such as a heavily doped region, which allows the second capacitor electrode 142 to obtain a stable and high conductivity.

[0510] For example, the substrate 101 further includes a second region 402, which is an N-type well region in the substrate 101. Figure 27B As shown, for example, the first data writing transistor P1 and resistor 130 are arranged side-by-side in the second region 402 in the second direction D2. Placing the resistor 130, made of polysilicon, in an N-type substrate helps reduce parasitic effects and improve circuit characteristics.

[0511] For example, in a direction parallel to the surface of the substrate 101, resistor (R) 130 and first data write transistor P1 are located on the same side of the second capacitor electrode 142. For example, in a direction parallel to the surface of the substrate 101, drive transistor N2 and bias transistor N3 are located on the same side of the second capacitor electrode 142.

[0512] For example, such as Figure 27B As shown, the first data write transistor P1 and the second data write transistor P1 are arranged side by side in the first direction D1 and are symmetrical about the axis of symmetry along the second direction D2. For example, the gate 160 of the first data write transistor P1 and the gate 170 of the second data write transistor P1 are arranged side by side in the first direction D1 and are symmetrical about the axis of symmetry along the second direction D2.

[0513] For example, resistor 130 has a U-shaped structure, such as an asymmetrical U-shaped structure, where the two branches of the U-shaped structure are of unequal length. For example, as... Figure 27B As shown, the second end 132 of resistor 130 is closer to the driving transistor N2.

[0514] Setting resistor 130 in a U-shape helps save the layout area occupied by the resistor, thereby improving the space utilization of the layout and contributing to the improvement of the display substrate resolution. For example, within the same space, a U-shaped resistor can increase the length of the resistor to obtain the desired resistance value.

[0515] Furthermore, designing resistor 130 as an asymmetric structure is also to make better use of layout space, for example, as Figure 27BAs shown, a contact hole region 411a is designed above the shorter branch of the U-shaped resistor. This contact hole region 411a is parallel to the second end 132 of the resistor 130 in the first direction D1. For example, this contact hole region 411a is an N-type heavily doped region (N+). For example, this contact hole region 411a is used to bias the well region 401 where the first data writing transistor P1 is located, thereby avoiding threshold voltage changes caused by latch-up effect and substrate bias effect, and improving circuit stability. For example, refer to... Figure 26B By applying a low-voltage bias to the P-type substrate 101 and a high-voltage bias to the N-type well region 402, the parasitic PN junction between the two can be reverse-biased, thereby electrically isolating the devices, reducing parasitic effects between the devices, and improving circuit stability.

[0516] For example, the opening of the U-shaped structure faces the first capacitor electrode 141, and the first end 131 and the second end 132 of the resistor 130 are located at the two ends of the U-shaped structure, respectively. As shown in the figure, the first end 131 of the resistor 130 is provided with a contact hole area 133 for electrical connection with the gate 150 of the driving transistor N2; the second end 132 of the resistor 130 is provided with a contact hole area 134 for electrical connection with the first electrode 121 of the light-emitting element 120.

[0517] For example, the material of the resistor 130 includes polycrystalline silicon, and the contact hole regions 133 and 134 are doped regions to reduce contact resistance; the main body region of the resistor 130 other than the contact hole regions is, for example, an intrinsic region or a low-doped region, thereby obtaining the desired resistance value.

[0518] For example, the first capacitor electrode 141 of the storage capacitor 140 is insulated from the resistor 130 in the same layer and both are made of polycrystalline silicon material; the doping concentration of the first capacitor electrode 141 of the storage capacitor 140 is higher than the doping concentration of the main body region of the resistor 130. For example, the main body region of the resistor 130 is made of intrinsic polycrystalline silicon material.

[0519] For example, the gates 160, 170, 150, and 180 of each transistor P1, N1-N3 are disposed on the same layer as the first capacitor electrode 141 of the storage capacitor 140, and all are made of polycrystalline silicon material. For example, as Figure 27B As shown, the gate 150 of the driving transistor N2 and the first capacitor electrode 141 are connected to each other as a single unit.

[0520] Figure 27BThe active regions P1a, N1a, N2a and N3a of each transistor P1, N1-N3 are also shown, along with the first electrode 161 and the second electrode 162 of the first data writing transistor P1, the first electrode 171 and the second electrode 172 of the second data writing transistor N1, the first electrode 151 and the second electrode 152 of the driving transistor N2, and the first electrode 181 and the second electrode 182 of the bias transistor N3.

[0521] Figure 27B The diagram also shows the gate contact region 165, first contact region 163, and second electrode contact region 164 of the first data writing transistor P1; the gate contact region 175, first contact region 173, and second electrode contact region 174 of the second data writing transistor N1; the gate contact region 155, first contact region 153, and second electrode contact region 154 of the driving transistor N2; and the gate contact region 185, first contact region 183, and second electrode contact region 184 of the bias transistor N3. For example, each first electrode contact region is the area where the corresponding first electrode is used to form an electrical contact; each second electrode contact region is the area where the corresponding second electrode contact region is used to form an electrical contact; and each gate contact region is the area where the corresponding gate is used to form an electrical contact.

[0522] For example, the active region P1a of the first data writing transistor P1 and the active region N1a of the second data writing transistor N1 are arranged side by side in the first direction D1 and are symmetrical about the axis of symmetry along the second direction D2.

[0523] like Figure 27B As shown, the area of ​​the active region N2a of the driving transistor N2 is larger than that of the active regions of other transistors, which can achieve a larger aspect ratio, thus helping to improve the driving capability of the driving transistor N2 and thereby improve the display effect.

[0524] like Figure 27B As shown, for transistors with large active regions, such as driving transistor N2 and bias transistor N3, there is enough space to set at least two contact hole regions on their first and second poles respectively, so that they can make sufficient contact with the structure to be connected and form a parallel structure, thereby reducing the contact resistance.

[0525] Figure 27B The diagram also shows a contact hole region 144 on the first capacitor electrode 141 and contact hole regions 145a and 145b configured to be electrically connected to the second capacitor electrode 142. Figure 27B As shown, the first capacitor electrode 141 and the second capacitor electrode 142 are respectively provided with at least two contact hole areas to reduce contact resistance.

[0526] Reference Figure 27AThe distribution of transistors (including the shape and size of each transistor) and storage capacitors and resistors in two adjacent sub-pixels 100 in the first direction D1 is symmetrical about the axis of symmetry along the second direction D2. That is, the corresponding structures in the two sub-pixels are symmetrical about the axis of symmetry along the second direction D2. The distribution of transistors in two adjacent sub-pixels 100 in the second direction D2 is symmetrical about the first direction axis.

[0527] This symmetrical arrangement can maximize the uniformity of process errors, thereby improving the uniformity of the display substrate. Furthermore, this symmetrical arrangement allows for the integral formation of interconnected structures within the same layer of the substrate. Compared to separate arrangements, this results in a more compact pixel layout, improving space utilization and ultimately increasing the resolution of the display substrate.

[0528] For example, such as Figure 27A As shown, the second region 402 of two adjacent sub-pixels 100 in the first direction D1 is a single structure, and the second region 402 of two adjacent sub-pixels 100 in the second direction D2 is also a single structure. That is, the first data writing transistor N1 and resistor 130 in these four adjacent sub-pixels 100 are located in the same well region. Compared to setting separate well regions, this arrangement can make the pixel arrangement more compact while meeting design rules, which helps to improve the resolution of the display substrate.

[0529] For example, such as Figure 27A As shown, the active regions P1a of the first data writing transistors P1 of two adjacent sub-pixels on the second direction D2 are connected to each other in a structure that is, the active regions P1a of the two first data writing transistors P1 are located in the same doped region A1 (P-well) of the same second region 402, and the first poles of the two first data transistors P1 are connected to each other in a structure to receive the same data signal Vd.

[0530] For example, such as Figure 27A As shown, the active regions N1a of the second data writing transistors N1 of two adjacent sub-pixels on the second direction D2 are connected to each other in a structure that is, the active regions N1a of the two second data writing transistors N1 are located in the same doped region A2 (N-well) of the substrate 101, and the first poles of the two second data writing transistors N1 are connected to each other in a structure to receive the same data signal Vd.

[0531] For example, such as Figure 27A As shown, the gates of the first data writing transistor P1 or the second data writing transistor N2 of two adjacent sub-pixels 100 in the first direction D1 are connected to each other as a single unit.

[0532] Since the gates of the first data write transistors P1 are configured to receive the same first control signal SEL for each row of pixels, and the gates of the second data write transistors N1 are configured to receive the same second control signal SEL_B, and since the transistors of two adjacent sub-pixels in the first direction D1 are mirror symmetrical, alternating between adjacent first write transistors P1 and adjacent second write transistors N1 in the first direction D1, the gates of two adjacent first data write transistors P1 can be directly connected into a single structure to form the first control electrode group 191, and the gates of adjacent second data write transistors N1 can be directly connected into a single structure to form the second control electrode group 192. This arrangement allows for a more compact pixel arrangement while meeting design requirements, thus contributing to improved resolution of the display substrate.

[0533] like Figure 27A As shown, for two adjacent sub-pixels 100 in the first direction D1, when their driving transistors N2 are adjacent, the active regions N2a of the two driving transistors N2 are connected to each other in a single structure, that is, the active regions N2a of the two driving transistors N2 are located in the same doped region B (N-well) of the substrate 101, and the first electrodes of the two driving transistors N2 are connected to each other in a single structure, forming a third control electrode group 193 to receive the same first power supply voltage VDD; when their bias transistors N3 are adjacent, the gates of the two bias transistors N3 are connected to each other in a single structure to receive the same second common voltage Vcom2; the active regions N3a of the two bias transistors N3 are connected to each other in a single structure, that is, the active regions N3a of the two bias transistors N3 are located in the same doped region C (N-well) of the substrate 101, and the first electrodes of the two bias transistors N3 are connected to each other in a single structure to receive the same second power supply voltage VSS.

[0534] This setup allows for a more compact pixel arrangement while still meeting design requirements, which helps improve the resolution of the display substrate.

[0535] Figures 28A-28D It shows Figure 27A The formation process of the substrate structure shown is illustrated, but for clarity, only two rows and two columns of sub-pixels, i.e., four adjacent sub-pixels 100, are shown in the figure. The following is combined with... Figures 28A-28D The formation process of the display substrate provided in the embodiments of this disclosure is illustrated by way of example, but this is not intended to limit the disclosure.

[0536] For example, a silicon substrate is provided, such as a P-type single-crystal silicon substrate. N-type transistors (e.g., driving transistors) can be fabricated directly on this P-type silicon substrate, that is, the P-type substrate acts as the channel region of the N-type transistor, which is beneficial to taking advantage of the high speed of NMOS devices and improving circuit performance.

[0537] like Figure 28A As shown, for example, N-type doping is performed on a P-type silicon substrate to form an N-type well region, namely the second region 402, to serve as the substrate for the first data writing transistor P1 and the resistor 130.

[0538] For example, the second regions 402 of two adjacent sub-pixels in the first direction D1 can be connected to each other, and the second regions 402 of two adjacent sub-pixels in the second direction D2 can be connected to each other. For example, during the N-type doping, the undoped regions on the substrate 101 are shielded.

[0539] Combination Figure 27B and Figure 28B As shown, for example, a first insulating layer 201 is formed on the substrate 101, and then a polysilicon layer 102 is formed on the first insulating layer 201.

[0540] The first insulating layer 201 includes the gate insulating layer of each transistor and the dielectric layer 104 of the storage capacitor Cst. The polysilicon layer 102 includes the first capacitor electrode 141, the resistor 130, and the gates 150, 160, 170, and 180 of each transistor (P1, N1-N3).

[0541] The gate of the first data writing transistor P1 is located in the second region 402, and the N-type well region serves as the channel region of the P-type transistor. The resistor 130 is also located in the second region 402. Forming the polysilicon resistor 130 in the N-type substrate helps reduce parasitic effects and improve circuit characteristics. Each N-type transistor is formed directly on the P-type substrate.

[0542] like Figure 28B As shown, the patterns of polysilicon layers in two adjacent sub-pixels in the first direction D1 are symmetrical about the axis of symmetry along the second direction D2; the patterns of polysilicon layers in two adjacent sub-pixels in the second direction D2 are symmetrical about the axis of symmetry along the first direction D1.

[0543] For example, the gates of the first data write transistor P1 and the second data write transistor N1 of two adjacent sub-pixels in the first direction D1 can be integrally formed.

[0544] For example, the first insulating layer is formed on a substrate by thermal oxidation. For example, the material of the first insulating layer is a silicon nitride, oxide, or oxynitride.

[0545] For example, a polysilicon material layer is formed on the first insulating layer by chemical vapor deposition (PVD), and then the polysilicon material layer is formed by photolithography.

[0546] Figure 28C The doped window region 103 of the substrate is shown (left image), and in Figure 28B The doped window region is shown on the substrate structure (right figure). For example, the doping is heavy doping to form contact hole regions for electrical connections on the substrate. For example, the doped window region includes the source and drain regions of each transistor. For example, the doped window region also includes contact hole regions of the substrate and contact hole regions of resistor 130, for example including... Figure 27B The contact hole regions shown are 400a, 400b, 411a, 411b, 145a, 145b, 133, and 134. For example, since the gate of the transistor is formed of polycrystalline silicon, it also needs to be doped. During doping, a barrier layer needs to be formed to shield the undoped areas, exposing only the corresponding doped window areas and amorphous silicon areas.

[0547] It should be noted that, Figure 28C The diagram only illustrates the doping window regions. In the actual doping process, corresponding barrier layers / mask layers are added to expose the respective doping window regions and polysilicon regions for doping. For example, the material of the barrier layer / mask layer can be photoresist or oxide material.

[0548] like Figure 28D As shown, a barrier layer 135 is formed corresponding to resistor 130. In order to protect the resistance value of resistor 130, resistor 130 needs to be shielded during the doping process to prevent resistor 130 from being damaged by doping. The barrier layer 135 shields the main body of resistor 130, exposing only the contact hole areas 133 and 134 at both ends of resistor 130.

[0549] For example, the barrier layer 135 can be a silicon nitride, oxide, or oxynitride, or it can be a photoresist material. After the doping process is completed, the barrier layer 135 can be retained in the display substrate or removed.

[0550] In other examples, the barrier layer 135 of the resistor 130 may also be formed together with the barrier layer / mask layer of other regions during doping, which is not limited in the embodiments disclosed herein.

[0551] For example, during the doping process, N-type doping and P-type doping need to be performed separately, to form the source and drain regions of an N-type transistor and the source and drain regions of a P-type transistor. During the N-type doping process, a barrier layer needs to be formed to shield the regions not doped with N-type doping; during the P-type doping process, a barrier layer needs to be formed to shield the regions not doped with P-type doping.

[0552] Figure 28E The image shows N-type doped region SN and P-type doped region SP using different shading patterns (left image), and... Figure 28D The substrate shown illustrates the N-type doped region SN and the P-type doped region SP (right figure). The N-type doped region SN and the P-type doped region SP are... Figure 27B It is also shown in the text, which can be referred to together.

[0553] For example, the N-type doping process includes forming a barrier layer to cover the P-type doped region SP, and covering the N-type doped region SN except for the doped window region and the polysilicon region, retaining only the doped window region and the polysilicon region in the N-type doped region SN, that is, the SN region and... Figure 28C The overlapping region of the doped window region 103 and the polysilicon region is shown; then an N-type doping process is performed. (Comparison) Figure 27B This N-type doping process can be used to form the gate, first electrode, and second electrode of transistors N1-N3, as well as contact hole regions 411a, 411b, 145a, and 145b. This N-type doping process can be, for example, an ion implantation process, and the doping element can be, for example, boron.

[0554] For example, a P-type doping process includes forming a barrier layer to cover the N-type doped region SN, and covering the P-type doped region SP except for the doped window region and the polysilicon region, retaining only the doped window region and the polysilicon region within the P-type doped region SP. That is, the SP region and... Figure 28C The overlapping region of the doped window region 103 and the polysilicon region is shown; then, a P-type doping process is performed. (Comparison) Figure 27B The gate, first electrode, and second electrode of transistor P1, as well as contact holes 400a, 400b, 133, and 134, can be formed through this P-type doping process. This P-type doping process can be, for example, an ion implantation process, and the doping element can be, for example, phosphorus.

[0555] During doping, such as with ion implantation, the polysilicon pattern can act as a mask, ensuring that ion implantation into the silicon substrate occurs precisely on both sides of the polysilicon, thus forming the first and second electrodes of each transistor and achieving self-alignment. Furthermore, the resistivity of the originally high-resistivity polysilicon decreases after doping, making it suitable for forming the gate of each transistor and the first capacitor electrode. Therefore, using polysilicon as the resistor and gate material offers several advantages and reduces processing costs.

[0556] Thus, it was formed Figure 27A The structure of the display substrate shown includes transistors P1, N1-N3, resistor 130, and storage capacitor Cst.

[0557] For example, in two adjacent sub-pixels in the first direction D1, the corresponding transistors, resistors, and storage capacitors Cst are symmetrical about the axis of symmetry along the second direction D2; in two adjacent sub-pixels in the second direction D2, the corresponding transistors, resistors, and storage capacitors Cst are symmetrical about the axis of symmetry along the first direction D1.

[0558] It should be noted that in this embodiment, the storage capacitor Cst is a field-effect capacitor. After a voltage is applied to the first capacitor electrode 141, an inverse charge is generated in the region of the substrate 101 located below the first capacitor electrode 141, which makes the lower plate of the storage capacitor Cst, i.e., the second capacitor electrode 142, conductive.

[0559] In other embodiments, the second capacitor electrode 142 may be formed by pre-conducting (e.g., doping) the region of the substrate 101 located below the first capacitor electrode 141. This disclosure does not limit this aspect.

[0560] exist Figure 27A The substrate shown is formed by sequentially forming a second insulating layer 202, a first conductive layer 301, a third insulating layer 203, a second conductive layer 302, a fourth insulating layer 204, a third conductive layer 303, a fifth insulating layer 205, and a fourth conductive layer 304, thus forming a... Figure 26A The display substrate shown.

[0561] Figure 29A and Figure 29B The pattern of the first conductive layer 301 and the first conductive layer 301 disposed on are shown respectively. Figure 27A The situation on the substrate structure shown. Figure 29C It shows Figure 29B A sectional view along section line IV-IV'; Figure 29B The image also shows a via in the second insulating layer 202, which is connected to... Figure 27B Each contact area in the diagram corresponds one-to-one, used to electrically connect each contact hole area to the pattern in the first conductive layer 301. For clarity, only two rows and six columns of sub-pixels are shown in the figure, and the area of ​​one sub-pixel 100 is indicated by a dashed box; furthermore, in Figure 29B The text also shows corresponding examples. Figure 26A The location of the mid-section line I-I'.

[0562] like Figure 29AAs shown, the pattern of the first conductive layer in two adjacent sub-pixels in the first direction D1 is symmetrical about the axis of symmetry along the second direction D2; the pattern of the first conductive layer in two adjacent sub-pixels in the second direction D2 is symmetrical about the axis of symmetry along the first direction D1. The pattern of the first conductive layer will be illustrated below using a single sub-pixel as an example.

[0563] like Figure 29A As shown, the first conductive layer 301 includes a connection electrode 313, which is used to electrically connect the first end 131 of the resistor 130 to the second electrode 152 of the drive sub-circuit 112.

[0564] For example, in conjunction with reference Figure 29B The first end of the connecting electrode 313 is electrically connected to the first end 131 of the resistor 130 through a via 225 in the second insulating layer 202; the second end of the connecting electrode 313 includes a first branch 331 and a second branch 332, which are combined with... Figure 26B The first branch 331 is electrically connected to the first electrode 151 of the driving transistor N2 through a via 226a in the second insulating layer 202, and the second branch 332 is electrically connected to the first electrode 181 of the bias transistor N3 through a via 226b in the second insulating layer 202.

[0565] For example, such as Figure 29B As shown, in the second direction D2, the via 225 and via 226a are located on opposite sides of the first capacitor electrode 141; that is, the orthogonal projection of the connecting electrode 313 on the substrate 101 passes through the orthogonal projection of the first capacitor electrode 141 on the substrate 101 in the second direction D2.

[0566] For example, at least two vias 226a and 226b can be provided to reduce contact resistance.

[0567] For example, in conjunction with reference Figure 29A and Figure 29B The first conductive layer 301 also includes a connecting electrode 314, which is electrically connected to the second end 132 of the resistor 130 through a via 229 in the second insulating layer 202. The connecting electrode 314 is used to electrically connect to the first electrode 121 of the light-emitting element 120.

[0568] For example, the connection electrode 314 is L-shaped, with one branch electrically connected to the second terminal 132 of the resistor 130 and the other branch electrically connected to the first electrode 121 of the light-emitting element 120.

[0569] For example, combining Figure 29B and Figure 29CAs shown, the first conductive layer 301 further includes a third capacitor electrode 315, which overlaps with the first capacitor electrode 141 in a direction perpendicular to the substrate. The third capacitor electrode 315 is electrically connected to the contact hole region 145a through a via 227 in the second insulating layer 202, so as to be electrically connected to the second capacitor electrode 142; that is, in a direction perpendicular to the substrate, the second capacitor electrode 142 and the third capacitor electrode 315 are located on both sides of the first capacitor electrode 141 and are electrically connected to each other, thereby forming a parallel capacitor structure and increasing the capacitance value of the storage capacitor Cst.

[0570] For example, combining Figure 29B and Figure 29C As shown, the first conductive layer 301 further includes a fourth capacitor electrode 316, which overlaps with both the first capacitor electrode 141 and the second capacitor electrode 142 in a direction perpendicular to the substrate. The fourth capacitor electrode 316 is electrically connected to the contact hole region 145b through a via 228 in the second insulating layer 202, thereby connecting to the second capacitor electrode 142. The fourth capacitor electrode 316 can further increase the capacitance value of the storage capacitor Cst, improving circuit performance.

[0571] For example, the third capacitor electrode 315 and the fourth capacitor electrode 316 are located on both sides of the connecting electrode 313 in the first direction D1.

[0572] For example, such as Figure 29A As shown, in the first direction, the adjacent third capacitor electrode 315 of two adjacent sub-pixels of D1 can be integrally formed to receive the same second power supply voltage VSS, and the adjacent fourth capacitor electrode 316 of two adjacent sub-pixels of D1 in the first direction can be integrally formed to receive the same second power supply voltage VSS.

[0573] For example, at least two vias 227 and 228 can be provided to reduce contact resistance; for example, the at least two vias 227 are arranged along the second direction D2, and the at least two vias 228 are arranged along the second direction D2.

[0574] For example, the first conductive layer 301 also includes a connection electrode 317, which is used to electrically connect the second end of the data writing sub-circuit to the first end of the storage sub-circuit, that is, to electrically connect the second electrode 161 of the first data writing transistor P1, the second electrode 171 of the second data writing transistor N1, and the first capacitor electrode 141.

[0575] Reference Figure 29A and Figure 29B The connection electrode 317 includes three ends, for example, a T-shaped structure. (Refer to reference...) Figure 26BThe first end of the connection electrode 317 is electrically connected to the second electrode of the first data writing transistor P1 through a via 261a in the second insulating layer 202, the second end of the connection electrode 317 is electrically connected to the second electrode of the second data writing transistor N1 through a via 261b in the second insulating layer 202, and the third end of the connection electrode 317 is electrically connected to the first capacitor electrode 141 through a via 261c in the second insulating layer 202.

[0576] For example, such as Figure 29B As shown, in the second direction D2, the third ends of the connecting electrode 314 and the connecting electrode 317 at least partially overlap. This arrangement makes the pixel layout more compact, thereby improving the space utilization of the display substrate and increasing the resolution of the display substrate.

[0577] Reference Figure 29A and Figure 29B The first conductive layer 301 further includes a first scan line connection portion 311 and a second scan line connection portion 312. The first scan line connection portion 311 is electrically connected to the first scan line so that the gate of the first data writing transistor P1 receives the first control signal SEL. The second scan line connection portion 312 is electrically connected to the second scan line so that the gate of the second data writing transistor N1 receives the first control signal SEL_B.

[0578] For example, the first scan line connection portion 311 is electrically connected to the gate of the first data writing transistor P1 through the via 221 in the second insulating layer 202, and the second scan line connection portion 312 is electrically connected to the gate of the second data writing transistor N1 through the via 222 in the second insulating layer 202.

[0579] For example, such as Figure 29A As shown, adjacent sub-pixels in the first direction D1 share the first scan line connection portion 311 or the second scan line connection portion 312.

[0580] like Figure 29A As shown, the first conductive layer 301 also includes a data line connection portion 245 (an example of the third connection electrode of this disclosure), which is used to electrically connect to the data line so that the first electrode of the first data writing transistor P1 and the first electrode of the second data writing transistor N1 receive the data signal Vd transmitted by the data line.

[0581] like Figure 29B As shown, the data line connection portion 245 is electrically connected to the first electrode 161 of the first data writing transistor P1 through the via 223 in the second insulating layer 202, and electrically connected to the first electrode 171 of the second data writing transistor N1 through the hole 224 in the second insulating layer 202.

[0582] For example, such as Figure 29A As shown, multiple data line connection portions 245 are arranged at intervals in the first direction D1, for example, located at the boundary between two sub-pixel rows. For example, two adjacent sub-pixels in the second direction D2 share one data line connection portion 245.

[0583] refer to Figure 29A and Figure 29B The first conductive layer 301 also includes a connection electrode 318, which is electrically connected to the first electrode of the driving transistor N2 through a via 230 in the second insulating layer 202.

[0584] refer to Figure 27A and Figure 27B The first conductive layer 301 also includes connecting electrodes 319a, 319b, and 319c. These connecting electrodes are provided for biasing the substrate of the transistor, for example, to connect the N-type substrate to the first power supply voltage terminal to receive the first power supply voltage VDD (high voltage), or to connect the P-type substrate to the second power supply voltage terminal to receive the second power supply voltage VSS (low voltage). This can avoid parasitic effects such as substrate biasing and improve the stability of the circuit.

[0585] Reference Figure 27B The connection electrodes 319a and 319b are electrically connected to the contact hole regions 411a and 411b in the second region (N-well region) 402 of the substrate 101 through vias 262a and 262b in the second insulating layer 202, respectively. These connection electrodes 319a and 319b are used to connect to the first voltage terminal VDD to bias the N-type substrate of the first data writing transistor P1. The connection electrode 319c is electrically connected to the contact hole region 400a in the substrate 101 through via 262c in the second insulating layer 202. This connection electrode 319c is used to connect to the second voltage terminal VSS to bias the P-type substrate where the second data writing transistor N1 is located.

[0586] Reference Figures 29A-29B The first conductive layer 301 also includes a bias voltage line 250, which extends along the first direction D1 and is electrically connected to the gate of the bias transistor N3 through a via 263 in the second insulating layer 202 to provide a second common voltage Vcom2.

[0587] Reference Figure 27B , Figures 29A-29BThe first conductive layer 301 further includes a power line 260 (an example of the ninth power line of this disclosure), which extends along a first direction D1 for transmitting a second power supply voltage VSS. The power line 260 is electrically connected to the first electrode of the bias transistor N3 through a via 264a in the second insulating layer 202 to provide the second power supply voltage VSS, and is electrically connected to the contact hole region 400b in the substrate 101 through a via 264b in the second insulating layer 202 to bias the P-type substrate (an example of the second doped region of this disclosure) where the second data writing transistor N1 is located.

[0588] Figure 30A A schematic diagram of the second conductive layer 302 is shown. Figure 30B A second conductive layer 302 is shown based on the first conductive layer 301. Figure 30B The figure also shows vias in the third insulating layer 203, which are used to connect the patterns in the first conductive layer 301 and the patterns in the second conductive layer 302. For clarity, only four rows and six columns of sub-pixels are shown in the figure, and the boundary between two sub-pixel rows is shown with dashed lines; furthermore, Figure 30B The text also shows corresponding examples. Figure 26A The location of the mid-section line I-I'.

[0589] like Figure 30A As shown, the pattern of the second conductive layer in two adjacent sub-pixels in the first direction D1 is symmetrical about the axis of symmetry along the second direction D2; the pattern of the second conductive layer in two adjacent sub-pixels in the second direction D2 is symmetrical about the axis of symmetry along the first direction D1. The pattern of the second conductive layer will be illustrated below using a single sub-pixel as an example.

[0590] like Figure 30A As shown, the second conductive layer 302 includes power lines 270a, 270b, 280a, and 280b extending along the first direction D1. Power lines 270a and 270b are used to transmit a second power supply voltage VSS, and power lines 280a and 280b are used to transmit a first power supply voltage VDD. The power lines 270a, 280a, 270b, and 280b are arranged alternately along the second direction D2.

[0591] Reference Figure 26B , Figure 30A and Figure 30BThe power line 270a (an example of a first power line in this disclosure) is electrically connected to the power line 260 in the first conductive layer 301 through a plurality of vias 235 in the third insulating layer 203, thereby forming a parallel structure and effectively reducing the resistance on the trace; the plurality of vias 235 are arranged along the first direction D1. For example, the power line 270b is electrically connected to the fourth capacitor electrode 316 through a via 236 in the third insulating layer 203 to provide the second power supply voltage VSS; for example, the plurality of vias 236 are arranged along the second direction D2. For example, the power line 270b is also electrically connected to the third capacitor electrode 315 through a via 267 in the third insulating layer 203 to provide the second power supply voltage VSS; for example, the plurality of vias 267 are arranged along the second direction D2.

[0592] For example, in the second direction D2, the average line width of the power line 270b (an example of the seventh power line of this disclosure) is greater than the average line width of the power line 270a. This is because the fourth capacitor electrode 316 and the third capacitor electrode 315, which are electrically connected to the power line 270b, both have a large area. Setting the power line 270b to have a larger width facilitates the formation of multiple connection holes 236 and 267 between the power line 270b and the fourth capacitor electrode 316 and the third capacitor electrode 315, thereby effectively reducing the contact resistance.

[0593] Reference Figure 30A and Figure 30B The power line 280a (an example of a second power line in this disclosure) is electrically connected to the connection electrode 318 (an example of a fifth connection electrode in this disclosure) in the first conductive layer 301 through a via 237 in the third insulating layer 203, thereby connecting to the first terminal of the driving transistor N2 to provide a first power supply voltage VDD. The power line 280b is electrically connected to the connection electrode 319a in the first conductive layer 301 through a via 238 in the third insulating layer 203, thereby providing a high voltage bias to the second region (N-well region) 402 (an example of a first doped region in this disclosure) in the substrate 101; for example, a plurality of vias 238 are arranged along the second direction D2.

[0594] For example, in the second direction D2, the average line width of the power line 280b (an example of the eighth power line of this disclosure) is greater than the average line width of the power line 280a. This is because the connecting electrode 319a, which is electrically connected to the power line 280b, has a larger size in the second direction D2. Setting the power line 280b to have a larger width facilitates the formation of multiple connecting holes 238 between it and the connecting electrode 319a, thereby increasing the contact area with the connecting electrode 319a and effectively reducing the contact resistance.

[0595] For example, the second conductive layer 302 further includes multiple first scan lines 210 and multiple second scan lines 220 extending along the first direction D1. For example, Figure 24A The scan line 11 shown can be either the first scan line 210 or the second scan line 220.

[0596] Reference Figure 29A and Figure 29B The first scan line 210 is electrically connected to the first scan line connection portion 311 through the via 231 in the third insulating layer 203, and the second scan line 220 is electrically connected to the second scan line connection portion 312 through the via 232 in the third insulating layer 203.

[0597] For example, in conjunction with reference Figure 26B , Figure 30A and Figure 30B The second conductive layer 302 further includes a connection electrode 323, which is electrically connected to the connection electrode 314 in the first conductive layer 301 through a via 239 in the third insulating layer 203, thereby connecting to the second terminal 132 of the resistor 130. The connection electrode 323 is used for electrical connection to the first electrode 121 of the light-emitting element 120. For example, the number of vias 239 is at least two.

[0598] For example, in conjunction with reference Figure 30A and Figure 30B The second conductive layer 302 also includes a connection electrode 324, which is electrically connected to the connection electrode 319b in the first conductive layer 301 through a via 265 in the third insulating layer 203, so as to be electrically connected to the contact hole region 411b in the second region (N-well region) 402 in the substrate 101.

[0599] For example, in conjunction with reference Figure 30A and Figure 30B The second conductive layer 302 further includes a connection electrode 325, which is electrically connected to the connection electrode 319c in the first conductive layer 301 through a via 266 in the third insulating layer 203, so as to be electrically connected to the contact hole region 400a in the substrate 101.

[0600] For example, the connecting electrode 325 has a cross-shaped structure. For example, the connecting electrode 324 and the connecting electrode 325 are alternately distributed in the first direction D1 and are located at the boundary of two sub-pixel rows.

[0601] For example, such as Figure 30A As shown, the second conductive layer 302 also includes a data line connection portion 244 (an example of the fourth connection electrode of this disclosure). (Referring to the reference...) Figure 30B The data line connection portion 244 is electrically connected to the data line connection portion 245 in the first conductive layer 301 through the via 233.

[0602] For example, such as Figure 30AAs shown, multiple data line connectors 244 are arranged at intervals in the first direction D1, and a connection electrode 324 or a connection electrode 325 is provided between each two adjacent data line connectors 244.

[0603] For example, the data line connection 244 is located at the boundary between two sub-pixel rows. For example, two adjacent sub-pixels in the second direction D2 share one data line connection 244.

[0604] For example, in conjunction with reference Figure 30A and Figure 30B In the second direction D2, the data line connection portion 244 located in each column of sub-pixels is alternately located on both sides of the data line connection portion 245, and is electrically connected to the first end and the second end of the data line connection portion 245 through vias 233 and 234 respectively, in order to connect the data line connection portion 245 to different data lines.

[0605] Figure 31A A schematic diagram of the third conductive layer 303 is shown. Figure 31B A third conductive layer 303 is shown based on the second conductive layer 302. Figure 31B The figure also shows vias in the fourth insulating layer 204, which are used to connect the patterns in the second conductive layer 302 and the patterns in the third conductive layer 303. For clarity, only the conductive patterns corresponding to four rows and six columns of sub-pixels are shown in the figure, and are marked with dashed lines. Figure 31A The diagram shows the boundary line between the two rows of sub-pixels; furthermore, in Figure 31B The text also shows corresponding examples. Figure 26A The location of the mid-section line I-I'.

[0606] For example, the third conductive layer 303 includes multiple data lines extending along the second direction D2, which are used to connect to the first end of the data writing sub-circuit in the sub-pixel to provide a data signal Vd. For example, as Figure 31A The multiple data lines shown include multiple first data lines 241 and multiple second data lines 242, which are arranged alternately in the first direction D1. For example, Figure 24A The data line 12 shown can be either the first data line 241 or the second data line 242.

[0607] For example, the data line is divided into multiple data line groups, each including a first data line 241 and a second data line 242. For instance, each sub-pixel column is connected to a corresponding data line group, that is, connected to one first data line 241 and one second data line 242; that is, one column of sub-pixels is driven by two data lines. This helps reduce the load on each data line, thereby improving the driving capability of the data line, reducing signal latency, and improving display quality.

[0608] refer to Figure 31B The first data line 241 passes through the via 403 in the fourth insulating layer 204 and... Figure 30B The data line connection portion 244 located between the first row sub-pixels and the second row sub-pixels in the second conductive layer 302 shown is electrically connected to the first and second row sub-pixels, thereby providing data signals to the first and second row sub-pixels; the second data line 242 is connected to the fourth insulating layer 204 through the via 404 in the fourth insulating layer 204. Figure 30B The data line connection portion 244 located between the third row sub-pixels and the fourth row sub-pixels in the second conductive layer 302 shown is electrically connected, thereby providing data signals to the third and fourth row sub-pixels.

[0609] The following points need to be explained:

[0610] (1) The accompanying drawings of the embodiments of this disclosure only involve the structures involved in the embodiments of this disclosure. Other structures can be referred to the general design.

[0611] (2) Where there is no conflict, features of the same embodiment and different embodiments of this disclosure can be combined with each other.

[0612] The above are merely specific embodiments of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A display substrate, comprising: A driving substrate, including a substrate and a driving circuit; The first planarization layer is located on the driving circuit; An anode layer is located on the side of the first planarization layer away from the driving substrate; A pixel defining layer is located on the side of the anode layer away from the driving substrate; A light-emitting functional layer is located on the side of the anode layer away from the driving substrate; A cathode layer is located on the side of the light-emitting functional layer away from the driving substrate; as well as An encapsulation layer is located on the side of the cathode layer away from the driving substrate; The driving circuit includes at least one transistor, and the transistor includes a semiconductor layer. The anode layer includes a plurality of anodes, and the display substrate includes a plurality of pixel openings located on the side of the plurality of anodes away from the driving substrate. The plurality of pixel openings are configured to at least overlap with the plurality of anodes. Each of the anodes includes a main body and a protrusion, the protrusion being connected to the main body. The size of the protrusion in a first direction is larger than the size of the main body in the first direction. The light-emitting functional layer includes multiple light-emitting portions, which are in contact with the main bodies of the multiple anodes. The orthographic projection of the pixel defining layer on the driving substrate overlaps with the orthographic projection of the protrusion on the driving substrate. The pixel defining layer includes a pixel defining portion, which includes: a pixel defining flat portion located between two adjacent anodes; and protrusion structures located on the side of the protrusion of each of the two adjacent anodes away from the driving substrate. The pixel defining flat portion connects the protrusion structures. Each of the protruding structures includes: a top surface; a first sidewall located on the side of the protruding structure near the center of the main body; and a second sidewall connecting the first sidewall and the top surface, wherein the second sidewall is further away from the driving substrate relative to the first sidewall; the slope angle of the first sidewall is greater than the slope angle of the second sidewall. Each of the aforementioned protrusion structures further includes: The third sidewall is located on the side of the protruding structure near the pixel-defined flat portion. Wherein, the slope angle of the first sidewall is α, the slope angle of the second sidewall is β, and the slope angle of the third sidewall is γ, and satisfies the following formula: β<γ<α, The protrusion of each anode includes a fourth sidewall located on the side of the protrusion near the center of the main body. Wherein, the slope angle of the fourth sidewall is δ, and satisfies the following formula: β < δ < α.

2. The display substrate according to claim 1, wherein, The protrusion is located around the periphery of the main body.

3. The display substrate according to claim 1, wherein, The pixel definition portion is symmetrically arranged about the center of the interval region between adjacent anodes.

4. The display substrate according to claim 1, wherein, The slope angle of the first sidewall ranges from 75 to 89 degrees, and the slope angle of the second sidewall ranges from 15 to 45 degrees.

5. The display substrate according to claim 1, wherein, The difference between the slope angle of the first sidewall and the slope angle of the second sidewall is equal to i times the slope angle of the third sidewall, where i ranges from 0.8 to 1.

2.

6. The display substrate according to claim 1, wherein, The slope angle α of the first sidewall, the slope angle β of the second sidewall, and the slope angle γ of the third sidewall satisfy the following formula: (α-β)=i*γ, The value of i ranges from 0.8 to 1.

2.

7. The display substrate according to claim 6, wherein, The difference between the slope angle of the first sidewall and the slope angle of the second sidewall is equal to j times the difference between the slope angle of the second sidewall and the slope angle of the third sidewall, where j ranges from 1.5 to 3.

8. The display substrate according to claim 1, wherein, The slope angle α of the first sidewall, the slope angle β of the second sidewall, and the slope angle γ of the third sidewall satisfy the following formula: (α-β)=j*(γ-β), The value of j ranges from 1.5 to 3.

9. The display substrate according to claim 1, wherein, The sum of the slope angles of the first sidewall and the second sidewall is equal to k times the slope angle of the third sidewall, where k ranges from 2 to 3.

10. The display substrate according to claim 1, wherein, The slope angle α of the first sidewall, the slope angle β of the second sidewall, and the slope angle γ of the third sidewall satisfy the following formula: (α+β)=k*γ-β, The value of k ranges from 2 to 3.

11. The display substrate according to claim 1, wherein, The slope angle of the third sidewall ranges from 45 to 60 degrees.

12. The display substrate according to claim 1, wherein, The orthographic projection of the third sidewall onto the driving substrate in the second direction is larger than the orthographic projection of the second sidewall onto the driving substrate in the second direction, and the orthographic projection of the second sidewall onto the driving substrate in the second direction is larger than the orthographic projection of the first sidewall onto the driving substrate in the second direction.

13. The display substrate according to claim 1, wherein, The dimension of the first sidewall in the first direction is H1, the dimension of the second sidewall in the first direction is H2, and the dimension of the third sidewall in the first direction is H3. H1, H2, and H3 satisfy the following formula: H3*cosγ > H2*cosβ > H1*cosα.

14. The display substrate according to claim 1, wherein, The protrusions of each of the anodes include: The first sub-anode layer is located on the side of the driving circuit away from the substrate; The second sub-anode layer is located on the side of the first sub-anode layer away from the driving substrate; and The third sub-anode layer is located on the side of the second sub-anode layer away from the driving substrate.

15. The display substrate according to claim 14, wherein, The first sub-anode layer has a larger dimension in the second direction than the third sub-anode layer in the second direction, and the third sub-anode layer has a larger dimension in the second direction than the second sub-anode layer in the second direction.

16. The display substrate according to claim 15, wherein, The dimension of the third sub-anode layer extending beyond the second sub-anode layer in the second direction is smaller than the dimension of the overlapping area in the second direction of the orthogonal projection of the pixel defining layer on the driving substrate and the orthogonal projection of the protrusion on the driving substrate.

17. The display substrate according to claim 14, wherein, The end of the first sub-anode layer away from the main body includes a raised portion, the thickness of which in the first direction is greater than the average thickness of the first sub-anode layer in the first direction.

18. The display substrate according to claim 14, wherein, The third sub-anode layer bends at the end away from the main body towards the first sub-anode layer.

19. The display substrate according to claim 14, wherein, The protrusions of each of the anodes further include: A fourth sub-anode layer is located between the second and third sub-anode layers, and the dimension of the fourth sub-anode layer in the second direction is smaller than the dimension of the second sub-anode layer in the second direction.

20. The display substrate according to claim 19, wherein, The dimension of the third sub-anode layer extending beyond the fourth sub-anode layer in the second direction is smaller than the dimension of the overlapping area in the second direction of the orthographic projection of the pixel defining layer on the driving substrate and the orthographic projection of the protrusion on the driving substrate.

21. The display substrate according to claim 19, wherein, The second sub-anode layer includes a fifth sidewall located on the side of the second sub-anode layer away from the main body, and the fourth sub-anode layer includes a sixth sidewall located on the side of the fourth sub-anode layer away from the main body. The slope angle of the fifth sidewall is greater than that of the fourth sidewall, the slope angle of the sixth sidewall is greater than that of the fourth sidewall, and the slope angle of the fifth sidewall is greater than that of the sixth sidewall.

22. The display substrate according to claim 19, wherein, The ratio of the thickness of the first sub-anode layer in the first direction perpendicular to the driving substrate to the thickness of the second sub-anode layer in the first direction perpendicular to the driving substrate is in the range of 1 / 15 to 1 / 5.

23. The display substrate according to claim 19, wherein, The ratio of the thickness of the first sub-anode layer in the first direction perpendicular to the driving substrate to the thickness of the third sub-anode layer in the first direction perpendicular to the driving substrate is in the range of 1 / 3 to 4 / 5.

24. The display substrate according to claim 19, wherein, The ratio of the thickness of the first sub-anode layer in the first direction perpendicular to the driving substrate to the thickness of the fourth sub-anode layer in the first direction perpendicular to the driving substrate is in the range of 1 / 24 to 1 / 8.

25. The display substrate according to claim 14, wherein, The ratio of the distance between two adjacent anodes to the length of the orthographic projection of the anode protrusion onto the drive substrate ranges from 2 to 4.

26. The display substrate according to claim 25, wherein, The ratio of the distance between two adjacent anodes to the length of the orthographic projection of the anode protrusion onto the drive substrate ranges from 2.5 to 3.

5.

27. The display substrate according to any one of claims 1-25, wherein, The protrusion is arranged around the main body.

28. The display substrate according to claim 27, wherein, The shape of the orthographic projection of the anode onto the driving substrate includes a hexagon.

29. The display substrate according to any one of claims 1-25, further comprising: A reflective electrode layer is located on the side of the first planar layer near the anode layer; as well as The second planar layer is located on the side of the reflective electrode layer closest to the anode layer.

30. The display substrate according to claim 29, wherein, The reflective electrode layer is continuously disposed in the pixel opening.

31. The display substrate according to any one of claims 1-25, wherein, There is a first pore between the light-emitting functional layer and the main body, and there is at least one second pore between the light-emitting functional layer and the pixel defining layer, wherein the space occupied by the first pore is greater than the space occupied by the second pore.

32. A display substrate, comprising: A driving substrate, including a substrate and a driving circuit; The first planarization layer is located on the driving circuit; An anode layer is located on the side of the first planarization layer away from the driving substrate; A pixel defining layer is located on the side of the anode layer away from the driving substrate; A light-emitting functional layer is located on the side of the anode layer away from the driving substrate; A cathode layer is located on the side of the light-emitting functional layer away from the driving substrate; as well as An encapsulation layer is located on the side of the cathode layer away from the driving substrate; The driving circuit includes at least one transistor, the transistor including a semiconductor layer, the semiconductor layer being at least partially located within the substrate. The anode layer includes a plurality of anodes, and the display substrate includes a plurality of pixel openings located on the side of the plurality of anodes away from the driving substrate. The plurality of pixel openings are configured to at least overlap with the plurality of anodes. Each of the anodes includes a main body and a protrusion, the protrusion being connected to the main body. The size of the protrusion in a first direction is larger than the size of the main body in the first direction. The light-emitting functional layer includes multiple light-emitting portions, which are in contact with the main bodies of the multiple anodes. The orthographic projection of the pixel defining layer on the driving substrate overlaps with the orthographic projection of the protrusion on the driving substrate. The pixel defining layer includes a pixel defining portion, which includes: a pixel defining flat portion located between two adjacent anodes; and protrusion structures located on the side of the protrusion of each of the two adjacent anodes away from the driving substrate. The pixel defining flat portion connects the protrusion structures. Each of the protruding structures includes: a top surface; a first sidewall located on the side of the protruding structure near the center of the main body; and a second sidewall connecting the first sidewall and the top surface, wherein the second sidewall is further away from the driving substrate relative to the first sidewall; the slope angle of the first sidewall is greater than the slope angle of the second sidewall. Each of the aforementioned protrusion structures further includes: The third sidewall is located on the side of the protruding structure near the pixel-defined flat portion. Wherein, the slope angle of the first sidewall is α, the slope angle of the second sidewall is β, and the slope angle of the third sidewall is γ, and satisfies the following formula: β<γ<α, The protrusion of each anode includes a fourth sidewall located on the side of the protrusion near the center of the main body. Wherein, the slope angle of the fourth sidewall is δ, and satisfies the following formula: β < δ < α.

33. The display substrate according to claim 32, wherein, The encapsulation layer includes: an inorganic encapsulation layer located on the side of the cathode layer away from the driving substrate; the inorganic encapsulation layer includes a plurality of sub-inorganic encapsulation layers; at least two of the plurality of sub-inorganic encapsulation layers are adjacent and made of different materials; and at least two of the plurality of sub-inorganic encapsulation layers are adjacent and made of the same material.

34. The display substrate according to claim 33, wherein, In the direction away from the driving substrate, the refractive index of the plurality of sub-inorganic encapsulation layers first increases and then decreases.

35. The display substrate according to claim 33, wherein, In the direction away from the driving substrate, the thickness of the plurality of sub-inorganic encapsulation layers gradually decreases in the first direction.

36. The display substrate according to claim 33, wherein, Each of the aforementioned sub-inorganic encapsulation layers includes: alternating flat regions and double-arched spacer regions, a first arched region located on the side of the flat region away from the double-arched spacer region, a second arched region located between the flat region and the double-arched spacer region, and a third arched region located on the flat region away from the second arched region. The first arched area and the second arched area are arranged symmetrically about the center of the flat area.

37. The display substrate according to claim 36, wherein, The orthographic projections of the first arched region, the second arched region, or the third arched region on the driving substrate overlap with the orthographic projections of the protrusion on the driving substrate; the orthographic projections of the flat region on the driving substrate overlap with the orthographic projections of the main body on the driving substrate. The distance between the surface of the first arched region, the second arched region, or the third arched region away from the driving substrate and the driving substrate is greater than the distance between the surface of the flat region away from the driving substrate and the driving substrate.

38. The display substrate according to claim 36, wherein, The orthographic projection of the double-arched spacing region on the driving substrate overlaps with the orthographic projection of the spacing region between two adjacent anodes on the driving substrate.

39. The display substrate according to claim 36, wherein, The plurality of sub-inorganic encapsulation layers include: The first inorganic encapsulation layer is located on the side of the cathode layer away from the driving substrate; The second sub-inorganic packaging layer is located on the side of the first sub-inorganic packaging layer away from the driving substrate; The third sub-inorganic packaging layer is located on the side of the second sub-inorganic packaging layer away from the driving substrate; and The fourth sub-inorganic packaging layer is located on the side of the third sub-inorganic packaging layer away from the driving substrate.

40. The display substrate according to claim 39, wherein, The refractive index of the first sub-inorganic encapsulation layer is less than that of the second sub-inorganic encapsulation layer, and the refractive index of the fourth sub-inorganic encapsulation layer is less than that of the third sub-inorganic encapsulation layer.

41. The display substrate according to claim 40, wherein, The refractive index of the second sub-inorganic encapsulation layer is equal to that of the third sub-inorganic encapsulation layer.

42. The display substrate according to claim 39, wherein, The flat region of the first sub-inorganic encapsulation layer has a first width in the second direction, the flat region of the second sub-inorganic encapsulation layer has a second width in the second direction, the flat region of the third sub-inorganic encapsulation layer has a third width in the second direction, and the flat region of the fourth sub-inorganic encapsulation layer has a fourth width in the second direction. The first width is greater than the second width, the second width is greater than the third width, and the third width is greater than the fourth width.

43. The display substrate according to claim 39, wherein, The first angle between the first line connecting the edge of the flat region of the first sub-inorganic encapsulation layer near the edge of the second arched region, the edge of the flat region of the second sub-inorganic encapsulation layer near the edge of the second arched region, the edge of the flat region of the third sub-inorganic encapsulation layer near the edge of the second arched region, and the edge of the flat region of the fourth sub-inorganic encapsulation layer near the edge of the second arched region, and the surface of the driving substrate away from the anode layer is a first angle. The second included angle is defined as the angle between the second line connecting the apex of the second arched region of the first sub-inorganic encapsulation layer, the apex of the second arched region of the second sub-inorganic encapsulation layer, the apex of the second arched region of the third sub-inorganic encapsulation layer, and the apex of the second arched region of the fourth sub-inorganic encapsulation layer, and the surface of the driving substrate away from the anode layer. The first included angle is smaller than the second included angle.

44. The display substrate according to claim 43, wherein, The first included angle ranges from 60 to 85 degrees, and the second included angle ranges from 85 to 89 degrees.

45. The display substrate according to claim 43, wherein, The intersection of the first connection and the second connection is located within the drive substrate.

46. ​​The display substrate according to claim 45, wherein, The driving circuit includes: A semiconductor layer is located within the substrate; A first conductive layer is located on the semiconductor layer; The second conductive layer is located on the side of the first conductive layer away from the substrate; A third conductive layer is located on the side of the second conductive layer away from the substrate; and The fourth conductive layer is located on the side of the third conductive layer away from the substrate.

47. The display substrate according to claim 46, wherein, The intersection of the first and second lines is located between the upper surface of the third conductive layer away from the substrate and the anode layer.

48. The display substrate according to claim 46, wherein, The distance between the intersection of the first line and the second line and the vertex of the protrusion structure of the pixel definition layer away from the upper surface of the substrate is greater than the thickness of the first sub-inorganic encapsulation layer in the first direction.

49. The display substrate according to claim 46, wherein, The distance between the intersection of the first line and the second line and the vertex of the protrusion structure of the pixel defining layer away from the upper surface of the substrate is less than the sum of the thickness of the first sub-inorganic encapsulation layer in the first direction and the thickness of the second sub-inorganic encapsulation layer in the first direction.

50. The display substrate according to claim 46, wherein, The angle between the third line connecting the edge of the second arched region of the first sub-inorganic encapsulation layer near the edge of the double arched spacer region, the edge of the second arched region of the second sub-inorganic encapsulation layer near the edge of the double arched spacer region, the edge of the second arched region of the third sub-inorganic encapsulation layer near the edge of the double arched spacer region, and the edge of the second arched region of the fourth sub-inorganic encapsulation layer near the edge of the double arched spacer region, and the surface of the driving substrate away from the anode layer, is a third angle, and the third angle is smaller than the second angle.

51. The display substrate according to claim 50, wherein, The intersection of the first and third lines is located between the upper surface of the second conductive layer away from the substrate and the lower surface of the third conductive layer near the substrate.

52. The display substrate according to claim 50, wherein, The intersection of the second and third lines is located between the lower surface of the first conductive layer near the substrate and the lower surface of the substrate away from the first conductive layer.

53. The display substrate according to claim 50, wherein, The fourth angle between the fourth line connecting the edge of the third arched region of the first sub-inorganic encapsulation layer away from the double arched spacer region, the edge of the third arched region of the second sub-inorganic encapsulation layer away from the double arched spacer region, the edge of the third arched region of the third sub-inorganic encapsulation layer away from the double arched spacer region, and the edge of the third arched region of the fourth sub-inorganic encapsulation layer away from the double arched spacer region, and the surface of the driving substrate away from the anode layer, is a fourth angle, which is smaller than the second angle.

54. The display substrate according to claim 53, wherein, The intersection of the first line and the fourth line is located on the side of the substrate away from the first conductive layer.

55. The display substrate according to claim 53, wherein, The intersection of the third line and the fourth line is located on the side of the substrate away from the first conductive layer.

56. The display substrate according to claim 39, wherein, The first arched region of the first sub-inorganic encapsulation layer has a first radius of curvature away from the upper surface of the substrate; the first arched region of the second sub-inorganic encapsulation layer has a second radius of curvature away from the upper surface of the substrate; the first arched region of the third sub-inorganic encapsulation layer has a third radius of curvature away from the upper surface of the substrate; and the first arched region of the fourth sub-inorganic encapsulation layer has a fourth radius of curvature away from the upper surface of the substrate. The first radius of curvature is smaller than the second radius of curvature, the second radius of curvature is smaller than the third radius of curvature, and the third radius of curvature is smaller than the fourth radius of curvature.

57. The display substrate according to claim 56, wherein, The illusory center of the first arched region of the fourth sub-inorganic encapsulation layer is located between the upper surface of the first sub-inorganic encapsulation layer away from the substrate and the lower surface of the fourth sub-inorganic encapsulation layer near the substrate.

58. The display substrate according to claim 39, wherein, The first sub-inorganic encapsulation layer has a first thickness in the first direction, the second sub-inorganic encapsulation layer has a second thickness in the first direction, the third sub-inorganic encapsulation layer has a third thickness in the first direction, and the fourth sub-inorganic encapsulation layer has a fourth thickness in the first direction. The first thickness is greater than the second thickness, the second thickness is greater than the third thickness, and the third thickness is greater than the fourth thickness.

59. The display substrate according to claim 58, wherein, The ratio of the difference between the first thickness and the second thickness to the difference between the third thickness and the fourth thickness is in the range of 1.5 to 2 times.

60. The display substrate according to claim 58, wherein, The ratio of the sum of the second thickness and the third thickness to the first thickness is in the range of 0.8 - 1.

2.

61. The display substrate according to claim 58, wherein, The first thickness ranges from 1000 to 1200 nanometers, the second thickness ranges from 500 to 660 nanometers, the third thickness ranges from 480 to 560 nanometers, and the fourth thickness ranges from 180 to 260 nanometers.

62. The display substrate according to claim 61, wherein, The first sub-inorganic encapsulation layer is made of silicon oxide and silicon oxynitride, the second sub-inorganic encapsulation layer is made of silicon nitride, the third sub-inorganic encapsulation layer is made of silicon nitride, and the fourth sub-inorganic encapsulation layer is made of silicon oxide.

63. The display substrate according to claim 33, wherein, The encapsulation layer further includes: An organic encapsulation layer is located on the side of the inorganic encapsulation layer away from the driving substrate. The organic encapsulation layer includes a first region, a second region, and a third region, wherein the average thickness of the first region is less than the average thickness of the second region, and the average thickness of the second region is less than the average thickness of the third region.

64. A display substrate, comprising: A driving substrate, including a substrate and a driving circuit; The first planarization layer is located on the driving circuit; An anode layer is located on the side of the first planarization layer away from the driving substrate; A pixel defining layer is located on the side of the anode layer away from the driving substrate; A light-emitting functional layer is located on the side of the anode layer away from the driving substrate; A cathode layer is located on the side of the light-emitting functional layer away from the driving substrate; as well as An encapsulation layer is located on the side of the cathode layer away from the driving substrate; The driving circuit includes at least one transistor, the transistor including a semiconductor layer, the semiconductor layer being at least partially located within the substrate. The anode layer includes a plurality of anodes, and the display substrate includes a plurality of pixel openings located on the side of the plurality of anodes away from the driving substrate. The plurality of pixel openings are configured to at least overlap with the plurality of anodes. Each of the anodes includes a main body and a protrusion, the protrusion being connected to the main body. The size of the protrusion in a first direction is larger than the size of the main body in the first direction. The light-emitting functional layer includes multiple light-emitting portions, which are in contact with the main bodies of the multiple anodes. The display substrate further includes a color filter layer located on the side of the encapsulation layer away from the driving substrate. The color filter layer includes a first color filter, a second color filter, and a third color filter. The first color filter and the second color filter have a first overlap region, the second color filter and the third color filter have a second overlap region, and the third color filter and the first color filter have a third overlap region. The orthographic projections of the first overlapping region, the second overlapping region, and the third overlapping region on the driving substrate overlap with the orthographic projections of the spacing region between two adjacent anodes on the driving substrate. The orthographic projection of the pixel defining layer on the driving substrate overlaps with the orthographic projection of the protrusion on the driving substrate. The pixel defining layer includes a pixel defining portion, which includes: a pixel defining flat portion located between two adjacent anodes; and protrusion structures located on the side of the protrusion of each of the two adjacent anodes away from the driving substrate. The pixel defining flat portion connects the protrusion structures. Each of the protruding structures includes: a top surface; a first sidewall located on the side of the protruding structure near the center of the main body; and a second sidewall connecting the first sidewall and the top surface, wherein the second sidewall is further away from the driving substrate relative to the first sidewall; the slope angle of the first sidewall is greater than the slope angle of the second sidewall. Each of the aforementioned protrusion structures further includes: The third sidewall is located on the side of the protruding structure near the pixel-defined flat portion. Wherein, the slope angle of the first sidewall is α, the slope angle of the second sidewall is β, and the slope angle of the third sidewall is γ, and satisfies the following formula: β<γ<α, The protrusion of each anode includes a fourth sidewall located on the side of the protrusion near the center of the main body. Wherein, the slope angle of the fourth sidewall is δ, and satisfies the following formula: β < δ < α.

65. The display substrate according to claim 64, wherein, The orthographic projections of the first overlapping area, the second overlapping area, and the third overlapping area on the driving substrate overlap with the orthographic projection of the protrusion on the driving substrate.

66. The display substrate according to claim 64, wherein, The size of the first overlapping region in the second direction is greater than the size of the second overlapping region in the second direction, and the size of the second overlapping region in the second direction is greater than the size of the third overlapping region in the second direction.

67. The display substrate according to claim 66, wherein, The first overlapping region has a size range of 400-600 nanometers in the second direction, the second overlapping region has a size range of 250-350 nanometers in the second direction, and the third overlapping region has a size range of 100-200 nanometers in the second direction.

68. The display substrate according to claim 64, wherein, The average size of the first color filter in the first direction is greater than the average size of the second color filter in the first direction, and smaller than the average size of the third color filter in the first direction.

69. The display substrate according to claim 68, wherein, The first color filter has an average size ranging from 2.3 to 2.6 micrometers in the first direction, the second color filter has an average size ranging from 1.7 to 1.95 micrometers in the first direction, and the third color filter has an average size ranging from 2.3 to 2.7 micrometers in the first direction.

70. The display substrate according to claim 69, wherein, The ratio of the difference between the average size of the first color filter in the first direction and the average size of the second color filter in the first direction and the difference between the average size of the first color filter in the first direction and the average size of the third color filter in the first direction is in the range of 2-3.

71. The display substrate according to claim 68, wherein, The first color filter includes a first edge portion, a second edge portion, and a middle portion located between the first edge portion and the second edge portion. The average size of the middle portion in the first direction is smaller than the average size of the first edge portion in the first direction and the average size of the second edge portion in the first direction.

72. The display substrate according to claim 71, wherein, The first color filter includes a first contact surface that contacts the second color filter; the second color filter includes a second contact surface that contacts the third color filter; and the third color filter includes a third contact surface that contacts the first color filter. The dimension of the first contact surface in a first direction perpendicular to the driving substrate is equal to the dimension of the second contact surface in the first direction, and smaller than the dimension of the third contact surface in the first direction.

73. The display substrate according to claim 64, wherein, The distance between the first color filter and the surface of the driving substrate away from the anode layer is greater than the distance between the third color filter and the surface of the driving substrate away from the anode layer, and less than the distance between the second color filter and the surface of the driving substrate away from the anode layer.

74. The display substrate according to claim 64, wherein, The first color filter is a red filter, the second color filter is a green filter, and the third color filter is a blue filter.

75. The display substrate according to claim 64, wherein, The material of the color filter layer includes a desiccant.

76. The display substrate according to claim 64, wherein, The color filter layer includes aluminum.

77. The display substrate according to claim 64, further comprising: A protective layer is located on the side of the color filter layer away from the driving substrate.

78. The display substrate according to claim 64, wherein, The color filter layer further includes: The black matrix is ​​located between any two adjacent colors among the first, second, and third color filters.

79. The display substrate according to claim 64, further comprising: A glass cover plate is located on the side of the color filter layer away from the driving substrate.

80. A display substrate, comprising: A driving substrate, including a substrate and a driving circuit; The first planarization layer is located on the driving circuit; An anode layer is located on the side of the first planarization layer away from the driving substrate; A pixel defining layer is located on the side of the anode layer away from the driving substrate; A light-emitting functional layer is located on the side of the anode layer away from the driving substrate; A cathode layer is located on the side of the light-emitting functional layer away from the driving substrate; as well as An encapsulation layer is located on the side of the cathode layer away from the driving substrate; The driving circuit includes at least one transistor, the transistor including a semiconductor layer, the semiconductor layer being at least partially located within the substrate. The anode layer includes a plurality of anodes, and the display substrate includes a plurality of pixel openings located on the side of the plurality of anodes away from the driving substrate. The plurality of pixel openings are configured to at least overlap with the plurality of anodes. Each of the anodes includes a main body and a protrusion, the protrusion being connected to the main body. The size of the protrusion in a first direction is larger than the size of the main body in the first direction. The light-emitting functional layer includes multiple light-emitting portions, which are in contact with the main bodies of the multiple anodes. The driving circuit includes: A driving transistor includes a control electrode, a first electrode, and a second electrode; The first transistor includes a control electrode, a first electrode, and a second electrode; and The second transistor includes a control electrode, a first electrode, and a second electrode. In this configuration, the first terminal of the first transistor and the first terminal of the second transistor are connected to the control terminal of the driving transistor; the second terminals of the first transistor and the second transistor are configured to receive data signals; and the control terminals of the first transistor and the second transistor are configured to receive scan signals. The second terminal of the driving transistor is electrically connected to the anode and is configured to drive the light-emitting functional layer in contact with the anode to emit light. The orthographic projection of the pixel defining layer on the driving substrate overlaps with the orthographic projection of the protrusion on the driving substrate. The pixel defining layer includes a pixel defining portion, which includes: a pixel defining flat portion located between two adjacent anodes; and protrusion structures located on the side of the protrusion of each of the two adjacent anodes away from the driving substrate. The pixel defining flat portion connects the protrusion structures. Each of the protruding structures includes: a top surface; a first sidewall located on the side of the protruding structure near the center of the main body; and a second sidewall connecting the first sidewall and the top surface, wherein the second sidewall is further away from the driving substrate relative to the first sidewall; the slope angle of the first sidewall is greater than the slope angle of the second sidewall. Each of the aforementioned protrusion structures further includes: The third sidewall is located on the side of the protruding structure near the pixel-defined flat portion. Wherein, the slope angle of the first sidewall is α, the slope angle of the second sidewall is β, and the slope angle of the third sidewall is γ, and satisfies the following formula: β<γ<α, The protrusion of each anode includes a fourth sidewall located on the side of the protrusion near the center of the main body. Wherein, the slope angle of the fourth sidewall is δ, and satisfies the following formula: β < δ < α.

81. A display device comprising a display substrate according to any one of claims 1-80.

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