Voting system for rail transit data

Abstract

The application discloses a kind of rail transit data voting systems.Therein, the system includes: first CPU, for sending the first voting frame of rail transit data to first FPGA;First FPGA is connected with first CPU and second FPGA, for receiving the first voting frame from first CPU and the second voting frame from second CPU, generates first voting result according to first voting frame and second voting frame;Second CPU is connected with second FPGA, for sending the second voting frame of rail transit data to second FPGA;Second FPGA is connected with second CPU and first FPGA, for receiving the first voting frame from first CPU and the second voting frame from second CPU, generates second voting result according to first voting frame and second voting frame.By the application, the technical problem of low efficiency of CPU voting in the related art is solved, and the response timeliness and overall safety of the train control system are enhanced.

Description

Technical Field

[0001] This invention relates to the field of track control, and more specifically, to a voting system for rail transit data. Background Technology

[0002] In related technologies, in fields such as industrial control, aerospace, and rail transportation, redundancy design is usually used as a fault tolerance mechanism to ensure system safety and reliability. For example, in rail transportation scenarios, to meet the safety requirements of the control system, a two-out-of-two architecture is usually adopted in the hardware, that is, two systems, a primary system and a backup system. Each system adopts a two-out-of-two redundancy design. The system internally votes on key information. If the vote passes, the relevant operation is executed normally. If the vote fails, the system enters the fault management mode.

[0003] In complex redundant systems, the amount of data to be voted on may be enormous in order to ensure the efficient and secure operation of the system. At the same time, some data is very time-sensitive and needs to obtain voting results in a very short time. Therefore, the efficiency and reliability of the voting algorithm are the core of the system's security and stability.

[0004] Most train control system voting schemes in related technologies are based on dual-CPU (or multi-CPU) architectures. The dual CPUs are redundantly designed, simultaneously controlling and monitoring the train's operating status. During train operation, the two CPUs transmit received instructions or train operating status information to each other in real time and vote. If the vote passes, the relevant operation is executed; otherwise, a fault management mode is entered. Each CPU is responsible for almost all functions, including instruction parsing, train operation control, train operation information monitoring, data transmission, and data voting. Data exchange between the two CPUs is achieved via serial port, bus, or Ethernet. Because the CPU handles almost all functions, including instruction parsing, train operation control, train operation information monitoring, data transmission, and data voting, CRC (Cyclic Redundancy Checksum) or other encoding methods are often added during data transmission and voting to meet system security requirements. These functions and algorithms significantly consume CPU performance, thus reducing the overall system performance. In certain emergency situations, train control systems have high real-time requirements, and factors such as instruction execution efficiency and data voting efficiency directly affect the safety of the train control system. The internal structure of a CPU is complex, especially when running an operating system. The execution time of each instruction is uncertain. Encoding, transmitting, verifying, and voting on large data streams makes the execution time even more difficult to control, making it difficult to assess time-sensitive security factors.

[0005] No effective solutions have yet been found to address the aforementioned problems in the relevant technologies. Summary of the Invention

[0006] This invention provides a voting system for rail transit data.

[0007] According to one aspect of the embodiments of this application, a voting system for rail transit data is provided. The system includes: a first CPU, configured to send a first voting frame of rail transit data to a first FPGA; a first FPGA, connected to the first CPU and a second FPGA, configured to receive the first voting frame from the first CPU and a second voting frame from the second CPU, and generate a first voting result based on the first voting frame and the second voting frame; a second CPU, connected to a second FPGA, configured to send a second voting frame of rail transit data to the second FPGA; and a second FPGA, connected to the second CPU and the first FPGA, configured to receive the first voting frame from the first CPU and the second voting frame from the second CPU, and generate a second voting result based on the first voting frame and the second voting frame.

[0008] Furthermore, the first FPGA includes: a transmission interface connected to the first CPU, used to send a first voting frame transmitted by the first CPU to an ID management module; the ID management module, connected to the transmission interface, a reliable transmission module, and a voting algorithm module, used to configure an ID number for the first voting frame and input the configured first voting frame to the reliable transmission module and the voting algorithm module; the reliable transmission module, connected to the second FPGA, used to output the first voting frame to the second FPGA, receive a second voting frame transmitted from the second CPU by the second FPGA, and transmit the second voting frame to the voting algorithm module; the voting algorithm module generates a first voting result based on the first voting frame and the second voting frame.

[0009] Furthermore, the first FPGA also includes: a voting result caching module, connected to the voting algorithm module, for receiving the first voting result output by the voting algorithm module and storing the first voting result; and a local area network port, connected to the voting result caching module, for redundantly outputting the first voting result to an external port.

[0010] Furthermore, the voting algorithm module is also used to: determine whether the ID numbers of the first voting frame and the second voting frame are the same; if the ID numbers of the first voting frame and the second voting frame are the same, vote on the first voting frame and the second voting frame based on a preset voting algorithm; if the vote passes, generate a first voting result based on the first voting frame or the second voting frame; if the vote fails, generate an error flag frame and determine the error flag frame as the first voting result.

[0011] Furthermore, the voting algorithm module is also used to: determine whether the first voting frame is encoded data; if the first voting frame is encoded data, decode and verify the first voting frame; if the verification fails, determine that the vote has failed, and generate a first voting result to characterize the encoding error.

[0012] Furthermore, the first CPU is also configured to read voting information from the first FPGA, wherein the voting information includes: the number of frames that have been voted on by the first FPGA, the voting result of the voting frame, and the reason for the voting failure.

[0013] Furthermore, the first CPU is also configured to: before sending the first voting frame to the first FPGA, query whether the first FPGA has a free ID number; if the first FPGA has a free ID number, determine to send the first voting frame to the first FPGA; if the first FPGA does not have a free ID number, refuse to send the first voting frame to the first FPGA.

[0014] Furthermore, the system also includes an AND logic module connected to the first FPGA and the second FPGA. The first FPGA further includes a first control output module for transmitting the first voting result of the first FPGA to the AND logic module. The second FPGA further includes a second control output module for transmitting the second voting result of the second FPGA to the AND logic module. The AND logic module is used to perform a logical AND operation on the first voting result and the second voting result. When both the first voting result and the second voting result are successful voting results, a valid control signal is output based on the first voting result and the second voting result.

[0015] Furthermore, the AND logic module is also used to: determine whether the first voting frame and the second voting frame are voting frames of a specified type; if the first voting frame and the second voting frame are voting frames of a specified type, generate an emergency control signal when the first voting result or the second voting result is a voting error.

[0016] Furthermore, the system also includes: a third CPU, which is a backup CPU for the first CPU; a third FPGA, which is a backup FPGA for the first FPGA, and maintains hot standby synchronization with the working state of the first FPGA in standby mode; a fourth CPU, which is a backup CPU for the second CPU; and a fourth FPGA, which is a backup FPGA for the second FPGA, and maintains hot standby synchronization with the working state of the second FPGA in standby mode.

[0017] According to another aspect of the embodiments of this application, a storage medium is also provided, the storage medium including a stored program that executes the steps in the above system when the program is run.

[0018] According to another aspect of the embodiments of this application, an electronic device is also provided, including a processor, a communication interface, a memory, and a communication bus, wherein the processor, the communication interface, and the memory communicate with each other through the communication bus; wherein: the memory is used to store computer programs; and the processor is used to execute the steps in the above system by running the programs stored in the memory.

[0019] This application also provides a computer program product containing instructions that, when run on a computer, cause the computer to perform the steps in the above-described system.

[0020] This invention comprises dual CPUs and dual FPGAs. A first CPU sends a first voting frame of rail transit data to a first FPGA. A first FPGA, connected to both the first and second CPUs, receives the first voting frame from the first CPU and a second voting frame from the second CPU, and generates a first voting result based on the first and second voting frames. A second CPU, connected to the second FPGA, sends a second voting frame of rail transit data to the second FPGA. The second FPGA, connected to both the second and first CPUs, receives the first voting frame from the first CPU and the second voting frame from the second CPU, and generates a second voting result based on the first and second voting frames. The CPU only needs to send the voting frames to the corresponding FPGA; the complex voting process and algorithm are completed by the FPGA. This significantly alleviates the system's performance requirements on the CPU, thereby improving the overall system performance and solving the technical problem of low CPU voting efficiency in related technologies. Compared to the CPU, the FPGA's superior parallel computing capabilities and precise time control enable more efficient implementation of the voting algorithm, improving voting efficiency, voting speed, and enhancing the response time and overall safety of the train control system. Attached Figure Description

[0021] The accompanying drawings, which are included to provide a further understanding of the invention and form part of this application, illustrate exemplary embodiments of the invention and, together with their description, serve to explain the invention and do not constitute an undue limitation thereof. In the drawings:

[0022] Figure 1 This is a structural diagram of a voting system for rail transit data according to an embodiment of the present invention;

[0023] Figure 2 This is a schematic diagram of the voting system under the two-out-of-two architecture of Embodiment 2 of the present invention. Detailed Implementation

[0024] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present application, and not all of them. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present application. It should be noted that, unless otherwise specified, the embodiments and features in the embodiments of the present application can be combined with each other.

[0025] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0026] As used below, the term "module" can refer to a combination of software and / or hardware that performs a predetermined function. Although the apparatus described in the following embodiments is preferably implemented in software, implementation in hardware, or a combination of software and hardware, is also possible and contemplated.

[0027] Example 1

[0028] This embodiment provides a voting system for rail transit data. Figure 1 This is a structural diagram of a voting system for rail transit data according to an embodiment of the present invention, which can be applied to voting scenarios in train control systems, such as... Figure 1 As shown, the system includes:

[0029] The first CPU 10 is used to send the first voting frame of rail transit data to the first FPGA (Field Programmable Gate Array).

[0030] The data to be voted on in the system is transmitted from the CPU to the FPGA in frames. The data to be voted on can be business data (such as train running direction, train running station, system time, etc.) and control signals (such as acceleration, deceleration, braking, etc.).

[0031] The first FPGA12 is connected to the first CPU and the second FPGA, and is used to receive a first voting frame from the first CPU and a second voting frame from the second CPU, and generate a first voting result based on the first voting frame and the second voting frame.

[0032] FPGA takes on some of the CPU's computation and data transmission tasks, thus alleviating the system's performance requirements on the CPU.

[0033] The second CPU14, connected to the second FPGA, is used to send the second voting frame of rail transit data to the second FPGA;

[0034] The second FPGA16, connected to the second CPU and the first FPGA, is used to receive a first voting frame from the first CPU and a second voting frame from the second CPU, and to generate a second voting result based on the first voting frame and the second voting frame.

[0035] The system described above includes dual CPUs and dual FPGAs. The first CPU sends a first voting frame of rail transit data to the first FPGA. The first FPGA, connected to both the first and second CPUs, receives the first voting frame from the first CPU and a second voting frame from the second CPU, and generates a first voting result based on the first and second voting frames. The second CPU, connected to the second FPGA, sends a second voting frame of rail transit data to the second FPGA. The second FPGA, connected to both the second and first CPUs, receives the first voting frame from the first CPU and the second voting frame from the second CPU, and generates a second voting result based on the first and second voting frames. The CPU only needs to send the voting frames to the corresponding FPGA; the complex voting process and algorithm are handled by the FPGA. This significantly alleviates the system's performance requirements on the CPU, thereby improving the overall system performance and solving the technical problem of low CPU voting efficiency in related technologies. Compared to the CPU, the FPGA's superior parallel computing capabilities and precise time control enable more efficient implementation of the voting algorithm, improving voting efficiency, thus increasing voting speed and enhancing the response time and overall safety of the train control system.

[0036] In this embodiment, the system further includes: a third CPU, which is a backup CPU for the first CPU; a third FPGA, which is a backup FPGA for the first FPGA, and maintains hot standby synchronization with the working state of the first FPGA when in standby mode; a fourth CPU, which is a backup CPU for the second CPU; and a fourth FPGA, which is a backup FPGA for the second FPGA, and maintains hot standby synchronization with the working state of the second FPGA when in standby mode.

[0037] Figure 2 This is a schematic diagram of a voting system under a two-out-of-two architecture according to an embodiment of the present invention. The voting system under this architecture consists of a primary system and a backup system. The primary and backup systems are identical in hardware structure, both employing a two-out-of-two redundancy design. The primary system includes: CPU_0 (first CPU), CPU_1 (second CPU), FPGA_0 (first FPGA), FPGA_1 (second FPGA), and logic modules, etc. Correspondingly, the backup system includes: CPU_2 (third CPU), CPU_3 (fourth CPU), FPGA_2 (third FPGA), FPGA_3 (fourth FPGA), and logic modules, etc. Within the same system, two FPGAs interact with each other through an isolation channel, forming an FPGA voting module. Data synchronization between the FPGA voting modules in the two systems is achieved through a local area network. During normal operation, the primary system is in working state, and the backup system is in hot standby state. When the primary system fails, the backup system immediately replaces the primary system, performing a primary-backup switchover.

[0038] Taking FPGA_0 as an example, it includes: PORT_0 (transmission interface), LAN_0, LAN_1, LAN_2, and LAN_3. Among them, LAN_2 and LAN_3 are responsible for synchronizing with the backup system, ensuring that the backup system maintains the same working state as the primary system. When the primary system fails for any reason, the backup system can seamlessly replace the primary system. PORT_0 between CPU_0 and FPGA can be a local area network, an external bus, an internal bus, or other forms of transmission link, and can include interrupt signals; LAN_0, LAN_1, LAN_2, and LAN_3 can be local area networks of any protocol.

[0039] In this embodiment, the first FPGA and the second FPGA have the same functional structure. The first FPGA will be used as an example for explanation. In one implementation of this embodiment, the first FPGA includes: a transmission interface connected to a first CPU, used to send a first voting frame transmitted by the first CPU to an ID management module; an ID management module connected to the transmission interface, a reliable transmission module, and a voting algorithm module, used to configure an ID number for the first voting frame and input the configured first voting frame to the reliable transmission module and the voting algorithm module; a reliable transmission module connected to the second FPGA, used to output the first voting frame to the second FPGA and receive a second voting frame transmitted from the second CPU by the second FPGA, and transmit the second voting frame to the voting algorithm module; and a voting algorithm module that generates a first voting result based on the first and second voting frames.

[0040] Optionally, the first FPGA also includes: a voting result cache module, connected to the voting algorithm module, for receiving the first voting result output by the voting algorithm module and storing the first voting result; and a local area network port, connected to the voting result cache module, for redundantly outputting the first voting result to an external port.

[0041] In this embodiment, the first CPU is CPU_0, the second CPU is CPU_1, the first FPGA is FPGA_0, and the second FPGA is FPGA_1. CPU_0 / CPU_1 sends the voting frame that needs to be voted to the ID management module through the interface PORT_0 / PORT_1. The ID management module will attach an ID number to the frame. The voting frame with the added ID number is simultaneously input to the reliable transmission module and the voting algorithm module. The reliable transmission module outputs the frame to the counterpart FPGA. The voting algorithm module votes on the voting frames from the ID management module and the reliable transmission module and outputs the voting result to the voting result buffer module. The voting result will be redundantly output through LAN_0 and LAN_1.

[0042] The reliable transmission module is used to realize data interaction between FPGAs. This module can be a serial port transmission of the HDLC protocol, or other protocol interfaces that can realize reliable transmission (with error control and flow control capabilities).

[0043] In one example, the voting algorithm module is also used to: determine whether the ID numbers of the first voting frame and the second voting frame are the same; if the ID numbers of the first voting frame and the second voting frame are the same, vote on the first voting frame and the second voting frame based on the preset voting algorithm; if the vote passes, generate a first voting result based on the first voting frame or the second voting frame; if the vote fails, generate an error flag frame and determine the error flag frame as the first voting result.

[0044] The voting algorithm module votes on two frames of data with the same ID number. This module uses different voting algorithms depending on the type of the voting frame. For example, for voting on the train's direction of travel, they must be completely identical for the vote to pass; for voting on the train's speed, a speed difference within a certain range is sufficient for a pass. If the vote passes, the voting frame is output to the voting result buffer module and then redundantly output through LAN_0 and LAN_1. If the vote fails, an error flag frame is output, indicating relevant information about the voted frame, including but not limited to its ID number, length, and the reason for the vote failure.

[0045] In some scenarios, the voting algorithm module is also used to: determine whether the first voting frame is encoded data; if the first voting frame is encoded data, decode and verify the first voting frame; if the verification fails, determine that the vote has failed, and generate a first voting result to characterize the encoding error.

[0046] The voting frame output from the CPU to the FPGA can be CRC-encoded or other encoded data. If the voting frame contains CRC encoding or other encoding, the voting algorithm module will first verify it. If the verification fails, the voting result for the corresponding ID will definitely fail, and the output voting result will indicate that the voting failure was due to an incorrect voting frame encoding. The output voting result can also be CRC-encoded or other encoded. The voting algorithm module will encode the voting result before outputting it to the voting result buffer module.

[0047] In this embodiment, the first CPU is further configured to read voting information from the first FPGA, wherein the voting information includes: the number of frames that the first FPGA has voted on, the voting result of the voting frame, and the reason for the voting failure.

[0048] The first CPU can read voting information through PORT_0. This voting information includes, but is not limited to, the number of frames voted on by the FPGA, whether the vote was successful, and the reason for any vote failure. This enables information exchange and feedback between the CPU and the FPGA.

[0049] Optionally, the first CPU is further configured to: before sending the first voting frame to the first FPGA, query whether the first FPGA has a free ID number; if the first FPGA has a free ID number, determine to send the first voting frame to the first FPGA; if the first FPGA does not have a free ID number, refuse to send the first voting frame to the first FPGA.

[0050] Before sending a voting frame, the first CPU should check if there are any available IDs via the PORT_0 interface. Only when there are available IDs can the voting frame be sent, thus ensuring the voting speed. The IDs are managed by the ID management module and are used to identify different voting frames. This allows multiple voting frames to be voted on independently without causing confusion.

[0051] In some implementation scenarios of this embodiment, the system further includes an AND logic module connected to the first FPGA and the second FPGA. The first FPGA further includes a first control output module for transmitting the first voting result of the first FPGA to the AND logic module. The second FPGA further includes a second control output module for transmitting the second voting result of the second FPGA to the AND logic module. The AND logic module is used to perform a logical AND operation on the first voting result and the second voting result. When both the first voting result and the second voting result are successful voting results, a valid control signal is output based on the first voting result and the second voting result.

[0052] In the voting scenario of train motion control, the voting module participates in the train's operation control. The first CPU / second CPU sends control commands to the first FPGA / second FPGA in the form of voting frames. When the vote passes, the control output module outputs a control signal to the AND logic module. The AND logic module performs a logical AND operation on the control signal; that is, a valid external control signal is output only when both control signals are valid. If one or both FPGAs fail to vote, a valid external control signal will not be output due to the protection function of the AND logic module. The control signal output by the control output module can be high or low level, pulses of different widths, PWM (Pulse Width Modulation) waves of different frequencies, or other types of signals.

[0053] Optionally, the AND logic module is further configured to: determine whether the first voting frame and the second voting frame are voting frames of a specified type; if the first voting frame and the second voting frame are voting frames of a specified type, generate an emergency control signal when the first voting result or the second voting result is a voting error.

[0054] When a voting error occurs in a specific type of voting frame, the external control module will also output a specific control signal to enable emergency handling of the train, such as emergency braking or shutting off a power source.

[0055] The solution in this embodiment provides a method for implementing data voting between two CPUs using an FPGA in the two-out-of-two architecture of the train control system.

[0056] The solution in this embodiment uses an FPGA to implement data voting between multiple CPUs. The CPU only needs to send the voting frame to the FPGA, and the complex voting process and voting algorithm are completed by the FPGA, which greatly alleviates the system's performance requirements on the CPU, thereby improving the overall performance of the system. Compared with the CPU, the FPGA's excellent parallel computing capabilities and precise time control capabilities can implement the voting algorithm more efficiently, improve the voting efficiency, and enhance the overall safety of the train control system.

[0057] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods according to the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) and includes several instructions to cause a terminal device (which may be a mobile phone, computer, server, or network device, etc.) to execute the methods described in the various embodiments of the present invention.

[0058] It should be noted that the above modules can be implemented by software or hardware. For the latter, they can be implemented in the following ways, but are not limited to: all the above modules are located in the same processor; or, the above modules are located in different processors in any combination.

[0059] In the several embodiments provided in this application, it should be understood that the disclosed technical content can be implemented in other ways. The device embodiments described above are merely illustrative; for example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the displayed or discussed mutual coupling, direct coupling, or communication connection may be through some interfaces; the indirect coupling or communication connection between units or modules may be electrical or other forms.

[0060] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0061] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0062] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as a USB flash drive, read-only memory (ROM), random access memory (RAM), portable hard drive, magnetic disk, or optical disk.

[0063] The above description is only a preferred embodiment of this application. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the principle of this application, and these improvements and modifications should also be considered within the scope of protection of this application.

Claims

1. A voting system for rail transit data, characterized in that, The system includes: The first CPU is used to send the first voting frame of rail transit data to the first FPGA; A first FPGA, connected to the first CPU and the second FPGA, is used to receive a first voting frame from the first CPU and a second voting frame from the second CPU, and to generate a first voting result based on the first voting frame and the second voting frame. The second CPU, connected to the second FPGA, is used to send the second voting frame of rail transit data to the second FPGA; The second FPGA, connected to the second CPU and the first FPGA, is used to receive a first voting frame from the first CPU and a second voting frame from the second CPU, and to generate a second voting result based on the first voting frame and the second voting frame. The first FPGA includes: a transmission interface connected to the first CPU, used to send a first voting frame transmitted by the first CPU to an ID management module; the ID management module, connected to the transmission interface, a reliable transmission module, and a voting algorithm module, used to configure an ID number for the first voting frame and input the configured first voting frame to the reliable transmission module and the voting algorithm module; the reliable transmission module, connected to the second FPGA, used to output the first voting frame to the second FPGA and receive a second voting frame transmitted from the second CPU by the second FPGA, and transmit the second voting frame to the voting algorithm module; the voting algorithm module generates a first voting result based on the first voting frame and the second voting frame. The system further includes an AND logic module connected to the first FPGA and the second FPGA. The first FPGA further includes a first control output module for transmitting the first voting result of the first FPGA to the AND logic module. The second FPGA further includes a second control output module for transmitting the second voting result of the second FPGA to the AND logic module. The AND logic module is used to perform a logical AND operation on the first voting result and the second voting result. When both the first voting result and the second voting result are successful voting results, a valid control signal is output based on the first voting result and the second voting result.

2. The system according to claim 1, characterized in that, The first FPGA also includes: A voting result caching module, connected to the voting algorithm module, is used to receive the first voting result output by the voting algorithm module and store the first voting result; The local area network port is connected to the voting result caching module and is used to redundantly output the first voting result to an external port.

3. The system according to claim 1, characterized in that, The voting algorithm module is also used for: Determine whether the ID numbers of the first voting frame and the second voting frame are the same; if the ID numbers of the first voting frame and the second voting frame are the same, vote on the first voting frame and the second voting frame based on a preset voting algorithm; If the vote passes, a first voting result is generated based on the first voting frame or the second voting frame. If the vote fails, an error flag frame is generated and the error flag frame is determined as the first voting result.

4. The system according to claim 3, characterized in that, The voting algorithm module is also used for: Determine whether the first voting frame is encoded data; if the first voting frame is encoded data, decode and verify the first voting frame; if the verification fails, determine that the vote has failed, and generate a first voting result to characterize the encoding error.

5. The system according to claim 1, characterized in that, The first CPU is further configured to read voting information from the first FPGA, wherein the voting information includes: the number of frames that have been voted on by the first FPGA, the voting result of the voting frame, and the reason for the voting failure.

6. The system according to claim 1, characterized in that, The first CPU is also used for: Before sending the first voting frame to the first FPGA, check if the first FPGA has a free ID number; if the first FPGA has a free ID number, determine to send the first voting frame to the first FPGA; if the first FPGA does not have a free ID number, refuse to send the first voting frame to the first FPGA.

7. The system according to claim 1, characterized in that, The logic module is further configured to: determine whether the first voting frame and the second voting frame are voting frames of a specified type; if the first voting frame and the second voting frame are voting frames of a specified type, generate an emergency control signal when the first voting result or the second voting result is a voting error.

8. The system according to claim 1, characterized in that, The system also includes: The third CPU is a backup CPU for the first CPU; The third FPGA is a backup FPGA for the first FPGA. In the standby state, it maintains hot standby synchronization with the working state of the first FPGA. The fourth CPU is a backup CPU for the second CPU; The fourth FPGA is a backup FPGA for the second FPGA. In standby mode, it maintains hot standby synchronization with the working state of the second FPGA.

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