FPGA-based digital array radar beam forming system

Abstract

This invention discloses an FPGA-based digital array radar beamforming system, relating to the field of radar signal processing technology. The system includes a data preprocessing module, a data copying and forwarding module, a parameter configuration module, and a beamforming processing module. The data preprocessing module parses and times-aligns the received data packets. The data copying and forwarding module copies the preprocessed data multiple times and distributes it to the various computational sub-chains of the beamforming processing module. The user configures the beamforming weight vector parameters through the host computer of the parameter configuration module. The beamforming processing module adopts a parallel link structure, with each sub-chain employing a pipelined processing structure to simultaneously perform multi-beam calculations and integrate and store the processing results. This system uses an FPGA as the core processing chip and designs a novel parallel processing architecture to achieve real-time beamforming of massive radar data under large-scale digital arrays, offering advantages such as high processing speed, high flexibility, and high scalability.

Description

Technical Field

[0001] This invention relates to the field of radar signal processing technology, and to a digital array radar signal processing system, particularly a radar beamforming system using an FPGA (Field Programmable Gate Array) as the core processing chip. Background Technology

[0002] Traditional radar systems typically employ mechanical or electronic scanning techniques to acquire target information. However, these traditional scanning methods have limitations, such as slow scanning speed, poor real-time target tracking, and limited target identification accuracy. Furthermore, traditional radar systems often require large mechanical components, resulting in bulky equipment and high maintenance costs.

[0003] To overcome the shortcomings of traditional radar systems, digital array radar systems have gradually attracted widespread attention in recent years. Digital array radar systems utilize an array of multiple antenna elements, and by weighting and phase-modulating the signals from each antenna element, they can control the direction of the target, thereby achieving faster and more accurate target detection and tracking.

[0004] Despite the immense potential of digital array radar systems for target detection and tracking, several challenges remain. One of these is the effective processing and analysis of massive amounts of radar echo data. For large-scale digital arrays, the volume of echo sampling data is enormous, and real-time beamforming places high demands on the system's processing power, especially when multiple beams need to be formed. CPUs, due to their architectural limitations, are unsuitable for processing large-scale data. While GPUs can process large-scale data in parallel, their high power consumption makes them unsuitable for power-sensitive scenarios. Existing technologies include some FPGA-based beamforming solutions, but none can achieve real-time processing of radar echo data from large-scale digital arrays. Therefore, research and solutions are needed to address the problem of real-time beamforming of massive radar data from large-scale arrays. Summary of the Invention

[0005] To overcome the problems of poor real-time performance and insufficient flexibility in beamforming of large amounts of radar data in large-scale digital array applications, this invention provides an FPGA-based digital array radar beamforming system. Using an FPGA as the core processing chip, a new parallel processing architecture is designed to perform beamforming processing on digital array radar data, and the processing flow is optimized. The processing results are output to a DDR memory, enabling real-time beamforming of massive radar data in large-scale digital array applications while providing high flexibility.

[0006] The present invention provides an FPGA-based digital array radar beamforming system, comprising a data preprocessing module, a data copying and forwarding module, a parameter configuration module, and a beamforming processing module.

[0007] The data preprocessing module is used to receive UDP (User Datagram Protocol) data packets sent by the radar antenna unit through the fiber optic network interface, parse the UDP data packets, determine whether packet loss has occurred, and if packet loss has occurred, zero-padding is performed on the lost data. The received radar echo signal data is time-aligned according to the sampling points and then output to the data copy and forwarding module.

[0008] The data copying and forwarding module is used to copy the preprocessed data output by the data preprocessing module and distribute it to each computation sub-chain within the beamforming processing module for parallel processing. In the case of multiple FPGA boards cascading, the data copying and forwarding module sends the copied data to each computation sub-chain on each FPGA according to the IP address and port number of each FPGA, thus achieving multi-board cascading processing.

[0009] The parameter configuration module is configured by the host computer via the PCIe controller, setting the beamforming weight vector parameters and sending them to the beamforming processing module. The parameter configuration module includes the host computer, the PCIe controller, the up_axi module, and RAM. The user configures the beamforming weight vector parameters and system parameters of the beamforming processing module via the host computer. System parameters include data transmission parameters and the framework parameters of the beamforming processing module. The framework parameters of the beamforming processing module include the number of cascaded FPGA boards, the number of computational subchains, the connection routing relationships between computational subchains, and the number of computing nodes in each computational subchain.

[0010] The beamforming processing module is used for conventional beamforming of the acquired data. The beamforming processing employs a parallel link structure, with each link using a pipelined processing structure. This pipelined structure contains multiple computing nodes, each forming a different beam. Multiple computing nodes within each link can simultaneously form multiple beams. The number of parallel links in the beamforming processing module can be configured via a host computer, according to the system parameter settings in the parameter configuration module.

[0011] The beneficial effects of this invention are as follows: This invention realizes a digital array radar beamforming system based on FPGA, which has the advantages of fast processing speed, high flexibility and high scalability; the beamforming parameters and system architecture can be configured flexibly through the host computer via PCIe; the beamforming processing module adopts a parallel chain processing structure and each chain adopts a pipeline processing structure, which improves the computing speed and meets the real-time requirements; in addition, the system is easy to expand, and the data forwarding module can realize high-bandwidth data communication between multiple boards, thereby realizing multi-board cascade processing, which greatly enhances the system scalability. Attached Figure Description

[0012] Figure 1 This is a block diagram of the FPGA-based digital array radar beamforming system of the present invention;

[0013] Figure 2 This is a structural diagram of the data preprocessing module of the present invention;

[0014] Figure 3 This is a structural diagram of the parameter configuration module of the present invention;

[0015] Figure 4 This is a structural diagram of the PCIE bus module of the present invention;

[0016] Figure 5 This is a structural diagram of an operational subchain in the beamforming processing module of the present invention. Detailed Implementation

[0017] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the embodiments and accompanying drawings.

[0018] For large-scale digital array applications, this invention provides an FPGA-based digital array radar beamforming system. By designing a novel parallel processing architecture, the processing flow is optimized. This architecture features multiple computational subchains, which can be cascaded across multiple FPGA chips via the FPGA's on-chip bus and external network to form a larger-scale processing system. Parallel processing significantly improves processing speed, meeting the requirements for real-time beamforming of large amounts of radar data and accommodating system upgrade and expansion needs. The functions of each computational subchain and the connection routing between them can be configured via a host computer using PCIe. This allows for flexible configuration of the beamforming module architecture, including the number of computational subchains and computing nodes.

[0019] This invention provides an FPGA-based digital array radar beamforming system, with an implementation framework as follows: Figure 1 As shown, it includes a data preprocessing module, a data replication and forwarding module, a parameter configuration module, and a beamforming processing module.

[0020] like Figure 2 As shown, the data preprocessing module includes a custom protocol parsing module, a multi-channel data alignment unit, and an AXIData mover module. The data preprocessing module aggregates multi-channel echo data. The FPGA receives data packets through a 100G fiber optic network interface and then sends the data packets to the custom protocol parsing module. The custom protocol parsing module performs custom protocol parsing, extracts the parameters contained in the data packet header and data frame header, and passes the parameters to the multi-channel data alignment unit. The multi-channel data alignment unit has the capability for precise alignment of multi-channel signal data and can control the time alignment of multiple unit radar echo signal data sampling points according to the parameters extracted by the custom protocol parsing unit. Since the echo sampling data is sent and received via the UDP protocol, which is a connectionless protocol, data packet loss may occur during data transmission. Therefore, the data preprocessing module of this invention determines whether packet loss has occurred based on the packet header information and performs zero-padding operation on the lost data. The data preprocessing module outputs the time-aligned multi-channel radar echo data to the data copying and forwarding module. Figure 2 As shown, RAM, CrossBar, and AddressCompute belong to the multi-channel data alignment unit. RAM is used to store parsed data. CrossBar aligns the sampling points of the data based on relevant parsed data such as timestamps, and determines whether packet loss has occurred based on the parsed frame header and frame tail data, and performs zero-padding operation. AddressCompute is used to calculate the storage address, which is provided by this module when RAM stores data. By setting the AXIData mover module, the bus protocol conversion is realized, converting the AXI4-Stream protocol to the AXI4-Full protocol. The radar echo signal data after sampling point alignment is input into FIFO for temporary storage, and then output to the AXIData mover module for protocol conversion, and then stored in a RAM for sending to the data copy and forwarding module.

[0021] The data copying and forwarding module acts as a route during data aggregation. Within the system, it can directly forward data, copying multiple copies of the data output from the data preprocessing module and sending them to the beamforming processing module. The beamforming processing module contains multiple chain-like processing structures, allowing each link to process data in parallel, thus increasing processing speed. Furthermore, the data copying and forwarding module can also send data to other FPGA boards, enabling cascaded processing across multiple boards. Based on data transmission parameters, including the IP address and port number of the target FPGA or terminal, the data copying and forwarding module forwards the copied data. When the beamforming processing module involves multiple cascaded FPGA boards, it sends the copied data to the respective computational sub-chains on each FPGA based on their IP address and port number. In this embodiment, the data copying and forwarding module copies the data multiple times and stores it in a FIFO for data buffering before inputting it into the computational sub-chains of the beamforming processing module.

[0022] like Figure 3 As shown, the parameter configuration module consists of a host computer, a PCIe (High-Speed ​​Serial Computer Expansion Bus) controller, an up_axi module, and two RAM chips. The PCIe bus interface comprises a host computer and an FPGA, with the PCIe controller implemented on the FPGA, as detailed below. Figure 4 As shown. In the parameter configuration module, the user configures and stores the beamforming weight vector parameters via the PCIe interface through the host computer, and also sets the parameters of each module in the system. The system parameters set include data transmission parameters, the number of cascaded FPGA boards in the beamforming processing module, the number of operation subchains, the connection routing relationship between operation subchains, the number of computing nodes in each operation subchain, and the function of each operation subchain, etc. The host computer configures the beamforming parameters through the PCIe bus interface; the up_axi module is used to transfer data between the PCIe controller and the beamforming processing module, which operate under different clocks, and to parse the system parameters configured by the user; two RAMs are used to store the beamforming weight vector parameters. In addition, the host computer can also use PCIe to set the system workflow in software. Figure 1 The DBF weight coefficient update in this context refers to receiving and storing the updated beamforming weight vector parameters from the host computer.

[0023] like Figure 4 As shown, the PCIe bus interface is mainly divided into two parts: the software part serving as the host computer and the hardware logic part of the FPGA, which respectively correspond to... Figure 3The system consists of a host computer and a PCIe controller. The host computer can be further divided into a control program and a driver program. The control program controls the communication between the host computer and the FPGA and handles the interaction of specific data, while the driver program mainly drives the PCIe interface to achieve data interaction with the FPGA. Users set system parameters and the architecture of the beamforming processing module, beamforming weight vector parameters, etc., through the host computer and send them to the PCIe controller. The FPGA part mainly uses the DMA module to configure the system control register and processing control register, and interacts with RAM to achieve data exchange. The system control register is used to configure the parameters of each module, including: for the 100G fiber optic data receiving module, the system control register is used to configure the local IP address, MAC address, and port, and control data transmission and reception; for the data copying and forwarding module, the system control register can control the switching of the module's working mode and configure the corresponding target FPGA or terminal IP address and port number; in the data preprocessing module, the system control register can configure parameters and modify the protocol content of user-defined protocols, control under what circumstances certain data frames will be discarded, and filter and intercept data for subsequent processing and calculation. The processing control register is used to store the configuration beamforming weight vector parameters, as well as the framework parameters for controlling and configuring the beamforming processing module, including the number of cascaded FPGA boards, the number of operation subchains, the connection routing relationship between operation subchains, the number of computing nodes in each subchain, and the function of each operation subchain.

[0024] The beamforming processing module contains multiple beamforming operation subchains, such as Figure 5 As shown, each computational subchain includes multiple computing nodes. The number of computing nodes can be configured via a host computer. Each computing node has different beamforming weight vector parameters, and each computing node forms different beams for a set of echo data input into the computational subchain. The computational subchain adopts a pipelined processing structure. The preprocessed data entering the subchain is copied multiple times and distributed to multiple computing nodes within the chain. Parallel processing between computing nodes can simultaneously form multiple beams, greatly accelerating the calculation speed. Since the digital array radar system uses multiple antenna elements to form subarrays, the entire array surface forms multiple different subarrays. For the sampling data of different subarrays at the same time, the computing nodes adopt a cyclic addition structure. That is, after processing the data of each subarray, the processing result is temporarily stored, and then the processing of the next subarray data continues. Finally, the results are added until all subarray sampling data at the same time has been processed. Figure 5 As shown, each computing node contains a FIFO. The radar echo sampling data is multiplied by the weight vector parameters and then superimposed to form a beam. Each computing node processes the radar echo sampling data of one subarray and stores it in the FIFO. The processing results of the subarray are added in the FIFO until the radar echo sampling data of all subarrays at the same time have been processed. Figure 5 The data integration module in each sub-chain concatenates the output results of all computing nodes and stores the resulting integrated result in DDR.

[0025] In one implementation of the system of the present invention, the data preprocessing module, the data copying and forwarding module, and the PCIe controller are mounted on the same FPGA board; the beamforming processing module comprises one or more cascaded FPGA boards. Each FPGA board has a data forwarding module, enabling high-bandwidth data communication between multiple boards.

[0026] The FPGA-based digital array radar beamforming system of this invention operates as follows: First, the user configures the beamforming weight vector parameters using a host computer. Different beams have different weight vector parameters, which are stored in the RAM of the parameter configuration module and read from the RAM during beamforming calculations. The sampling data from the radar front end is sent to the system via a 100G optical port in the form of UDP packets. The system's data preprocessing module parses the UDP packets and performs operations such as data sampling point alignment and zero-padding for lost packets. After preprocessing, the data copying and distribution module copies the preprocessed data multiple times and distributes it to the computational sub-chains in the beamforming computation module. Then, the beamforming computation module reads the beamforming weight vector parameters from the RAM of the parameter configuration module. Each computational sub-chain adopts a pipelined processing structure, containing multiple computation nodes, ultimately completing the beamforming calculation. After the calculation, the data from multiple computational sub-chains are integrated and stored in DDR memory.

[0027] The FPGA-based digital array radar beamforming system of the present invention has excellent scalability; since each FPGA board has a data forwarding module, high-bandwidth data communication between multiple boards can be realized, thereby enabling multi-board cascading processing.

[0028] The FPGA-based digital array radar beamforming system of the present invention has high flexibility; the system can be defined by a host computer user, and the number of beams can be configured by configuring the number of computational subchains of the beamforming processing module and the number of computing nodes within the subchains.

[0029] The FPGA-based digital array radar beamforming system of the present invention utilizes the high data throughput and high parallelism of FPGA to realize the aggregation and beamforming processing of echo data from digital array radar antenna elements in hardware. In addition, based on the reconfigurability and massive computing resources of FPGA, the system also has flexible programmability and strong processing capabilities.

[0030] While specific embodiments of the present invention have been described above, those skilled in the art should understand that the specific embodiments described are merely illustrative and not intended to limit the scope of the present invention. Equivalent modifications and variations made by those skilled in the art in accordance with the spirit of the present invention should be covered within the scope of protection of the claims of the present invention.

Claims

1. An FPGA-based digital array radar beamforming system, characterized by, The system includes a data preprocessing module, a data replication and forwarding module, a parameter configuration module, and a beamforming processing module; The data preprocessing module receives UDP data packets sent by the radar antenna unit through the fiber optic network interface, parses the UDP data packets, performs zero-padding on lost data, aligns the received radar echo signal data according to the sampling points in time, and outputs it to the data copy and forwarding module. The data copying and forwarding module copies the input data and distributes it to each operation sub-chain within the beamforming processing module according to the data transmission parameters; the data transmission parameters include the IP address and port number of the target FPGA or terminal. The parameter configuration module includes a host computer and a PCIe controller. The user configures the beamforming weight vector parameters and system parameters through the host computer, and the host computer sends the beamforming weight vector parameters to the beamforming processing module through the PCIe controller. The system parameters include data transmission parameters and the framework parameters of the beamforming processing module. The framework parameters of the beamforming processing module include the number of cascaded FPGA boards, the number of computation subchains, the connection routing relationship between computation subchains, and the number of computing nodes in each computation subchain. The beamforming processing module is configured with a parallel sub-chain structure. Each sub-chain employs a pipelined processing structure, which contains multiple computing nodes, each forming a different beam. The structure of the beamforming processing module is set according to the system parameters in the parameter configuration module. Each sub-chain contains multiple computing nodes, each with different beamforming weight vector parameters. The sub-chain copies the received data and sends it to each computing node. Each computing node contains a FIFO. The beam is formed by multiplying the radar echo sampling data with the beamforming weight vector parameters and then superimposing the results. After processing the data of one subarray of a radar system array antenna, the processing result is added to the result stored in the FIFO, and the FIFO is updated. This process is repeated until the data of all subarrays at the same time has been processed. FPGA stands for Field Programmable Gate Array, UDP stands for User Datagram Protocol, and PCIe stands for High Speed ​​Serial Computer Expansion Bus Standard.

2. The FPGA-based digital array radar beamforming system according to claim 1, characterized in that, The data preprocessing module includes a custom protocol parsing module, a multi-channel data alignment unit, and an AXI Data mover module; The custom protocol parsing module parses the received UDP packets, extracts the parameters contained in the packet header and frame header, and passes them to the multiplex data alignment unit. The multi-channel data alignment unit determines whether packet loss has occurred based on the packet header, performs zero-padding on the lost data, and performs time alignment of the multi-channel radar echo signal data according to the sampling points based on the received parameters; the AXI Data mover module implements bus protocol conversion, and outputs the time-aligned multi-channel radar echo data to the data copy and forwarding module after protocol conversion.

3. The FPGA-based digital array radar beamforming system according to claim 1, characterized in that, The parameter configuration module also includes an up_axi module and RAM; the up_axi module is used for cross-clock domain data transfer between the PCIe controller and the beamforming processing module, and also parses the system parameters configured by the user.

4. A FPGA-based digital array radar beamforming system according to claim 1 or 2, characterized in that, The PCIe controller receives user-configured system parameters and beamforming weight vector parameters from the host computer. The PCIe controller includes a system control register and a processing control register. The system control register stores system parameters including: the IP address, MAC address, and port of the fiber optic data receiving module, as well as control data transmission and reception; the operating mode conversion and data transmission parameters of the data copying and forwarding module; the parameters and protocol content of the user-defined protocol in the data preprocessing module; and the processing control register stores beamforming weight vector parameters and the framework parameters of the beamforming processing module.

5. The FPGA-based digital array radar beamforming system according to claim 1, characterized in that, The data copying and forwarding module obtains data transmission parameters from the parameter configuration module. When multiple FPGA boards are cascaded, the data copying and forwarding module sends the copied data to each operation subchain on each FPGA according to the IP address and port number of each FPGA.

6. The FPGA-based digital array radar beamforming system according to claim 1, characterized in that, The data preprocessing module, data copy and forwarding module, and PCIe controller are mounted on the same FPGA board; the beamforming processing module includes one or more cascaded FPGA boards.

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