Method for identification and measurement of overlay error in a photolithography process

Abstract

The application discloses a kind of identification and measurement method of overlay error in photoetching process.The novel overlay error identification in the application is composed of two parts of front layer and current layer, and the overlay error identification of front layer and current layer is all center-symmetric figure relative to the same center point, and the overlay error identification of front layer and current layer is staggered arrangement;The overlay error identification includes four units of center symmetry, and each unit includes three parts of identification sub-element: identification sub-element is composed of different density line group or line, and the spacing between different sub-elements is also different.Due to the different anti-interference of different identification sub-element to process factor, therefore, when measuring overlay error, different identification sub-element can be selected for measurement according to the damage condition of overlay error identification.The novel overlay error identification used in the application enhances the anti-interference and utilization rate of overlay error identification, and saves cutting path space.

Description

Technical Field

[0001] This invention belongs to the field of photolithography technology and relates to a method for marking and measuring overlay errors in photolithography. Background Technology

[0002] In semiconductor manufacturing, photolithography is a crucial technology for pattern transfer. A chip requires the fabrication of many layers, and proper alignment between these layers is essential for its proper functioning. Otherwise, product performance will fail, and production yield will decrease. Overlay error refers to the offset between two layers on a wafer. It confirms whether the photoresist pattern of the current layer accurately covers the circuit pattern of the previous layer and is a vital parameter describing the overlay accuracy between the current and reference layers.

[0003] Therefore, during chip fabrication, the overlay performance of each layer needs to be characterized after each photolithography step. Ideally, the two patterns are perfectly aligned, with zero overlay error. However, in actual chip manufacturing, due to various reasons, the overlay error cannot be zero. When the overlay error is too large, it will affect the circuitry and electrical performance matching of the device, leading to a decrease in production yield.

[0004] Overlay stability is a critical performance indicator for product performance and manufacturing, and is key to improving process capabilities and increasing process windows. Based on experience in semiconductor manufacturing, overlay error should generally be less than 20%–30% of the critical dimension. However, as semiconductor manufacturing nodes continue to shrink, this poses a significant challenge to both overlay error measurement instruments and methods.

[0005] For overlay detection, there are currently two main measurement techniques on the market: image-based overlay (IBO) and diffraction-based overlay (DBO).

[0006] Existing IBO technology obtains images of overlay measurement marks on two layers of the wafer inside the measurement stage, then analyzes the grayscale of the mark images to determine the center of the measurement mark images, and thus obtains the relative displacement between the two layers. In this method, the quality of the overlay error mark and the clarity of the overlay error mark image have a significant impact on the overlay measurement results.

[0007] Several factors affect the clarity of the overlay error mark image: ① Impurity particles: Impurity particles are generated during the entire production process. The generation of these particles is unavoidable. If these particles are located on the overlay error mark, causing localized damage, it will directly affect the measurement of the overlay error, or even make it impossible to measure the overlay error (e.g., ...). Figure 2 ② Unstable process parameters: For AIM markers (Advanced Image Metrology markers) with narrow-pitch lines, their morphology is easily affected by unstable process parameters, such as lithography energy and focus, baking time, baking temperature, etc. Their process window is small, and changes in process conditions may cause AIM markers to be damaged, bridging between internal lines, blurring of images, and inability to perform measurements.

[0008] In actual production, impurity particles may be introduced under different processes and environments, making complete avoidance impossible. Furthermore, changes in machine performance and actual manufacturing conditions can alter the process window, affecting the marking of overlay errors. The inability to completely resolve both the impurity particle problem and the instability of process parameters means that these two influencing factors cannot be avoided.

[0009] Most existing IBO technologies use three typical overlay error marking methods: Box-in-Box, Bar-in-Bar (BIB), and Advanced Image Metrology (AIM).

[0010] Because the aforementioned unavoidable factors can cause overlay error markers to break and become ineffective, multiple types of markers are used in actual production for overlay alignment between two layers. When one type of overlay error marker breaks, another type is used for remeasurement, a cumbersome and time-consuming process. Furthermore, using multiple types of overlay error markers for measuring overlay errors between two layers wastes dicing space. With the continuous advancement of integrated circuit manufacturing processes, linewidths are decreasing, and semiconductor device areas are shrinking, resulting in less space for dicing on photomasks. Placing too many overlay error measurement markers occupies significant layout design space. The space occupied by overlay error markers forces the abandonment of some test patterns on the photomask, resulting in wasted space.

[0011] Based on the above, this invention proposes a novel overlay error marking method, which aims to identify and measure overlay errors that are resistant to external interference. This marking and measurement method can save cutting track space. Summary of the Invention

[0012] The purpose of this invention is to address the technical problems of existing IBO technology being severely affected by external factors and wasting cutting space in actual production, and to propose a new method for identifying and measuring overlay errors.

[0013] In a first aspect, the present invention provides a method for identifying and measuring overlay errors in a photolithography process, comprising the following steps:

[0014] Step S1: Place the overlay error markers in the corresponding mask cutting paths of the previous layer and the current layer respectively; wherein the overlay error markers of the previous layer and the current layer are both centrally symmetrical with respect to the same center point, and the overlay error markers of the previous layer and the current layer are staggered.

[0015] The overlay error marking includes four centrally symmetrical units, each unit comprising three marking sub-elements: the first marking sub-element includes multiple parallel lines with a spacing of a and a length of d1; the second marking sub-element includes multiple parallel lines with a spacing of b and a length of d2; the third marking sub-element includes a line with a length of d3; d1>0, d2>0, d3>0;

[0016] The distance between the first identifier sub-element and the second identifier sub-element is b;

[0017] The third identifier sub-element is close to the first identifier sub-element or the second identifier sub-element, and its distance from the adjacent identifier sub-element is c; c>b>0, c>a>0, b≠a;

[0018] Step S2: Place the mask corresponding to the previous layer processed in step S1 into a photolithography machine for exposure, and then perform at least etching, deposition, and chemical mechanical polishing on the exposed wafer; place the mask corresponding to the current layer processed in step S1 into a photolithography machine for exposure and development;

[0019] Step S3: Perform overlay error measurement on the wafer processed in step S2. Specifically: 3-1 Determine whether the overlay error mark of the current layer and the previous layer is damaged. If it is damaged, proceed to step 3-2; otherwise, proceed to step 3-3.

[0020] The standard for whether the overlay error mark is damaged is as follows: if the overlay error marks of the previous layer and the current layer are complete, the image is clear and there are no particles or impurities, then the overlay error mark is considered to be undamaged; otherwise, the overlay error mark is considered to be damaged.

[0021] 3-2 Determine whether the first identifier sub-element of the marking error indicator for the previous layer and the current layer is damaged. If the first identifier sub-element is damaged, proceed to step 3-3; if the first identifier sub-element is not damaged, use the first identifier sub-element to measure the overlay error.

[0022] 3-3 Continue to determine whether the second identifier sub-element of the previous layer and the current layer is damaged. If the second identifier sub-element is damaged, proceed to step 3-4; if the second identifier sub-element is not damaged, use the second identifier sub-element to measure the overlay error.

[0023] 3-4 Continue to determine whether the third identifier sub-element of the previous layer and the current layer is damaged. If the third identifier sub-element is damaged, it is considered that the current overlay error mark is unusable; if the third identifier sub-element is not damaged, the overlay error is measured using the third identifier sub-element.

[0024] Secondly, the present invention provides an overlay error indicator, comprising:

[0025] The four units are centrally symmetrical. Each unit includes three identification sub-elements: the first identification sub-element includes multiple parallel lines with a spacing of a and a length of d1; the second identification sub-element includes multiple parallel lines with a spacing of b and a length of d2; and the third identification sub-element includes a line with a length of d3.

[0026] The distance between the first identifier sub-element and the second identifier sub-element is b;

[0027] The third identifier sub-element is close to the first identifier sub-element or the second identifier sub-element, and its distance from the adjacent identifier sub-element is c; c>b, c>a, b≠a.

[0028] Thirdly, the present invention provides a chip manufacturing process, including the method for identifying and measuring overlay errors.

[0029] Fourthly, the present invention provides a real-time monitoring and feedback control process for chip manufacturing, which measures the overlay error in real time through the identification and measurement method of the overlay error, and provides timely feedback and adjusts the chip manufacturing process parameters.

[0030] Fifthly, the present invention provides a computer-readable storage medium having a computer program stored thereon, which, when executed in a computer, causes the computer to perform the method for identifying and measuring overlay errors.

[0031] In a sixth aspect, the present invention provides a computing device, including a memory and a processor, wherein the memory stores executable code, and when the processor executes the executable code, it implements the method for identifying and measuring overlay errors.

[0032] The beneficial effects of this invention are:

[0033] This invention proposes a novel overprinting error marker. By using lines of different densities inside the marker, the resistance to external interference of the overprinting error marker is enhanced. This allows the overprinting error marker to be measured using marker sub-elements in different locations under different damage conditions. Ultimately, this improves the process window and utilization rate of the overprinting error, and also reduces the number of overprinting error markers that need to be placed, saving space in the cutting channel. Attached Figure Description

[0034] Figure 1 The existing classic overlay error markings are: a) Box-in-Box marking; b) Bar-in-Bar marking (BIB); c) Advanced Image Metrology marking (AIM).

[0035] Figure 2 This is a schematic diagram of an AIM mark with impurity particles on its surface.

[0036] Figure 3 This is a normal BIB identifier.

[0037] Figure 4 The images are of AIM tags, where a: normal AIM tags; b and c: damaged AIM tags.

[0038] Figure 5 This is a schematic diagram of the layout of the engraving error markings in the corresponding mask cutting channels of the front and current layers of the present invention, according to Embodiment 1.

[0039] Figure 6 This is a schematic diagram of the engraving error marking in Embodiment 1 of the present invention.

[0040] Figure 7 This is a schematic diagram of the engraving error marking and measurement method according to Embodiment 1 of the present invention.

[0041] Figure 8 This is a schematic diagram of the engraving error marking in Embodiment 2 of the present invention. Detailed Implementation

[0042] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0043] Furthermore, the technical features involved in the various embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0044] Figure 1Three classic overlay error markers are used: a) Box-in-Box, b) Bar-in-Bar (BIB), and c) Advanced Image Metrology (AIM). In the BIB, the outer black lines represent the current layer's fabrication, while the inner gray lines represent the previous layer's fabrication. After the chip fabrication yields both patterns, the IBO acquires images of the overlay error markers and analyzes their grayscale levels to determine the centers of the current and current layer's overlay error markers. The deviation between these centers yields the relative displacement (i.e., overlay error) between the two wafer layers. The AIM marker, composed of a series of equidistant lines, exhibits a higher signal-to-noise ratio compared to the other two markers.

[0045] Figure 2 This is a schematic diagram showing impurity particles generated during the manufacturing process located on the overlay error mark. At this time, the overlay error is partially damaged, making the image of the overlay error mark unclear, which in turn affects the measurement of the overlay error.

[0046] Figure 3 For two normal BIB marking images in actual manufacturing, after the measuring machine acquires the marking images, it measures the deviation of the center of the inner and outer frame positions, and then obtains the overlay error between the two corresponding layers.

[0047] Figure 4 Images of normal and damaged AIM markers are shown. Image a is a normal AIM marker, while images b and c are AIM markers damaged due to the manufacturing process. It can be seen that in a normal AIM marker, the lines are clearly defined and the image is sharp. However, in a damaged AIM marker, the lines are bridged, making it impossible to determine the marker's center from the image, thus leading to overprinting errors.

[0048] Example 1: Figure 7 A method for identifying and measuring overlay errors in photolithography is provided, comprising the following steps:

[0049] Step S1: Place the overlay error markers in the corresponding mask cutting paths of the previous and current layers, respectively; whereby... Figure 5 Both the overlay error markings for the previous and current layers are centrally symmetrical about the same center point, and each marking is divided into four quadrants. The specific distribution of the new markings is illustrated by excerpting the lower right quadrant (e.g., ...). Figure 6 The overlay error indicators for the previous layer and the current layer are set separately.

[0050] The overlay error markings in the front layer consist of four centrally symmetrical units, each unit comprising three marking sub-elements: the first marking sub-element 1-1 includes three parallel lines with a spacing of 0.7 micrometers, a length of 5.75 micrometers, and a width of 1.1 micrometers; the second marking sub-element 1-2 includes three parallel lines with a spacing of 1.4 micrometers, a length of 5.75 micrometers, and a width of 1.1 micrometers; the third marking sub-element 1-3 includes a line with a length of 12.5 micrometers and a width of 1.1 micrometers; the second marking sub-elements 1-2 and the third marking sub-elements 1-3 are respectively distributed on both sides of the first marking sub-elements 1-1, with a distance of 1.4 micrometers between the second marking sub-elements 1-2 and the first marking sub-elements 1-1; and a distance of 2.1 micrometers between the third marking sub-elements 1-3 and the first marking sub-elements 1-1; the third marking sub-elements 1-3 is located closer to the center point.

[0051] The overlay error marking of the current layer includes four centrally symmetrical units. Each unit includes three marking sub-elements: the first marking sub-element 2-1 of the current layer includes three parallel lines with a spacing of 0.7 micrometers, a length of 5.75 micrometers, and a width of 1.1 micrometers; the second marking sub-element 2-2 of the current layer includes three parallel lines with a spacing of 1.4 micrometers, a length of 5.75 micrometers, and a width of 1.1 micrometers; the third marking sub-element 2-3 of the current layer includes a line with a length of 12.5 micrometers and a width of 1.1 micrometers. The second marking sub-elements 2-1 and the third marking sub-elements 2-3 of the current layer are respectively distributed on both sides of the first marking sub-elements 2-2 of the current layer, with a distance of 1.4 micrometers between the second marking sub-elements 2-2 and the first marking sub-elements 2-1 of the current layer; and a distance of 2.1 micrometers between the third marking sub-elements 2-3 and the first marking sub-elements 2-2 of the current layer. The third marking sub-elements 2-3 of the current layer is far from the center point.

[0052] The first identifier sub-element 1-1, the second identifier sub-element 1-2, the first identifier sub-element 2-1, and the second identifier sub-element 2-2 of the current layer are all located between the third identifier sub-element 1-3 of the previous layer and the third identifier sub-element 2-3 of the current layer. The lines of the first identifier sub-element 1-1, the second identifier sub-element 1-2, the third identifier sub-element 1-3, the first identifier sub-element 2-1, the second identifier sub-element 2-2, and the third identifier sub-element 2-3 of the current layer are arranged in parallel.

[0053] The first identifier sub-element 1-1 of the previous layer and the first identifier sub-element 2-1 of the current layer are symmetrically arranged and are 1 micrometer apart. The second identifier sub-element 1-2 of the previous layer and the second identifier sub-element 2-2 of the current layer are symmetrically arranged and are 1 micrometer apart.

[0054] Step S2: Place the mask corresponding to the previous layer processed in step S1 into a photolithography machine for exposure, and then perform at least etching, deposition, and chemical mechanical polishing on the exposed wafer; place the mask corresponding to the current layer processed in step S1 into a photolithography machine for exposure and development;

[0055] Step S3: Perform overlay error measurement on the wafer processed in step S2. Specifically: 3-1 Send the wafer processed in S2 into the KLA Archer 300 overlay error measurement machine for overlay error measurement.

[0056] 3-2 Determine whether the overlay error mark in the current layer and the previous layer is damaged. If the previous layer or the current layer is damaged, proceed to step 3-3; otherwise, proceed to step 3-4.

[0057] The standard for whether the overlay error mark is damaged is as follows: if the overlay error mark of the previous or current layer is complete, the image is clear and there are no particles or impurities, then the overlay error mark is considered to be undamaged; otherwise, the overlay error mark is considered to be damaged.

[0058] 3-3 Determine if the first marking sub-element for marking the error between the current and previous layers is damaged. Since the first sub-element has the smallest internal line spacing among the three sub-elements of the current and previous layers, it is most prone to damage during processing. If the first marking sub-element is damaged, proceed to step 3-4; if the first marking sub-element is not damaged, use the first marking sub-element to measure the overlay error.

[0059] 3-4 Continue to determine whether the second identifier sub-element of the current layer and the previous layer is damaged. The second sub-element of the previous layer and the current layer is composed of line groups, and the spacing between the lines inside is larger than that of the first sub-element, making it less susceptible to damage; the third sub-element is an isolated line with a larger spacing from other parts, making the second sub-element more susceptible to damage than the third sub-element. If the second identifier sub-element is damaged, proceed to step 3-5; if the second identifier sub-element is not damaged, use the second identifier sub-element to measure the overprinting error;

[0060] 3-5 Continue to determine whether the third identifier sub-element of the current layer and the previous layer is damaged. The third sub-element is composed of a single line and is far away from other sub-elements, making it the least likely to be damaged. If the third identifier sub-element is damaged, the current overprinting error indicator is considered unusable; if the third identifier sub-element is not damaged, the overprinting error is measured using the third identifier sub-element.

[0061] Example 2:

[0062] Based on Example 1, the only difference is the setting of the overlay error indicator:

[0063] In the overlay error marking, the first marking sub-element 1-1 of the front layer is close to the center point, and the first marking sub-element 1-1 and the third marking sub-element 1-3 of the front layer are located on both sides of the second marking sub-element 1-2 of the front layer, respectively.

[0064] In the current layer overlay error marking, the first marking sub-element 2-1 of the current layer is close to the center point, and the first marking sub-element 2-1 and the third marking sub-element 2-3 of the current layer are located on both sides of the second marking sub-element 2-2 of the current layer, respectively;

[0065] The current layer overlay error indicator is located outside the previous layer overlay error indicator.

[0066] The first identifier sub-element 1-1 of the previous layer is symmetrically arranged with respect to the first identifier sub-element 2-1 of the current layer, and there is a distance of 1 micrometer between them. The second identifier sub-element 1-2 of the previous layer is symmetrically arranged with respect to the second identifier sub-element 2-2 of the current layer, and there is a distance of 1 micrometer between them. The third identifier sub-element 1-3 of the previous layer is symmetrically arranged with respect to the third identifier sub-element 2-3 of the current layer, and there is a distance of 1 micrometer between them.

[0067] In the above description, the technical details of the patterning, etching, etc., of each layer are not described in detail. However, those skilled in the art should understand that layers, regions, etc., of the desired shape can be formed by various technical means. Furthermore, in order to form the same structure, those skilled in the art can also design methods that are not entirely the same as those described above. Additionally, although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination. Moreover, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first," "second," or "third" may explicitly or implicitly include at least one of that feature. In the description of this disclosure, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0068] The embodiments of this disclosure have been described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of this disclosure. The scope of this disclosure is defined by the appended claims and their equivalents. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of this disclosure, and all such substitutions and modifications should fall within the scope of this disclosure.

Claims

1. A method for measuring overlay error in photolithography, characterized in that... The method includes the following steps: Step S1: Place the overlay error markers in the corresponding mask cutting paths of the previous layer and the current layer respectively; wherein the overlay error markers in the previous layer and the current layer are both centrally symmetrical with respect to the same center point, and the overlay error markers in the previous layer and the current layer are staggered. The overlay error marking includes four centrally symmetrical units, each unit comprising three marking sub-elements: the first marking sub-element includes multiple parallel lines with a spacing of a and a length of d1; the second marking sub-element includes multiple parallel lines with a spacing of b and a length of d2; and the third marking sub-element includes a line with a length of d3. The distance between the first identifier sub-element and the second identifier sub-element is b; The third identifier sub-element is close to the first identifier sub-element or the second identifier sub-element, and its distance from the adjacent identifier sub-element is c; c>b, c>a, b≠a; Step S2: Place the mask corresponding to the previous layer processed in step S1 into a photolithography machine for exposure, and then perform at least etching, deposition, and chemical mechanical polishing on the exposed wafer; place the mask corresponding to the current layer processed in step S1 into a photolithography machine for exposure and development; Step S3: Measure the overlay error of the wafer processed in step S2; specifically: 3-1 Check whether the overlay error mark is damaged for the current layer and the previous layer one by one. If it is damaged, proceed to step 3-2; otherwise, proceed to step 3-3. The standard for whether the overprinting error mark is damaged is as follows: if the overprinting error mark is intact, the image is clear and there are no particles or impurities, the overprinting error mark is considered to be undamaged; otherwise, the overprinting error mark is considered to be damaged. 3-2 Determine whether the first marking sub-element of the marking error is damaged. If the first marking sub-element is damaged, proceed to step 3-3; if the first marking sub-element is not damaged, use the first marking sub-element to measure the marking error. 3-3 Continue to determine whether the second identifier sub-element is damaged. If the second identifier sub-element is damaged, proceed to step 3-4; if the second identifier sub-element is not damaged, use the second identifier sub-element to measure the overlay error. 3-4 Continue to determine whether the third identification sub-element is damaged. If the third identification sub-element is damaged, it is considered that the current overlay error mark cannot be used; if the third identification sub-element is not damaged, the overlay error is measured using the third identification sub-element.

2. A real-time monitoring and feedback control process for chip manufacturing, characterized in that... The method described in claim 1 is used to measure overlay error in real time, and to provide timely feedback and adjust chip manufacturing process parameters.

3. A computer-readable storage medium having a computer program stored thereon, which, when executed in a computer, causes the computer to perform the method of claim 1.

4. A computing device, comprising a memory and a processor, wherein the memory stores executable code, and the processor, when executing the executable code, implements the method of claim 1.

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