A full-chip photolithography negative development simulation method

Abstract

The present application relates to simulation method technical field, especially relates to a kind of full-chip photoetching negative development simulation method, comprising the following steps: constructing initial level set function, and according to the initial material distribution function of negative development photoresist distribution determination;Set design optimization target and contour constraint, construct Lagrange function according to the design optimization target and the contour constraint of initial grid, and determine update strategy;Provide the contour element consisting of several calibration elements and calculate the sensitivity parameter of each contour element for design optimization target variation degree;According to the update speed of each point determined according to sensitivity parameter, update level set function, and update material distribution function and Lagrange function according to the updated level set function;Convergence analysis is carried out to sensitivity parameter, if convergence, optimization ends, if not convergence, iteration is carried out to the position of constructing Lagrange function according to design optimization target and contour constraint, and determining update strategy.The method provided by the present application can improve precision.

Description

[Technical Field]

[0001] This invention relates to the field of simulation method technology, and in particular to a full-chip photolithography negative development simulation method. [Background Technology]

[0002] Existing simulated negative development techniques require re-optimization of model parameters when the material of the developing film layer or the developer solution changes, resulting in insufficient robustness, low stability and reliability, and increased difficulty in mass production. This invention designs a method based on topological connectivity, providing a full-chip computational lithography negative development simulation method. This method can accurately describe the topological relationship between the portion lost due to thermal shrinkage during negative development and the original mask, improving the speed and accuracy of full-chip modeling. [Summary of the Invention]

[0003] To address the issue that the accuracy of simulated negative development technology is affected by the material of the developing film layer, resulting in insufficient robustness, this invention provides a full-chip photolithography negative development simulation method.

[0004] To solve the above-mentioned technical problems, this invention provides the following technical solution: a full-chip photolithography negative development simulation method, comprising the following steps: constructing an initial level set function based on the mask shape, and determining an initial material distribution function based on the negative development photoresist distribution; setting a design optimization objective and contour constraints, constructing an initial Lagrangian function based on the design optimization objective and the contour constraints, and determining an update strategy based on the contour constraints; providing contour elements composed of several calibration elements and calculating the sensitivity parameters of each contour element to the degree of change of the design optimization objective; determining the update rate of each point based on the sensitivity parameters, updating the level set function, and updating the material distribution function and Lagrangian function based on the updated level set function; performing convergence analysis on the sensitivity parameters; if converged, the optimization ends; if not converged, iterate until the position of constructing the Lagrangian function based on the design optimization objective and the contour constraints and determining the update strategy is reached.

[0005] Preferably, the sensitive parameters include topological sensitivity and elemental sensitivity.

[0006] Preferably, obtaining the topological sensitivity of each contour element includes: selecting a calibration element among the contour elements as a target calibration element, and obtaining a first Lagrangian function through the target calibration element; adding an infinitesimal space, and obtaining a second Lagrangian function at the infinitesimal space; and calculating the topological sensitivity of the target calibration element based on the first Lagrangian function and the second Lagrangian function.

[0007] Preferably, obtaining the element sensitivity of each contour element includes: providing a calibration element among the contour elements as a target element and as a first input value to obtain a first design objective function; selecting at least one calibration element among the contour elements that is different from the calibration element in the first input value and adding it to the target element, adding it to the first input value to obtain a second input value, and obtaining a second design objective function; and obtaining the element sensitivity of the target calibration element based on the difference between the first design objective function and the second design objective function.

[0008] Preferably, the phase of an element is calculated using the wavelength of the light source, and the level set function is updated based on the topological sensitivity and the phase of the element.

[0009] Preferably, the convergence analysis of the sensitive parameters includes performing convergence analysis on element sensitivity and topology sensitivity respectively. If both element sensitivity and topology sensitivity converge, the optimization ends.

[0010] Preferably, if either the element sensitivity or the topology sensitivity fails to converge, the iteration continues until the Lagrangian function is constructed based on the design optimization objective and the contour constraints.

[0011] Preferably, the element sensitivity parameters are first subjected to convergence analysis. If the element sensitivity parameters converge, then the topological sensitivity analysis is performed.

[0012] To solve the above-mentioned technical problems, the present invention provides another technical solution as follows: a storage medium for storing a full-chip photolithography negative development simulation method.

[0013] To solve the above-mentioned technical problems, the present invention provides another technical solution as follows: a lithography machine, which establishes a model through a full-chip lithography negative development simulation method and performs lithography on the entire chip.

[0014] Compared with existing technologies, the full-chip photolithography negative development simulation method provided by this invention has the following beneficial effects:

[0015] 1. This invention provides a full-chip photolithography negative development simulation method, comprising the following steps: constructing an initial level set function based on the mask shape, and determining an initial material distribution function based on the negative development photoresist distribution; setting design optimization objectives and contour constraints, constructing an initial Lagrangian function based on the design optimization objectives and contour constraints, and determining an update strategy based on the contour constraints; providing contour elements composed of several calibration elements and calculating the sensitivity parameters of each contour element to the degree of change of the design optimization objectives; determining the update rate of each point based on the sensitivity parameters, updating the level set function, and updating the material distribution function and Lagrangian function based on the updated level set function; performing convergence analysis on the sensitivity parameters; if converged, the optimization ends; if not converged, iterates until the position of constructing the Lagrangian function based on the design optimization objectives and contour constraints and determining the update strategy is determined. Based on topological connectivity considerations, by describing the interrelationships between elements on the mask, the mutual influence between shape contours during the development process can be accurately described, and the topological relationship between the part lost due to thermal shrinkage during negative development and the original mask can be accurately described, achieving targeted recovery, eliminating the influence of developer density, greatly improving model robustness, and adapting to large-scale mass production.

[0016] 2. The present invention provides a full-chip photolithography negative development simulation method, wherein the sensitive parameters include topology sensitivity and element sensitivity, which are used to describe the degree of change of the calibrated elements relative to the design optimization target.

[0017] 3. The present invention provides a full-chip photolithography negative development simulation method, wherein obtaining the topological sensitivity of each contour element includes: selecting a calibration element among the contour elements as a target calibration element, and obtaining a first Lagrangian function through the target calibration element; adding an infinitesimal space, and obtaining a second Lagrangian function at the infinitesimal space; calculating the topological sensitivity of the target calibration element based on the first and second Lagrangian functions. Topological sensitivity (topo) s It is used to measure the degree of change of the objective function at the target calibration element when an infinitesimal space is added, and to reflect the topological relationship between each contour element. It is used to compensate for the part of the mask lost in the thermal shrinkage effect.

[0018] 4. The present invention provides a full-chip photolithography negative development simulation method, which obtains the element sensitivity of each contour element by: providing a calibration element among the contour elements as a target element and as a first input value to obtain a first design objective function; selecting at least one calibration element among the contour elements that is different from the calibration element in the first input value and adding it to the target element, adding it to the first input value to obtain a second input value, and obtaining a second design objective function; and obtaining the element sensitivity of the target calibration element based on the difference between the first design objective function and the second design objective function. The element sensitivity is used to describe the boundary of a single contour element and the degree of fit of the boundary relative to the design target.

[0019] 5. This invention provides a full-chip photolithography negative development simulation method, which calculates the phase of an element by measuring the wavelength of the light source, and updates the level set function based on the topological sensitivity and the phase of the element to determine a new material distribution function and Lagrangian function. The updated level set function, material distribution function, and Lagrangian function are used in the next simulation calculation.

[0020] 6. The present invention provides a full-chip photolithography negative development simulation method, which performs convergence analysis on the sensitive parameters, including convergence analysis on elemental sensitivity and topological sensitivity respectively. If both elemental sensitivity and topological sensitivity converge, the optimization ends. Convergence of the sensitive parameters, i.e., their tendency to a constant value, indicates that the simulation calculation results are close to the design optimization target, and the optimization ends.

[0021] 7. The present invention provides a full-chip photolithography negative development simulation method. If either the element sensitivity or the topology sensitivity fails to converge, the method iterates until the Lagrangian function is constructed based on the design optimization objective and the contour constraints. If the sensitivity parameter fails to converge, it indicates that the simulation results do not match the design optimization objective, and the Lagrangian coefficients need to be readjusted and simulation calculations performed again.

[0022] 8. The present invention provides a full-chip photolithography negative development simulation method. First, convergence analysis is performed on the element sensitivity parameters. If the element sensitivity parameters converge, then topological sensitivity analysis is performed. The changes in element sensitivity within the contour are relatively small, while the changes at the boundaries are larger. Therefore, performing convergence analysis on element sensitivity first can efficiently determine the location of elements. Then, performing convergence analysis on topological sensitivity for elements near the contour can reduce the analysis workload and save time.

[0023] 9. The present invention provides a storage medium for storing a full-chip photolithography negative development simulation method, which has the same beneficial effects as the above-mentioned full-chip photolithography negative development simulation method, and will not be described in detail here.

[0024] 10. The lithography machine provided by the present invention has the same beneficial effects as the above-mentioned full-chip lithography negative development simulation method, which will not be elaborated here. [Attached Image Description]

[0025] Figure 1 This is a flowchart of a full-chip photolithography negative development simulation method provided in the first embodiment of the present invention.

[0026] Figure 2 This is a flowchart of constructing an initial Lagrangian function based on design optimization objectives and contour constraints, provided in the first embodiment of the present invention.

[0027] Figure 3 This is a flowchart of the updated material distribution and Lagrange function provided in the first embodiment of the present invention.

[0028] Figure 4 This is a flowchart of the convergence analysis provided in the first embodiment of the present invention.

Detailed Implementation Methods

[0029] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0030] It's important to note that robustness refers to the stability and reliability of a system or algorithm when faced with external disturbances, abnormal situations, or input changes. A robust system or algorithm can maintain good performance under different environments and handle various abnormal situations. In computer science and engineering, robustness is an important design goal.

[0031] Please see Figure 1 The first embodiment of the present invention provides a full-chip photolithography negative development simulation method, including the following steps:

[0032] S1: Construct the initial level set function based on the mask shape, and determine the initial material distribution function based on the negative development photoresist distribution;

[0033] S2: Set the design optimization objective and contour constraints, construct the initial Lagrangian function based on the design optimization objective and contour constraints, and determine the update strategy;

[0034] S3: Provides a profile element consisting of several calibration elements and calculates the sensitivity parameter of each profile element to the degree of change of the design optimization target;

[0035] S4: Determine the update speed of the initial level set function at each point based on the sensitive parameters, update the level set function according to the update speed, and update the material distribution function and Lagrangian function according to the updated level set function;

[0036] S5: Perform convergence analysis on the sensitive parameters. If convergence is achieved, the optimization ends. If convergence is not achieved, iterate until the position where the Lagrangian function is constructed based on the design optimization objective and profile constraints.

[0037] It should be noted that in step S1, the initial level set function ψ(x,y,z) is constructed according to the signed distance function method, and the material distribution function M(x,y,z) is determined according to the initial negative development photoresist distribution. The expression of the initial level set function ψ(x,y,z) is as follows:

[0038]

[0039] Where x, y, z are level set design variables.

[0040] It should be noted that you should refer to [link / reference]. Figure 2 Step S2 specifically includes the following steps:

[0041] S21: Express the shape of the bunker using the design optimization objective f(x,y,z);

[0042] S22: Describe the bunker outline using the outline constraint c(x,y,z);

[0043] S23: Construct the Lagrangian function based on the design optimization objective f(x,y,z) and the contour constraint c(x,y,z). The expression of the Lagrangian function is:

[0044]

[0045] Where λ and Λ are the Lagrange coefficients, and initial values ​​of the Lagrange coefficients need to be input in the first simulation calculation;

[0046] S24: The update strategy is determined based on the contour constraints as follows:

[0047]

[0048] Where 0 < α < 1.

[0049] Specifically, the Lagrangian function introduces contour constraints into the objective function, making the solution process more flexible, and obtains the optimal design parameters and corresponding optimal Lagrangian coefficients that satisfy the constraints by solving the minimization problem.

[0050] Specifically, the update strategy is a topological update of the Lagrange function. New Lagrange coefficients can be obtained through the update strategy, and these new Lagrange coefficients are used as preset values ​​for the Lagrange coefficients.

[0051] It should be noted that in step S3, each contour element is a rectangular or L-shaped geometric figure composed of several calibration elements.

[0052] Specifically, sensitive parameters include topology sensitivity (topometry). s And element sensitivity d, where topo s The element sensitivity d refers to the degree of change in the objective function at the calibration element when an infinitesimally small space is added.

[0053] Specifically, the sensitive parameters reflect the degree of change of the contour elements from the design optimization target by increasing the infinitesimal space and increasing the calibration elements.

[0054] Specifically, the topological sensitivity (topo) of each contour element. s The formula for calculation is:

[0055]

[0056] Specifically, in calculating topological sensitivity (topometry)... s When selecting a calibration element as the target calibration element, the first Lagrange function is obtained through the target calibration element.

[0057] Add an infinitesimal space and obtain the second Lagrangian function at that infinitesimal space;

[0058] The topological sensitivity of the target calibration element is calculated based on the first and second Lagrange functions.

[0059] Furthermore, topo s It can be used to determine the topological relationship between two adjacent contour elements and to represent the degree of fit between the contour element and the design optimization target. When the target calibration element is not on the boundary, the perturbation of the added infinitesimal space affects the topology. s The impact is relatively small; when the target element is on the boundary, the increased perturbation of the infinitesimal space has little effect on the topo. s The impact is significant, thus determining whether the target calibration element is located on the bunker outline.

[0060] Specifically, the element sensitivity d is used to connect individual labeled elements on the boundary, distinguishing the outline of the cover. The formula for calculating the element sensitivity d of each target labeled element is:

[0061]

[0062] Specifically, a calibration element is provided as the target element and used as the first input value to obtain the first design objective function;

[0063] Select at least one calibration element from the calibration element group that is different from the first input value and add it to the target element. Add it to the first input value to obtain the second input value and obtain the second design objective function.

[0064] The element sensitivity of the target calibration element is derived from the difference between the first and second design objective functions.

[0065] Specifically, in the actual calculation process, d and u are obtained through matrix calculations. e The identity matrix for the target elements. K is the transpose of the identity matrix of the target calibration elements. e This represents a matrix consisting of the target calibration element and its neighboring elements. The element sensitivity value is obtained by multiplying the three matrices. By calculating the element sensitivity between the target calibration element and its neighboring elements, the connection relationship with the adjacent contour elements is obtained, and the target continuously approaches the contour constraint.

[0066] In this embodiment, a 3×3 matrix is ​​formed by selecting the target calibration element and its eight adjacent calibration elements as the center. The information of each selected element is incorporated into the matrix for calculation to obtain the element sensitivity d of the target calibration element.

[0067] Specifically, the element sensitivity d can be used to represent the boundary of a contour element. Calculating d can improve the accuracy of contour calculation and reduce errors.

[0068] It should be noted that you should refer to [link / reference]. Figure 3 Step 4 specifically includes the following steps:

[0069] S 41: The phase ω of the element is calculated based on the wavelength of the light source.

[0070] S 42: Determine the update rate at each element point based on phase, element sensitivity, and topology sensitivity, and update the level set function. The formula for calculating the update rate is:

[0071]

[0072]

[0073]

[0074] Specifically, update speed, i.e. Used to update the level set function ψ(x,y,z), reflecting the speed of the level set function update.

[0075] Specifically, the calculated results Multiply the result by the time taken for real-time updates and add it to the original level set function ψ(x,y,z) to obtain the new level set function ψ(x,y,z).

[0076] S 43: Update the material distribution and Lagrangian function based on the updated level set function.

[0077] Specifically, the preset values ​​of the Lagrange coefficients are substituted to obtain the updated Lagrange function, and the Lagrange coefficients are updated at the same time.

[0078] Furthermore, in the next iteration, the updated Lagrange coefficients are substituted into the updated Lagrange function in S2.

[0079] It should be noted that you should refer to [link / reference]. Figure 4 Step 5 specifically includes the following steps:

[0080] S 51: Convergence analysis of element sensitivity;

[0081] S 52a: If the element sensitivity converges, perform a convergence analysis on the topological sensitivity;

[0082] S 53a: If the topology sensitivity converges, then the optimization ends;

[0083] S 53b: If the topological sensitivity does not converge, iterate to S2;

[0084] S 52b: If the element sensitivity does not converge, iterate to S2.

[0085] It should be noted that S52a and S52b are two different execution methods; that is, after step S51, either S52a or S52b is selected for execution based on the result of the judgment. Similarly, S53a and S53b are two different execution methods; that is, after step S52a, either S53a or S53b is selected for execution based on the result of the judgment.

[0086] The convergence analysis of the sensitive parameters includes performing convergence analysis on element sensitivity and topology sensitivity separately. If both element sensitivity and topology sensitivity converge, the optimization ends; if either element sensitivity or topology sensitivity fails to converge, the iteration proceeds to S2, where the new Lagrangian function is constructed based on the design optimization objective and the contour constraints.

[0087] Furthermore, during iteration S2, the Lagrange function and Lagrange coefficients are updated based on the Lagrange coefficients updated in S43.

[0088] Furthermore, since the sensitivity variation of calibrated elements at the boundary is greater, when performing convergence analysis on the sensitivity parameters, we first perform convergence analysis on the element sensitivity parameters, making the iterative process more efficient. If convergence fails, we iterate to S2; if the element sensitivity parameters converge, we then perform topological sensitivity analysis. This scheme can efficiently determine the location of elements, reduce the workload of calculation and analysis, and save simulation time.

[0089] Understandably, the solution provided by this invention is unaffected by the selection of the developing film material and the developing solution material. Therefore, when the developing film material and the developing solution material change, the parameters in the simulation process do not need to be adjusted. For different mask requirements, only the design optimization objectives f(x,y,z) and c(x,y,z) need to be adjusted accordingly. Therefore, after eliminating the largest influencing factor, namely the impact of material changes, the solution provided by this invention can better observe the influence of other influencing factors on the parameters.

[0090] Understandably, this scheme does not consider the thermal shrinkage effect during the simulation process, resulting in a more accurate mask shape. Furthermore, the topology sensitivity can reflect the relationship between two adjacent contour elements. Therefore, it can accurately describe the topological relationship between the part lost due to thermal shrinkage during negative development and the original mask. It can also achieve targeted restoration of the mask for different material properties, thus eliminating the influence of developer density and greatly improving the robustness of the model for large-scale mass production.

[0091] The second embodiment of the present invention provides a storage medium for storing a full-chip photolithography negative development simulation method provided in the first embodiment.

[0092] Specifically, storage media include hard disk drives, solid-state drives, removable storage media, and network storage. The storage media also store the data generated by the simulation method and perform operations such as data transmission and backup.

[0093] The third embodiment of this invention provides a lithography machine, including the storage medium provided in the second embodiment, and performs full-chip modeling using a full-chip lithography negative development simulation method provided in the first embodiment, transferring the constructed integrated circuit pattern model onto the chip. During negative development, thermal shrinkage causes the pattern size to decrease, thus affecting the dimensional accuracy and precision of the chip. The model constructed by this lithography machine only focuses on the topological relationships between elements; therefore, the model is unaffected by thermal shrinkage, is more accurate, and the accuracy and speed of full-chip modeling are significantly improved.

[0094] In the embodiments provided by this invention, it should be understood that "B corresponding to A" means that B is associated with A, and B can be determined based on A. However, it should also be understood that determining B based on A does not mean determining B solely based on A; B can also be determined based on A and / or other information.

[0095] It should be understood that the phrase "one embodiment" or "an embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of the invention. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. Those skilled in the art should also recognize that the embodiments described in the specification are optional embodiments, and the actions and modules involved are not necessarily essential to the invention.

[0096] In various embodiments of the present invention, it should be understood that the sequence number of each process does not necessarily imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present invention.

[0097] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of this application. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It is particularly important to note that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0098] Compared with existing technologies, the full-chip photolithography negative development simulation method provided by this invention has the following beneficial effects:

[0099] 1. This invention provides a full-chip photolithography negative development simulation method, comprising the following steps: constructing an initial level set function based on the mask shape, and determining an initial material distribution function based on the negative development photoresist distribution; setting design optimization objectives and contour constraints, constructing an initial Lagrangian function based on the design optimization objectives and contour constraints, and determining an update strategy based on the contour constraints; providing contour elements composed of several calibration elements and calculating the sensitivity parameters of each contour element to the degree of change of the design optimization objectives; determining the update rate of each point based on the sensitivity parameters, updating the level set function, and updating the material distribution function and Lagrangian function based on the updated level set function; performing convergence analysis on the sensitivity parameters; if converged, the optimization ends; if not converged, iterates until the position of constructing the Lagrangian function based on the design optimization objectives and contour constraints and determining the update strategy is determined. Based on topological connectivity considerations, by describing the interrelationships between elements on the mask, the mutual influence between shape contours during the development process can be accurately described, and the topological relationship between the part lost due to thermal shrinkage during negative development and the original mask can be accurately described, achieving targeted recovery, eliminating the influence of developer density, greatly improving model robustness, and adapting to large-scale mass production.

[0100] 2. The present invention provides a full-chip photolithography negative development simulation method, wherein the sensitive parameters include topology sensitivity and element sensitivity, which are used to describe the degree of change of the calibrated elements relative to the design optimization target.

[0101] 3. The present invention provides a full-chip photolithography negative development simulation method, wherein obtaining the topological sensitivity of each contour element includes: selecting a calibration element among the contour elements as a target calibration element, and obtaining a first Lagrangian function through the target calibration element; adding an infinitesimal space, and obtaining a second Lagrangian function at the infinitesimal space; calculating the topological sensitivity of the target calibration element based on the first and second Lagrangian functions. Topological sensitivity (topo) s It is used to measure the degree of change of the objective function at the target calibration element when an infinitesimal space is added, and to reflect the topological relationship between each contour element. It is used to compensate for the part of the mask lost in the thermal shrinkage effect.

[0102] 4. The present invention provides a full-chip photolithography negative development simulation method, which obtains the element sensitivity of each contour element by: providing a calibration element among the contour elements as a target element and as a first input value to obtain a first design objective function; selecting at least one calibration element among the contour elements that is different from the calibration element in the first input value and adding it to the target element, adding it to the first input value to obtain a second input value, and obtaining a second design objective function; and obtaining the element sensitivity of the target calibration element based on the difference between the first design objective function and the second design objective function. The element sensitivity is used to describe the boundary of a single contour element and the degree of fit of the boundary relative to the design target.

[0103] 5. This invention provides a full-chip photolithography negative development simulation method, which calculates the phase of an element by measuring the wavelength of the light source, and updates the level set function based on the topological sensitivity and the phase of the element to determine a new material distribution function and Lagrangian function. The updated level set function, material distribution function, and Lagrangian function are used in the next simulation calculation.

[0104] 6. The present invention provides a full-chip photolithography negative development simulation method, which performs convergence analysis on the sensitive parameters, including convergence analysis on elemental sensitivity and topological sensitivity respectively. If both elemental sensitivity and topological sensitivity converge, the optimization ends. Convergence of the sensitive parameters, i.e., their tendency to a constant value, indicates that the simulation calculation results are close to the design optimization target, and the optimization ends.

[0105] 7. The present invention provides a full-chip photolithography negative development simulation method. If either the element sensitivity or the topology sensitivity fails to converge, the method iterates until the Lagrangian function is constructed based on the design optimization objective and the contour constraints. If the sensitivity parameter fails to converge, it indicates that the simulation results do not match the design optimization objective, and the Lagrangian coefficients need to be readjusted and simulation calculations performed again.

[0106] 8. The present invention provides a full-chip photolithography negative development simulation method. First, convergence analysis is performed on the element sensitivity parameters. If the element sensitivity parameters converge, then topological sensitivity analysis is performed. The changes in element sensitivity within the contour are relatively small, while the changes at the boundaries are larger. Therefore, performing convergence analysis on element sensitivity first can efficiently determine the location of elements. Then, performing convergence analysis on topological sensitivity for elements near the contour can reduce the analysis workload and save time.

[0107] 9. The present invention provides a storage medium for storing a full-chip photolithography negative development simulation method, which has the same beneficial effects as the above-mentioned full-chip photolithography negative development simulation method, and will not be described in detail here.

[0108] 10. The lithography machine provided by the present invention has the same beneficial effects as the above-mentioned full-chip lithography negative development simulation method, which will not be elaborated here.

[0109] The above provides a detailed description of a full-chip photolithography negative development simulation method disclosed in the embodiments of the present invention. Specific examples have been used to illustrate the principles and implementation methods of the present invention. The descriptions of the above embodiments are only for the purpose of helping to understand the method and core ideas of the present invention. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of the present invention. Therefore, the content of this specification should not be construed as a limitation of the present invention. Any modifications, equivalent substitutions, and improvements made within the principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A full-chip photolithography negative development simulation method, characterized in that, Includes the following steps: An initial level set function is constructed based on the mask shape, and an initial material distribution function is determined based on the negative development photoresist distribution. Set design optimization objectives and contour constraints, construct an initial Lagrangian function based on the design optimization objectives and contour constraints, and determine an update strategy based on the contour constraints; Provide a contour element consisting of several calibration elements and calculate the sensitivity parameter of each contour element to the degree of change of the design optimization target; The update rate for each point is determined based on the sensitive parameters, the level set function is updated, and the material distribution function and Lagrangian function are updated based on the updated level set function. Convergence analysis is performed on the sensitive parameters. If convergence is achieved, the optimization ends. If convergence is not achieved, the iteration continues until the Lagrangian function is constructed based on the design optimization objective and profile constraints, and the position of the update strategy is determined.

2. The full-chip photolithography negative development simulation method as described in claim 1, characterized in that: The sensitive parameters include topology sensitivity and element sensitivity.

3. The full-chip photolithography negative development simulation method as described in claim 2, characterized in that, Obtaining the topology sensitivity for each contour element includes: Select one of the contour elements as the target calibration element, and obtain the first Lagrangian function through the target calibration element; Add an infinitesimal space and obtain the second Lagrangian function at that infinitesimal space; The topological sensitivity of the target calibration element is calculated based on the first and second Lagrange functions.

4. The full-chip photolithography negative development simulation method as described in claim 2, characterized in that, Obtaining the element sensitivity for each contour element includes: Provide one calibration element from the contour elements as the target calibration element and as the first input value to obtain the first design objective function; Select at least one calibration element from the contour elements that is different from the first input value and add it to the target element. Add it to the first input value to obtain the second input value, and obtain the second design objective function. The element sensitivity of the target calibration element is derived based on the difference between the first design objective function and the second design objective function.

5. The full-chip photolithography negative development simulation method as described in claim 2, characterized in that: The phase of an element is calculated using the wavelength of the light source, and the level set function is updated based on the topological sensitivity and the phase of the element.

6. The full-chip photolithography negative development simulation method as described in claim 2, characterized in that: The convergence analysis of the sensitive parameters includes performing convergence analysis on element sensitivity and topology sensitivity respectively. If both element sensitivity and topology sensitivity converge, the optimization ends.

7. The full-chip photolithography negative development simulation method as described in claim 6, characterized in that: If either the element sensitivity or the topology sensitivity fails to converge, the iteration continues until the Lagrangian function is constructed based on the design optimization objective and the contour constraints.

8. The full-chip photolithography negative development simulation method as described in claim 6, characterized in that, The convergence analysis of the sensitive parameters includes: first performing convergence analysis on the element sensitivity parameters; if the element sensitivity parameters converge, then performing topological sensitivity analysis.

9. A storage medium, characterized in that: Used for storing a full-chip photolithography negative development simulation method according to any one of claims 1 to 8.

10. A lithography machine, characterized in that: The storage medium includes the one described in claim 9, wherein a model is established using the full-chip photolithography negative development simulation method described in any one of claims 1 to 8, and photolithography is performed on the entire chip.

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