Backlight control method and display driving circuit thereof

Abstract

A backlight control method and a display driving circuit thereof are disclosed. The backlight control method is used in a display screen for displaying at a variable refresh rate during a plurality of frame periods, each of which has a fixed period and a variable period. The method comprises the following steps: generating a first backlight control signal during the fixed period of a first frame period; determining whether a liquid crystal transition period corresponding to the first frame period ends before an end time of the variable period of the first frame period; generating a second backlight control signal during the variable period of the first frame period when the liquid crystal transition period ends before the end time of the variable period of the first frame period; and generating a compensation backlight control signal during a second frame period after the first frame period according to a backlight duty cycle of the first frame period.

Description

Technical Field

[0001] This invention relates to a control method for a display screen, and more particularly to a backlight control method for a display screen and a display driving circuit for performing the backlight control method. Background Technology

[0002] Variable Refresh Rate (VRR) is a new technology for displays that allows the display's refresh rate to be adjusted adaptively based on the current processing speed of the image provider (such as the Graphics Processing Unit (GPU)). This avoids various visual problems, such as tearing and image sticking, that occur when the GPU is too busy to output image frames in time.

[0003] For displays using variable refresh rate technology, achieving synchronized backlight control is more challenging. In typical synchronous backlight control schemes, the backlight control signal and the vertical synchronization signal of the input image are synchronized. Therefore, when the frame duration is variable, the duty cycle of the backlight control signal cannot remain consistent across different frame durations, and the continuously changing duty cycle will cause image flicker. In asynchronous backlight control schemes, the backlight control signal pulses are output at a predetermined frequency regardless of frame rate changes. However, in asynchronous backlight control schemes, the output pulses of the backlight control signal are prone to overlap with the liquid crystal transition periods, resulting in blurred displayed images.

[0004] Therefore, it is necessary to propose a backlight control method with synchronous backlight control function and provide a stable and controllable backlight control signal duty cycle to realize the application of variable refresh rate. Summary of the Invention

[0005] Therefore, the main objective of this invention is to propose a novel backlight control method and a display driving circuit for executing the backlight control method, so as to solve the above-mentioned problems.

[0006] An embodiment of the present invention discloses a backlight control method for a display screen, the display screen being used to display at a variable refresh rate during a plurality of frame periods, each of the plurality of frame periods having a fixed period and a variable period. The method includes the following steps: generating a first backlight control signal during the fixed period of a first frame period; determining whether a liquid crystal transition period corresponding to the first frame period ends before an end time of the variable period of the first frame period; when the liquid crystal transition period ends before the end time of the variable period of the first frame period, generating a second backlight control signal during the variable period of the first frame period; and generating a compensation backlight control signal during a second frame period following the first frame period according to a backlight duty cycle of the first frame period.

[0007] Another embodiment of the present invention discloses a display driving circuit for performing backlight control of a display screen. The display screen is used to display at a variable refresh rate during multiple frame periods, each of the multiple frame periods having a fixed period and a variable period. The display driving circuit includes a first signal generator, a main control circuit, and a second signal generator. The first signal generator is used to generate a first backlight control signal during the fixed period of a first frame period. The main control circuit is used to determine whether a liquid crystal transition period corresponding to the first frame period ends before an end time of the variable period of the first frame period. The second signal generator is used to generate a second backlight control signal during the variable period of the first frame period when the liquid crystal transition period ends before the end time of the variable period of the first frame period, and to generate a compensation backlight control signal during a second frame period following the first frame period according to a backlight duty cycle of the first frame period.

[0008] Another embodiment of the present invention discloses a display driving circuit for performing backlight control of a display screen. The display screen is used to display at a variable refresh rate during multiple frame periods, each of the multiple frame periods having a fixed period and a variable period. The display driving circuit includes a signal generator and a main control circuit. The signal generator is used to generate a first backlight control signal during the fixed period of a first frame period. The main control circuit is used to determine whether a liquid crystal transition period corresponding to the first frame period ends before an end time of the variable period of the first frame period. The signal generator is further used to generate a second backlight control signal during the variable period of the first frame period when the liquid crystal transition period ends before the end time of the variable period of the first frame period, and to generate a compensation backlight control signal during a second frame period following the first frame period according to a backlight duty cycle of the first frame period. Attached Figure Description

[0009] Figure 1 This is a waveform diagram of a typical backlight control scheme used in a variable refresh rate display system.

[0010] Figure 2A and Figure 2B This is a schematic diagram of the display system according to Embodiment 1 of the present invention.

[0011] Figure 3 This is a waveform diagram of a backlight control scheme for a variable refresh rate display system according to an embodiment of the present invention.

[0012] Figure 4 This is a waveform diagram of another backlight control scheme for a variable refresh rate display system according to an embodiment of the present invention.

[0013] Figure 5 This is a waveform diagram of a backlight control scheme for a variable refresh rate display system using partitioned backlight control, according to an embodiment of the present invention.

[0014] Figure 6 This is a waveform diagram of another backlight control scheme for a variable refresh rate display system using partitioned backlight control, according to an embodiment of the present invention.

[0015] Figure 7A and Figure 7B This is a schematic diagram of a display system used to implement zoned backlight control according to an embodiment of the present invention.

[0016] Figure 8 This is a flowchart of the backlight control process in Embodiment 1 of the present invention.

[0017] The reference numerals in the attached figures are explained as follows:

[0018] Vsync vertical synchronization signal

[0019] 20, 25, 70, 75 display systems

[0020] 200 display screens

[0021] 202 Backlight Controller

[0022] 204 Display Driver Circuit

[0023] 210 Image Scaler

[0024] 212 Main Control Circuit

[0025] 220 First Signal Generator

[0026] 222 Second signal generator

[0027] 224 Third Signal Generator

[0028] 226 Compensation Controller

[0029] 230 Synthesizer

[0030] VLED driving voltage

[0031] DE Data Start Signal

[0032] PWM1, PWM2, PWM3 backlight control signals

[0033] PWM_OUT, PWM_OUT1, Backlight control output signals

[0034] PWM_OUT2, PWM_OUT3

[0035] 250 signal generator

[0036] L_1~L_N display data rows

[0037] During frames F1 to F4

[0038] Backlight duty cycle of D1_A~D4_A, D1_B~D4_B

[0039] R1~R3 area

[0040] 702, 712, 714 output circuits

[0041] 704 Delay Circuit

[0042] 80 Backlight Control Process

[0043] Steps 800-810 Detailed Implementation

[0044] Figure 1 This is a waveform diagram of a typical backlight control scheme for a variable refresh rate (VRR) display system. In a VRR display system, the display driver circuit receives display data from the image provider and correspondingly receives or generates a vertical synchronization signal Vsync. Then, the display driver circuit converts the display data into a data voltage for output to the display screen and correspondingly outputs a backlight control signal to control the backlight timing of the display screen.

[0045] like Figure 1As shown, each pulse of the vertical sync signal Vsync indicates the start of a frame period. Since the refresh rate is variable, each frame period has a different length, and each frame period has an active period for receiving one frame of display data, with the remaining time intervals being blank periods. Generally, since the display data for each frame has a fixed size, the length of the active period within each frame period is consistent. In this case, the variable refresh rate can be controlled by adjusting the length of the blank period.

[0046] Figure 1 The diagram illustrates the backlight control signals under synchronous and asynchronous backlight control schemes. In the synchronous backlight control scheme, the backlight control signal has a series of pulses, each pulse being synchronized with the vertical sync signal Vsync within a frame period and having the same pulse width under the same brightness setting. Because the frame period length is not fixed, synchronous backlight control results in an unstable duty cycle, causing the displayed image to flicker. In the asynchronous backlight control scheme, the backlight control signal pulses have a predetermined frequency regardless of frame rate changes. These pulses easily overlap with the Liquid Crystal Transition Time (LCT). In this case, the backlight emits light when the liquid crystal molecules on the display change state, easily causing the displayed image to blur.

[0047] This invention proposes a backlight control method for variable refresh rate display systems to control the consistency of the duty cycle, thereby reducing image persistence, blurring, and flickering in the displayed image. In one embodiment, a frame period can be divided into a fixed period and a variable period, wherein the fixed period can be an active period, and the variable period can be a blank period. A first backlight control signal has a pulse assigned to each fixed period, while a second backlight control signal assigned to the variable period may include a series of small pulses. A specific backlight duty cycle can be achieved based on the duty cycle of the small pulses, thereby adjusting according to the length variation of the variable period. Furthermore, if the actual pulse width of the second backlight control signal cannot achieve the desired backlight duty cycle, a compensation pulse can be output in the next frame period to compensate for the backlight duty cycle of the current frame period, thus avoiding image blurring, especially at extremely low refresh rates.

[0048] Figure 2A This is a schematic diagram of the display system 20 according to Embodiment 1 of the present invention. Figure 2AAs shown, the display system 20 includes a display screen 200, a backlight controller 202, and a display driver circuit 204. The backlight of the display screen 200 can be provided by setting an array of light-emitting diodes (LEDs). The LEDs in the LED array emit light when they receive a corresponding driving voltage VLED, and the emission time is determined by the backlight controller 202. Based on one or more backlight control output signals from the display driver circuit 204, the backlight controller 202 can output current to each channel of the LEDs to control their emission time. The backlight controller 202 includes a current source for providing current to drive the LED array. The backlight controller 202 can be a control circuit integrated with the display screen 200 or a separate control circuit.

[0049] The display driver circuit 204 can be used to generate a backlight control output signal and provide the backlight control output signal to the backlight controller 202 and the display screen 200. In one embodiment, the display driver circuit 204 can also be used to provide display data to the display screen 200. Examples of the display driver circuit 204 include a source driver integrated circuit (Source Driver IC), but are not limited to this. Figure 2A As shown, the display driving circuit 204 includes an image scaler 210, a main control circuit 212, a first signal generator 220, a second signal generator 222, a third signal generator 224, a compensation controller 226, and a synthesizer 230.

[0050] Image scaler 210 receives display data from a front-end image provider (such as a graphics processing unit, GPU) and modifies the display data according to the resolution of display screen 200. Generally, the resolution of the video source received by the image provider is lower than the resolution of display screen 200; therefore, image scaler 210 can embed interpolated data into the original display data to expand the display data. Furthermore, based on the modified display data, image scaler 210 can generate a vertical synchronization signal Vsync and a data start signal DE, and output the vertical synchronization signal Vsync and the data start signal DE to the backlight signal generator. Alternatively, the vertical synchronization signal Vsync and / or the data start signal DE can be provided by the image provider. It should be noted that the vertical synchronization signal Vsync is used to indicate the start of each frame period, and the data start signal DE is used to indicate the valid period of display data output to display screen 200 and the blank period of no display data output. The vertical synchronization signal Vsync and the data start signal DE enable the backlight signal generator to generate backlight control signals according to appropriate timing.

[0051] The main control circuit 212 can provide other information for generating the backlight control signal, including, but not limited to, backlight duty cycle and delay information. For example, to avoid overlap between the backlight control signal and the liquid crystal transition period, delay information regarding the liquid crystal transition period can be provided to the backlight signal generator to output pulses at appropriate time points without affecting the liquid crystal transition and causing a blurred image. Furthermore, the backlight duty cycle is used to determine the pulse width of the backlight control signal, thereby producing the desired brightness. In one embodiment, the main control circuit 212 can be a microcontroller unit (MCU) or any other type of control circuit or device.

[0052] The first signal generator 220, the second signal generator 222, and the third signal generator 224 are used to generate a backlight control signal PWM1, a backlight control signal PWM2, and a backlight control signal PWM3, respectively. Each signal generator can be a pulse width modulation (PWM) generator, used to generate pulse signals as backlight control signals PWM1, PWM2, and PWM3, and to control the pulse width and timing. The pulses of the backlight control signals PWM1, PWM2, and PWM3 can be output in different forms, such as different frequencies, widths, and / or timings.

[0053] In detail, the first signal generator 220, the second signal generator 222, and / or the third signal generator 224 can receive the vertical synchronization signal Vsync and / or the data start signal DE from the image scaler 210, and receive information on the backlight duty cycle and / or delay time from the main control circuit 212, thereby determining the pulse timing and width in the backlight control signals PWM1, PWM2, and PWM3. Furthermore, the first signal generator 220, the second signal generator 222, and the third signal generator 224 can coordinate with each other to avoid pulse overlap. In one embodiment, each of the first signal generator 220, the second signal generator 222, and the third signal generator 224 includes a counter for calculating the pulse width and delay time based on the backlight duty cycle and delay information from the main control circuit 212.

[0054] The compensation controller 226 can be used to calculate the compensation pulse that the second signal generator 222 or the third signal generator 224 wants to output. As described above, the display driving circuit 204 can output a compensation pulse during the next frame period to compensate for the backlight duty cycle during the current frame period, thereby maintaining a consistent backlight duty cycle. The purpose of the compensation controller 226 is to calculate and determine the width of the compensation pulse. For example, based on the expected pulse width corresponding to the backlight duty cycle during the frame period and the sum of the pulse widths already generated in the backlight control signal, the compensation controller 226 can calculate the remaining pulse width for this frame period, thereby determining the width of the compensation pulse. In one embodiment, the compensation controller 226 may include a counter for calculating the remaining pulse width, so that the second signal generator 222 or the third signal generator 224 can output the compensation pulse according to the calculation result.

[0055] Synthesizer 230 can be used to combine the backlight control signals PWM1, PWM2, and PWM3 generated by the first signal generator 220, the second signal generator 222, and / or the third signal generator 224 to generate a backlight control output signal PWM_OUT, and output the backlight control output signal PWM_OUT to the backlight controller 202. Through the compensation method executed by the compensation controller 226, the combination of the backlight control signals PWM1, PWM2, and PWM3 can achieve the desired backlight duty cycle.

[0056] exist Figure 2A In one embodiment, the backlight control signals PWM1, PWM2, and PWM3 are generated by the first signal generator 220, the second signal generator 222, and the third signal generator 224, respectively. In another embodiment, these signal generators can be integrated into a single signal generator, that is, the backlight control signals PWM1, PWM2, and PWM3 can be generated by the same signal generator. Figure 2B One related implementation is shown, wherein a display system 25 includes a single signal generator 250 for generating and outputting backlight control signals PWM1, PWM2 and / or PWM3. Figure 2B The other signals and components are similar to Figure 2A The corresponding signals and components in the circuit are therefore represented by the same symbols. The operation of these circuit components is similar to... Figure 2A The display system 20 is not described in detail here.

[0057] Figure 3 This is a waveform diagram of a backlight control scheme for a variable refresh rate display system according to an embodiment of the present invention. This variable refresh rate display system can be, for example... Figure 2A Display system 20 or Figure 2B The display system 25. Figure 3The waveforms of the data start signal DE, backlight control signals PWM1-PWM3, and backlight control output signal PWM_OUT are shown, along with the scanning of rows of pixels on the display screen 200 as the display operation is performed. A "high" level for the data start signal DE represents the valid period for receiving a frame of display data, while a "low" level represents a blank period with no display data received. The display operation is performed sequentially from the first row L_1 to the last row L_N within each valid period. When a row of pixels is scanned and display data is received, the liquid crystal molecules need a short period to change their state, that is, to transition from the state corresponding to the previous display data to the state corresponding to the currently received display data; this period is called the "liquid crystal transition period." Figure 3 As shown, after a frame of display data is received at the end of the valid period, an additional short period of time is needed to complete the transition of the liquid crystal molecules in the last few rows, so that the liquid crystal transition period continues for a short time after the valid period ends.

[0058] It should be noted that the length of the liquid crystal transition period can be predicted and determined in advance. In one embodiment, the characteristics of the liquid crystal molecules on the display screen 200 can be measured to obtain an appropriate liquid crystal transition period, and the relevant information is stored in the main control circuit 212 to determine the delay time of the backlight control signal. As mentioned above, it is preferable to control the backlight to emit light when the liquid crystal is not in a transition state to avoid a blurred image. Therefore, the pulse of the backlight control signal can be generated after the liquid crystal transition period within the blank period, such as... Figure 3 As shown.

[0059] In a variable refresh rate display system, frame periods F1 to F4 have different lengths. Since the size of the display data in each frame is the same, the effective period for receiving the display data has a fixed length and can be considered a fixed period. Therefore, different frame periods F1 to F4 have different blank period lengths, and the blank period can be considered a variable period. Since the display driver circuit 204 does not know the length of the current blank period until it receives the display data of the next frame or the indication of a vertical synchronization signal Vsync or a data start signal DE, it is difficult to achieve the desired backlight duty cycle at the end of a frame period. Therefore, after the end of the frame period, the display driver circuit 204 can know the length of the blank period and the output pulse width, and calculate the remaining pulse width of the compensation pulse accordingly (e.g., calculated by the compensation controller 226), and output the compensation pulse in the next frame period. In this case, the overall backlight duty cycle can still reach its desired target value.

[0060] like Figure 3As shown, the first signal generator 220 (or signal generator 250) can generate a backlight control signal PWM1 for the effective period. Each effective period of the backlight control signal PWM1 includes a pulse whose pulse width satisfies the backlight duty cycle (D1_A to D4_A) of the effective period within the frame. Assuming that frame periods F1 to F4 are set to have the same backlight duty cycle (i.e., D1_A to D4_A are all equal), the pulse width of the backlight control signal PWM1 within each effective period is the same, thereby achieving a fixed backlight duty cycle within the effective period.

[0061] The second signal generator 222 (or signal generator 250) can generate a backlight control signal PWM2 for the blank period. To avoid the backlight control signal PWM2 pulse overlapping with the liquid crystal transition period, which would cause the displayed image to become blurry, the start time of the backlight control signal PWM2 can be determined based on the liquid crystal transition period. More specifically, the backlight control signal PWM2 pulse can be delayed to start at or after the end of the liquid crystal transition period, and the pulse width is required to satisfy the backlight duty cycle (D1_B to D4_B) during the blank period, taking into account the length of the liquid crystal transition period. However, since the length of the blank period is undetermined, if the length of the blank period is insufficient to cover the expected width of the pulse used to satisfy the desired backlight duty cycle, it is necessary to generate additional compensation pulses during the next frame. On the other hand, if the blank period is too long and extends beyond the end of the backlight control signal PWM2 pulse, additional pulses also need to be generated during the blank period to satisfy the target backlight duty cycle during the blank period.

[0062] In another embodiment, if the pulses of the backlight control signal PWM2 cannot be ideally positioned after the end of the liquid crystal transition period, then the backlight control signal PWM2 needs to start earlier and slightly overlap with the liquid crystal transition period. As long as the backlight control signal PWM2 can be positioned according to the liquid crystal transition period, all related implementations should fall within the scope of this invention.

[0063] In addition, based on the liquid crystal transition period, the main control circuit 212 can further determine whether the liquid crystal transition period ends before the end time of the blank period. If the blank period is too short so that the liquid crystal molecules cannot complete the transition within the blank period, then no pulse of the backlight control signal PWM2 can be generated within the blank period. Only when the liquid crystal transition period ends within the blank period (i.e., ends before the end time of the blank period) can the pulse of the backlight control signal PWM2 be generated within the blank period.

[0064] During frame period F1, the expected pulse width should satisfy the backlight duty cycle D1_B during the blank period. However, the blank period is not long enough, causing the pulse width of the backlight control signal PWM2 to fail to reach the expected width. Therefore, the pulse of the backlight control signal PWM2 ends at the end of the blank period of frame period F1. In this case, a compensation pulse is necessary to compensate for the pulse of the backlight control signal PWM2. The second signal generator 222 (or signal generator 250) can output the compensation pulse during the effective period of the next frame period F2, i.e. Figure 3 The backlight control signal PWM2 is shown.

[0065] In this case, the width of the compensation pulse is equal to the expected pulse width of the backlight control signal PWM2 minus the actual pulse width of the backlight control signal PWM2 during the blank period. The compensation pulse width can be obtained by the compensation controller 226, which calculates the remaining pulse width based on the backlight duty cycle and determines the width of the compensation pulse accordingly. It is also important to note that the compensation pulse of the backlight control signal PWM2, located in the next valid period, should be staggered from the pulse of the backlight control signal PWM1 used for the next frame period. That is, the compensation pulse needs to be output at a time that does not overlap with the pulse of the backlight control signal PWM1, thereby ensuring that the synthesizer 230 generates an accurate duty cycle after combination. Therefore, based on the pulse position of the backlight control signal PWM1, the corresponding delay information can be provided to the second signal generator 222 (or signal generator 250) to output the compensation pulse with an appropriate delay time. Figure 3 As shown, the compensation pulse for the blank period of frame period F1 is generated during the effective period of frame period F2 after the backlight control signal PWM1 pulse for frame period F2 ends.

[0066] Within frame period F2, the length of the blank period is long enough to cover a pulse with the expected width, which satisfies the desired backlight duty cycle D2_B during the blank period. Therefore, the actual pulse width of the backlight control signal PWM2 during the blank period is equal to the expected width. Since the blank period continues for a period of time after the pulse of the backlight control signal PWM2 ends, the third signal generator 224 (or signal generator 250) can be used to generate the backlight control signal PWM3 to achieve the target backlight duty cycle. In this example, the backlight control signal PWM3 includes a series of small pulses, all with the same duty cycle as the desired backlight duty cycle D2_B during the blank period. Therefore, the overall duty cycle of the blank period will approach the desired backlight duty cycle D2_B, and the number of these small pulses corresponds to the length of the blank period. In other words, the longer the blank period, the more pulses there are. Since the actual duty cycle of the blank period approaches the desired backlight duty cycle D2_B, no compensation pulses need to be generated in the next frame period.

[0067] like Figure 3 As shown, frame period F2 is used to illustrate extremely low frame rates with a fairly long blank period. Because the blank period lasts for a considerable time after the liquid crystal molecules have completed their transition, there is an optimal period during which the backlight can emit light without being affected by the liquid crystal transition, thus preventing a blurred image.

[0068] Frame period F3 illustrates another case with an extremely short blank period, where the liquid crystal molecules have not yet fully changed state by the end of the blank period. In this case, the pulse of the backlight control signal PWM2 is not generated during the blank period of frame period F3. Therefore, the corresponding compensation pulse can still be calculated based on the desired backlight duty cycle D3_B and generated during the effective period of the next frame period F4. The compensation controller 226 can calculate the remaining pulse width based on the desired backlight duty cycle D3_B and the length of the blank period, thereby determining the width of the compensation pulse to be generated during the effective period of the next frame period F4.

[0069] Within frame period F4, the length of the blank period is long enough to cover the expected pulse width, which satisfies the desired backlight duty cycle D4_B within the blank period. The detailed operation of the backlight control signal within frame period F4 is similar to that within frame period F2 and will not be repeated here.

[0070] Figure 4 This is a waveform diagram of another backlight control scheme for a variable refresh rate display system according to an embodiment of the present invention. Figure 4 The detailed operation method of backlight control is similar to Figure 3 Therefore, signals with similar functions are represented by the same symbol. Figure 4 and Figure 3 The difference between them is that, Figure 4 The embodiment does not include the backlight control signal PWM3 output by the third signal generator 224. In other words, the third signal generator 224 in the display driver circuit 204 may be disabled, or the display driver circuit 204 in the display system 20 may not include the third signal generator 224 (only two signal generators or pulse width modulation generators are included).

[0071] Without the third signal generator 224, the backlight control signal PWM2 generated by the second signal generator 222 can be applied to situations with long idle periods. For example... Figure 4As shown, within frame period F2, the blank period is relatively long and ends after the end time of the first pulse of the backlight control signal PWM2. The backlight control signal PWM2 also includes at least one pulse with a specific width and duty cycle to achieve the desired backlight duty cycle D2_B within the blank period of frame period F2. For example, the second signal generator 222 can continuously output pulses with the same width and spacing (i.e., the same duty cycle) at the same frequency until the blank period of frame period F2 ends. If the remaining time does not meet the backlight duty cycle D2_B, compensation pulses can be used in the next frame period F3 to compensate. This compensation pulse can be calculated and generated in a manner similar to the aforementioned embodiments.

[0072] Based on the aforementioned backlight control scheme, the backlight duty cycle can be achieved by providing backlight control signals during a fixed active period and a variable idle period. For a frame period set with a target backlight duty cycle (e.g., 30%), a first backlight control signal including a fixed pulse can achieve a 30% duty cycle during the active period. During the idle period, the pulse of the second backlight control signal can be generated after the liquid crystal transition period ends, and the pulse width can be adjusted according to the 30% duty cycle of the idle period. Since the length of the idle period is variable, the pulse width of the second backlight control signal may not reach a 30% duty cycle at the end of the idle period. Therefore, an additional compensation pulse can be generated during the active period of the next frame period to meet the desired backlight duty cycle. In this case, if a series of frame periods are set with the same backlight duty cycle, the pulse signals during an idle period and the next active period can completely achieve the desired backlight duty cycle, thereby maintaining a consistent overall backlight duty cycle.

[0073] It is worth noting that the purpose of this invention is to provide a backlight control method and related display driving circuit for improving visual effects in a variable refresh rate display system. Those skilled in the art will be able to make modifications or variations accordingly, and are not limited thereto. For example, in the above embodiments, the backlight control method can be applied to a variable refresh rate display system with a variable blanking period. In another embodiment, the backlight control method can also be applied to a fixed refresh rate display system. Furthermore, in the above embodiments, the display screen receives a global backlight control output signal, that is, the backlight of the entire display screen is controlled by the same signal. In another embodiment, the display screen can be divided into multiple areas, and the backlight module of the display screen can include multiple groups of light-emitting diodes (LEDs), where each group of LEDs is responsible for providing backlight for one area. Therefore, the display driving circuit can provide different backlight control output signals for different groups of LEDs to achieve zoned backlight control.

[0074] For example, a display screen can be divided into multiple areas from top to bottom. Depending on the scanning sequence of the display operation, different areas have different liquid crystal transition periods. The liquid crystal transition period in the upper area starts and ends earlier, while the liquid crystal transition period in the lower area starts and ends later. Therefore, the backlight control output signals for different areas are output with different delays, thus arranging the pulses of the backlight control output signals to be staggered with the liquid crystal transition periods of the corresponding areas. For example, the backlight control output signal pulses for the upper area can be output with a shorter delay, while the backlight control output signal pulses for the lower area can be output with a longer delay.

[0075] Figure 5 This is a waveform diagram of a backlight control scheme for a variable refresh rate display system using zoned backlight control, according to an embodiment of the present invention. Figure 5 As shown, the display screen can be divided into three areas R1 to R3, which are controlled by three backlight control output signals PWM_OUT1, PWM_OUT2, and PWM_OUT3, respectively. Compared to the aforementioned embodiment using full-area backlight control, using local partition backlight control can significantly reduce the liquid crystal transition period length in each area. Therefore, the backlight control output signals PWM_OUT1, PWM_OUT2, and PWM_OUT3 can be well arranged so that no pulse overlaps with the liquid crystal transition period. In this case, local partition backlight control can achieve better visual effects and avoid producing blurry images.

[0076] For example, in the backlight control output signal PWM_OUT1 for region R1, a pulse with a specific width can be generated to achieve the backlight duty cycle for each effective period. This pulse can be delayed to start at the same time as or after the end of the liquid crystal transition period. Next, a series of small pulses can be generated to achieve the backlight duty cycle for each variable blank period. The duty cycle of these small pulses can be equal to the desired backlight duty cycle within the blank period, so that the overall duty cycle within the blank period approaches the desired backlight duty cycle. These small pulses can continue to be output until the start of the next frame's liquid crystal transition period. Since the actual duty cycle of the blank period achieved by the small pulses is close to its target backlight duty cycle, no compensation pulses are required.

[0077] like Figure 5As shown, regions R1 to R3 have different liquid crystal transition periods. Therefore, the backlight control output signals PWM_OUT1, PWM_OUT2, and PWM_OUT3 can have different delays to avoid overlapping with the liquid crystal transition periods. Since different regions typically have the same brightness setting and duty cycle within the same frame period, the backlight control output signals PWM_OUT1, PWM_OUT2, and PWM_OUT3 can include pulses of the same width and shape, and are output to different regions with different delays. For example, the backlight control output signal PWM_OUT2 has a delay relative to the backlight control output signal PWM_OUT1, while the backlight control output signal PWM_OUT3 has a delay relative to the backlight control output signal PWM_OUT2. From another perspective, the backlight control output signal PWM_OUT2 has a shorter delay than the backlight control output signal PWM_OUT3, while the backlight control output signal PWM_OUT2 has a longer delay than the backlight control output signal PWM_OUT1.

[0078] Figure 6 The waveform diagram shows another backlight control scheme for a variable refresh rate display system using partitioned backlight control, as described in an embodiment of the present invention. Figure 6 The detailed operation method of backlight control is similar to Figure 5 Therefore, signals with similar functions are represented by the same symbol. Figure 6 and Figure 5 The difference between them is that, Figure 6 The embodiment employs one or more large pulses in the backlight control output signal used during the blank period, the pulse width and spacing of which meet the desired duty cycle, and a compensation pulse is required in the next frame period to compensate for the remaining time in the blank period. This compensation pulse can be shifted or adjusted to any appropriate position to offset other pulses in the same backlight control output signal.

[0079] Figure 7A This is a schematic diagram of a display system 70 used to implement zoned backlight control according to an embodiment of the present invention. The structure of the display system 70 is similar to... Figure 2A The structure of system 20 is shown in the image; therefore, signals or components with similar functions are represented by the same symbol. For example... Figure 7A As shown, the display driving circuit 204 of the display system 70 includes an output circuit 702 and a delay circuit 704. The output circuit 702 can be used to output a backlight control output signal PWM_OUT1, which includes a compensation controller, a synthesizer, and two or three signal generators, such as... Figure 2A The illustrated implementation may include a compensation controller, a synthesizer, and a single signal generator, such as... Figure 2BThe illustrated implementation shows a delay circuit 704 coupled to the output circuit 702. This delay circuit can be implemented by any circuit component with a delay function, such as a delay chain consisting of multiple inverters. The delay circuit 704 can add a delay to the backlight control output signal PWM_OUT1 to generate a backlight control output signal PWM_OUT2. The backlight control output signals PWM_OUT1 and PWM_OUT2 can be used on two different areas of the display screen.

[0080] In another embodiment, the display driving circuit may include more than one delay circuit with different delay times, or the delay circuit may be able to output multiple backlight control output signals with different delay times, thereby providing more backlight control output signals with different delays.

[0081] Figure 7B This is a schematic diagram of another display system 75 used to implement zoned backlight control according to an embodiment of the present invention. The structure of the display system 75 is similar to... Figure 2A The structure of system 20 is shown in the image; therefore, signals or components with similar functions are represented by the same symbol. For example... Figure 7B As shown, the display driving circuit 204 in the display system 75 includes output circuits 712 and 714, used to output backlight control output signals PWM_OUT1 and PWM_OUT2 respectively. Each output circuit 712 and 714 includes a compensation controller, a synthesizer, and two or three signal generators, such as... Figure 2A The illustrated implementation may include a compensation controller, a synthesizer, and a single signal generator, such as... Figure 2B The implementation shown is similar. Similarly, the backlight control output signals PWM_OUT1 and PWM_OUT2 can be used on two different areas of the display screen.

[0082] In another embodiment, the display driving circuit may also include three or more output circuits for generating and outputting three or more backlight control output signals with different delay times for different areas on the display screen. Since each output circuit has its own compensation controller for timing / delay control, each backlight control output signal can be generated independently.

[0083] The above-mentioned backlight control operations can be summarized into a backlight control process 80, such as... Figure 8 As shown. The backlight control process 80 can be implemented in a display driver circuit of a variable refresh rate display system, such as... Figure 2A , 2B The display driver circuit 204 in 7A or 7B controls the backlight of the display screen during variable blank periods. Figure 8 As shown, the backlight control process 80 includes the following steps:

[0084] Step 800: Begin.

[0085] Step 802: Generate a first backlight control signal during the effective period of a first frame period in a plurality of frame periods.

[0086] Step 804: Determine whether a liquid crystal transition period corresponding to the first frame period ends before an end time of a blank period in the first frame period.

[0087] Step 806: When the liquid crystal transition period ends before the end time of the blank period in the first frame period, a second backlight control signal is generated at or after the end of the liquid crystal transition period in the blank period of the first frame period.

[0088] Step 808: Based on a backlight duty cycle during the first frame period, generate a compensation backlight control signal during a second frame period following the first frame period.

[0089] Step 810: End.

[0090] For detailed implementation and variations of the backlight control process 80, please refer to the explanation in the above paragraphs, which will not be repeated here.

[0091] In summary, this invention proposes a novel backlight control scheme applicable to a variable refresh rate display system, wherein each frame period can be divided into a fixed active period and a variable idle period. A first backlight control signal with a fixed pulse can be used to achieve the backlight duty cycle during the active period. A second backlight control signal with a series of pulses can be used to achieve the backlight duty cycle during the idle period. If the backlight duty cycle during the idle period cannot be met due to the uncertain length of the idle period, or if the length of the idle period is insufficient to cover the pulse width required to achieve the expected backlight duty cycle, a compensation pulse can be generated during the active period of the next frame period to compensate for the missing pulse width and / or the remaining time of the idle period. In this case, the overall backlight duty cycle can reach its target value, and the backlight duty cycle can remain consistent over a series of frame periods. The backlight control output signal of this invention can be used for global backlight control or local dimming backlight control on the display screen. In one embodiment, the pulses of the backlight control signal can be staggered with the liquid crystal transition period to avoid producing a blurred image, which has better performance under local dimming backlight control.

[0092] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A backlight control method for a display screen, the display screen being used to display at a variable refresh rate during a plurality of frame periods, each of the plurality of frame periods having a fixed period and a variable period, characterized in that, The method includes: A first backlight control signal is generated during a fixed period of a first frame period in the plurality of frame periods; Determine whether a liquid crystal transition period corresponding to the first frame period ends before an end time of the variable period of the first frame period; When the liquid crystal transition period ends before the end time of the variable period of the first frame period, a second backlight control signal is generated during the variable period of the first frame period; and Based on a backlight duty cycle during the first frame period, a compensation backlight control signal is generated during a second frame period following the first frame period.

2. The method as described in claim 1, characterized in that, The second backlight control signal is initiated at a time point determined based on the liquid crystal transition period.

3. The method as described in claim 1, characterized in that, The second backlight control signal is initiated at the end of or after the liquid crystal transition period.

4. The method as described in claim 1, characterized in that, Also includes: Combining the first backlight control signal, the second backlight control signal, and the compensation backlight control signal, To generate a first backlight control output signal; as well as The first backlight control output signal is output to a backlight controller of the display screen.

5. The method as described in claim 4, characterized in that, The display screen is divided into multiple areas, and the first backlight control output signal is used for a first area among the multiple areas.

6. The method as described in claim 5, characterized in that, During the liquid crystal transition period, a second backlight control output signal for a second region in the plurality of regions and a first backlight control output signal for the first region have different delays.

7. The method as described in claim 5, characterized in that, A second backlight control output signal for a second region in the plurality of regions and a first backlight control output signal for the first region are each generated independently.

8. The method as described in claim 1, characterized in that, The compensation backlight control signal during the fixed period of the second frame is staggered from another backlight control signal used during the second frame.

9. The method as described in claim 1, characterized in that, The first backlight control signal includes a first pulse, the width of which corresponds to the backlight duty cycle during the first frame.

10. The method as described in claim 1, characterized in that, The second backlight control signal includes a second pulse, the width of which is equal to a predetermined width when the length of the variable period during the first frame is sufficient to cover a predetermined width of the second pulse, wherein the predetermined width corresponds to the backlight duty cycle during the first frame.

11. The method as described in claim 10, characterized in that, Also includes: After the second pulse ends, a third backlight control signal is generated during the variable period of the first frame, wherein the third backlight control signal includes at least one third pulse, the number of which corresponds to the length of the variable period of the first frame.

12. The method as described in claim 10, characterized in that, The second backlight control signal also includes at least one fourth pulse following the end of the second pulse, each of the at least one fourth pulse having a specific width corresponding to the backlight duty cycle during the first frame.

13. The method as described in claim 12, characterized in that, The backlight compensation control signal includes a compensation pulse to compensate for the backlight duty cycle during the first frame, and the method further includes: The width of the compensation pulse is calculated based on the at least one fourth pulse and the backlight duty cycle during the first frame.

14. The method as described in claim 1, characterized in that, The second backlight control signal includes a second pulse, which ends at the end time of the variable period during the first frame when the length of the variable period during the first frame is insufficient to cover a desired width of the second pulse, wherein the desired width corresponds to the backlight duty cycle during the first frame.

15. The method as described in claim 14, characterized in that, The backlight compensation control signal includes a compensation pulse to compensate for the backlight duty cycle during the first frame, and the method further includes: The width of the compensation pulse is calculated based on the second pulse and the backlight duty cycle during the first frame, wherein the width of the compensation pulse is equal to the expected width minus an actual width of the second pulse.

16. A display driving circuit for performing backlight control of a display screen for displaying at a variable refresh rate during a plurality of frame periods, each of the plurality of frame periods having a fixed period and a variable period, characterized in that, The display driver circuit includes: A first signal generator is configured to generate a first backlight control signal during a fixed period of a first frame period in the plurality of frame periods. A main control circuit is used to determine whether a liquid crystal transition period corresponding to the first frame period ends before an end time of the variable period of the first frame period; and A second signal generator is configured to generate a second backlight control signal during the variable period of the first frame period when the liquid crystal transition period ends before the end time of the variable period of the first frame period, and to generate a compensation backlight control signal during a second frame period after the first frame period according to a backlight duty cycle of the first frame period.

17. The display driving circuit as described in claim 16, characterized in that, The second backlight control signal is initiated at a time point determined based on the liquid crystal transition period.

18. The display driving circuit as described in claim 16, characterized in that, The second backlight control signal is initiated at the end of or after the liquid crystal transition period.

19. The display driving circuit as described in claim 16, characterized in that, Also includes: A synthesizer is used to combine the first backlight control signal, the second backlight control signal and the compensation backlight control signal to generate a first backlight control output signal, and output the first backlight control output signal to a backlight controller of the display screen.

20. The display driving circuit as described in claim 19, characterized in that, The display screen is divided into multiple areas, and the first backlight control output signal is used for a first area among the multiple areas.

21. The display driving circuit as described in claim 20, characterized in that, During the liquid crystal transition period, a second backlight control output signal for a second region in the plurality of regions and a first backlight control output signal for the first region have different delays.

22. The display driving circuit as described in claim 20, characterized in that, A second backlight control output signal for a second region in the plurality of regions and a first backlight control output signal for the first region are each generated independently.

23. The display driving circuit as described in claim 16, characterized in that, The compensation backlight control signal during the fixed period of the second frame is staggered from another backlight control signal used during the second frame.

24. The display driving circuit as described in claim 16, characterized in that, The first backlight control signal includes a first pulse, the width of which corresponds to the backlight duty cycle during the first frame.

25. The display driving circuit as described in claim 16, characterized in that, The second backlight control signal includes a second pulse, the width of which is equal to a predetermined width when the length of the variable period during the first frame is sufficient to cover a predetermined width of the second pulse, wherein the predetermined width corresponds to the backlight duty cycle during the first frame.

26. The display driving circuit as described in claim 25, characterized in that, Also includes: A third signal generator is configured to generate a third backlight control signal during the variable period of the first frame after the second pulse ends, wherein the third backlight control signal includes at least one third pulse, the number of which corresponds to the length of the variable period of the first frame.

27. The display driving circuit as described in claim 25, characterized in that, The second backlight control signal also includes at least one fourth pulse following the end of the second pulse, each of the at least one fourth pulse having a specific width corresponding to the backlight duty cycle during the first frame.

28. The display driving circuit as described in claim 27, characterized in that, The backlight compensation control signal includes a compensation pulse to compensate for the backlight duty cycle during the first frame, and the display driving circuit further includes: A compensation controller is used to calculate the width of the compensation pulse based on the at least one fourth pulse and the backlight duty cycle during the first frame.

29. The display driving circuit as described in claim 16, characterized in that, The second backlight control signal includes a second pulse, which ends at the end time of the variable period during the first frame when the length of the variable period during the first frame is insufficient to cover a desired width of the second pulse, wherein the desired width corresponds to the backlight duty cycle during the first frame.

30. The display driving circuit as described in claim 29, characterized in that, The backlight compensation control signal includes a compensation pulse to compensate for the backlight duty cycle during the first frame, and the display driving circuit further includes: A compensation controller is configured to calculate the width of the compensation pulse based on the second pulse and the backlight duty cycle during the first frame, wherein the width of the compensation pulse is equal to the expected width minus an actual width of the second pulse.

31. A display driving circuit for performing backlight control of a display screen for displaying at a variable refresh rate during a plurality of frame periods, each of the plurality of frame periods having a fixed period and a variable period, characterized in that, The display driver circuit includes: A signal generator is configured to generate a first backlight control signal during a fixed period of a first frame period among the plurality of frame periods; and A main control circuit is used to determine whether a liquid crystal transition period corresponding to the first frame period ends before an end time of the variable period of the first frame period; The signal generator is further configured to generate a second backlight control signal during the variable period of the first frame when the liquid crystal transition period ends before the end time of the variable period of the first frame period, and to generate a compensation backlight control signal during a second frame period after the first frame period according to a backlight duty cycle of the first frame period.

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