Storage medium simulator and storage medium simulation method

Abstract

The application discloses a storage medium simulation scheme, which receives a signal group from a medium interface controller simulator, identifies a command according to the signal group, configures a target simulation module for simulating a target in the storage medium, identifies a target submodule corresponding to the command, sends the command to the target submodule, receives a result fed back by the target submodule, and sends the result to the medium interface controller simulator. The application improves the granularity of simulation, can reach the accuracy of a clock cycle, and further judges the correctness of signal transmission in a flash memory channel.

Description

Technical Field

[0001] This application generally relates to the field of integrated circuit testing. More specifically, this application relates to a storage medium simulator and a storage medium simulation method. Background Technology

[0002] Figure 1A An exemplary block diagram of a storage device is shown. Storage device 100 is coupled to a host to provide storage capabilities to the host. The host and storage device 100 can be coupled in various ways, including but not limited to connections via, for example, Serial Advanced Technology Attachment (SATA), Small Computer System Interface (SCSI), Serial Attached SCSI (SAS), Integrated Drive Electronics (IDE), Universal Serial Bus (USB), Peripheral Component Interconnect Express (PCIe), NVM Express (NVMe), Ethernet, Fibre Channel, and wireless communication networks. Furthermore, the host can be an information processing device capable of communicating with storage device 100 via the aforementioned methods. For example, the host can be a personal computer, tablet computer, server, laptop computer, network switch, router, cellular phone, personal digital assistant, etc. Additionally, storage device 100 may include interface 101, control unit 102, dynamic random access memory (DRAM) 103, and one or more non-volatile memory (NVM) chips 104.

[0003] The aforementioned NVM chip 104 can be, for example, common memory such as NAND flash memory, phase change memory, ferroelectric RAM (FeRAM), magnetoresistive random access memory (MRAM), resistive random access memory (RRAM), XPoint memory, etc.

[0004] The aforementioned control unit 102 is used to control data transmission between interface 101, NVM chip 104, and DRAM 103. It is also used for storage management, mapping host logical addresses to flash memory physical addresses, controlling erase leveling, and bad block management. Furthermore, the control unit 102 can be implemented through software, hardware, firmware, or a combination thereof. For example, the control unit 102 can be in the form of a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), or a combination thereof. The control unit 102 may also include a processor or controller, in which software manipulates the hardware of the control unit 102 to process I / O (Input / Output) commands. The control unit 102 can also be coupled to DRAM 103 and can access data in DRAM 103, wherein DRAM 103 can store FTL tables and / or cached I / O command data.

[0005] See Figure 1B The control unit 102 includes a host interface 1021, a host command processing unit 1022, a storage command processing unit 1023, a storage media management unit 1024, and a media interface controller 1025. The host interface 1021 receives I / O commands from the host. The host command processing unit 1022 generates storage commands based on the I / O commands and provides them to the storage command processing unit 1023. Each storage command can access a storage space of the same size, such as 4KB. The data unit recorded in the NVM chip corresponding to the data accessed by a storage command is called a data frame. A physical page records one or more data frames. For example, if the size of a physical page is 17664 bytes and the size of a data frame is 4KB, then one physical page can store four data frames.

[0006] The storage media management unit 1024 maintains the logical address to physical address translation for each storage command. For example, the storage media management unit 1024 includes an FTL table (explained below). For a read command, the storage media management unit 1024 outputs the physical address corresponding to the logical address (LBA) accessed by the storage command. For a write command, the storage media management unit 1024 allocates an available physical address and records the mapping between the accessed logical address (LBA) and the allocated physical address. The storage media management unit 1024 also maintains functions required for managing the NVM chip, such as garbage collection and wear leveling.

[0007] The storage command processing unit 1023, based on the physical address provided by the storage media management unit 1024, operates the media interface controller (also known as the flash interface controller or NVM interface controller) 1025 to issue storage media access commands to the NVM chip 104. The storage media access commands follow the interface protocol of the NVM chip and include, for example, read commands, programming commands, or erase commands. Known NVM chip 104 interface protocols include "Toggle," "ONFI," etc. Chinese patent applications CN201610009789.6 and CN201510253428.1 provide microinstruction execution methods and apparatus for flash interface controllers; Chinese patent application CN 201610861793.5 provides a microinstruction sequence scheduling method and apparatus; Chinese patent application CN 201611213754.0 provides an IO command processing method and solid-state storage device; and Chinese patent application CN201611213755.5 provides a high-capacity NVM interface controller.

[0008] The media interface controller 1025 couples NVM chips through one or more flash memory channels. One flash memory channel couples, for example, two NVM chips. The flash memory channel includes a set of signal lines for transmitting signals conforming to the interface protocol of the NVM chips. Part of this set of signal lines is shared by the multiple NVM chips it is coupled to; that is, these signal lines are simultaneously connected to corresponding pins with the same function on multiple NVM chips. This set of signal lines also includes some signal lines that are exclusive to each of the multiple NVM chips it is coupled to, and these signal lines (e.g., CE signal, chip select signal) are connected to each of the multiple NVM chips respectively.

[0009] Signals are transmitted on flash memory channels in cycles. Each cycle transmits signals with different meanings, indicated by a cycle type. Cycle types include, for example, command cycle (CMD type), address cycle (ADDR type), data input cycle (Data In type), and data output cycle (Data Out type). In some cases, cycles are distinguished by a clock signal transmitted via a clock signal line (CLK); in others, cycles are distinguished by other signal lines without a clock signal line. In each cycle, one or more signal lines on the flash memory channel transmit a set of signals, some or all of which are meaningful, while others can be ignored. A set of signals from one or more cycles forms a signal group.

[0010] For clarity, commands sent from the host to the storage device are called I / O commands; commands sent from the host command processing unit to the storage command processing unit are called storage commands; commands sent from the storage command processing unit to the media interface controller are called media interface commands; and commands sent from the media interface controller to the NVM chip are called storage media access commands. Storage media access commands conform to the NVM chip's interface protocol.

[0011] A memory target is one or more logic units (LUNs) within a NAND flash memory package that share a common chip enable (CE) signal. A NAND flash memory package may include one or more dies. Typically, a logic unit corresponds to a single die. A logic unit may include multiple planes. Multiple planes within a logic unit can be accessed in parallel, while multiple logic units within a NAND flash memory chip can execute commands and report status independently of each other.

[0012] An NVM chip includes one or more Logic Units (LUNs). An NVM chip package may include one or more dies. Typically, a Logic Unit corresponds to a single die. A Logic Unit may include multiple Planes. Multiple Planes within a Logic Unit can be accessed in parallel, while multiple Logic Units within an NVM chip can execute commands and report status independently of each other. The meanings of target, Logic Unit, and Plane are provided in the "Open NAND Flash Interface Specification (Revision 3.0)" available at http: / / www.micron.com / ~ / media / Documents / Products / Other%20Documents / ONFI3_0Gold.ashx, which is part of the prior art.

[0013] After receiving I / O commands from the host, the media interface controller in the control unit of the storage device issues storage media access commands to the NVM chip and / or receives data or other information read from the NVM chip through the execution of a microinstruction sequence. During the development of the storage device, engineers can program, update, and / or modify the microinstruction sequence to enable the media interface controller to interact with NVM chips from different manufacturers. For example, if the NVM chip of the storage device is upgraded, a corresponding microinstruction sequence needs to be developed to make the media interface controller compatible with the upgraded NVM chip.

[0014] We require simulators to assist in the development of microinstruction sequences. For example, in the early stages of development, it may be impossible to obtain a physical NVM chip for integration testing with the control unit. Therefore, to verify the correctness of the designed microinstruction sequences, we need a storage media simulator that can interact with the media interface controller and simulate the external behavior of a physical NVM chip. Furthermore, when the control unit is upgraded, in the early stages of development, a physical control unit chip may not be available for debugging the microinstruction sequences. A media interface controller simulator is also needed to run the developed microinstruction sequences and interact with the storage media simulator. Still, we also require assistance in identifying erroneous behaviors in the microinstruction sequences and the media interface controller, and in verifying the correctness of the microinstruction sequences and the media interface controller.

[0015] Patent CN109684150A discloses a performance testing system for a memory chip controller, which includes a host control center, at least one memory chip controller simulation platform connected to the host control center, and at least one memory chip simulator corresponding to each memory chip controller simulation platform for NAND simulation. However, this patent does not specifically disclose the granularity of the simulation, the specific interaction process between the controller and the memory chip simulator, the internal structure of the memory chip simulator, and its implementation method.

[0016] The media interface controller applies signal sets to the flash channels to operate the individual NVM chips of the storage device, rather than directly operating the individual NVM chips. Therefore, it is desirable for the storage media simulator to not only simulate the NVM chips but also the flash channels, to receive and respond to the signal sets provided by the media interface controller or its simulator without requiring additional adjustments or adaptations. Summary of the Invention

[0017] In order to at least partially solve the technical problems mentioned in the background art, the present application provides a storage medium simulator, a storage medium simulation method, and a computer-readable storage medium thereof.

[0018] According to a first aspect of this application, a first storage medium simulator is provided, connected to a media interface controller simulator. The media interface controller simulator simulates and generates signal groups conforming to the NVM interface protocol corresponding to multiple clock cycles. The storage medium simulator is characterized by comprising an interface module, a target simulation module, an allocation module, and a response module. The interface module receives signal groups from the media interface controller simulator and identifies commands based on the signal groups. The target simulation module simulates targets in the storage medium and includes one or more sub-modules. When the command relates to accessing data stored in the storage medium, the sub-modules simulate logical units in the target and obtain the result of the command. The allocation module identifies the target sub-module corresponding to the command and sends the command to the target sub-module. The response module receives the result fed back by the target sub-module and sends the result to the media interface controller simulator through the interface module.

[0019] According to the first storage medium simulator of the first aspect of this application, a second storage medium simulator according to the first aspect of this application is provided. The second storage medium simulator further includes a processing module that, when a command accesses the same target submodule as a previous command, responds to the result of the previous command from the response module and sends the command from the interface module to the allocation module.

[0020] According to the second storage medium simulator of the first aspect of this application, a third storage medium simulator according to the first aspect of this application is provided, wherein the interface module determines whether the signal group conforms to the NVM interface protocol, and if so, sends the command to the processing module.

[0021] According to the third storage medium simulator of the first aspect of this application, a fourth storage medium simulator according to the first aspect of this application is provided, wherein the storage medium simulator simulates a flash memory channel connected to at least two NVM chips, and the NVM interface protocol is the ONFI protocol.

[0022] According to the second storage medium simulator of the first aspect of this application, a fifth storage medium simulator according to the first aspect of this application is provided, wherein when the command is not related to accessing the data stored in the storage medium, the processing module executes the command and sends the execution result to the media interface controller simulator through the interface module.

[0023] According to the first storage medium simulator of the first aspect of this application, a sixth storage medium simulator according to the first aspect of this application is provided, wherein when the command is a read command, the target submodule reads data from the corresponding address, and the result is data.

[0024] According to the first storage medium simulator of the first aspect of this application, a seventh storage medium simulator according to the first aspect of this application is provided, wherein when the command is a write command, the target submodule writes the data in the command to the corresponding address and generates a successful write signal, and the result is a successful write signal.

[0025] According to the first storage medium simulator of the first aspect of this application, an eighth storage medium simulator according to the first aspect of this application is provided, wherein when the interface module receives the result, it sends a first control signal to the media interface controller simulator to indicate that the result is ready to be sent, and responds to a second control signal from the media interface controller simulator that responds to the first control signal, and sends the result to the media interface controller simulator in a manner conforming to the NVM interface protocol based on the clock cycle.

[0026] According to the first storage medium simulator of the first aspect of this application, a ninth storage medium simulator according to the first aspect of this application is provided, wherein the storage medium simulator is a simulation model implemented in SystemC language.

[0027] According to the first storage medium simulator of the first aspect of this application, a tenth storage medium simulator according to the first aspect of this application is provided, wherein the media interface controller simulator is connected to a test case generator, the test case generator is used to generate test cases, and when the storage medium simulator identifies an error in a signal group, it generates error information and sends the error information to the test case generator.

[0028] According to the tenth storage medium simulator of the first aspect of this application, an eleventh storage medium simulator according to the first aspect of this application is provided, wherein a processing module generates error information and an interface module sends the error information to a test case generator.

[0029] According to the tenth storage medium simulator of the first aspect of this application, a twelfth storage medium simulator according to the first aspect of this application is provided, wherein the interface module performs an operation once in each clock cycle, obtains a set of data corresponding to the clock cycle from the media interface controller simulator, the multiple sets of data in multiple consecutive clock cycles form a signal group, and generates a command based on the multiple sets of data.

[0030] According to the twelfth storage medium simulator of the first aspect of this application, a thirteenth storage medium simulator according to the first aspect of this application is provided, wherein when multiple sets of data cannot generate commands, the processing module generates error information.

[0031] According to the first storage medium simulator of the first aspect of this application, a fourteenth storage medium simulator according to the first aspect of this application is provided, wherein the command triggering allocation module identifies whether the target submodule is idle; if so, it sends a command to the target submodule; if not, it suspends sending commands to the target submodule.

[0032] According to the fourteenth storage medium simulator of the first aspect of this application, a fifteenth storage medium simulator according to the first aspect of this application is provided, wherein a command triggers a target submodule to perform an operation to obtain the result of the command, wherein the target submodule simulates the time required to obtain the result of the command.

[0033] According to the fifteenth storage medium simulator of the first aspect of this application, a sixteenth storage medium simulator according to the first aspect of this application is provided, wherein the result triggers the response module to perform an operation to send the result to the interface module.

[0034] According to the first storage medium simulator of the first aspect of this application, a seventeenth storage medium simulator according to the first aspect of this application is provided, wherein the signal group includes a chip selection signal, and the allocation module identifies a target submodule according to the chip selection signal.

[0035] According to the first storage medium simulator of the first aspect of this application, an eighteenth storage medium simulator according to the first aspect of this application is provided, wherein during the period when the allocation module or the target submodule executes a command, the interface module receives the next signal group.

[0036] According to the eighteenth storage medium simulator of the first aspect of this application, a nineteenth storage medium simulator according to the first aspect of this application is provided, wherein during the period when the response module receives the result, the processing module or the allocation module executes the command for the next signal group.

[0037] According to the storage medium simulation method of the second aspect of this application, the storage medium simulation method simulates a target in the storage medium based on a target simulation module. The target simulation module includes one or more sub-modules, which are used to simulate logical units in the target and obtain the result of the command. The storage medium simulation method includes: receiving a signal group, wherein the signal group is multiple sets of data simulated by a media interface controller simulator based on the NVM interface protocol in multiple clock cycles; identifying a command based on the signal group; identifying the target sub-module corresponding to the command and sending the command to the target sub-module; obtaining the result of the command; and sending the result to the media interface controller simulator.

[0038] This application improves the granularity of simulation by simulating various components of the NVM interface controller, especially down to the precision of clock cycles, allowing for the description of behavior in each cycle. Furthermore, this application simulates a real flash memory channel by receiving signal groups. It also determines the correctness of signal transmission within the flash memory channel by acquiring error information and identifying the format and sequence of received commands using a storage medium simulator. Attached Figure Description

[0039] The above and other objects, features, and advantages of exemplary embodiments of this application will become readily understood by reading the following detailed description with reference to the accompanying drawings. In the drawings, several embodiments of this application are illustrated by way of example and not limitation, and the same or corresponding reference numerals denote the same or corresponding parts. Wherein:

[0040] Figure 1A This is an exemplary block diagram illustrating a storage device;

[0041] Figure 1B This is an exemplary block diagram illustrating the control components;

[0042] Figure 2A This is a schematic diagram showing a set of signals between the coupling medium interface controller and the flash memory channel of the NVM chip;

[0043] Figure 2B This is a schematic diagram showing a set of signals between the coupling medium interface controller and the flash memory channels of two NVM chips;

[0044] Figure 3 This is a schematic diagram illustrating the simulation platform of an embodiment of this application;

[0045] Figure 4 This is a schematic diagram of the signal group for a read command according to an embodiment of this application;

[0046] Figure 5 This is a schematic diagram illustrating a storage medium simulator according to an embodiment of this application;

[0047] Figure 6 This is a schematic diagram illustrating a storage medium simulator simulating parallel processing according to an embodiment of this application;

[0048] Figure 7 This is a flowchart illustrating a storage medium simulation method according to another embodiment of this application. Detailed Implementation

[0049] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0050] The media interface controller, acting as a device for information exchange between the control components and the NVM chip, is connected to the NVM chip via a set of signal lines. The meaning of these signal lines and the data transmission method are defined by the NVM chip's interface protocol. Figure 2A A schematic diagram showing a set of signals between the coupling medium interface controller and the flash memory channel of the NVM chip is presented.

[0051] Figure 2A In this example, the flash channel is connected to one NVM chip. Figure 2A The illustrated flash memory channel includes a group of 16 signal lines, comprising input / output signal line group 201 and logic control signal line group 202. Input / output signal line group 201 includes a DQ signal line group (including, for example, 8 signal lines) and a DQS signal line. Logic control signal line group 202 includes CE#, CLE, ALE, CLK (WE#), WP#, RE# (W / R), and SR (R / B#) signal lines, etc. The signal lines defined in different NVM chip interface protocols may vary slightly, but all are prior art in the relevant field. The media interface controller transmits storage media access commands to the NVM chip through this group of signal lines.

[0052] Figure 2B A schematic diagram showing a set of signals between the coupling medium interface controller and the flash memory channels of two NVM chips is presented.

[0053] Figure 2B In this example, the flash channel connects two NVM chips. The input / output signal line group 201 and the CLE, ALE, CLK, WP#, RE#, and SR signal lines in the flash channel are shared by the two NVM chips. Each of these signal lines is connected to the corresponding identical pin on both NVM chips. The flash channel includes CE0# and CE1# signal lines, which are connected to the chip enable pins of the two NVM chips respectively. Because some signal lines are shared, at any given time, only one of the two NVM chips coupled to the same flash channel can utilize the flash channel to transmit signals.

[0054] Figure 3 A schematic diagram of a simulation platform according to an embodiment of this application is shown.

[0055] The simulation platform according to the embodiments of this application is used for simulation Figure 1B The interaction process between the media interface controller and the NVM chip is used to verify whether there are any design errors in the media interface controller, such as verifying whether there are any errors in the microinstruction sequence executed by the media interface controller. Figure 3 The simulation platform shown in this embodiment includes a test case generator 301, a microinstruction sequence 302, a media interface controller simulator 303, and a storage media simulator 304.

[0056] Test case generator 301 is used to generate test cases. See also: Figure 1BThe test case generator 301, replacing the storage command processing unit 1023 of the control unit, provides input to the media interface controller simulator 303 and acquires the output of the media interface controller simulator 303 to identify whether the operation of the media interface controller simulator 303 meets expectations. For clarity, the input provided by the test case generator 301 to the media interface controller simulator 303 is referred to as a media interface command. The storage media simulator 304 provides, for example, a queue to receive the media interface commands provided by the test case generator 301, and provides the processing results of the media interface commands to the test case generator 301 through the queue.

[0057] A test case is a description of a task performed on the media interface controller simulator 303, including one or more media interface commands and the expected processing results of these media interface commands. During the processing of test cases generated by the test case generator 301, the media interface controller 303 generates storage media access commands that are provided to the storage media simulator 304.

[0058] Microinstruction sequence 302 is used to provide a series of microinstructions.

[0059] The media interface controller simulator 303 is connected to the test case generator 301 to simulate... Figure 1B The behavior of the media interface controller 1025 is described below. Specifically, the media interface controller simulator 303 receives test cases from the test case generator 301 and multiple sets of input microinstruction sequences. It executes these microinstruction sequences to send storage media access commands to the NVM chip or to read data or other information from the NVM chip. For example, the media interface controller simulator 303 can generate multiple clock cycles of signal groups conforming to the NVM interface protocol by executing the microinstruction sequences. The design of the media interface controller 1025 is converted into the media interface controller simulator 303 using existing conversion tools, thus the media interface controller simulator 303 exhibits the same behavior as the media interface controller 1025, with both having identical behavior in each clock cycle. Therefore, the microinstruction sequence 302 developed for the media interface controller 1025 can be directly executed by the media interface controller simulator 303, and the output provided by the media interface controller simulator 303 to the storage media simulator 304 describes the various signals transmitted on the flash memory channels coupled to the media interface controller simulator 303 and the storage media simulator 304 in each cycle.

[0060] according to Figure 3In some embodiments, the storage media simulator 304, in addition to providing responses to storage media commands to the media interface controller simulator 303 via the flash memory channel, may also be coupled to, for example, a test case generator 301, or other modules of the simulation platform, to report its operational status or identified anomalous behavior. For example, the signals or signal sequences applied by the media interface controller simulator 303 to the flash memory channel may not conform to the ONFI specification, or the operation of the storage media simulator 304 may be non-compliant (e.g., reapplying programming commands to a physical page that has already been written with data).

[0061] In this embodiment, the NVM interface protocol is the ONFI protocol. In the ONFI protocol, a command signal requires several cycles to be transmitted. Therefore, the media interface controller simulator 303 sends a set of data in each clock cycle. Multiple sets of data in multiple consecutive clock cycles form a signal group, and this signal group corresponds to a command. Figure 4 This diagram illustrates a signal group for a read command as defined in the ONFI protocol. The DQ value of the first cycle of the DQ signal is used to notify the storage medium simulator 304 of the read command initiation. The DQ values ​​of the following five cycles are used to indicate address data, informing the storage medium simulator 304 where to retrieve data. 30h is the DQ value of the last cycle of the DQ signal, indicating that the read command transmission has been completed, thus ending the read command signal transmission cycle. From the above, it can be seen that... Figure 4 In the embodiment shown, a read command requires 7 clock cycles (7 sets of data) of signal groups to be implemented.

[0062] The storage media simulator 304 is connected to the media interface controller simulator 303 to simulate NVM chips and / or flash memory channels. For example, it simulates an NVM chip receiving storage media access commands sent by the media interface controller simulator 303, performing corresponding operations based on the commands, and feeding back the results. If the command sent by the media interface controller simulator 303 is a read command, the storage media simulator 304 simulates receiving the read command, acquiring the corresponding data, and sending it to the media interface controller simulator 303. As an example, the storage media simulator 304 simulates at least two NVM chips coupled to a flash memory channel; furthermore, in addition to simulating NVM chips, the storage media simulator 304 also simulates the flash memory channels connected to the NVM chips.

[0063] A real media interface controller may be connected to multiple different NVM chips via multiple flash memory channels, for example, 8-channel or 16-channel. To simulate the relationship between a real media interface controller and NVM chips, the media interface controller simulator 303 in this embodiment can be coupled with multiple (at least two) storage media simulators 304. Figure 3 An illustrative example shows connections to four storage media simulators 304, each simulating an NVM chip connected to a flash channel. In other words, a media interface controller simulator 303 couples one or more simulated flash channels, which, in a real, non-simulated scenario, could be coupled to at least two NVM chips. Figure 3 In this example, the media interface controller simulator 303 couples four flash channels. Each flash channel simulated by the storage media simulator 304 may have the same or different configurations; for example, the number of NVM chips and / or storage capacity on each flash channel may be the same or different.

[0064] As an example, each model in this simulation platform is implemented in SystemC language. The media interface controller simulator 303 is a SystemC model generated based on the existing HDL code of the media interface controller 1025.

[0065] Figure 5 The schematic diagram of the storage medium simulator 304 of this embodiment is shown. The storage medium simulator 304 includes an interface module 501, a processing module 502, an allocation module 503, a target simulation module 504, and a response module 505.

[0066] The interface module 501 acquires signals from the media interface controller simulator 303 in each cycle, receives signal groups from the media interface controller simulator 303, identifies the cycle type of each cycle based on the acquired signals, and then determines whether the signal group conforms to the ONFI protocol. Then... Figure 4 Taking the signal group as an example, the cycles represented by the DQ signal are "CMD-ADDR-ADDR-ADDR-ADDR-ADDR-CMD", where "CMD" represents the command cycle and "ADDR" represents the address cycle. The DQ values ​​in the two consecutive "CMD" cycle types are 0x00h and 0x30h, respectively. The interface module 501 identifies this as a read command based on the cycle type sequence "CMD-ADDR-ADDR-ADDR-ADDR-ADDR-CMD". On the one hand, it extracts that the current command is a read command, and on the other hand, it extracts the read addresses as C1, C2, R1, R2, and R3. These read addresses, when concatenated, are the physical addresses of the storage medium to be accessed.

[0067] If one or more received cycle types conform to, for example, the ONFI protocol, the interface module 501 sends a command (here, the command is used for internal interaction within the storage medium simulator 304, and its form does not necessarily have to be the same as the storage medium access command received by the storage medium simulator 304) to the processing module 502; if it does not conform to the ONFI protocol, the storage medium simulator 304 generates an error message. The storage medium simulator 304 can send the error message to the test case generator 301 or other modules of the simulation platform for determining the cause of the signal group error.

[0068] For example, error messages are generated and sent by interface module 501. Interface module 501 performs an operation once per cycle, obtaining a set of signals corresponding to that cycle from media interface controller simulator 303. Multiple sets of signals across multiple consecutive clock cycles form the aforementioned signal group, and commands are generated based on these signal groups. For example... Figure 4 For example, interface module 501 continuously receives 7 sets of signals for 7 cycles, forming a signal group, and decodes the read command including the physical address. When the signal group is faulty and cannot generate a command, interface module 501 generates error information and sends it to test case generator 301 or other modules of the simulation platform.

[0069] Processing module 502 receives and processes commands from interface module 501. When the command is unrelated to accessing the data stored on the storage medium, such as a set feature command or a reset command, processing module 502 directly processes such commands and sends the execution result to media interface controller simulator 303 through interface module 501. When the command is related to accessing the data stored on the storage medium, the command is sent to allocation module 503. Understandably, the execution result of the commands sent by interface module 501 to media interface controller simulator 303 also simulates the various cycle signals generated on the flash memory channel and conforms to requirements such as the ONFI protocol.

[0070] The allocation module 503 identifies the logical unit to be accessed by the command based on the physical address and sends the command to the submodule that simulates the logical unit.

[0071] The target simulation module 504 simulates the target in the NVM chip, simulating the logic units in the target and generating the results of command processing (e.g., data read by a read command, data written by a programming command, and optionally, error bits generated during the read / programming command processing). Multiple NVM chips may be included on the flash memory channel, and each NVM chip may include multiple targets. Correspondingly, there may be multiple target simulation modules 504. The figure exemplarily shows two target simulation modules 504 (i.e., two targets). Since each target in an actual NVM chip includes one or more logic units 109, each target simulation module 504 correspondingly includes one or more sub-modules. The example in the figure shows each target simulation module 504 including two sub-modules: sub-module 1 and sub-module 2, and sub-module 3 and sub-module 4. Each sub-module simulates one logic unit 109. The allocation module 503 sends commands to the target sub-modules. After completing the command, the target sub-module sends the result to the response module 505. The target sub-module refers to the sub-module corresponding to the logic unit accessed by the command.

[0072] After the response module 505 receives the result fed back by the target submodule, it sends the result to the interface module 501, which then sends the result to the media interface controller simulator 303. At the same time, it notifies the processing module 502 that the task of the signal group has been completed.

[0073] The following will further explain the operation of each module by executing commands related to accessing the data stored on the storage medium.

[0074] Taking a read command as an example, the interface module 501 identifies the read command from the signal group and sends it to the processing module 502. If two consecutive read commands access the same target submodule (logic unit), and the subsequent read command is received before the previous command has finished executing, this does not meet the requirements of the NVM chip. Similarly, the NVM chip also requires that read, program, and erase commands not be applied to the same logic unit before the previous programming command has finished executing, but commands such as program-suspend can be applied.

[0075] As a simulation platform, the storage medium simulator 304 according to embodiments of this application identifies such cases that do not meet the requirements of the NVM chip and reports errors. However, this situation may occur due to defects in the microinstruction sequence or other reasons, therefore, the storage medium simulator 304 according to embodiments of this application also performs simulation processing on it.

[0076] One optional processing method is that the processing module 502 maintains a submodule status list, which records the current status (e.g., busy, idle) of all submodules of the storage medium simulator. Optionally, the submodule status list also records the command type (read, program, erase, etc.) being processed by the busy submodule. In response to the processing module 502 sending a command to one of the submodules, the status of that submodule is set to busy in the submodule status list, and optionally, the command type sent to that submodule is also recorded. In response to the processing module 502 receiving an indication from the response module 505 that a submodule has completed processing a command, the status of that submodule is set to idle in the submodule status list. When processing, for example, a read command, the processing module 502 identifies the submodule to be accessed based on the physical address in the read command and queries the submodule status list for the status of that submodule. If a submodule is busy, or if a submodule is busy and the type of command it is processing requires that the submodule can no longer process the current command, the processing module 502 will not send the current read command to the allocation module 503, and optionally will also report the error to the test case generator 301 or other modules of the simulation platform. If the submodule is idle, the processing module 502 will send the read command from the interface module 501 to the allocation module 503. In this processing mode, the processing module 502 determines the timing of sending the read command, and the allocation module 503 does not make a judgment. As an example, the preceding command that accesses the same target submodule as the read command can be sequential in time with the read command, such as the preceding command being the previous command of the read command; or they can be discontinuous in time, such as when the interface module 501 sends four commands to the processing module 502 in chronological order, namely command 1, command 2, command 3 and command 4 (the numbers indicate the order in which the interface command 501 sends the commands to the processing module 502). If the read command refers to command 3, then the preceding command can be either command 1 or command 2.

[0077] Another optional processing method is that the processing module 502 sends the read command directly to the allocation module 503 without making any judgment. The read command triggers the allocation module 503 to identify the target submodule from submodules 1 to 4 based on the physical address accessed by the read command, and determine whether the target submodule is in a busy or idle state. For example, the allocation module 503 maintains a list of submodule statuses, or the submodule provides an interface to the allocation module 503 to query its busy / idle status. The allocation module 503 obtains the busy / idle status of the target submodule through this interface, and optionally the type of command being executed by the target submodule. If the target submodule is in an idle state, the allocation module 503 sends the read command to the target submodule; if the target submodule is in a running state, the allocation module 503 does not send a command to the target submodule and reports an error. Under this judgment mechanism, the processing module 502 does not make any judgment, and the allocation module 503 determines the timing of sending the read command.

[0078] When the target submodule is idle, regardless of whether other submodules are busy or idle, a read command will be sent to the target submodule to trigger it to process the read command, such as reading the corresponding data from the corresponding physical address. Submodules 1 to 4 of the storage medium simulator 304 can simulate the time required for the storage medium to obtain the result of the read command. After reading the data, the target submodule sends back the result (data, read indication, and read data) to the response module 505. In response, the response module 505 performs an operation to send the result to the interface module 501 and notifies the processing module 502 that the command has been completed. As an example, in one embodiment, the target submodule is used to simulate the behavior of logic units, but the data stored in each logic unit is stored in memory in this simulation platform. When the target submodule receives a read command allocated by the allocation module 503, it reads the corresponding data from the corresponding address in memory according to the command. In another implementation, the target submodule does not store the data of the simulated logic unit. For example, for a programming command, it discards the data to be written to the logic unit and, after simulating the processing time of the programming command (e.g., 1 ms), indicates to the response module 505 that the programming command was successfully processed (or failed). Next, when the target submodule receives a read command, after simulating the processing time of the read command (e.g., 70 µs), it indicates to the response module 505 that the read command was successfully processed (or failed) and generates specified data or random data as the read result of the read command. Optionally, the submodule also simulates the storage characteristics of the storage medium (e.g., adding specified error bits to the read result, or the rate of added error bits changing over time).

[0079] After receiving the result, interface module 501 sets the state of a specified signal line of the flash memory channel, i.e., the first control signal, according to the NVM chip's interface protocol. This allows media interface controller simulator 303 to know that the read command has been processed and the data read by the read command can be sent when it reads the state of the signal line. Media interface controller simulator 303 sends a signal indicating that data has been read (i.e., the second control signal) back to interface module 501. Interface module 501 responds to the signal indicating that data has been read and periodically sends the read data to media interface controller simulator 303 in a manner conforming to the ONFI protocol. The above describes the process of storage media simulator 304 simulating the operation of a read command.

[0080] Taking the write command as an example, the interface module 501 decodes the programming command from the signal group and sends it to the processing module 502. Similarly, in this embodiment, the timing of sending the programming command can be determined by the processing module 502 or the allocation module 503, which will not be elaborated further.

[0081] When the target submodule is idle, a programming command is sent to it, and the submodule processes the command, such as writing data to the corresponding address. Sub-interface modules 1 to 4 of the storage medium simulator 304 can simulate the time required for the NVM chip to process the programming command (e.g., 1 ms). After processing the programming command, the target submodule generates a success (or failure) signal and sends it to the response module 505. This triggers the response module 505 to perform an operation, sending the corresponding result to the interface module 501 and notifying the processing module 502 that the command has been completed. In one implementation, the target submodule does not store the data to be written by the programming command; instead, it discards the data to be written to the logic unit and, after simulating the processing time of the programming command (e.g., 1 ms), indicates to the response module 505 that the programming command processing was successful (or failed).

[0082] When the interface module 501 receives the result, it sets the state of a specified signal line of the flash memory channel according to the NVM chip's interface protocol, so that the media interface controller simulator 303 can know that the programming command has been processed when it reads the state of the signal line. The above is the process of the storage media simulator 304 simulating the execution of the write command.

[0083] In an optional implementation, the flash memory channel simulated by the storage medium simulator is coupled to, for example, two or more targets. Interface module 501 identifies which target corresponds to the acquired signal group based on which of the multiple chip select signals (e.g., CE0# and CE1#) is valid during the signal acquisition period, and then determines which target simulator should process the command carried by the acquired signal group. Optionally, interface module 501 also identifies whether the chip select signal conforms to the requirements of the NVM chip interface protocol; for example, at any given time, at most one chip select signal is valid, and if two or more chip selects are valid in a given cycle, interface module 501 reports an error. Still optionally, in each cycle of acquiring signals from the flash memory channel, interface module 501 further identifies whether the chip select signal is valid, and only acquires and processes (other) signals from the flash memory channel when a valid chip select signal exists. Alternatively, for a valid command, the valid chip select signal should not change over its multiple cycles (e.g., it should not change from CE0# to CE1# valid). The interface module 501 also recognizes a valid command where the valid chip select signal does not change over its multiple cycles, and reports an error otherwise.

[0084] In one implementation, the simulation platform is implemented using the SystemC hardware description language. Figure 5Each module in the storage medium simulator 405 is implemented as a "Module" (referred to as a SystemC module) provided by the SystemC language. Since SystemC supports parallel processing between SystemC modules, the modules of the storage medium simulator 304 in this embodiment can work in parallel. For example, the interface module 501, processing module 502, allocation module 503, target simulation module 504, and response module 505 can each work independently. For example, the interface module 501 initiates an execution in response to a period or clock signal obtained from the flash memory channel. The period or clock signal obtained from the flash memory channel is provided by the media interface controller simulator 303, or is the same as the period or clock signal applied to the media interface controller simulator 303. The operation of the other modules of the storage medium simulator 405, except for the interface module 501, is not directly related to the clock cycle, but rather triggers an execution based on the received signals, commands, or wait times provided by timers. For example, interface module 501 is triggered by a state change of the CLK signal or other signals of the flash memory channel; processing module 502 is triggered by receiving a command from interface module 501; allocation module 503 is triggered by receiving a command from processing module 502; response module 505 is triggered by receiving a result; and sub-modules are triggered by receiving commands from allocation module. Optionally, they may also be triggered based on the expiration of the simulated command processing time. At any given time, the above modules can work in parallel.

[0085] Figure 6 The diagram illustrates parallel processing simulated by the storage medium simulator 304. Interface module 501 receives signals, for example, in each cycle, and receives a signal group for read command 1 (R1) within a certain time period. After generating a command, it sends it to processing module 502. Read command 1 triggers processing module 502, which, after determining that the target submodule (e.g., submodule 1) is idle, sends read command 1 to allocation module 503. Read command 1 triggers allocation module 503 to send the command to submodule 1 according to the physical address, and submodule 1 reads the data at that physical address. After submodule 1 reads the data required by read command 1, it sends the result of read command 1 to response module 505. The result triggers response module 505, which sends the result back to interface module 501.

[0086] During the processing of read command 1 by submodule 1, interface module 501 receives the signal group of read command 2 (R2), generates a command, and sends it to processing module 502. Similarly, during the processing of read command 1 by submodule 1, read command 2 triggers processing module 502, which, after determining that the target submodule (e.g., submodule 2) is in an idle state, sends read command 2 to allocation module 503. During the processing of the result of read command 1 by response module 505, read command 2 triggers allocation module 503 to send read command 2 to submodule 2 according to the physical address. During the reading of data at that physical address by submodule 2, interface module 501 sends the result of read command 1 to media interface controller simulator 303.

[0087] from Figure 6 As the examples illustrate, apart from interface module 501, other modules are triggered to run based on the output of the preceding module. When a module is executing a command, the preceding module may be executing the next command, while the following module may still be executing the previous command. For example, while allocation module 503 or target submodule is executing a command, interface module 501 may be receiving the next signal group. Similarly, while response module 505 is receiving a result, processing module 501 or allocation module 503 may be executing the command for the next signal group. Such parallel simulation will cause some changes to the processing flow of storage medium simulator 304. Taking interface module 501 as an example, although media interface controller simulator 303 sends the signal groups of read command 1 and read command 2 sequentially, from... Figure 6 It can be seen that interface module 501 first processes the reception of read command 1, then processes the reception of read command 2, and then processes the transmission of the result of read command 1.

[0088] This embodiment enables cycle-level granularity, allowing for rapid and precise verification of the correctness of microinstruction sequences. It can also identify the correctness of signal groups, proceeding with subsequent processing when correct and providing error feedback to the test case generator or other modules of the simulation platform when errors occur. Furthermore, this embodiment simulates parallel processing of various modules, enabling more accurate detection of design flaws.

[0089] Another embodiment of this application is a storage medium simulation method, in which a storage medium simulator simulates the response of a media interface controller simulator of an NVM chip by executing the method. Figure 7 A flowchart illustrating this embodiment is shown.

[0090] In step 701, a signal group is received, wherein the signal group is a plurality of signals simulated by the media interface controller simulator over multiple clock cycles based on the NVM interface protocol. In this embodiment, the NVM interface protocol is, for example, the ONFI protocol. Specifically, this step samples the signal in one or more cycles, performing an operation once per cycle to obtain a set of signals corresponding to that clock cycle from the media interface controller simulator, and the plurality of signal groups over multiple consecutive clock cycles form the aforementioned signal group.

[0091] In step 702, the cycle type of each cycle is identified based on the acquired signal to determine whether the signal group conforms to the ONFI protocol. If it conforms to the ONFI protocol, step 703 is executed, identifying, for example, the physical address to be accessed based on the signal group. If it does not conform to the ONFI protocol, step 704 is executed, generating error information and sending the error information to the test case generator or other modules of the simulation platform.

[0092] In step 705, the target submodule corresponding to the command is identified, and the command is sent to the target submodule. For example, based on the physical address identified by the command signal group, the logic unit corresponding to the physical address is determined, and the sub-analog corresponding to the logic unit is taken as the target submodule.

[0093] After executing step 705, step 706 is executed to obtain the command result. Optionally, the target submodule also simulates the time required for the NVM chip to process the command. The command processing result is generated only after a specified time.

[0094] In step 707, the notification command has been completed.

[0095] In step 708, the result is sent to the media interface controller simulator.

[0096] The storage medium simulation method of this embodiment has the function of simulating parallel processing, that is, each step can work independently. Except for step 701, which is based on periodic operation, the other steps are not directly related to the clock cycle, but are triggered based on the completion of the previous step. When a certain step is executing a command, the preceding step may be executing the next command, while the subsequent step may still be executing the previous command.

[0097] This embodiment enables cycle-level granularity, rapidly verifying the correctness of microinstruction sequences and identifying the correctness of signal groups. If correct, subsequent processing is performed; if incorrect, error information is provided. Furthermore, this embodiment possesses the ability to simulate parallel hardware processing, thereby accurately identifying design flaws.

[0098] Another embodiment of this application is a computer-readable storage medium storing computer program code for a storage medium emulation method. When the computer program code is run by a processor, it executes... Figure 7 The method. In some implementation scenarios, the integrated unit described above can be implemented as a software program module. If implemented as a software program module and sold or used as an independent product, the integrated unit can be stored in a computer-readable storage memory. Based on this, when the solution of this application is embodied in the form of a software product (e.g., a computer-readable storage medium), the software product can be stored in a memory, which may include several instructions to cause a computer device (e.g., a personal computer, a server, or a network device, etc.) to execute some or all of the steps of the method described in the embodiments of this application. The aforementioned memory may include, but is not limited to, various media capable of storing program code, such as USB flash drives, flash drives, read-only memory (ROM), random access memory (RAM), portable hard drives, magnetic disks, or optical disks.

[0099] It should be noted that, for the sake of brevity, this application describes some methods and their embodiments as a series of actions and combinations thereof. However, those skilled in the art will understand that the solution of this application is not limited to the order of the described actions. Therefore, based on the disclosure or teachings of this application, those skilled in the art will understand that some steps can be performed in other orders or simultaneously. Furthermore, those skilled in the art will understand that the embodiments described in this application can be considered as optional embodiments, that is, the actions or modules involved are not necessarily essential for the implementation of one or more solutions of this application. In addition, depending on the solution, the description of some embodiments in this application also has different emphases. In view of this, those skilled in the art will understand that parts not described in detail in a certain embodiment of this application can also be referred to the relevant descriptions of other embodiments.

[0100] The embodiments of this application have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The description of the above embodiments is only for the purpose of helping to understand the method and core ideas of this application. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. A storage medium simulator connected to a media interface controller simulator, wherein the media interface controller simulator simulates and generates multiple clock cycles corresponding to signal groups conforming to the NVM interface protocol, characterized in that, The storage medium simulator includes: The interface module receives the signal group from the media interface controller simulator and identifies the command based on the signal group; A target simulation module is used to simulate a target in a storage medium. The target simulation module includes one or more sub-modules. When the command relates to accessing data stored in the storage medium, the sub-modules are used to simulate logical units in the target and obtain the result of the command. The allocation module identifies the target submodule corresponding to the command and sends the command to the target submodule. The response module receives the result fed back by the target submodule and sends the result to the media interface controller simulator through the interface module; When the command accesses the same target submodule as the previous command, the processing module responds to the result of the previous command from the response module and sends the command from the interface module to the allocation module.

2. The storage medium simulator according to claim 1, wherein the interface module determines whether the signal group conforms to the NVM interface protocol, and if so, sends the command to the processing module.

3. The storage medium simulator according to any one of claims 1-2, wherein the storage medium simulator simulates a flash memory channel, the flash memory channel is connected to at least two NVM chips, and the NVM interface protocol is the ONFI protocol.

4. The storage medium simulator according to any one of claims 1-2, wherein the interface module receives the result, sends a first control signal to the media interface controller simulator to indicate that the result is ready to be sent, and responds to a second control signal from the media interface controller simulator that responds to the first control signal, and sends the result to the media interface controller simulator in a manner conforming to the NVM interface protocol based on a clock cycle.

5. The storage medium simulator according to any one of claims 1-2, wherein the interface module performs an operation once per clock cycle, obtains a set of data corresponding to the clock cycle from the media interface controller simulator, the multiple sets of data for multiple consecutive clock cycles form the signal group, and the command is generated based on the multiple sets of data.

6. The storage medium simulator according to any one of claims 1-2, wherein the command triggers the allocation module to identify whether the target submodule is idle; if so, the command is sent to the target submodule; if not, the sending of the command to the target submodule is paused.

7. The storage medium simulator according to any one of claims 1-2, wherein during the execution of the command by the allocation module or the target submodule, the interface module receives the next group of signals.

8. The storage medium simulator of claim 7, wherein during the period when the response module receives the result, the processing module or the allocation module executes the command for the next signal group.

9. A storage medium simulation method, wherein the storage medium simulation method simulates a target in a storage medium based on a target simulation module, the target simulation module comprising one or more sub-modules, the sub-modules being used to simulate logical units in the target and to obtain command results, characterized in that, The storage medium simulation method includes: Receive signal groups, wherein the signal groups are multiple sets of data simulated by the media interface controller simulator based on the NVM interface protocol over multiple clock cycles; The command is identified based on the signal group; When the command accesses the same target submodule as the previous command, respond to the execution result of the previous command, and then send the current command to the allocation module for target submodule identification; Identify the target submodule corresponding to the command and send the command to the target submodule; Obtain the result of the command; The results are sent to the media interface controller simulator.

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