Method of monitoring a semiconductor element

Abstract

A semiconductor device monitoring method includes: providing a semiconductor device, the semiconductor device including a first metal layer, a second metal layer, and a conductive via connected between the first metal layer and the second metal layer; placing the semiconductor device in a first state, wherein the first metal layer is electrically connected to a first conductive element and the second metal layer is electrically connected to a second conductive element; placing the semiconductor device in a second state, wherein the first metal layer is electrically connected to the second conductive element and the second metal layer is electrically connected to a third conductive element; and electrically connecting a power supply component and a ground component of a test device to the conductive elements to obtain first voltage and current values and second voltage and current values of the semiconductor device placed in the first state and the second state. The method can avoid material waste and save time.

Description

Technical Field

[0001] This invention relates to a method for monitoring semiconductor devices. Background Technology

[0002] Before wafer-level semiconductor devices are shipped after manufacturing, they undergo a series of wafer acceptance tests (WAT). These tests include electrical tests for NMOS devices, PMOS devices, resistors, capacitors, bipolar junction transistors (BJTs), and more. In particular, for resistance testing, the industry typically uses a four-wire measurement method (Kelvin measurement) to measure the voltage and current values ​​of semiconductor devices (e.g., test element groups (TEGs) located on the wafer dicing track). The resistance value of the semiconductor device is then calculated from the measured voltage and current values. By analyzing the resistance value, it is possible to further monitor whether there is overlay shift between the metal layers and conductive vias in the semiconductor device due to manufacturing defects, thereby determining the overall manufacturing condition of the wafer's die.

[0003] However, due to the numerous factors that influence the measured resistance of semiconductor components, even current resistance testing methods cannot definitively deduce the presence of coverage shift based solely on the measured resistance value. Furthermore, current resistance testing methods can only detect coverage shift in a single direction on the production line. In other words, if the semiconductor component actually exhibits coverage shift in a direction different from the aforementioned single direction, current resistance testing methods may fail to detect this shift, leading to problems only being discovered during subsequent integrated circuit wafer packaging processes, resulting in waste. Therefore, another solution in the industry is to use scanning electron microscopy (SEM) images after the aforementioned resistance testing to determine the exact direction of the coverage shift. However, waiting for SEM image output is time-consuming, thus impacting the production efficiency of integrated circuit wafers.

[0004] Therefore, how to propose a monitoring method for semiconductor components, especially a monitoring method that can more effectively monitor coverage offset problems on the production line, is one of the problems that the industry urgently needs to invest research and development resources to solve. Summary of the Invention

[0005] In view of this, one object of the present invention is to provide a monitoring method for semiconductor devices that can solve the above-mentioned problems.

[0006] To achieve the above objectives, according to one embodiment of the present invention, a method for monitoring a semiconductor element includes: providing a semiconductor element, the semiconductor element comprising a first metal layer, a second metal layer, and one or more conductive connecting pillars, the second metal layer being disposed above the first metal layer, and the one or more conductive connecting pillars being connected between the first metal layer and the second metal layer; placing the semiconductor element in a first state, wherein the first metal layer is electrically connected to a first conductive element and the second metal layer is electrically connected to a second conductive element; placing the semiconductor element in a second state, wherein the first metal layer is electrically connected to the second conductive element and the second metal layer is electrically connected to a third conductive element; electrically connecting a power supply component and a ground component of a test element to the first conductive element and the second conductive element, respectively, to obtain a first voltage value and a first current value of the semiconductor element placed in the first state; and electrically connecting the power supply component and the ground component of the test element to the second conductive element and the third conductive element, respectively, to obtain a second voltage value and a second current value of the semiconductor element placed in the second state.

[0007] In one or more embodiments of the present invention, the phase difference between the first-state semiconductor element and the second-state semiconductor element is 90 degrees.

[0008] In one or more embodiments of the present invention, the first conductive element, the second conductive element, and the third conductive element are electrical testing pads.

[0009] In one or more embodiments of the present invention, semiconductor elements of a first state are arranged in a first direction, and semiconductor elements of a second state are arranged in a second direction.

[0010] In one or more embodiments of the present invention, the test element is a probe station.

[0011] According to one embodiment of the present invention, the step of electrically connecting the power supply component and the grounding component of the test element to the first conductive element and the second conductive element, respectively, is performed after the step of placing the semiconductor element in the first state and before the step of placing the semiconductor element in the second state.

[0012] In one or more embodiments of the present invention, the step of electrically connecting the power supply component and the grounding component of the test element to the second conductive element and the third conductive element, respectively, is performed after the step of placing the semiconductor element in the second state.

[0013] In one or more embodiments of the present invention, the method for monitoring a semiconductor element further includes: placing the semiconductor element in a second state, wherein a first metal layer is electrically connected to a third conductive element and a second metal layer is electrically connected to a fourth conductive element; and electrically connecting a power supply component and a grounding component of a test element to the third conductive element and the fourth conductive element, respectively, to obtain a second voltage value and a second current value of the semiconductor element placed in the second state.

[0014] In one or more embodiments of the present invention, the step of electrically connecting the power supply component and the grounding component of the test element to the third conductive element and the fourth conductive element, respectively, is performed after the step of electrically connecting the power supply component and the grounding component of the test element to the first conductive element and the second conductive element, respectively.

[0015] In one or more embodiments of the present invention, the step of electrically connecting the power supply component and the grounding component of the test element to the third conductive element and the fourth conductive element, respectively, is performed after the step of placing the semiconductor element in the second state.

[0016] In summary, in the semiconductor device monitoring method of the present invention, since the semiconductor device is placed in a second state after acquiring the first voltage and first current values ​​of the semiconductor device in the first state, and then the second voltage and second current values ​​are acquired, the resistance values ​​of the semiconductor device in several directions are calculated respectively. This allows the semiconductor device to reliably detect coverage offset problems on the production line and determine in which direction the coverage offset occurred. Furthermore, in the semiconductor device monitoring method of the present invention, since the voltage and current values ​​of the semiconductor device are measured on the production line when placed in the first and second states respectively, the monitor can promptly report the detected problems to the front-end process technicians. This not only avoids material waste during the semiconductor device manufacturing process but also saves process time.

[0017] The above description is only used to illustrate the problem to be solved by the present invention, the technical means to solve the problem, and the effects produced, etc. The specific details of the present invention will be described in detail in the following embodiments and related drawings. Attached Figure Description

[0018] To make the above and other objects, features, advantages and embodiments of the present invention more apparent and understandable, the accompanying drawings are described below:

[0019] Figure 1 A flowchart illustrating a method for monitoring a semiconductor device according to an embodiment of the present invention is provided.

[0020] Figure 2AA schematic diagram illustrating a wafer according to an embodiment of the present invention.

[0021] Figure 2B A partially enlarged view of a wafer according to an embodiment of the present invention is shown.

[0022] Figure 3 A schematic diagram illustrating a semiconductor element according to an embodiment of the present invention is provided.

[0023] Figure 4 A schematic diagram illustrating a semiconductor element according to an embodiment of the present invention is provided.

[0024] Figure 5 This is a schematic diagram illustrating the monitoring stage of a semiconductor device monitoring method according to an embodiment of the present invention.

[0025] Figure 6 This is a schematic diagram illustrating the monitoring stage of a semiconductor device monitoring method according to an embodiment of the present invention.

[0026] Figure 7 This is a schematic diagram illustrating the monitoring stage of a semiconductor device monitoring method according to an embodiment of the present invention.

[0027] Figure 8 This is a schematic diagram illustrating the monitoring stage of a semiconductor device monitoring method according to an embodiment of the present invention.

[0028] Figure 9 This is a schematic diagram illustrating the monitoring stage of a semiconductor device monitoring method according to an embodiment of the present invention.

[0029] Figure 10 This is a schematic diagram illustrating the monitoring stage of a semiconductor device monitoring method according to an embodiment of the present invention.

[0030] Figure 11 A flowchart illustrating a method for monitoring a semiconductor device according to an embodiment of the present invention is provided. Detailed Implementation

[0031] The following describes several embodiments of the present invention with reference to the accompanying drawings. For clarity, many practical details will be described in the following description. However, it should be understood that these practical details are not intended to limit the invention. That is, in some embodiments of the invention, these practical details are not essential. Furthermore, for the sake of simplicity, some conventional structures and elements will be shown in the drawings in a simple schematic manner. The same reference numerals will be used to denote the same or similar elements in all the drawings.

[0032] Spatially relative terms (e.g., "below," "below," "under," "above," "above," etc.) are used here to simply describe the relationship between an element or feature as shown in the figure and another element or feature. In use or operation, these spatially relative terms cover different orientations of the device, in addition to the orientation shown in the figure. Furthermore, these devices are rotatable (rotating 90 degrees or other angles), and the spatially relative descriptive terms used herein can be interpreted accordingly. Additionally, the term "made of" can mean "contains" or "composes of."

[0033] Please refer to Figure 1 This is a flowchart illustrating a semiconductor device monitoring method 100 according to an embodiment of the present invention. Figure 1 As shown, the semiconductor device monitoring method 100 includes steps S101, S102, S103, S104, and S105. This document describes in detail... Figure 1 Please refer to the following when referring to steps S101 to S105: Figure 2A , Figure 2B as well as Figures 3 to 10 .

[0034] The following describes in detail the operations of steps S101, S102, S103, S104, and S105.

[0035] First, perform step S101: provide a semiconductor element.

[0036] Please refer to Figure 2A as well as Figure 2B It provides a semiconductor element 200. In this embodiment, the semiconductor element 200 is located on the dicing track SL of the wafer W. More specifically, as Figure 2A As shown, the wafer W includes a plurality of wafers D and cleaving paths SL surrounding these wafers D, wherein the cleaving paths SL define the extent of the wafers D. In some embodiments, the wafer W includes a plurality of laterally extending cleaving paths SL and a plurality of vertically extending cleaving paths SL. In some embodiments, each laterally extending cleaving path SL is perpendicular to each vertically extending cleaving path SL. In some embodiments, the cleaving paths SL serve as cleaving paths for the manufacturer to cut the wafer W into a plurality of separate wafers D.

[0037] Please refer to the following: Figure 2B It depicts a magnified view of a portion of wafer W. For example... Figure 2B As shown, the dicing track SL further includes a plurality of semiconductor elements 200 and a plurality of conductive elements P. For example, the plurality of semiconductor elements 200 and the plurality of conductive elements P are arranged alternately on each laterally extending dicing track SL and each longitudinally extending dicing track SL. In other words, as... Figure 2BAs shown, semiconductor element 200 is located between two conductive elements P, and conductive element P is located between two semiconductor elements 200.

[0038] In some implementations, semiconductor element 200 may be a test element group (TEG) located on the dicing track SL. Operators / monitors can determine the manufacturing status of the remaining semiconductor elements in the die by testing the semiconductor element 200 used as a test element group.

[0039] In some embodiments, the conductive element P can be used as an electrical test pad for electrical testing of the semiconductor element 200. Specifically, by contacting a test element, such as a probe, with two adjacent conductive elements P, electrical parameters (e.g., voltage, current, etc.) of the semiconductor element 200 located between the two conductive elements P can be obtained.

[0040] It should be noted that, as Figure 2A as well as Figure 2B The size, shape, arrangement, and quantity of the wafer D, cleaving track SL, semiconductor element 200, and conductive element P shown are merely illustrative examples and are not intended to limit the size, shape, arrangement, and quantity of the wafer D, cleaving track SL, semiconductor element 200, and conductive element P.

[0041] Please refer to Figure 3 .like Figure 3 As shown, a semiconductor device 300 is provided. It should be noted that... Figure 3 Semiconductor element 300 and Figure 2B The semiconductor element 200 is substantially the same. In this embodiment, the semiconductor element 300 includes a first metal layer 310, a dielectric material layer 320, a second metal layer 330, and a conductive connecting post 340. The dielectric material layer 320 is disposed on the first metal layer 310. The second metal layer 330 is disposed above the first metal layer 310 and on the dielectric material layer 320, such that the dielectric material layer 320 is disposed between the first metal layer 310 and the second metal layer 330. The conductive connecting post 340 penetrates the dielectric material layer 320 and connects the first metal layer 310 and the second metal layer 330.

[0042] In some embodiments, the first metal layer 310 may be made of a metallic material such as copper or tungsten, but the invention is not limited thereto. In some embodiments, the first metal layer 310 may be made of any conductive metallic material. Alternatively, in some embodiments, the first metal layer 310 may also be made of a conductive material such as polysilicon, but the invention is not limited thereto. In some embodiments, the first metal layer 310 may be made of any conductive material.

[0043] In some embodiments, the dielectric material layer 320 may be an oxide layer formed of a material such as SiO2, but the invention is not limited thereto. In some embodiments, the dielectric material layer 320 may be a nitride layer formed of a material such as silicon nitride, but the invention is not limited thereto. In some embodiments, the dielectric material layer 320 may be made of any dielectric material that can serve as a dielectric layer (e.g., a low-k material).

[0044] In some embodiments, the second metal layer 330 may be made of a metallic material such as copper or tungsten, but the invention is not limited thereto. In some embodiments, the second metal layer 330 may be made of any conductive metallic material. Alternatively, in some embodiments, the second metal layer 330 may be made of a conductive material such as polysilicon, but the invention is not limited thereto. In some embodiments, the second metal layer 330 may be made of any conductive material.

[0045] In some embodiments, the conductive connecting post 340 may be made of a metallic material such as copper or tungsten, but the invention is not limited thereto. In some embodiments, the conductive connecting post 340 may be made of any conductive metallic material. Alternatively, in some embodiments, the conductive connecting post 340 may be made of a conductive material such as polysilicon, but the invention is not limited thereto. In some embodiments, the conductive connecting post 340 may be made of any conductive material.

[0046] In some embodiments, the first metal layer 310, the dielectric material layer 320, the second metal layer 330, and the conductive connecting pillar 340 can be formed by, for example, physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), or other possible processes. This invention is not intended to limit the methods of forming the first metal layer 310, the dielectric material layer 320, the second metal layer 330, and the conductive connecting pillar 340.

[0047] Please refer to Figure 4 .like Figure 4 As shown, a top view of an exemplary semiconductor device 300 is illustrated. In this embodiment, at least one of the first metal layer 310 and the second metal layer 330 may have a special routing pattern. For example, as Figure 4 As shown, the first metal layer 310 can be a flat conductive material layer (in other words, without a winding pattern), and the second metal layer 330 can be a conductive material layer with a finger-shaped winding pattern. By way of example and not limitation, the aforementioned finger-shaped winding pattern of the second metal layer 330 can be elongated in at least one direction (e.g., direction X) and arranged parallel in another direction (e.g., direction Y), but the invention is not limited thereto.

[0048] like Figure 4 As shown, for example, the finger-shaped winding pattern of the second metal layer 330 is arranged in seven columns in the other direction (e.g., direction Y). This is merely an example for illustrative purposes, and the invention is not limited thereto.

[0049] In some embodiments, the finger-shaped winding pattern of the second metal layer 330 may be arranged in about ten to about fifty columns in the other direction (e.g., direction Y), but the present invention is not limited thereto.

[0050] In some embodiments, the semiconductor element 300 may have one or more conductive connecting posts 340 connected between the first metal layer 310 and the second metal layer 330. For example, such as Figure 4 As shown, the exemplary semiconductor element 300 may have a plurality of conductive connecting posts 340. The present invention is not intended to limit the number of conductive connecting posts 340.

[0051] Next, step S102 is performed: placing the semiconductor device in the first state.

[0052] Please refer to Figure 5 .like Figure 5 As shown, it illustrates a schematic arrangement of several semiconductor elements 300 and conductive elements P1, P2, P3 and P4 located on the dicing track SL (not shown) of wafer W (not shown).

[0053] like Figure 5As shown, each semiconductor element 300 located on the dicing track SL of wafer W includes a planar first metal layer 310 and a second metal layer 330 having a finger-like winding pattern, wherein the finger-like winding pattern is elongated in at least one direction (e.g., direction X) and arranged parallel in another direction (e.g., direction Y). In other words, each semiconductor element 300 is placed on wafer W in the same manner. Figure 5 In the process, semiconductor element 300 is placed along with wafer W such that the finger-shaped wire-wound pattern of the second metal layer 330 is along the horizontal direction (i.e., equivalent to...). Figure 5 The direction X) is stretched and extended in the vertical direction (i.e., equivalent to Figure 5 If the elements are arranged in parallel along the direction Y, such a state is defined as the first state F1.

[0054] Please refer to this again. Figure 6 as well as Figure 7 In this embodiment, one of the first metal layer 310 and the second metal layer 330 is electrically connected to the conductive element P1, and the other of the first metal layer 310 and the second metal layer 330 is electrically connected to the conductive element P2. For example, such as Figure 6 as well as Figure 7 As shown, the first metal layer 310 is electrically connected to the conductive element P1, and the second metal layer 330 is electrically connected to the conductive element P2. Alternatively, in some embodiments, the first metal layer 310 may be electrically connected to the conductive element P2, and the second metal layer 330 may be electrically connected to the conductive element P1.

[0055] For simplicity, in Figure 5 Only four semiconductor elements 300 are shown in the diagram, but in reality, more than four semiconductor elements 300 can be contained on the dicing channel SL of the wafer W. Similarly, in Figure 5 Only four conductive elements are shown in the figure (e.g., conductive element P1, conductive element P2, conductive element P3, and conductive element P4), but in reality, the dicing channel SL of the wafer W can contain more than four conductive elements.

[0056] like Figure 5 As shown, conductive elements P1, P2, and a semiconductor element 300 located between conductive elements P1 and P2 are arranged in one direction (e.g., direction X). This is merely an example for illustrative purposes; in reality, the cutting path SL may have several alternating arrangements of conductive elements P1 and P2 in said direction (e.g., direction X). Specifically, the conductive elements P1, P2, and semiconductor element 300 on the cutting path SL extending along said direction (e.g., direction X) may be arranged, for example, "conductive element P1, semiconductor element 300, conductive element P2, semiconductor element 300, conductive element P1, ...".

[0057] like Figure 5 As shown, conductive elements P3, P4, and a semiconductor element 300 located between conductive elements P3 and P4 are arranged in one direction (e.g., direction X). This is merely an example for illustrative purposes; in reality, the cutting path SL may have several alternating arrangements of conductive elements P3 and P4 in the stated direction (e.g., direction X). Specifically, the conductive elements P3, P4, and semiconductor element 300 on the cutting path SL extending along the stated direction (e.g., direction X) may be arranged, for example, "conductive element P3, semiconductor element 300, conductive element P4, semiconductor element 300, conductive element P3, ...".

[0058] like Figure 5 As shown, conductive elements P1, P4, and the semiconductor element 300 located between conductive elements P1 and P4 are arranged in another direction (e.g., direction Y). This is merely an example for illustrative purposes; in reality, the cutting path SL may have several alternating arrangements of conductive elements P1 and P4 in the other direction (e.g., direction Y). Specifically, the conductive elements P1, P4, and semiconductor element 300 on the cutting path SL extending along the other direction (e.g., direction Y) may be arranged, for example, "conductive element P1, semiconductor element 300, conductive element P4, semiconductor element 300, conductive element P1, ...".

[0059] like Figure 5 As shown, conductive elements P2, P3, and the semiconductor element 300 located between conductive elements P2 and P3 are arranged in another direction (e.g., direction Y). This is merely an example for illustrative purposes; in reality, the cutting path SL may have several alternating arrangements of conductive elements P2 and P3 in the other direction (e.g., direction Y). Specifically, the conductive elements P2, P3, and semiconductor element 300 on the cutting path SL extending along the other direction (e.g., direction Y) may be arranged, for example, "conductive element P2, semiconductor element 300, conductive element P3, semiconductor element 300, conductive element P2, ...".

[0060] In some implementations, such as Figure 5 , Figure 6 as well as Figure 7As shown, one of the first metal layer 310 and the second metal layer 330 can be electrically connected to the conductive element P1 via a wire L1, and the other of the first metal layer 310 and the second metal layer 330 can be electrically connected to the conductive element P2 via a wire L2. For example, the first metal layer 310 can be electrically connected to the conductive element P1 via a wire L1, and the second metal layer 330 can be electrically connected to the conductive element P2 via a wire L2.

[0061] In some embodiments, wires L1 and L2 can be made of any suitable conductive material, but the invention is not limited thereto. In some embodiments, the material of wire L1 is the same as the material of the first metal layer 310, and the material of wire L2 is the same as the material of the second metal layer 330, but the invention is not limited thereto. In some embodiments, the material of wire L1 may be different from the material of the first metal layer 310, and the material of wire L2 may also be different from the material of the second metal layer 330.

[0062] Next, step S103 is executed: the power supply component and grounding component of the test element are electrically connected to the first conductive element and the second conductive element, respectively, to obtain the first voltage value and the first current value of the semiconductor element placed in the first state.

[0063] Please refer to Figure 5 This diagram illustrates the monitoring phase of a semiconductor device monitoring method 100. In this embodiment, electrically connecting a test element (not shown) to conductive elements P1 and P2 allows the acquisition of the voltage and current values ​​of the semiconductor device 300 placed in the first state F1. More specifically, the test element includes a power supply component TP and a ground component TG, with the power supply component TP serving as the power supply terminal and the ground component TG serving as the ground terminal. In this embodiment, one of the power supply component TP and the ground component TG is electrically connected to conductive element P1, and the other is electrically connected to conductive element P2. In one application scenario, such as... Figure 5 , Figure 6 as well as Figure 7 As shown, the operator / monitor can connect the power supply component TP to the conductive element P1 and the grounding component TG to the conductive element P2, and then apply power to the test element, so that the power supply component TP is electrically connected to the conductive element P1 and the grounding component TG is electrically connected to the conductive element P2, thereby generating a potential difference and current between the conductive elements P1 and P2, and then obtain the voltage and current values ​​of the semiconductor element 300 placed in the first state F1. The operator / monitor can calculate the resistance value using the voltage and current values ​​obtained by the monitoring method described above.

[0064] In some embodiments, the test element may be a probe station, for example, but the present invention is not intended to limit this.

[0065] Please refer to Figure 6 In another embodiment of the invention, the semiconductor element 300 includes a first metal layer 310, an offset second metal layer 330S, and conductive connecting posts 340. This embodiment differs in that the offset second metal layer 330S has a coverage offset during the manufacturing process of the semiconductor element 300 (e.g., in a top view, the second metal layer 330 does not completely cover all conductive connecting posts 340). Such a coverage offset may be caused by the second metal layer 330 not being aligned with the first metal layer 310 and the conductive connecting posts 340 located beneath it during the formation of the second metal layer 330. Specifically, the finger-shaped winding pattern of the offset second metal layer 330S is at least entirely offset relative to the conductive connecting posts 340, so that the resulting finger-shaped winding pattern of the offset second metal layer 330S is in the vertical direction (i.e., equivalent to) the finger-shaped winding pattern of the normally manufactured second metal layer 330. Figure 6 It has an offset in the direction Y).

[0066] In one application scenario, the operator / monitor can connect the power supply component TP to the conductive element P1 electrically connected to the first metal layer 310, and the ground component TG to the conductive element P2 electrically connected to the offset second metal layer 330S. Then, power is applied to the test element, so that the power supply component TP is electrically connected to the conductive element P1 and the ground component TG is electrically connected to the conductive element P2, generating a potential difference and current between the conductive elements P1 and P2. Based on this, another voltage value and another current value of the semiconductor element 300 placed in the first state F1 are obtained. In this case, the other resistance value calculated from the other voltage value and the other current value measured by the test element (i.e., the resistance value of the semiconductor element 300 with the offset second metal layer 330S) is larger than the resistance value calculated from the voltage value and the current value measured by the test element (i.e., the resistance value of the semiconductor element 300 with the unoffset second metal layer 330S, or the "ideal resistance value").

[0067] In other words, when the operator / monitor does not yet know whether the semiconductor element 300 has a coverage offset during the manufacturing process, they can perform step S103 to electrically connect the power supply component TP and the ground component TG of the test element to the conductive element P1 or the conductive element P2, respectively. If the calculated resistance value is larger than the ideal resistance value, the operator / monitor can determine that the semiconductor element 300 has at least a coverage offset in one direction (e.g., direction Y).

[0068] Next, step S104 is performed: placing the semiconductor device in the second state.

[0069] Please refer to Figure 8 .like Figure 8 As shown, it depicts something similar to Figure 5 A schematic arrangement of several semiconductor elements 300 and conductive elements P1, P2, P3 and P4 located on the cleavage track SL (not shown) of the wafer W (not shown). Figure 8 The arrangement of semiconductor element 300, conductive element P1, conductive element P2, conductive element P3, and conductive element P4 is relative to Figure 5 The configuration rotates 90 degrees (e.g., Figure 8 Compared to Figure 5 Rotate 90 degrees clockwise.

[0070] like Figure 8 As shown, each semiconductor element 300 located on the dicing track SL of wafer W includes a planar first metal layer 310 and a second metal layer 330 having a finger-like winding pattern, wherein the finger-like winding pattern is elongated in at least one direction (e.g., direction X) and arranged parallel in another direction (e.g., direction Y). In other words, each semiconductor element 300 is placed on wafer W in the same manner. Figure 8 In the process, semiconductor element 300 is placed along with wafer W such that the finger-shaped wire-wound pattern of the second metal layer 330 is along the vertical direction (i.e., equivalent to...). Figure 8 The direction X) is stretched and extended in the horizontal direction (i.e., equivalent to Figure 8 If the elements are arranged in parallel along the direction Y, such a state is defined as the second state F2.

[0071] In one use case, the operator / monitor can rotate the wafer W by 90 degrees (e.g., clockwise or counterclockwise). For example, as shown... Figure 5 The semiconductor element 300 shown is rotated 90 degrees clockwise. This causes the semiconductor element 300 to rotate from... Figure 5 The first state sample F1 shown becomes as follows Figure 8 The second state sample F2 is shown.

[0072] Please refer to this again. Figure 9 as well as Figure 10 In this embodiment, one of the first metal layer 310 and the second metal layer 330 is electrically connected to the conductive element P2, and the other of the first metal layer 310 and the second metal layer 330 is electrically connected to the conductive element P3. For example, such as Figure 9 as well as Figure 10As shown, the first metal layer 310 is electrically connected to the conductive element P2, and the second metal layer 330 is electrically connected to the conductive element P3. Alternatively, in some embodiments, the first metal layer 310 may be electrically connected to the conductive element P3, and the second metal layer 330 may be electrically connected to the conductive element P2.

[0073] In some implementations, such as Figure 8 , Figure 9 as well as Figure 10 As shown, one of the first metal layer 310 and the second metal layer 330 can be electrically connected to the conductive element P2 via a wire L1, and the other of the first metal layer 310 and the second metal layer 330 can be electrically connected to the conductive element P3 via a wire L2. For example, the first metal layer 310 can be electrically connected to the conductive element P2 via a wire L1, and the second metal layer 330 can be electrically connected to the conductive element P3 via a wire L2.

[0074] Next, step S105 is performed: the power supply component and grounding component of the test element are electrically connected to the second conductive element and the third conductive element, respectively, to obtain the second voltage value and the second current value of the semiconductor element placed in the second state.

[0075] Please refer to Figure 8 This diagram illustrates the monitoring phase of a semiconductor element monitoring method 100. In this embodiment, electrically connecting a test element (not shown) to conductive elements P2 and P3 allows the acquisition of the voltage and current values ​​of the semiconductor element 300 placed in the second state F2. In this embodiment, one of the power supply component TP and the grounding component TG is electrically connected to conductive element P1, and the other of the power supply component TP and the grounding component TG is electrically connected to conductive element P2. In one application scenario, such as... Figure 8 , Figure 9 as well as Figure 10 As shown, the operator / monitor can connect the power supply component TP to the conductive element P2 and the grounding component TG to the conductive element P3, and then apply power to the test element, so that the power supply component TP is electrically connected to the conductive element P2 and the grounding component TG is electrically connected to the conductive element P3, thereby generating a potential difference and current between the conductive elements P2 and P3, and then obtain the voltage and current values ​​of the semiconductor element 300 placed in the second state F2. The operator / monitor can calculate the resistance value using the voltage and current values ​​obtained by the monitoring method described above.

[0076] Please refer to Figure 9 In another embodiment of the invention, the semiconductor element 300 is like... Figure 6The diagram shows a first metal layer 310, an offset second metal layer 330S, and a conductive connecting post 340. Specifically, the finger-shaped winding pattern of the offset second metal layer 330S is at least entirely offset relative to the conductive connecting post 340, and because... Figure 9 Semiconductor element 300 relative to Figure 6 The semiconductor element 300 is rotated 90 degrees clockwise, so the resulting offset finger-wound pattern of the second metal layer 330S is in the horizontal direction relative to the normally manufactured finger-wound pattern of the second metal layer 330 (i.e., equivalent to...). Figure 9 It has an offset in the direction Y).

[0077] In one application scenario, the operator / monitor can contact the power supply component TP with the conductive element P2 electrically connected to the first metal layer 310, and contact the ground component TG with the conductive element P3 electrically connected to the offset second metal layer 330S. Then, power is applied to the test element, so that the power supply component TP is electrically connected to the conductive element P2 and the ground component TG is electrically connected to the conductive element P3 to generate a potential difference and current between the conductive elements P2 and P3, and then obtain another voltage value and another current value of the semiconductor element 300 placed in the second state F2. In this case, since the semiconductor element 300 of the second state sample F2 is rotated 90 degrees relative to the semiconductor element 300 of the first state sample F1, the other resistance value calculated from the other voltage value and the other current value measured by the test element (i.e., the resistance value of the semiconductor element 300 with the offset second metal layer 330S) is theoretically the same as the resistance value calculated from the voltage value and the current value measured by the test element (i.e., the resistance value of the semiconductor element 300 with the unoffset second metal layer 330, or the "ideal resistance value").

[0078] In summary, when the operator / monitor is unaware of whether the semiconductor element 300 has a coverage offset during the manufacturing process, they can perform steps S103 and S105 to electrically connect the power supply component TP and ground component TG of the test element to conductive element P1 or conductive element P2, and then electrically connect them to conductive element P2 or conductive element P3. If the calculated resistance value of the semiconductor element 300 in the first state sample F1 and / or the second state sample F2 is larger than the ideal resistance value, the operator / monitor can determine that the semiconductor element 300 has at least a coverage offset in any direction (e.g., direction X and / or direction Y).

[0079] By performing the above steps S101, S102, S103, S104 and S105, the operator / monitor can reliably detect any possible coverage offset of the semiconductor element 300 through the semiconductor element monitoring method 100.

[0080] The semiconductor device monitoring method 100 has advantages. Its advantage lies in the fact that the operator / monitor can monitor adjacent semiconductor devices to detect whether there is a coverage offset in at least one direction among several semiconductor devices on the entire wafer W. Furthermore, by implementing the semiconductor device monitoring method 100, the operator / monitor can promptly report the detected coverage offset to the front-end process technicians, thereby avoiding material waste during the semiconductor device manufacturing process and saving semiconductor device processing time.

[0081] Please refer to Figure 11 This is a flowchart illustrating a monitoring method 1100 for another semiconductor device according to an embodiment of the present invention. Figure 11 As shown, the semiconductor device monitoring method 1100 includes steps S1101, S1102, S1103, S1104, and S1105. This document describes in detail... Figure 11 Please refer to the following when referring to steps S1101 to S1105: Figure 2A as well as Figure 2B .

[0082] The following describes in detail the operations of steps S1101, S1102, S1103, S1104, and S1105.

[0083] In this embodiment, steps S1101, S1102 and S1103 are similar to steps S101, S102 and S103.

[0084] In step S1101, the semiconductor element described therein is actually the same as the one described above. Figure 2B The semiconductor element 200 shown or such Figures 3 to 10 The semiconductor element 300 shown is the same.

[0085] In step S1102, the operator / monitor can first, as follows: Figure 2A The wafer W shown is positioned such that conductive elements Pa and Pb are in... Figure 2B They are arranged alternately in the horizontal direction (i.e., like the first state F1).

[0086] In step S1103, the operator / monitor can electrically connect the power supply component TP and the grounding component TG of the test element (not shown) to, for example, a conductive element Pa or a conductive element Pb, to obtain, for example, a first voltage value and a first current value of a semiconductor element 200 (or semiconductor element 300) placed in the first state F1.

[0087] In this embodiment, step S1104, like step S104, changes the placement of semiconductor element 200 (or semiconductor element 300) from the first state F1 to the second state F2. However, step S1104 differs from step S104. In step S1104, semiconductor element 200 (or semiconductor element 300) refers to semiconductor element 200 located between conductive element Pc and conductive element Pd. Therefore, the difference between step S1104 and step S104 is that while conductive element (e.g., conductive element P2) is reused in step S104, step S1104 utilizes conductive elements that are not reused in steps S1102 and S1103.

[0088] In this embodiment, step S1105 differs from step S105. In step S1105, the operator / monitor electrically connects the power supply component TP and the ground component TG of the test element to conductive elements Pc and Pd, respectively, to obtain the second voltage value and the second current value of the semiconductor element 200 (or semiconductor element 300) placed in the second state F2. Therefore, the difference between step S1105 and step S105 is that the conductive element (e.g., conductive element P2) was reused in step S103, but step S1105 utilizes a conductive element that is not reused in steps S1102 and S1103. Specifically, the operator / monitor electrically connects the power supply component TP and the ground component TG to conductive elements Pa and Pb, respectively, and then electrically connects them to conductive elements Pc and Pd, respectively, to obtain the aforementioned first voltage value, first current value, second voltage value, and second current value of the semiconductor element 200 (or semiconductor element 300).

[0089] By performing the above steps S1101, S1102, S1103, S1104 and S1105, the operator / monitor can reliably detect the possible coverage offset of the semiconductor element 200 (or semiconductor element 300) through the semiconductor element monitoring method 1100.

[0090] The semiconductor device monitoring method 1100 has advantages. Its advantage lies in that when any conductive element on the dicing track SL of wafer W fails, the operator / monitor can monitor non-adjacent semiconductor elements, or even several semiconductor elements across the entire wafer W, to detect any coverage offset in at least one direction. Furthermore, by implementing the semiconductor device monitoring method 1100, the operator / monitor can promptly report the detected coverage offset to front-end process technicians, thereby avoiding material waste during semiconductor device manufacturing and saving process time.

[0091] From the detailed description of the specific embodiments of the present invention above, it is clear that in the semiconductor device monitoring method of the present invention, after obtaining the first voltage value and the first current value of the semiconductor device placed in the first state sample, the semiconductor device is placed in the second state sample, and its second voltage value and second current value are obtained accordingly. Furthermore, the resistance values ​​of the semiconductor device in several directions are calculated, enabling reliable monitoring of the coverage offset problem on the production line and determining in which direction the coverage offset occurred. In addition, in the semiconductor device monitoring method of the present invention, since the voltage and current values ​​of the semiconductor device are measured on the production line when placed in the first and second state samples respectively, the monitor can promptly report the detected problems to the front-end process technicians. This not only avoids material waste during the semiconductor device manufacturing process but also saves process time.

[0092] The foregoing outlines the features of several embodiments, enabling those skilled in the art to better understand the nature of this invention. Those skilled in the art should understand that the foregoing can be readily used as the basis for designs or modifications to achieve other variations without departing from the spirit and scope of this invention, in order to implement the same objectives and / or realize the same advantages of the embodiments described herein. The foregoing should be understood as illustrative of the invention, and its scope of protection should be determined by the claims.

[0093] [Symbol Explanation]

[0094] 100, 1100: Monitoring methods for semiconductor devices

[0095] 200, 300: Semiconductor components

[0096] 310: First metal layer

[0097] 320: Dielectric material layer

[0098] 330: Second metal layer

[0099] 330S: Offset of the second metal layer

[0100] 340: Conductive connecting post

[0101] D: Chip

[0102] F1: First state sample

[0103] F2: Second state sample

[0104] L1, L2: Wires

[0105] P, P1, P2, P3, P4, Pa, Pb, Pc, Pd: Conductive elements

[0106] S101, S102, S103, S104, S105, S1101, S1102, S1103, S1104, S1105: Steps

[0107] SL: Cutting Track

[0108] TP: Power Supply Unit

[0109] TG: Grounding component

[0110] W: Wafer

[0111] X, Y: Direction.

Claims

1. A method for monitoring semiconductor devices, characterized in that, Include: A semiconductor element is provided, the semiconductor element comprising a first metal layer, a second metal layer and one or more conductive connecting pillars, the second metal layer being disposed above the first metal layer, and the one or more conductive connecting pillars being connected between the first metal layer and the second metal layer; The semiconductor element is placed in a first state, wherein the first metal layer is electrically connected to a first conductive element and the second metal layer is electrically connected to a second conductive element; The semiconductor element is placed in a second state, wherein the first metal layer is electrically connected to the second conductive element and the second metal layer is electrically connected to the third conductive element, wherein the phase difference between the semiconductor element in the first state and the semiconductor element in the second state is 90 degrees. The power supply component and grounding component of the test element are electrically connected to the first conductive element and the second conductive element, respectively, to obtain the first voltage value and the first current value of the semiconductor element placed in the first state. as well as The power supply component and the grounding component of the test element are electrically connected to the second conductive element and the third conductive element, respectively, to obtain the second voltage value and the second current value of the semiconductor element placed in the second state.

2. The method according to claim 1, characterized in that, The first conductive element, the second conductive element, and the third conductive element are electrical testing pads.

3. The method according to claim 1, characterized in that, The semiconductor elements of the first state are arranged in a first direction, and the semiconductor elements of the second state are arranged in a second direction perpendicular to the first direction.

4. The method according to claim 1, characterized in that, The test element is a probe station.

5. The method according to claim 1, characterized in that, The step of electrically connecting the power supply component and the grounding component of the test element to the first conductive element and the second conductive element, respectively, is performed after the step of placing the semiconductor element in the first state and before the step of placing the semiconductor element in the second state.

6. The method according to claim 1, characterized in that, The step of electrically connecting the power supply component and the grounding component of the test element to the second conductive element and the third conductive element, respectively, is performed after the step of placing the semiconductor element in the second state.

7. The method according to claim 1, characterized in that, Further includes: The semiconductor element is placed in the second state, wherein the first metal layer is electrically connected to the third conductive element and the second metal layer is electrically connected to the fourth conductive element; as well as The power supply component and the grounding component of the test element are electrically connected to the third conductive element and the fourth conductive element, respectively, to obtain the second voltage value and the second current value of the semiconductor element placed in the second state.

8. The method according to claim 7, characterized in that, The step of electrically connecting the power supply component and the grounding component of the test element to the third conductive element and the fourth conductive element, respectively, is performed after the step of electrically connecting the power supply component and the grounding component of the test element to the first conductive element and the second conductive element, respectively.

9. The method according to claim 7, characterized in that, The step of electrically connecting the power supply component and the grounding component of the test element to the third conductive element and the fourth conductive element, respectively, is performed after the step of placing the semiconductor element in the second state.

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