Semiconductor device and method of forming the same

Abstract

A semiconductor device and a method of forming the same are disclosed. The semiconductor device includes a substrate, first and second gate structures, third and fourth gate structures, a conductive structure, an insulating layer, and an etch stop layer. The first and second gate structures are disposed on a first region of the substrate. The third and fourth gate structures are disposed on a second region of the substrate. The conductive structure is disposed on an isolation structure of a third region of the substrate. The insulating layer covers the first, second, and third gate structures and the conductive structure. The fourth gate structure is disposed on the insulating layer. The etch stop layer includes first and second portions. The first portion is disposed between the insulating layer and the first, second, and third gate structures. The second portion is disposed between the insulating layer and the conductive structure.

Description

Technical Field

[0001] This invention relates to a semiconductor structure and a method for forming the same. Background Technology

[0002] Bipolar-complementary metal-oxide-semiconductor (CMOS)-double-diffused metal-oxide-semiconductor (DMOS) fabrication technology (BCD process) is a manufacturing process that can fabricate bipolar devices, CMOS devices, and DMOS devices on a single chip. Bipolar devices are suitable for analog circuits, CMOS devices are suitable for digital circuits, and DMOS devices are suitable for handling high-voltage operations. Therefore, the BCD process combines the advantages of these three types of devices and has attracted increasing attention. However, engineers continue to improve the BCD process to avoid making it too complex and thus hindering its industrial production goals, such as poor yields that prevent mass production. Summary of the Invention

[0003] The present invention provides a semiconductor device and a method for forming the same, which improves the reliability of the semiconductor device by designing the etch stop layer to include a first portion disposed between an insulating layer and first, second and third gate structures and a second portion disposed between an insulating layer and a conductive structure.

[0004] An embodiment of the present invention provides a semiconductor device including a substrate, a first gate structure, a second gate structure, a third gate structure, and a fourth gate structure, a conductive structure, an insulating layer, and an etch stop layer. The substrate includes a first region, a second region, and a third region. The substrate includes an isolation structure disposed in the third region. The first gate structure and the second gate structure are disposed on the first region. The third gate structure and the fourth gate structure are disposed on the second region. The conductive structure is disposed on the isolation structure in the third region. The insulating layer is disposed on the first, second, and third regions of the substrate and covers the first gate structure, the second gate structure, the third gate structure, and the conductive structure. The fourth gate structure is disposed on the insulating layer. The etch stop layer includes a first portion and a second portion. The first portion is disposed between the insulating layer and the first, second, and third gate structures. The second portion is disposed between the insulating layer and the conductive structure.

[0005] In some embodiments, the first and second portions of the etch stop layer are separated by an insulating layer.

[0006] In some embodiments, the etch stop layer is in direct contact with the first gate structure, the second gate structure, the third gate structure, and the conductive structure.

[0007] In some embodiments, the semiconductor device further includes a silicide barrier layer disposed on the third gate structure and including portions disposed between the etch stop layer and the third gate structure and between the insulating layer and the third gate structure.

[0008] In some embodiments, the insulating layer includes a notch disposed between the third gate structure and the conductive structure. A fourth gate structure is disposed within the notch and includes a first metal gate disposed on the bottom of the notch and a second metal gate disposed on the sidewall of the notch.

[0009] In some embodiments, the first metal gate and the second metal gate are spaced apart from each other.

[0010] In some embodiments, the fourth gate structure includes a hard mask layer disposed on the first metal gate and the second metal gate.

[0011] In some embodiments, the semiconductor device further includes a metal layer disposed on an insulating layer in the third region. A first gate structure and a second gate structure form part of a first element in the first region. A third gate structure and a fourth gate structure form part of a second element in the second region. A conductive structure, a metal layer, and an insulating layer disposed between the conductive structure and the metal layer form part of a third element in the third region.

[0012] An embodiment of the present invention provides a method for forming a semiconductor device, comprising the following steps: providing a substrate, wherein the substrate includes a first region, a second region, and a third region, and the substrate includes an isolation structure disposed in the third region; forming a first gate structure and a second gate structure on the first region; forming a third gate structure on the second region; forming a conductive structure on the isolation structure in the third region; forming an etch stop layer on the first region, the second region, and the third region to cover the first gate structure, the second gate structure, the third gate structure, and the conductive structure; forming a first insulating layer on the etch stop layer; removing the first insulating layer and the etch stop layer located on a portion of the second region to form an opening exposing a portion of the second region; forming a second insulating layer on the first insulating layer and on the sidewalls and bottom surface of the opening, wherein the second insulating layer includes a notch corresponding to the location of the opening; and forming a fourth gate structure in the notch.

[0013] In some embodiments, the step of forming the fourth gate structure includes: forming a metal material layer on a second insulating layer, wherein the metal material layer is formed on the sidewalls and bottom surface of the notch; forming a hard mask material layer on the metal material layer; and patterning the hard mask material layer and the metal material layer to form a first metal gate and a second metal gate on the bottom surface and sidewalls of the notch, respectively, and forming a hard mask layer on the first metal gate and the second metal gate.

[0014] In some embodiments, the first metal gate and the second metal gate are spaced apart from each other.

[0015] In some embodiments, during the step of patterning the hard mask material layer and the metal material layer, the metal layer is formed on a second insulating layer located on a third region, wherein: a first gate structure and a second gate structure form part of a first element in the first region; a third gate structure and a fourth gate structure form part of a second element in the second region; and a conductive structure, the metal layer, and the second insulating layer disposed between the conductive structure and the metal layer form part of a third element in the third region.

[0016] In some embodiments, the method of forming a semiconductor device further includes: performing a planarization process on a first insulating layer prior to forming an opening.

[0017] Based on the above, in the above-mentioned semiconductor device and its formation method, by designing the etch stop layer to include a first portion disposed between the insulating layer and the first, second and third gate structures and a second portion disposed between the insulating layer and the conductive structure, the fabrication process used to form the contacts can be improved, thereby enhancing the reliability of the semiconductor device. Attached Figure Description

[0018] Figures 1 to 6 This is a cross-sectional schematic diagram of a method for forming a semiconductor device according to an embodiment of the present invention;

[0019] Figure 7 This is a cross-sectional schematic diagram of the fourth gate structure according to another embodiment of the present invention.

[0020] Symbol Explanation

[0021] 10: Semiconductor devices

[0022] 100: Base

[0023] 102, 104, 106: Doped regions / silicide layers

[0024] 108: Isolation Structure

[0025] 110a, 110b, 110c: Gate

[0026] 110d: Conductive layer

[0027] 112a, 112b, 112c, 112d: Interstitial walls

[0028] 114a, 114b, 114c, 114d: silicide layers

[0029] 120, 122: Silicide barrier layer

[0030] 130, 132: Etching stop layer

[0031] 140, 142: First insulating layer

[0032] 150: Second insulation layer / insulation layer

[0033] 150R: Notch

[0034] 160: Metallic material layer

[0035] 162a, 162a': First metal gate

[0036] 162b, 162b': Second metal gate

[0037] 164: Metal layer

[0038] 170: Hard mask material layer

[0039] 172, 172', 174: Hard mask layers

[0040] 180: Third insulation layer

[0041] CS: Conductive structure

[0042] CT1, CT2, CT3, CT4, CT5: Contact elements

[0043] D1: First element / element

[0044] D2: Second element / component

[0045] D3: Third Component / Component

[0046] GS1: First gate structure

[0047] GS2: Second gate structure

[0048] GS3: Third gate structure

[0049] GS4: Fourth gate structure

[0050] OP: Open

[0051] A: Area

[0052] R1: First Region

[0053] R2: Second Region

[0054] R3: Third Region Detailed Implementation

[0055] The invention is described more fully with reference to the accompanying drawings of this embodiment. However, the invention may be embodied in various different forms and should not be limited to the embodiments described herein. The thicknesses of layers and regions in the drawings are enlarged for clarity. The same or similar reference numerals denote the same or similar elements, which will not be repeated in the following paragraphs.

[0056] It should be understood that when an element is referred to as being "on" or "connected" to another element, it may be directly on or connected to the other element, or there may be intermediate elements present. If an element is referred to as being "directly on" or "directly connected" to another element, there are no intermediate elements present. As used herein, "connection" may refer to a physical and / or electrical connection, while "electrical connection" or "coupling" may refer to the presence of other elements between two elements. As used herein, "electrical connection" may include physical connections (e.g., wired connections) and physical disconnections (e.g., wireless connections).

[0057] As used herein, “about,” “approximately,” or “substantially” includes the average of the mentioned values ​​and specific values ​​within an acceptable range of deviation that can be determined by one of ordinary skill in the art, taking into account the measurement under discussion and the specific number of errors associated with the measurement (i.e., limitations of the measurement system). For example, “about” may mean within one or more standard deviations of the value, or within ±30%, ±20%, ±10%, ±5%. Furthermore, the use of “about,” “approximately,” or “substantially” herein may be chosen based on the optical, etched, or other properties, selecting a more acceptable range of deviations or standard deviations, rather than applying a single standard deviation to all properties.

[0058] The terminology used herein is for illustrative purposes only and is not intended to limit the invention. In this context, the singular form includes the plural form unless the context otherwise requires.

[0059] Figures 1 to 6 This is a cross-sectional schematic diagram of a method for forming a semiconductor device according to an embodiment of the present invention. Figure 7 This is a cross-sectional schematic diagram of the fourth gate structure according to another embodiment of the present invention. Figure 5 The area A shown is... Figure 7 The area shown corresponds to region A.

[0060] First, please refer to Figure 1A substrate 100 is provided. The substrate 100 includes a first region R1, a second region R2, and a third region R3. The first region R1 may include a doped region 102. The second region R2 may include doped regions 104 and 106. The third region may include an isolation structure 108. In some embodiments, the second region R2 may be disposed between the first region R1 and the third region R3. The substrate 100 may be any type of semiconductor substrate (e.g., silicon, SiGe, SOI, etc.) and any other type of semiconductor layer and / or epitaxial layer associated therewith. The isolation structure 108 may include one or more dielectric materials. The dielectric materials may include oxides (e.g., silicon oxide), tetraethyl orthosilicate (TEOS), nitrides (e.g., silicon nitride, silicon oxynitride, etc.), carbides (e.g., silicon carbide, silicon oxycarbide, etc.), or the like.

[0061] Next, a first gate structure GS1 and a second gate structure GS2 are formed on the first region R1, a third gate structure GS3 is formed on the second region R2, and a conductive structure CS is formed on the isolation structure 108 in the third region R3.

[0062] The first gate structure GS1 may include a gate 110a formed on a substrate 100, a spacer wall 112a formed on the sidewall of the gate 110a, and a silicide layer 114a formed on the top surface of the gate 110a. The second gate structure GS2 may include a gate 110b formed on a substrate 100, a spacer wall 112b formed on the sidewall of the gate 110b, and a silicide layer 114b formed on the top surface of the gate 110b. In some embodiments, a doped region 102 may be formed between the gate 110a and the gate 110b and below the spacer walls 112a and 112b that face each other. The material of the gate 110a or the gate 110b may include polysilicon. The spacer wall 112a or the spacer wall 112b may be a single layer or multiple layers. In some embodiments, the spacer wall 112a or the spacer wall 112b may be formed as a multilayer including a nitride layer, an oxide layer, and a nitride layer. The material of the silicide layer 114a or silicide layer 114b may include metal silicides such as tungsten silicide, titanium silicide, cobalt silicide, zirconium silicide, platinum silicide, molybdenum silicide, copper silicide, or nickel silicide.

[0063] The third gate structure GS3 may be formed between doped regions 104 and 106 and may include a gate 110c formed on the substrate 100, a spacer wall 112c formed on the sidewall of the gate 110c, and a silicide layer 114c formed on the top surface of the gate 110c. The material of the gate 110c may include polysilicon. The spacer wall 112c may be a single layer or multiple layers. In some embodiments, the spacer wall 112c may be formed as a multilayer including a nitride layer, an oxide layer, and a nitride layer. The material of the silicide layer 114c may include metal silicides such as tungsten silicide, titanium silicide, cobalt silicide, zirconium silicide, platinum silicide, molybdenum silicide, copper silicide, or nickel silicide.

[0064] The conductive structure CS may include a conductive layer 110d formed on the isolation structure 108, a spacer wall 112d formed on the sidewalls of the conductive layer 110d, and a silicide layer 114d formed on the top surface of the conductive layer 110d. The material of the conductive layer 110d may include polycrystalline silicon. The spacer wall 112d may be a single layer or multiple layers. In some embodiments, the spacer wall 112d may be formed as a multilayer comprising a nitride layer, an oxide layer, and a nitride layer. The material of the silicide layer 114d may include metal silicides such as tungsten silicide, titanium silicide, cobalt silicide, zirconium silicide, platinum silicide, molybdenum silicide, copper silicide, or nickel silicide.

[0065] In some embodiments, silicide layers 114a, 114b, 114c, and 114d can be formed by performing a self-aligned metal silicide fabrication process on the top surfaces of gates 110a, 110b, 110c, and conductive layer 110d. In some embodiments, doped regions 102, 104, and 106 can also be formed into silicide layers by the aforementioned self-aligned metal silicide fabrication process; that is, doped regions 102, 104, and 106 can also be referred to as silicide layers 102, 104, and 106.

[0066] In some embodiments, the silicide barrier layer 120 may be formed on a portion of the top surface of the gate 110c and extend to one end of the doped region 106 without covering the doped region 106. In this way, during the self-aligned metal silicide fabrication process described above, the silicide layer will not form on the portions covered by the silicide barrier layer 120, such as the aforementioned portion of the top surface of the gate 110c, the portion of the spacer wall 112c facing the doped region 106, and the portion of the second region R2 located between the spacer wall 112c and the doped region 106. The thickness of the silicide barrier layer 120 may be approximately 20 nm.

[0067] Then, an etch stop layer 130 is formed on the first region R1, the second region R2, and the third region R3 to cover the first gate structure GS1, the second gate structure GS2, the third gate structure GS3, and the conductive structure CS. The etch stop layer 130 may be a contact etch stop layer (CESL). The material of the etch stop layer 130 may include silicon nitride. The etch stop layer 130 may be in direct contact with the first gate structure GS1, the second gate structure GS2, the third gate structure GS3, the conductive structure CS, the doped region 102, the doped region 104, the doped region 106, and the isolation structure 108. In some embodiments, the etch stop layer 130 may be in direct contact with the silicide barrier layer 120. The thickness of the etch stop layer 130 may be approximately 30 nm.

[0068] Then, please refer to Figure 2 A first insulating layer 140 is formed on the etch stop layer 130. The material of the first insulating layer 140 may include silicon oxide. The first insulating layer 140 may be an interlayer dielectric (ILD). In some embodiments, the first insulating layer 140 may be subjected to a planarization process such as chemical mechanical polishing (CMP).

[0069] Then, please refer to Figure 3 The first insulating layer 140 and etch stop layer 132 located on a portion of the second region R2 are removed to form an opening OP that exposes the portion of the second region R2. From a top view, the opening OP may be located between the third gate structure GS3 and the doped region 106. In some embodiments, the opening OP does not expose the doped region 106. In some embodiments, a patterning fabrication process may be used to form the opening OP. In some embodiments, where the silicide barrier layer 120 is formed on a portion of the top surface of the gate 110c and extends to one end of the doped region 106 without covering the doped region 106, the portion of the silicide barrier layer 120 located between the spacer wall 112c and the doped region 106 is also removed during the step of forming the opening OP. In some embodiments, such as Figure 3 As shown, the opening OP can expose a portion of the silicide barrier layer 122 and a portion of the etch stop layer 132.

[0070] Next, please refer to Figure 4A second insulating layer 150 is formed on the first insulating layer 142 and on the sidewalls and bottom surface of the opening OP. The second insulating layer 150 includes a notch 150R corresponding to the location of the opening OP. That is, the notch 150R may be configured above the second region R2 between the third gate structure GS3 and the conductive structure CS. In some embodiments, the material of the second insulating layer 150 may include oxides, such as high aspect ratio process (HARP) oxides. The thickness of the second insulating layer 150 may be approximately 80 nm.

[0071] Then, please refer to Figure 4 and Figure 5 A fourth gate structure GS4 is formed in the notch 150R. In some embodiments, the fourth gate structure GS4 may be formed by the following steps.

[0072] First, please refer to Figure 4 A metal material layer 160 is formed on the second insulating layer 150. The metal material layer 160 fills the recess 150R and is formed on the bottom surface and sidewalls of the recess 150R. The metal material layer 160 does not completely fill the recess 150R, leaving a central portion of the recess 150R. That is, the metal material layer 160 may be conformally formed on the surface of the second insulating layer 150. The material of the metal material layer 160 may include copper, tungsten, ruthenium, aluminum, and / or similar materials.

[0073] Next, a hard mask material layer 170 is formed on the metal material layer 160. The hard mask material layer 170 fills the notch 150R and is formed above the bottom surface and sidewalls of the notch 150R. The hard mask material layer 170 does not completely fill the notch 150R, leaving a central portion of the notch 150R. That is, the hard mask material layer 170 can be conformally formed on the surface of the metal material layer 160. The material of the hard mask material layer 170 may include silicon nitride.

[0074] Then, please refer to Figure 4 and Figure 5 A patterning process is performed on the hard mask material layer 170 and the metal material layer 160 to form a first metal gate 162a and a second metal gate 162b on the bottom surface and sidewall of the notch 150R, respectively. A metal layer 164 is formed on the second insulating layer 150 in the third region R3. The hard mask layer 172 is formed on the first metal gate 162a and the second metal gate 162b, and the hard mask layer 174 is formed on the metal layer 164. In this way, a fourth gate structure GS4, including the first metal gate 162a, the second metal gate 162b, and the hard mask layer 172, can be formed in the notch 150R. The first gate structure GS1 and the second gate structure GS2 can form a first element (such as...) in the first region R1. Figure 6The element D1 shown is a portion of the first element D1. In some embodiments, the first element D1 may be, for example, a static random access memory (SRAM). The third gate structure GS3 and the fourth gate structure GS4 may form the second element (e.g., ...) in the second region D2. Figure 6 The element D2 shown is a part of the second element D2. In some embodiments, the second element D2 may be, for example, a laterally diffused metal-oxide-semiconductor field-effect transistor (LDMOS). The conductive structure CS, the metal layer 164, and the etch stop layer 132, the first insulating layer 142, and the second insulating layer 150 disposed between the conductive structure CS and the metal layer 164 may form a third element (such as...) in the third region R3. Figure 6 The element D3 shown is part of the third element D3. In some embodiments, the third element D3 may be, for example, a metal-insulator-poly (MIP) capacitor.

[0075] In some embodiments, the first metal gate 162a and the second metal gate 162b are spaced apart from the metal layer 164. In some embodiments, the hard mask layer 172 and the hard mask layer 174 are spaced apart from each other. In some embodiments, the first metal gate 162a and the second metal gate 162b may be as follows: Figure 5 The film is formed as a continuous layer. In other embodiments, the first metal gate 162a and the second metal gate 162b can be formed as shown. Figure 7 The first metal gate 162a' and the second metal gate 162b' are shown to be spaced apart from each other, wherein the hard mask layer 172' is formed on the first metal gate 162a' and does not contact the second metal gate 162b'.

[0076] Next, a third insulating layer 180 is formed on the second insulating layer 150, the fourth gate structure GS4, and the hard mask layer 174. The third insulating layer 180 covers the fourth gate structure GS4 and fills the notch 150R. The material of the third insulating layer 180 may include oxide.

[0077] Then, please refer to Figure 6 A contact CT1 electrically connected to the first element D1 is formed in a first region R1. Contacts CT2, CT3, and CT4 electrically connected to the second element D2 are formed in a second region R2. A contact CT5 electrically connected to the third element D3 is formed in a third region R3. In some embodiments, contacts CT1, CT2, CT3, CT4, and CT5 may be formed simultaneously in the same fabrication process. Contacts CT1, CT2, CT3, CT4, and CT5 may comprise conductive materials, such as copper, tungsten, ruthenium, aluminum, and / or the like.

[0078] Generally, in traditional BCD fabrication processes, an oxide layer exists between the CESL and the first element D1, the second element D2, and the third element D3. Therefore, the contacts electrically connected to the first element D1, the second element D2, and the third element D3 must pass through the oxide layer formed above the CESL, the CESL itself, and the oxide layer formed below the CESL to make contact with the first element D1, the second element D2, and the third element D3. In other words, the fabrication process for removing oxides and nitrides needs to be frequently switched during the contact formation process. On the other hand, the thickness of the oxide layer below the CESL varies at different locations, causing some issues to be considered during contact formation. For example, over-etching may occur at locations with thinner oxide layers, while at locations with thicker oxide layers, residual oxide layers between the first element D1, the second element D2, or the third element D3 and the contact may prevent a good electrical connection.

[0079] However, contacts CT1, CT2, CT3, CT4, and CT5 respectively penetrate the oxide layer (e.g., the third insulating layer 180, the second insulating layer 150, and / or the first insulating layer 142) on the etch stop layer 132, as well as the etch stop layer 132, hard mask layer 172, or hard mask layer 174 formed of a material including silicon nitride, to contact the corresponding first element D1, second element D2, and third element D3. In this way, the steps of forming contacts CT1, CT2, CT3, CT4, and CT5 do not require frequent switching of the oxide and nitride removal processes, and there are no oxide layers of different thicknesses between the etch stop layer 132 and the doped regions 102, 104, between the hard mask layer 172 and the first metal gate 162a, and between the hard mask layer 174 and the metal layer 164. Therefore, the fabrication process used to form the contacts can be improved, thereby enhancing the reliability of the semiconductor device.

[0080] The following will be through Figure 6 To illustrate semiconductor device 10. It should be noted that... Figure 6 The semiconductor device 10 shown can be formed by the method described above, but is not limited to this method.

[0081] Please refer to Figure 6The semiconductor device 10 includes a substrate 100, a first gate structure GS1, a second gate structure GS2, a third gate structure GS3, and a fourth gate structure GS4, a conductive structure CS, an insulating layer 150, and an etch stop layer 132. The substrate 100 includes a first region R1, a second region R2, and a third region R3, wherein the substrate 100 includes an isolation structure 108 disposed in the third region R3. The first gate structure GS1 and the second gate structure GS2 are disposed on the first region R1. The third gate structure GS3 and the fourth gate structure GS4 are disposed on the second region R2. The conductive structure CS is disposed on the isolation structure 108 in the third region R3. The insulating layer 150 is disposed on the first region R1, the second region R2, and the third region R3 of the substrate 100 and covers the first gate structure GS1, the second gate structure GS2, the third gate structure GS3, and the conductive structure CS, wherein the fourth gate structure GS4 is disposed on the insulating layer 150. The etch stop layer 132 includes a first part and a second part, wherein the first part is disposed between the insulating layer 150 and the first gate structure GS1, the second gate structure GS2 and the third gate structure GS3, and the second part is disposed between the insulating layer 150 and the conductive structure CS.

[0082] In some embodiments, a first portion and a second portion of the etch stop layer 132 are spaced apart by an insulating layer 150. In some embodiments, the etch stop layer 132 is in direct contact with the first gate structure GS1, the second gate structure GS2, the third gate structure GS3, and the conductive structure CS. In some embodiments, the semiconductor device 10 further includes a silicide barrier layer 120 disposed on the third gate structure GS3, wherein the silicide barrier layer 120 includes a portion disposed between the etch stop layer 132 and the third gate structure GS3 and a portion disposed between the insulating layer 150 and the third gate structure GS3. In some embodiments, the semiconductor device 10 further includes a metal layer 164 disposed on the insulating layer 150 in the third region R3, wherein the first gate structure GS1 and the second gate structure GS2 form a portion of the first element D1 in the first region R1, the third gate structure GS3 and the fourth gate structure GS4 form a portion of the second element D2 in the second region R2, and the conductive structure CS, the metal layer 164, and the insulating layer 150 disposed between the conductive structure CS and the metal layer 164 form a portion of the third element D3 in the third region R3.

[0083] In some embodiments, the insulating layer 150 includes a recess 150R disposed between the third gate structure GS3 and the conductive structure CS. A fourth gate structure GS4 is disposed in the recess 150R and includes a first metal gate 162a disposed on the bottom of the recess 150R and a second metal gate 162b disposed on the sidewall of the recess 150R. In some embodiments, the first metal gate 162a and the second metal gate 162b may be as follows: Figure 7 The first metal gate 162a' and the second metal gate 162b' are shown to be spaced apart from each other. In some embodiments, the fourth gate structure GS4 includes a hard mask layer 172 disposed on the first metal gate 162a and the second metal gate 162b.

[0084] In summary, in the semiconductor device and its formation method in the above embodiments, by designing the etch stop layer to include a first portion disposed between the insulating layer and the first, second, and third gate structures and a second portion disposed between the insulating layer and the conductive structure, the fabrication process used to form the contacts can be improved, thereby enhancing the reliability of the semiconductor device.

Claims

1. A semiconductor device, comprising: The substrate includes a first region, a second region, and a third region, wherein the substrate includes an isolation structure disposed in the third region; A first gate structure and a second gate structure are disposed on the first region; The third gate structure and the fourth gate structure are disposed on the second region; A conductive structure is disposed on the isolation structure in the third region; An insulating layer is disposed on the first region, the second region, and the third region of the substrate and covers the first gate structure, the second gate structure, the third gate structure, and the conductive structure, wherein the fourth gate structure is disposed on the insulating layer; as well as An etch stop layer includes a first portion and a second portion, wherein the first portion is disposed between the insulating layer and the first gate structure, the second gate structure and the third gate structure, the second portion is disposed between the insulating layer and the conductive structure, and the etch stop layer is in direct contact with the first gate structure, the second gate structure, the third gate structure, the conductive structure, the substrate between the first gate structure and the second gate structure, and the substrate between the second gate structure and the third gate structure.

2. The semiconductor device of claim 1, wherein the first portion and the second portion of the etch stop layer are spaced apart by the insulating layer.

3. The semiconductor device of claim 1, further comprising: A silicide barrier layer is disposed on the third gate structure and includes a portion disposed between the etch stop layer and the third gate structure, and a portion disposed between the insulating layer and the third gate structure.

4. The semiconductor device of claim 1, wherein the insulating layer includes a notch disposed between the third gate structure and the conductive structure, the fourth gate structure being disposed in the notch and including a first metal gate disposed on the bottom of the notch and a second metal gate disposed on the sidewall of the notch.

5. The semiconductor device of claim 4, wherein the first metal gate and the second metal gate are spaced apart from each other.

6. The semiconductor device of claim 4, wherein the fourth gate structure includes a hard mask layer disposed on the first metal gate and the second metal gate.

7. The semiconductor device of claim 1, further comprising: A metal layer is disposed on the insulating layer in the third region, wherein: The first gate structure and the second gate structure form part of the first element in the first region; The third gate structure and the fourth gate structure form part of the second element in the second region; The conductive structure, the metal layer, and the insulating layer disposed between the conductive structure and the metal layer form part of a third element in the third region.

8. A method of forming a semiconductor device, comprising: A substrate is provided, wherein the substrate includes a first region, a second region and a third region, and the substrate includes an isolation structure disposed in the third region; A first gate structure and a second gate structure are formed on the first region; A third gate structure is formed on the second region; A conductive structure is formed on the isolation structure in the third region; An etch stop layer is formed on the first region, the second region, and the third region to cover the first gate structure, the second gate structure, the third gate structure, and the conductive structure; A first insulating layer is formed on the etch stop layer; Remove the first insulating layer and the etch stop layer located on a portion of the second region to form an opening that exposes the portion of the second region; A second insulating layer is formed on the first insulating layer and on the sidewalls and bottom surface of the opening, wherein the second insulating layer includes a notch corresponding to the location of the opening; as well as A fourth gate structure is formed in the notch. The etch stop layer is in direct contact with the first gate structure, the second gate structure, the third gate structure, the conductive structure, the substrate between the first gate structure and the second gate structure, and the substrate between the second gate structure and the third gate structure.

9. The method of forming a semiconductor device as claimed in claim 8, wherein the step of forming the fourth gate structure comprises: A metal material layer is formed on the second insulating layer, wherein the metal material layer is formed on the sidewalls and bottom surface of the notch; A hard mask material layer is formed on the metal material layer; as well as The hard mask material layer and the metal material layer are patterned to form a first metal gate and a second metal gate on the bottom surface and the sidewall of the notch, respectively, and a hard mask layer is formed on the first metal gate and the second metal gate.

10. The method of forming a semiconductor device as claimed in claim 9, wherein the first metal gate and the second metal gate are formed to be spaced apart from each other.

11. The method of forming a semiconductor device as claimed in claim 9, wherein in the step of patterning the hard mask material layer and the metal material layer, the metal layer is formed on the second insulating layer located on the third region, wherein: The first gate structure and the second gate structure form part of the first element in the first region; The third gate structure and the fourth gate structure form part of the second element in the second region; The conductive structure, the metal layer, and the second insulating layer disposed between the conductive structure and the metal layer form part of the third element in the third region.

12. The method of forming a semiconductor device as claimed in claim 8, further comprising: Before forming the opening, the first insulating layer is subjected to a planarization process.

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