Image sensor and method of manufacturing the same and photolithography mask

Abstract

The application provides an image sensor, a manufacturing method and a photoetching mask, wherein the image sensor comprises: a first chip area, the first chip area comprising at least a first sub-chip area arranged along a first preset direction and a second sub-chip area different from the first sub-chip area; and a second chip area arranged along a second preset direction relative to the first chip area, wherein the first preset direction and the second preset direction have an included angle, and the circuit arrangement of the first chip area and the second chip area is the same. The application arranges one area of a plane array image sensor chip, forms a pattern of one chip area through at least one translation and corresponding at least two exposures, can splice the pattern during exposure, and can make the chip longer and not limited by the mask.

Description

Technical Field

[0001] This invention relates to the field of chip technology, and in particular to an area array image sensor and its fabrication method, a method for fabricating a stacked image sensor, and a photomask. Background Technology

[0002] Chips come in many varieties, such as processors and image sensors. Regardless of the type, all chips undergo multiple exposure and development processes. Resolution is a crucial indicator of a CMOS image sensor (CIS). High-resolution CIS provides more detail and better image quality. Large-array CIS has extremely important applications in aerospace, machine vision, industrial monitoring, and medical imaging. However, as the number of pixels in CMOS image sensors continues to increase, the chip size is also growing larger, especially for large-array sensors such as medium format sensors. The horizontal and vertical dimensions of these chips can reach several centimeters or even tens of centimeters, exceeding the maximum size of masks in current photolithography equipment.

[0003] As market demands increase the requirements for resolution, full-well capacity, and photosensitivity of area-array CMOS image sensors, their size is increasing while pixel size and spacing are decreasing. However, reducing pixel size and spacing leads to a decrease in full-well capacity and photosensitivity, which is unacceptable in many applications. Therefore, increasing the size of CMOS image sensors has become the mainstream approach. Large-size area-array CMOS image sensors result in excessively long horizontal and vertical dimensions, even exceeding the maximum size of photomasks in current lithography equipment. Due to the limitations of photomask size, the size of area-array CMOS image sensors has gradually reached its limit. Therefore, how to manufacture large-size area-array CMOS image sensors has become a current challenge.

[0004] It should be noted that the above introduction to the technical background is only for the purpose of providing a clear and complete explanation of the technical solutions of this application and facilitating understanding by those skilled in the art. It should not be assumed that these technical solutions are known to those skilled in the art simply because they have been described in the background section of this application. Summary of the Invention

[0005] In order to overcome the shortcomings and deficiencies of the prior art, the present invention aims to provide an area array image sensor and its fabrication method, a method for fabricating a stacked image sensor and a corresponding photomask, so as to solve the problem that it is difficult to fabricate large-size area array image sensors due to the limitation of photomask size in the prior art.

[0006] To achieve the above and other related objectives, the present invention provides an area array image sensor, the area array image sensor comprising: The first chip region includes at least a first sub-chip region arranged along a first preset direction and a second sub-chip region different from the first sub-chip region. The second chip area is arranged relative to the first chip area along a second preset direction, wherein there is an angle between the first preset direction and the second preset direction, and the circuit layout of the first chip area and the second chip area is the same.

[0007] Optionally, the area array image sensor further includes a third chip region to an Nth chip region, wherein the first chip region to the Nth chip region are arranged along the second preset direction, and N is an integer greater than or equal to 3.

[0008] Optionally, the circuit layouts of the first chip region to the Nth chip region are all the same.

[0009] Optionally, at least one intermediate chip region may be included between the first sub-chip region and the second sub-chip region.

[0010] Optionally, the first sub-chip area includes a first main area and a first auxiliary area, and the second sub-chip area includes a second main area and a second auxiliary area, with the corresponding areas in the first sub-chip area and the second sub-chip area being symmetrically distributed.

[0011] Optionally, the first sub-chip area includes a first column of light-shielding pixel areas, and the second sub-chip area includes a second column of light-shielding pixel areas, with the first column of light-shielding pixel areas and the second column of light-shielding pixel areas located on both sides of the first chip area.

[0012] Optionally, each chip area arranged along the second preset direction is provided with a column of light-shielding pixels corresponding to the first chip area.

[0013] Optionally, the first sub-chip region includes a first pad region, the second sub-chip region includes a second pad region, and the first pad region and the second pad region are located on both sides of the first chip region.

[0014] Optionally, each chip area arranged along the second preset direction is provided with a pad area corresponding to the first chip area.

[0015] Optionally, the area array image sensor further includes a chip functional area, which is disposed on at least one side of each chip area along the second preset direction.

[0016] Optionally, the chip functional area includes at least two sub-chip functional areas corresponding to the sub-chip area of ​​the first chip area.

[0017] Optionally, the sub-chip functional area includes at least one of a test structure area and a shielding ring.

[0018] Optionally, the area array image sensor includes a first chip and a second chip stacked with the first chip, wherein the first chip area and the second chip area are disposed in the first chip, and the second chip is provided with logic control circuits corresponding to each chip area.

[0019] Optionally, the logic control circuit includes several sub-circuit regions corresponding to each sub-chip region, wherein each sub-chip region includes a pixel array, and each sub-circuit region includes at least a pixel control circuit and a signal quantization circuit electrically connected to the pixel array in the corresponding sub-chip region.

[0020] Optionally, the width of the sub-circuit region along the first preset direction is less than or equal to the width of the corresponding sub-chip region.

[0021] Optionally, the second chip has an encapsulation bump on the side away from the first chip.

[0022] Optionally, the stacked first chip and the second chip are electrically connected by a hybrid bonding method.

[0023] The present invention also provides a method for manufacturing an area array image sensor according to any one of the above solutions, the method comprising: Provide semiconductor substrates; A first mask is provided and the semiconductor substrate is exposed for the first time using the first mask as a shield, wherein the area of ​​the first exposure corresponds to the first chip area; The first mask includes a first sub-mask corresponding to the first sub-chip region and a second sub-mask corresponding to the second sub-chip region; A second photomask is provided, and the semiconductor substrate is moved relative to the first photomask by a first preset distance in a second preset direction; Based on the first preset distance and using the second mask as a shield, the semiconductor substrate is exposed a second time, and the area of ​​the second exposure corresponds to the second chip area; The exposure of a chip region in the semiconductor substrate is completed based on the first exposure and the second exposure, wherein the chip region includes the first chip region and the second chip region.

[0024] Optionally, after the second exposure, the method further includes the following steps: The semiconductor substrate is continuously moved relative to the (N-1)th mask in the second preset direction by a preset distance of (N-1)th distance; wherein, based on the (N-1)th preset distance, the semiconductor substrate is exposed for the Nth time using the Nth mask as a shield, and the area of ​​the Nth exposure corresponds to the Nth chip area, where N is an integer greater than or equal to 3; The exposure of a chip region in the semiconductor substrate is completed based on the first exposure to the Nth exposure, wherein the chip region includes the first chip region to the Nth chip region.

[0025] Optionally, the first to the Nth mask are the same mask.

[0026] Optionally, the first preset distance is less than or equal to the length of the first mask in the second preset direction; and / or, the second preset distance is less than or equal to the length of the second mask in the second preset direction; and / or, the (N-1)th preset distance is less than or equal to the length of the (N-1)th mask in the second preset direction.

[0027] Optionally, the manufacturing method further includes: The semiconductor substrate is moved a preset distance relative to the current chip region, and the steps of the first exposure and the second exposure are repeated to complete the exposure of another chip region; the above steps are repeated until all chip regions in the semiconductor substrate are exposed.

[0028] Optionally, the semiconductor substrate includes a semiconductor substrate and an etching mask layer formed on the semiconductor substrate: The etching mask layer is exposed for the first time using the first mask as a shield; the etching mask layer is exposed for the second time using the second mask as a shield; and when the Nth mask exists, the etching mask layer is exposed for the Nth time using the Nth mask as a shield, where N is an integer greater than or equal to 3.

[0029] Optionally, after exposure of all chip regions on the semiconductor substrate is completed, the etched mask layer is developed to detect the splicing between adjacent chip regions.

[0030] Optionally, each mask is provided with a first alignment mark pattern and a second alignment mark pattern that cooperates with the first alignment mark pattern at both ends of the second preset direction.

[0031] Optionally, corresponding first alignment mark and second alignment mark are formed on the semiconductor substrate based on the first alignment mark pattern and the second alignment mark pattern.

[0032] Optionally, the first alignment mark pattern is block-shaped, the second alignment mark pattern is ring-shaped, and the outer edge dimension of the first alignment mark pattern is smaller than the inner edge dimension of the second alignment mark pattern; or, the first alignment mark pattern is ring-shaped, the second alignment mark pattern is block-shaped, and the outer edge dimension of the second alignment mark pattern is smaller than the inner edge dimension of the first alignment mark pattern.

[0033] Optionally, the manufacturing method further includes: Based on measurements of the first comparison mark and the second alignment mark, the positions of the first exposure and the second exposure are detected.

[0034] Optionally, each of the photomasks further includes a third alignment mark pattern and a fourth alignment mark pattern that are respectively disposed at both ends in the second preset direction, and the first line connecting the first alignment mark pattern and the second alignment mark pattern is parallel to each other and has a gap with the second line connecting the third alignment mark pattern and the fourth alignment mark pattern.

[0035] Optionally, the first alignment mark pattern, the second alignment mark pattern, the third alignment mark pattern, and the fourth alignment mark pattern are disposed at the top corners of the corresponding photomask.

[0036] Optionally, the line connecting the first alignment mark pattern and the third alignment mark pattern is located outside the device pattern area, and the line connecting the second alignment mark pattern and the fourth alignment mark pattern crosses the device pattern area; or, the line connecting the first alignment mark pattern and the third alignment mark pattern crosses the device pattern area, and the line connecting the second alignment mark pattern and the fourth alignment mark pattern is located outside the device pattern area.

[0037] The present invention also provides a method for manufacturing a stacked image sensor, the method comprising: A first chip is prepared by using the fabrication method of an area array image sensor as described in any of the above schemes, the first chip including a pixel array region; A second chip is prepared by using the fabrication method of the area array image sensor described in any of the above schemes, the second chip including a logic control circuit area; The first chip and the second chip are stacked and bonded to achieve an electrical connection between the logic control circuit area and the pixel array area.

[0038] The present invention also provides a photomask suitable for fabricating a planar image sensor as described in any of the above embodiments, wherein the photomask is at least one of the first mask and the second mask; wherein, when continuously present up to the Nth mask, the photomask is at least one of the first mask to the Nth mask.

[0039] Optionally, the photomask includes a device pattern area and an alignment pattern area, wherein when at least one of a first alignment mark pattern, a second alignment mark pattern, a third alignment mark pattern, and a fourth alignment mark pattern is present, each alignment mark pattern is located in the alignment pattern area.

[0040] The area array image sensor, its fabrication method, its stacked image sensor fabrication method, and the corresponding photomask of this invention offer the following advantages: A splicing process is used to assemble a complete CIS chip based on a set of photomasks. A pattern for a chip region is formed through at least one translation and corresponding exposure. By splicing the pattern during exposure, the chip can be made longer. Furthermore, it is compatible with existing fabrication equipment, and the process is simple, requiring no complex operations or complex packaging and splicing techniques. This allows for the production of larger area array image sensors, with the size limited only by the wafer size, not by the photomask size. The modular design and splicing method enables the manufacture of larger area array image sensors and reduces wafer area waste. Additionally, the modular design allows for the splicing of the same module area into sensors of various sizes, improving the utilization rate of the photomask. Fewer photomasks effectively reduce chip costs. Moreover, reusable photomasks can be quickly put into production, shortening the chip production cycle. Attached Figure Description

[0041] Figure 1 The diagram shows a planar structure of the area array image sensor in Embodiment 1 of the present invention. Figure 2 The diagram shown illustrates the semiconductor substrate provided in the fabrication method of Example 2. Figure 3 The diagram shown is a structural schematic of the first mask provided in the manufacturing method of Embodiment 2; Figure 4 The diagram shown illustrates the first exposure during the manufacturing process of Example 2; Figure 5 The diagram shows a second exposure during the manufacturing process of Example 2; Figure 6 This is a schematic diagram of the structure obtained after exposure and development in the manufacturing method of Example 2; Figure 7 The image shown is a plan view of an area array image sensor chip obtained in Example 2; Figure 8 This is a schematic diagram of the structure of another first mask provided in Embodiment 2; Figure 9 This is a schematic diagram showing that one wafer corresponds to multiple chip regions during the fabrication process of Example 2; Figure 10 The diagram shown is a schematic diagram of another area array image sensor chip obtained by the present invention; Figure 11 This is a schematic diagram of another type of area array image sensor chip. Figure 12 This invention provides an image sensor chip with BLC columns. Figure 13 This invention provides an image sensor chip with a chip functional area. Figure 14 This invention presents a stacked area array image sensor chip. Detailed Implementation

[0042] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0043] In the detailed description of embodiments of the present invention, for ease of explanation, the cross-sectional views illustrating the device structure may be partially enlarged and not to scale. Furthermore, the schematic diagrams are merely examples and should not limit the scope of protection of the present invention. In actual fabrication, the three-dimensional spatial dimensions of length, width, and depth should be included.

[0044] For ease of description, spatial relation terms such as "below," "below," "less than," "below," "above," and "upper" may be used herein to describe the relationship between one element or feature shown in the accompanying drawings and other elements or features. It will be understood that these spatial relation terms are intended to include directions other than those depicted in the drawings for devices in use or operation. When a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or there may be one or more layers in between. Furthermore, the term "between" as used in this invention includes both endpoint values.

[0045] In the context of this application, the structure described above the first feature may include embodiments in which the first and second features are formed in direct contact, or embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

[0046] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the illustrations only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0047] To further illustrate the technical means and effects adopted by the present invention to achieve the intended purpose, the following detailed description, in conjunction with the accompanying drawings and preferred embodiments, details the specific implementation methods, structure, features, and effects of the fabrication method of the area array image sensor proposed according to the present invention: Example 1: Figure 1 This is a schematic diagram of the planar structure of the area array image sensor in Embodiment 1 of the present invention. Figure 2-7 This is a schematic diagram of the structure obtained in each step of the fabrication process of the area array image sensor in Embodiment 1 of the present invention, wherein, Figure 3 This is a schematic diagram of the planar structure of a mask used in Embodiment 1 of the present invention. Additionally, Figure 8 This is a schematic diagram of the planar structure of another mask provided in Embodiment 1 of the present invention.

[0048] like Figure 1 As shown, Embodiment 1 of the present invention provides an area array image sensor 10, wherein the area array image sensor 10 includes a first chip region 10a, the first chip region 10a including at least a first sub-chip region 11 arranged along a first preset direction and a second sub-chip region 12 different from the first sub-chip region 11; wherein, the difference between the two means that their circuit settings are different, that is, their circuit designs are not completely the same. In this embodiment, the two are prepared based on different masks. In addition, the circuit settings of each sub-chip can be set according to the circuit requirements in the actual image sensor.

[0049] In addition, the area array image sensor 10 further includes a second chip region 10b, which is arranged relative to the first chip region 10a along a second preset direction. The first preset direction and the second preset direction form an angle, and the circuit arrangements of the first chip region 10a and the second chip region 10b are identical. In this embodiment, the first preset direction and the second preset direction are mutually perpendicular, and can represent the row and column directions of the area array image sensor. Of course, in other embodiments, other angles can be set according to actual needs.

[0050] In this design, the first chip region 10a and the second chip region 10b have the same circuit layout, meaning their circuit designs are identical. They can be fabricated using the same mask through a translational splicing method. This simplifies the chip's structural design. CMOS image sensors (CIS) are largely composed of repetitive units. Based on the repetitive pixel array and peripheral logic control circuit structure, modular design is possible. For this purpose, a splicing technique can be used to reuse a single mask to fabricate a complete CIS chip. Specifically, pixels and peripheral readout circuits are divided into smaller repetitive unit blocks. The same mask is exposed multiple times to form several identical repetitive unit blocks. Finally, these repetitive unit blocks can be spliced ​​together with very high precision to fabricate a complete single CIS chip.

[0051] As an example, the area array image sensor further includes a third to an Nth chip region, the first to the Nth chip regions being arranged along a second preset direction, where N is an integer greater than or equal to 3. See also Figure 7 As shown in the figure, a single image sensor chip also includes a third chip region 10c, with the first to third chip regions arranged sequentially along a second preset direction. Therefore, based on this invention, a simplified structure can be used to design an area array sensor chip of the required size. In one example, the dimensions of both the first and second sub-chip regions are 30mm × 15mm. Furthermore, in other examples, this invention can be used to arrange and fabricate medium format image sensors of different sizes, such as 45mm x 30mm, 60mm x 45mm, and 60mm x 60mm. The modular design and splicing method overcomes mask size limitations, enabling the fabrication of ultra-large array sensors such as medium format sensors. Additionally, fewer masks can effectively reduce chip costs.

[0052] In a further example, the circuit layout of the first chip region to the Nth chip region is the same; that is, each chip region can be fabricated using the same set of photomasks. See also... Figure 7 In the example, the first chip region 10a, the second chip region 10b, and the third chip region 10c are all fabricated using the same set of masks, so a single area array image sensor chip in this example can be fabricated using only one set of masks.

[0053] Additionally, in other embodiments, see Figure 10 As shown, a single area array image sensor chip can also include a first chip region 10a, a second chip region 10b, a third chip region 10c, and a fourth chip region 10d arranged sequentially along the second direction. It can be understood that the image sensor 10 can be considered as a chip region, that is, a single area array image sensor chip. A semiconductor substrate can have multiple chip regions as described above; in other words, multiple single chips can be formed.

[0054] As an example, at least one intermediate chip region is further included between the first sub-chip region 11 and the second sub-chip region 12. See also Figure 11 As shown in the figure, an intermediate chip region 13 is disposed between the first sub-chip region 11 and the second sub-chip region 12. The circuit design of the intermediate chip region can be set according to actual needs, and its corresponding mask can be the same as or different from the first sub-mask, and similarly, it can be the same as or different from the second sub-mask. It is understood that in this example, the first sub-mask corresponding to the first sub-chip region 11, the second sub-mask corresponding to the second sub-chip region 12, and the mask corresponding to the intermediate chip region 13 together constitute the first mask of this embodiment. The modular design and splicing method allows for the manufacture of larger area array image sensors and reduces wasted wafer area. Furthermore, the modular design allows for the splicing of the same modules into sensors of various sizes, helping to improve mask utilization; fewer masks can effectively reduce chip costs. Reusable masks can also be quickly put into production, shortening the chip production cycle.

[0055] As an example, see Figure 12As shown, the first sub-chip region 11 includes a first main region 11a and a first auxiliary region 11b, and the second sub-chip region 12 includes a second main region 12a and a second auxiliary region 12b. In this example, the first auxiliary region 11b is arranged relative to the first main region 11a along a first preset direction, and the second auxiliary region 12b is arranged relative to the second main region 12a along the first preset direction. The corresponding regions in the first sub-chip region 11 and the second sub-chip region 12 are symmetrically distributed. In this example, the first main region 11a and the second main region 12a are symmetrically distributed along the splicing plane of the two sub-chip regions, and the first auxiliary region 12a and the second auxiliary region 12b are symmetrically distributed along the splicing plane of the two sub-chip regions. This facilitates the modularization and arrangement of the various functional areas of the area array image sensor chip and is also beneficial for wiring.

[0056] See further examples. Figure 12 As shown, the first sub-chip area 11 includes a first column of light-shielding pixel areas 401, and the second sub-chip area 12 includes a second column of light-shielding pixel areas 402. The first column of light-shielding pixel areas 401 and the second column of light-shielding pixel areas 402 are located on both sides of the first chip area 10a. The first column of light-shielding pixel areas 401 includes at least one column of pixels, and the second column of light-shielding pixel areas 402 includes at least one column of pixels. The first column of light-shielding pixel areas 401 is located on the left side of the first sub-chip area 11, and the second column of light-shielding pixel areas 402 is located on the right side of the second sub-chip area 12, thus providing BLC (black level correction) columns on both sides of the first chip area 10a. In this example, the first column of light-shielding pixel areas 401 can be considered to correspond to the aforementioned first auxiliary area 11b, and the second column of light-shielding pixel areas 402 can be considered to correspond to the aforementioned first auxiliary area 12b. The first column of light-shielding pixel areas 401 and the second column of light-shielding pixel areas 402 are symmetrically distributed, and the remaining circuitry corresponds to the aforementioned main area, also symmetrically distributed.

[0057] In a further example, each chip region arranged along the second preset direction is provided with a column of light-shielding pixels corresponding to the first chip region. For example, such as Figure 12 In the chip shown, the second chip region 10b also has a third column of light-shielding pixel regions 403 corresponding to the first column of light-shielding pixel regions 401 in the first chip region 10a, and a fourth column of light-shielding pixel regions 404 corresponding to the second column of light-shielding pixel regions 402. This ensures that both sides of the entire area array image sensor chip have BLC columns, effectively improving dark current.

[0058] As an example, the first sub-chip region 11 includes a first pad region (not shown in the figure), and the second sub-chip region 12 includes a second pad region (not shown in the figure). The first pad region and the second pad region are located on both sides of the first chip region. The pad regions can be located outside the pixel array and peripheral logic control circuits to allow for electrical outlining of each circuit based on the actual image sensor requirements. A symmetrical arrangement similar to the column-shading pixel regions in the figure can be referenced.

[0059] As an example, see Figure 13 As shown, the area array image sensor further includes a chip functional area 500, which is disposed on at least one side of each chip area along the second preset direction. For example, Figure 13 In this embodiment, the chip functional area 500 is located above the first chip area 10a and the second chip area 10b. Of course, in other embodiments, it can also be located below, to the left or to the right of each chip area.

[0060] In a further example, continue to participate Figure 13 As shown, the chip functional area 500 includes at least two sub-chip functional areas corresponding to the sub-chip areas of the first chip area 10a. For example, the chip functional area 500 includes a first sub-chip functional area 500a corresponding to the first sub-chip area 11 and a second sub-chip functional area 500b corresponding to the second sub-chip area 12. Further optionally, the sub-chip functional areas correspond to the positions of the sub-chips in each chip area, which can facilitate the implementation of auxiliary functions within the functional areas.

[0061] In one example, the sub-chip functional area (such as the first sub-chip functional area 500a) includes at least one of a test key area 501 and a seal ring 502. The test key area can be used to detect process conditions during wafer fabrication, and the seal ring can prevent moisture intrusion. Additionally, the seal ring can be grounded to shield against external interference. Of course, in other examples, seal rings can be provided on both the left and right sides of each chip area to further protect the chip. Furthermore, in other examples, other necessary structures can be fabricated in the chip functional area 500.

[0062] As an example, see Figure 14As shown in the example, this provides a design for a stacked area array image sensor 600. The area array image sensor 600 includes a first chip 601 and a second chip 602 stacked with the first chip 601. The first chip region 10a and the second chip region 10b are disposed within the first chip 601, and the second chip 602 is provided with logic control circuits corresponding to each chip region (such as the first chip region 10a and the second chip region 10b). The logic control circuits are electrically connected to their respective chip regions to enable operation with each chip region.

[0063] In a further example, the logic control circuit includes several sub-circuit regions corresponding to each sub-chip region, for example, Figure 14 The structure shown can be understood as a sub-chip region and a corresponding sub-circuit region. The sub-chip region includes a pixel array, which comprises several pixel units 601a arranged in rows and columns. Each pixel unit can be composed of a single photosensitive element and its corresponding pixel circuit, or multiple photosensitive elements sharing a common structure, depending on the actual design. Furthermore, the sub-circuit region includes at least a pixel control circuit and a signal quantization circuit electrically connected to the pixel array in the corresponding sub-chip region. The sub-circuit region can be any circuit in the peripheral logic control circuitry of an existing image sensor. In one example, such as... Figure 14 As shown, the sub-circuit area includes several signal quantization circuits 602a corresponding to columns in the pixel array. Of course, other circuits can be set according to the actual working requirements of the image sensor, as shown in the other necessary circuit areas in the figure.

[0064] As an example, the width of the sub-circuit area along the first preset direction is less than or equal to the width of the corresponding sub-chip area (such as pixel pitch), which facilitates wiring and enables electrical connection between the chip and the circuit, such as reserving space for column ADC control circuit and routing.

[0065] As an example, the second chip has a ballgrid array (BGA) on the side away from the first chip, which can effectively achieve chip packaging.

[0066] As an example, the first and second stacked chips are electrically connected via hybrid bonding (HB). Any existing hybrid bonding method can be used for this interconnection, enabling chip-to-chip interconnection within the stack. This allows for dense interconnection between the stacked first and second chips based on hybrid bonding technology, facilitating a smaller form factor and allowing for more interconnections between the two chips, resulting in smaller and simpler circuits. Furthermore, they can be stacked on top of each other without the need for fan-in and fan-out configurations.

[0067] Example 2: like Figure 2-8 As shown, and see also Figure 1 and Figure 9-14 The method for fabricating an area array image sensor provided in Embodiment 2 of this invention is applicable to the fabrication of any type of image sensor described in Embodiment 1. The description of the structure and related aspects of this method can be found in Embodiment 1 and will not be repeated here. The method for fabricating the area array image sensor includes: First, such as Figure 2 As shown, a semiconductor substrate is provided. Specifically, in one example, the semiconductor substrate includes a semiconductor substrate 100 and an etching mask layer 200 formed on the semiconductor substrate 100. Of course, in other embodiments, the semiconductor substrate can also be any substrate structure commonly used in the art, suitable for subsequent steps, and can be an intermediate structure stack in the device fabrication process.

[0068] In this embodiment, the etching mask layer 200 can be a photoresist, such as a negative photoresist. Of course, the photoresist can also be a positive photoresist. The semiconductor substrate 100 is a wafer. In other embodiments, the etching mask layer 200 can also be made of other materials used to block etching.

[0069] Next, as Figure 3 and Figure 4 As shown, a first mask 300a is provided, and the semiconductor substrate is subjected to a first exposure using the first mask 300a as a shield. The area of ​​the first exposure corresponds to the first chip region 10a. Figure 2 The first mask 300a has a light-transmitting area and a non-light-transmitting area. The light-transmitting area and the non-light-transmitting area together form the exposure pattern. The exposed pattern corresponds to the circuit pattern on the area array image sensor 10. The specific pattern is set according to actual conditions.

[0070] Specifically, in one example, the etch mask layer 200 is first exposed using a first mask 300a and a stepper lithography machine. For example... Figure 4As shown, after the first exposure, the etch mask layer 200 forms a pattern corresponding to a portion of the circuitry in the area array image sensor 10 at the corresponding position in the first chip region 10a. It is understood that the pattern will become visible after the etch mask layer 200 is developed. The figure does not show the specific pattern of the mask; its specific pattern can be arranged according to the actual circuit design, etc.

[0071] The first mask 300a includes a first sub-mask 301 corresponding to the first sub-chip region 11 and a second sub-mask 302 corresponding to the second sub-chip region 12. It is understood that the first sub-mask 301 and the second sub-mask 302 together constitute a set of masks as the first mask 300a. It is also understood that when the first chip region 10a includes other sub-chip regions, the masks corresponding to these additional sub-chip regions collectively serve as the first mask 300a. In one example, the corresponding first sub-chip region 11 and second sub-chip region 12 can be fabricated based on the first sub-mask 301 and the second sub-mask 302 respectively to obtain the first chip region 10a. That is, they are fabricated in different process steps, such as fabricating the first sub-chip region 11 first and then the second sub-chip region 12. Of course, in other examples, other existing splicing processes can also be used to fabricate it.

[0072] Continue, as Figure 3 and Figure 5 As shown, the semiconductor substrate is moved a first preset distance relative to the first mask 300a in a second preset direction. The second preset direction is the same as one of the directions in which the area array image sensor 10 needs to be stitched together. Specifically, in one example, after the first exposure is completed, the semiconductor substrate is carried by the stage and stepped a first preset distance to the position of the next exposure field.

[0073] Furthermore, a second mask 300b is provided. After moving a first preset distance, the semiconductor substrate is exposed a second time using the second mask 300b as a shield. The area exposed in the second exposure corresponds to the first chip region 10b. Figure 2 As can be understood, in the illustrated example, the first mask 300a and the second mask 300b are fabricated using the same mask. Thus, based on the design of this invention, exposure of two chip regions can be achieved using the same mask. To clearly illustrate the concept of this example, they are shown as 300a and 300b respectively, but in reality, they use the same mask.

[0074] Specifically, the etched mask layer 200 is subjected to a second exposure using a second mask and a stepper lithography machine. After the second exposure, the etched mask layer 200 forms a pattern in the first chip region 10a corresponding to a portion of the circuitry in the area array image sensor 10. It is understood that the size of the exposed area is the same as, or slightly smaller than, the size of the corresponding mask, thereby ensuring that other areas of the etched mask layer 200 are not exposed and become ineffective.

[0075] Based on the first and second exposures, a chip region (as shown in the corresponding image) in the semiconductor substrate is completed. Figure 2 The exposure of the image sensor 10 is performed by two exposures to expose a chip region in the semiconductor substrate. The chip region includes a first chip region 10a and a second chip region 10b.

[0076] In this embodiment, the chip region is formed based on two exposure stitching processes; that is, the pattern of one area array image sensor 10 is formed based on photolithography stitching. Each chip region corresponds to one area array image sensor 10 chip. In one example, such as Figure 7 As shown, each chip region (such as the first chip region 10a and the second chip region 10b) corresponds to three vertically arranged device distribution blocks. Based on the splicing of these two, the lowermost device area of ​​the first chip region 10a and the uppermost device of the second chip region 10b can be spliced ​​together, thereby obtaining effective devices, such as a precisely spliced ​​pixel array. Of course, in other embodiments, a chip region can also be formed by three or more exposures, that is, in addition to the first chip region 10a and the second chip region 10b, a chip region can also include more regions such as the third chip region 10c. (See reference...) Figure 7 As shown. Of course, depending on the length and width of the area array image sensor 10, it can be divided into more chip areas to be formed through more exposures and stitching, so that the size of the area array image sensor 10 is not limited by the size of the mask; the structure of the image sensor that can be formed can be seen in [reference needed]. Figure 10 and Figure 11 The example is shown in the image.

[0077] As an example, see Figure 9As shown, the process also includes the step of fabricating other chip regions on a semiconductor substrate. That is, several area array sensor chips can be fabricated on a single semiconductor substrate (such as a wafer). During fabrication, the process may involve: after one chip region is exposed, the semiconductor substrate is moved relative to the corresponding mask in the desired direction by a preset interval distance. For example, after the current chip region is exposed, it is moved relative to the mask used when the last set region or preset region was formed, until the next chip region begins exposure. The steps described above, such as the first and second exposures, are repeated to complete the exposure of at least one other chip region 10. Of course, in one example, a third or subsequent exposure can be performed to obtain an area array image sensor of the required size. Further, the above steps are repeated until all chip regions on the semiconductor substrate have been exposed.

[0078] It is understandable that multiple chip regions are designed on each semiconductor substrate. Figure 9 The substrate has 7 chip regions. A chip region is formed based on the first exposure, the second exposure, etc. After the exposure of a chip region is completed, the mask needs to be moved to the next chip region that needs to be exposed, and the first exposure, the second exposure, etc. are repeated for the next chip region, and so on, until the chip regions on the entire semiconductor substrate are exposed.

[0079] The required direction is determined based on the position of the chip regions designed on the wafer. For example, it could be the direction of chip region ① moving to chip region ② (arrow m in the diagram); it could also be the direction of chip region ② moving to chip region ③; or it could be the direction of chip region ③ moving to chip region ⑥ (arrow n in the diagram), depending on the actual setting. In this example, chip regions ①, ②, ③, ④, ⑤, ⑥, and ⑦ are numbered sequentially from top to bottom and left to right. Arrow m aligns with the first preset direction, and arrow n forms an angle with the first preset direction. In one example, each module region in the image sensor is stitched together in a serpentine pattern. Of course, in other examples, other stitching sequences can be used to complete the fabrication of the area array sensor in both the horizontal and vertical directions.

[0080] In one example, a semiconductor substrate is moved relative to another chip by a predetermined interval distance in a first predetermined direction or in a direction perpendicular to the first predetermined direction. This can serve as a dicing path between adjacent chips, where the predetermined interval distance for each movement can be specifically set. In a preferred example, the adjacent chips are positioned so that the first predetermined direction and the second predetermined direction perpendicular to it are aligned. This improves process stability, simplifies the process, and increases yield.

[0081] In this embodiment, the first and second masks are the same mask, meaning the patterns for the two exposures are identical. Therefore, it is not necessary to change to a mask with a different pattern for each exposure; only the semiconductor substrate needs to be moved to the next exposure area. Furthermore, the circuitry of the array image sensor 10 can be arranged so that the circuit patterns of the first chip region 10a and the second chip region 10b are identical. The specific mask pattern is determined based on actual settings. Of course, in other examples, the first and second masks can also be different masks, meaning the patterns on the first and second masks are not identical.

[0082] In one example, the first preset distance is less than or equal to the length of the first mask in the second preset direction. This facilitates the alignment or partial overlap of the edges of the first chip region 10a and the second chip region 10b, which can improve the stitching effect between the pattern of the next exposure and the pattern of the previous exposure. It is also beneficial for the application of the area array image sensor 10, where the circuitry between the first chip region 10a and the second chip region 10b requires conductive connection. Of course, in other embodiments, the first preset distance can be greater than the length of the first mask in the second preset direction, thereby allowing for control over the distance requirements between adjacent exposure areas. For example, when the circuitry between the first chip region 10a and the second chip region 10b does not require conductive connection. Furthermore, the spacing between the first chip region 10a and the second chip region 10b can be controlled to ensure that the spacing between two adjacent pixels in the first preset direction is the same.

[0083] Of course, similarly, the second preset distance and the subsequent possible Nth preset distance can all be designed as described above, that is, the Nth preset distance is less than or equal to the length of the N-1th preset mask in the second preset direction, which is equivalent to being less than or equal to the length of the previous preset mask.

[0084] In this embodiment, see Figure 3 As shown, each mask has a first alignment mark pattern 310 and a second alignment mark pattern 320 that cooperates with the first alignment mark pattern 310 at both ends in the second preset direction. The first alignment mark pattern 310 and the second alignment mark pattern 320 are, for example, OVL boxes. Each mask may include a first mask to an Nth mask. When the semiconductor substrate is exposed by the mask for masking, a first alignment mark 311 corresponding to the first alignment mark pattern 310 and a second alignment mark 321 corresponding to the second alignment mark pattern 320 will be formed on the semiconductor substrate.

[0085] Among them, see Figure 6As shown, after exposure of all chip regions 10 on the semiconductor substrate is completed, the etching mask layer 200 is developed. In this embodiment, the etching mask layer 200 uses negative photoresist. Therefore, after developing the etching mask layer 200, the negative photoresist in the unilluminated areas is retained, while the negative photoresist in the illuminated areas is removed. After forming the patterned etching mask layer 200, the semiconductor substrate 100 is then subjected to further processing steps, such as dry etching, wet etching, oxidation, etc.

[0086] In a specific example, a first alignment mark 311 corresponding to the first alignment mark pattern 310 and a second alignment mark 321 corresponding to the second alignment mark pattern 320 are formed on the etching mask layer 200 of the semiconductor substrate. The first alignment mark 311 and the second alignment mark 321 are used as a reference for subsequent detection of the exposure position. That is, by detecting the positional relationship between the first alignment mark 311 and the second alignment mark 321, the exposure position can be determined, thereby achieving ideal splicing based on the mutually cooperating alignment marks. It will be understood by those skilled in the art that the cooperation here can be understood as the cooperation of adjacent positions during device fabrication. For example, the lower side of the first mask has a second alignment mark pattern, and the upper side of the second mask has a first alignment mark pattern. Corresponding alignment marks can be formed on the semiconductor substrate based on the first alignment mark pattern on the upper side of the second mask and the second alignment mark pattern on the lower side of the first mask, and then measurements can be performed based on the cooperation between the alignment marks to detect splicing.

[0087] Furthermore, the fabrication method also includes: detecting the positions of the first exposure and the second exposure based on the measurement of the first alignment mark 311 and the second alignment mark 321. In a specific example, when the etch mask layer 200 is exposed, the first alignment mark 311 and the second alignment mark 321 are formed in both the first chip region 10a and the second chip region 10b. After exposure, the etch mask layer 200 is developed to reveal all the first alignment marks 311 and the second alignment marks 321. Then, the developed semiconductor substrate is transferred to an OVL metrology instrument for measurement.

[0088] In one example, after exposure of all chip regions on the semiconductor substrate is completed, the etch mask layer is developed. That is, after the entire wafer has been exposed, the wafer is developed, and then transferred to an OVL metrology system for measurement. In a further example, the measurement of alignment marks, as described in other prior art, can also be performed simultaneously.

[0089] As an example, in the second preset direction, the first alignment mark pattern 310 is block-shaped, and the second alignment mark pattern 320 is ring-shaped, with the outer edge dimension of the first alignment mark pattern 310 being smaller than the inner edge dimension of the second alignment mark pattern 320. Of course, in other embodiments, the first alignment mark pattern 310 can also be ring-shaped, and the second alignment mark pattern 320 can be block-shaped, with the outer edge dimension of the second alignment mark pattern 320 being smaller than the inner edge dimension of the first alignment mark pattern 310. By setting one of the first alignment mark pattern 310 and the second alignment mark pattern 320 to be block-shaped and the other to be ring-shaped, it is easier to detect whether the exposure stitching was successful subsequently. Whether the first alignment mark pattern 310 or the second alignment mark pattern 320 is ring-shaped depends on the polarity of the photoresist used. Of course, in other embodiments, the first alignment mark pattern 310 and the second alignment mark pattern 320 can also be other patterns, as long as the actual exposure position can be detected subsequently.

[0090] In one example, the semiconductor substrate moves a first predetermined distance relative to the first mask in a second predetermined direction, equal to the distance between the center points of the first alignment mark pattern 310 and the second alignment mark pattern 320 on the mask. Thus, after two exposures, the center points of the second alignment mark in the first chip region 10a and the first alignment mark in the second chip region 10b are aligned, facilitating measurement.

[0091] Specifically, if the measurement positions of the first and second exposures are the same as the preset exposure positions, it indicates that the stitching of the two exposures is successful. In a further optional example, if the stitching is successful, subsequent process steps can be directly performed. If the measurement shows that the stitching is unsuccessful, the photolithographic mask layer (such as a photoresist layer) can be removed, and the exposure can be repeated. Subsequent etching steps can then be performed after successful stitching is detected, thus avoiding unnecessary steps and enabling stitching detection based on the photoresist layer. Of course, in other examples, alignment marks can also be fabricated at the positions corresponding to the dicing paths, and detection can be performed based on these alignment marks. Marks located on the dicing paths do not affect device fabrication.

[0092] In one example, if Figure 7 If a1 is equal to half the width difference between the first alignment mark pattern 310 and the second alignment mark pattern 320, and b1 is equal to half the length difference between the first alignment mark pattern 310 and the second alignment mark pattern 320, then the stitching of the two exposures is successful. Of course, a standard for successful stitching can be formed based on the design of the alignment marks. Figure 9 In the middle, c1 represents the gap between the two alignment marks between the two chip regions 10. Figure 7 The measurements of a1 and b1 can be used to detect whether the splicing within a chip is successful; Figure 9In this context, c1 can represent the region between two adjacent chips, such as a cutting channel area where subsequent cutting is performed to obtain the corresponding chip. In one example, scene measurement for c1 may not be required.

[0093] Alternatively, the photolithographic mask layer 200 can also be implemented based on positive photoresist, i.e., the fabrication process and the resulting marking pattern are based on positive photoresist for splicing detection. For example, the first alignment marking pattern 310 is block-shaped, and the second alignment marking pattern 320 is ring-shaped, with the outer edge dimension of the second alignment marking pattern being smaller than the inner edge dimension of the first alignment marking pattern. This can be achieved using a similar approach described above.

[0094] As an example, similar to the first and second alignment mark patterns, each mask also has a third and a fourth alignment mark pattern. Specifically, each mask has a third alignment mark pattern and a fourth alignment mark pattern that mates with the third alignment mark pattern at both ends in the second preset direction, further improving the splicing effect. Furthermore, the third and fourth alignment marks are obtained during the process to facilitate splicing detection.

[0095] Specifically, in one example, such as Figure 3 As shown, each photomask (such as the first photomask 300a) further includes a third alignment mark pattern 330 and a fourth alignment mark pattern 340 that cooperates with the third alignment mark pattern 330 at both ends in a second preset direction. The first line connecting the first alignment mark pattern 310 and the second alignment mark pattern 320 is parallel to and spaced from the second line connecting the third alignment mark pattern 330 and the fourth alignment mark pattern 340. For example, the first alignment mark pattern 310 and the second alignment mark pattern 320 are located on the left side of the photomask, and the third alignment mark pattern 330 and the fourth alignment mark pattern 340 are located on the right side. Preferably, the first alignment mark pattern 310 and the third alignment mark pattern 330 have the same pattern, only their positions on the photomask are different; the second alignment mark pattern 320 and the fourth alignment mark pattern 340 have the same pattern, only their positions on the photomask are different. By providing alignment mark patterns on both the left and right edges of the photomask, it is easier to subsequently detect the actual exposure position. Of course, other patterns and locations can be designed in other examples.

[0096] Furthermore, the first alignment mark pattern 310, the second alignment mark pattern 320, the third alignment mark pattern 330, and the fourth alignment mark pattern 340 are disposed at the top corners of the corresponding photomasks, such as corresponding to the chip dicing area. When the wafer is diced, the alignment marks on the semiconductor substrate 100 can be cut off, so that there are no alignment marks on the edge of the linear image sensor 10.

[0097] When splicing different modules (blocks), it is necessary to ensure a smooth transition of circuitry at the splicing lines. However, the complex edge structures of modules make it difficult to achieve perfect splicing of components, wires, and holes using conventional methods. Furthermore, CIS (Computer Integrated Systems) is highly sensitive to changes in pixel structure, which can easily lead to uneven images at the splicing lines of different modules, affecting consistency. The design based on this embodiment facilitates efficient splicing.

[0098] As an example, the method for fabricating an area array image sensor of the present invention further includes the step of providing a functional mask, and exposing the semiconductor substrate based on the functional mask to form functional regions in the semiconductor substrate, wherein the functional regions are located on one side of each chip region. In one example, see [reference needed]. Figure 13 As shown, for example, a functional mask can be used to fabricate a testkey and a seal ring. The testkey can be used to detect process conditions during wafer fabrication, while the seal ring prevents moisture intrusion. Furthermore, grounding the seal ring can shield against external interference. The structure of the chip's functional areas can be found in the description in Embodiment 1, and will not be repeated here.

[0099] As an example, after the second exposure, the procedure further includes: moving the semiconductor substrate relative to the first mask by a second preset distance in a second preset direction; then, after exposure based on the second mask, continuously providing the Nth mask, and correspondingly continuously moving the semiconductor substrate relative to the (N-1)th mask by a (N-1)th preset distance in the second preset direction; wherein, based on the (N-1)th preset distance, and using the Nth mask as a shield, the semiconductor substrate is exposed for the Nth time, and the area of ​​the Nth exposure corresponds to the Nth chip region, where N is an integer greater than or equal to 3; that is, in this step, at least three exposures are performed on the second preset square, and the exposure of a chip region in the semiconductor substrate is completed based on the first exposure to the Nth exposure, and the chip region includes the first chip region to the Nth chip region, thereby obtaining a sensor with the required size along the second preset direction.

[0100] Furthermore, the first to Nth masks are all the same mask. In this embodiment, as... Figure 7 As shown, the first, second, and third masks are all the same mask, and the patterns on each mask are identical, thus obtaining several identical device modules.

[0101] Preferably, the semiconductor substrate moves the same distance from the first preset distance to the Nth preset distance in the second preset direction, and each distance is less than or equal to the length of the mask in the second preset direction. This ensures that the edges of adjacent regions in a chip region 10 are aligned or partially overlapped, so that the pattern of the next exposure is stitched together with the pattern of the previous exposure.

[0102] Those skilled in the art should understand that the remaining structures and working principles of this embodiment are the same as those of Embodiment 1, and will not be repeated here.

[0103] Example 3: This embodiment also provides a method for fabricating a stacked image sensor, wherein the method includes the steps of: fabricating a first chip using the fabrication method of an area array image sensor as described in any one of the above embodiments, the first chip including a pixel array region; fabricating a second chip using the fabrication method of an area array image sensor as described in any one of the above embodiments, the second chip including a logic control circuit region; stacking and bonding the first chip and the second chip to achieve an electrical connection between the logic control circuit region and the pixel array region. The fabrication processes of the first chip and the second chip can be found in the descriptions of Embodiments 1 and 2, and will not be repeated here.

[0104] Specifically, in this embodiment, the pixel array and readout circuit can be designed as a stacked structure, consisting of a first chip (pixel array die) 601 and a second chip (ASIC die) 602, which are then connected by bonding (e.g., HB, hybrid bond) 603. In one example, the pixel array die mainly comprises an m×n pixel array; the ASIC die includes a column ADC (column quantization circuit) and other necessary circuits. The column ADC is used to quantize the Vrst (reset) signal and Vsig (image) signal output by the pixels, completing the A / D conversion (analog-to-digital conversion). Furthermore, it should be noted that the design of each specific circuit in the aforementioned pixel array area and readout circuit area can adopt existing designs.

[0105] In one example, the electrical connection between the first chip and the second chip is achieved through hybrid bonding (HB), where HB connections can provide more and tighter interconnections between stacked chips, helping to reduce chip size. In another example, at least one of the sides of the second chip away from the first chip is provided with a ball grid array (BGA), meaning that the chip pads can be placed on the back side, which is beneficial for BGA packaging.

[0106] Example 4: like Figure 3 and Figure 8 As shown, this application also provides a photolithographic mask (hereinafter referred to as a mask), which is suitable for the fabrication method of the area array image sensor as described above, wherein the photolithographic mask is at least one of the first to the Nth mask. Figure 3 This is a schematic diagram of the planar structure of the mask plate in Embodiment 1 of the present invention. Figure 8 This is a schematic diagram of the planar structure of the photomask in another embodiment of the present invention. Additionally, this application also provides a photolithographic photomask suitable for the fabrication method of the stacked image sensor described above. The structure of the photomask can be found in the descriptions of Embodiments 1, 2, and 3, and will not be repeated here.

[0107] Specifically, the photomask includes a device pattern area and an alignment pattern area. The device pattern area corresponds to the circuit pattern on the area array image sensor 10, and the alignment pattern area is used to set alignment mark patterns. In one example, the alignment pattern area is located around the device pattern area, such as... Figure 3 As shown; in another example, the alignment pattern area is located on three sides of the device pattern area, as shown. Figure 8 As shown. Wherein, when at least one of the first alignment mark pattern 310, the second alignment mark pattern 320, the third alignment mark pattern 330, and the fourth alignment mark pattern 340 is present, each alignment mark pattern is located in the alignment pattern area. Preferably, the alignment pattern area is located on the left and right sides of the device pattern area, thereby facilitating the vertical alignment of the photomask for stitching together the circuit patterns on the area array image sensor 10.

[0108] Furthermore, such as Figure 8 As shown, the line connecting the first alignment mark pattern 610 and the third alignment mark pattern 630 is located outside the device pattern area, and the line connecting the second alignment mark pattern 620 and the fourth alignment mark pattern 640 crosses the device pattern area. Furthermore, the lowermost outer edges of the second alignment mark pattern 620 and the fourth alignment mark pattern 640 are aligned with the lowermost outer edge of the device pattern area. This facilitates the alignment of the lower side of the device pattern area with the lower edge of the photomask. Alternatively, in other embodiments, the line connecting the first alignment mark pattern 610 and the third alignment mark pattern 630 may cross the device pattern area, and the line connecting the second alignment mark pattern 620 and the fourth alignment mark pattern 640 may be located outside the device pattern area. Furthermore, the uppermost outer edges of the first alignment mark pattern 610 and the third alignment mark pattern 630 may be aligned with the uppermost outer edge of the device pattern area.

[0109] In this document, the directional terms such as up, down, left, right, front, and back are defined according to the position of the structures in the accompanying drawings and the relative positions of the structures, and are only used for clarity and convenience in expressing the technical solution. It should be understood that the use of these directional terms should not limit the scope of protection claimed in this application. It should also be understood that the terms "first" and "second," etc., used herein are only used for distinction in name and are not used to limit the number or order.

[0110] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content without departing from the scope of the technical solution of the present invention, which are equivalent embodiments with equivalent changes. Any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of the present invention without departing from the scope of the technical solution of the present invention shall still fall within the protection scope of the technical solution of the present invention.

Claims

1. An area array image sensor, characterized in that, The area array image sensor includes: The first chip region includes at least a first sub-chip region arranged along a first preset direction and a second sub-chip region different from the first sub-chip region. The second chip region is arranged relative to the first chip region along a second preset direction, wherein there is an angle between the first preset direction and the second preset direction, and the circuit layout of the first chip region and the second chip region is the same. The first chip region and the second chip region are prepared based on the same mask by translation and splicing. When the area array image sensor includes a first chip and a second chip stacked with the first chip, the first chip area and the second chip area are disposed in the first chip; the second chip includes logic control circuits corresponding to each chip area, the logic control circuits include several sub-circuit areas corresponding to each sub-chip area, the sub-chip area includes a pixel array area, the pixel array area includes several pixel units arranged in rows and columns; or The circuit configurations of the first sub-chip region and the second sub-chip region are different, and the first sub-chip region and the second sub-chip region are fabricated based on different masks. When the first sub-chip region includes a first column of light-shielding pixel regions and the second sub-chip region includes a second column of light-shielding pixel regions, the first and second columns of light-shielding pixel regions are symmetrically distributed on both sides of the first chip region. The second chip region includes a third column of light-shielding pixel regions corresponding to the first column of light-shielding pixel regions, and a fourth column of light-shielding pixel regions corresponding to the second column of light-shielding pixel regions, so that black level correction columns are provided on both sides of the area array image sensor chip. When the area array image sensor also includes a chip functional region, the chip functional region includes at least two sub-chip functional regions corresponding to the sub-chip regions of the first chip region, and the positions of the sub-chip functional regions correspond to the sub-chips of each chip region.

2. The area array image sensor according to claim 1, characterized in that, The area array image sensor further includes a third chip area to an Nth chip area, the first chip area to the Nth chip area are arranged along the second preset direction, wherein N is an integer greater than or equal to 3.

3. The area array image sensor according to claim 2, characterized in that, The circuit layouts of the first chip area to the Nth chip area are all the same.

4. The area array image sensor according to claim 1, characterized in that, The first sub-chip area and the second sub-chip area also include at least one intermediate chip area.

5. The area array image sensor according to claim 1, characterized in that, The first sub-chip region includes an adjacent first main body region and a first auxiliary region, and the second sub-chip region includes an adjacent second main body region and a second auxiliary region, wherein the corresponding regions in the first sub-chip region and the second sub-chip region are symmetrically distributed.

6. The area array image sensor according to claim 1, characterized in that, The first sub-chip region includes a first pad region, and the second sub-chip region includes a second pad region. The first pad region and the second pad region are distributed on both sides of the first chip region.

7. The area array image sensor according to claim 6, characterized in that, Each chip region arranged along the second preset direction is provided with a column of light-shielding pixel regions corresponding to the first chip region; and / or, each chip region arranged along the second preset direction is provided with a pad region corresponding to the first chip region.

8. The area array image sensor according to claim 1, characterized in that, The chip functional areas are arranged along the second preset direction on at least one side of each chip area.

9. The area array image sensor according to claim 1, characterized in that, The sub-chip functional area includes at least one of a test structure area and a shielding ring.

10. The area array image sensor according to claim 1, characterized in that, The sub-circuit region includes at least a pixel control circuit and a signal quantization circuit that are electrically connected to the pixel units in the pixel array region of the corresponding sub-chip region.

11. The area array image sensor according to claim 10, characterized in that, The width of the sub-circuit region along the first preset direction is less than or equal to the width of the corresponding sub-chip region.

12. The area array image sensor according to claim 1, characterized in that, The second chip has a packaging bump on the side away from the first chip; and / or, the stacked first chip and the second chip are electrically connected by a hybrid bonding method.

13. A method for manufacturing an area array image sensor as described in any one of claims 1-12, characterized in that, The manufacturing method includes: Provide semiconductor substrates; A first mask is provided and the semiconductor substrate is exposed for the first time using the first mask as a shield, wherein the area of ​​the first exposure corresponds to the first chip area; The first mask includes a first sub-mask corresponding to the first sub-chip region and a second sub-mask corresponding to the second sub-chip region; A second photomask is provided, and the semiconductor substrate is moved relative to the first photomask by a first preset distance in a second preset direction; Based on the first preset distance and using the second mask as a shield, the semiconductor substrate is exposed a second time, and the area of ​​the second exposure corresponds to the second chip area; The exposure of a chip region in the semiconductor substrate is completed based on the first exposure and the second exposure, wherein the chip region includes the first chip region and the second chip region.

14. The method for manufacturing an area array image sensor according to claim 13, characterized in that, The second exposure is followed by the following steps: The semiconductor substrate is continuously moved relative to the (N-1)th mask in the second preset direction by the (N-1)th preset distance; wherein, based on the (N-1)th preset distance and using the Nth mask as a shield, the semiconductor substrate is exposed for the Nth time, and the area of ​​the Nth exposure corresponds to the Nth chip area, where N is an integer greater than or equal to 3; The exposure of a chip region in the semiconductor substrate is completed based on the first exposure to the Nth exposure, wherein the chip region includes the first chip region to the Nth chip region.

15. The method for manufacturing an area array image sensor according to claim 14, characterized in that, The first mask to the Nth mask are the same mask.

16. The method for manufacturing an area array image sensor according to claim 14, characterized in that, The first preset distance is less than or equal to the length of the first mask in the second preset direction; and / or, the first preset distance is less than or equal to the length of the second mask in the second preset direction; And / or, the (N-1)th preset distance is less than or equal to the length of the (N-1)th mask in the second preset direction.

17. The method for manufacturing an area array image sensor according to claim 13, characterized in that, The manufacturing method further includes: The semiconductor substrate is moved a preset interval distance relative to the current chip region, and the steps of the first exposure and the second exposure are repeated at least to complete the exposure of another chip region; the above steps are repeated until the exposure of all chip regions in the semiconductor substrate is completed.

18. The method for manufacturing an area array image sensor according to claim 14, characterized in that, The semiconductor substrate includes a semiconductor substrate and an etching mask layer formed on the semiconductor substrate: The etching mask layer is exposed for the first time using the first mask as a shield; the etching mask layer is exposed for the second time using the second mask as a shield; and when the Nth mask is continuously present, the etching mask layer is continuously exposed for the Nth time using the corresponding mask as a shield, where N is an integer greater than or equal to 3.

19. The method for manufacturing an area array image sensor according to claim 18, characterized in that, After exposing all chip regions in the semiconductor substrate, the etched mask layer is developed.

20. The method for manufacturing an area array image sensor according to any one of claims 13-19, characterized in that, Each mask has a first alignment mark pattern and a second alignment mark pattern that cooperates with the first alignment mark pattern at both ends of the second preset direction.

21. The method for manufacturing an area array image sensor according to claim 20, characterized in that, Based on the first alignment mark pattern and the second alignment mark pattern, corresponding first alignment mark and second alignment mark are formed on the semiconductor substrate. Based on the measurement of the first alignment mark and the second alignment mark, the position of the first exposure and the position of the second exposure are detected.

22. The method for manufacturing an area array image sensor according to claim 20, characterized in that, The first alignment mark pattern is block-shaped, and the second alignment mark pattern is ring-shaped, with the outer edge dimension of the first alignment mark pattern being smaller than the inner edge dimension of the second alignment mark pattern; or, the first alignment mark pattern is ring-shaped, and the second alignment mark pattern is block-shaped, with the outer edge dimension of the second alignment mark pattern being smaller than the inner edge dimension of the first alignment mark pattern.

23. The method for manufacturing an area array image sensor according to claim 20, characterized in that, Each of the photomasks further includes a third alignment mark pattern and a fourth alignment mark pattern that are respectively provided at both ends in the second preset direction, and the first line connecting the first alignment mark pattern and the second alignment mark pattern is parallel to each other and has a gap with the second line connecting the third alignment mark pattern and the fourth alignment mark pattern.

24. The method for manufacturing an area array image sensor according to claim 23, characterized in that, The first alignment mark pattern, the second alignment mark pattern, the third alignment mark pattern, and the fourth alignment mark pattern are located at the top corners of the corresponding photomask.

25. The method for manufacturing an area array image sensor according to claim 24, characterized in that, The line connecting the first alignment mark pattern and the third alignment mark pattern is located outside the device pattern area, and the line connecting the second alignment mark pattern and the fourth alignment mark pattern crosses the device pattern area; or, the line connecting the first alignment mark pattern and the third alignment mark pattern crosses the device pattern area, and the line connecting the second alignment mark pattern and the fourth alignment mark pattern is located outside the device pattern area.

26. A method for fabricating a stacked image sensor, characterized in that, The manufacturing method includes: A first chip is prepared by the fabrication method of an area array image sensor as described in any one of claims 13-25, the first chip comprising a pixel array region; A second chip is prepared by the fabrication method of the area array image sensor as described in any one of claims 13-25, the second chip including a logic control circuit area; The first chip and the second chip are stacked and bonded to achieve an electrical connection between the logic control circuit area and the pixel array area.

27. A photolithographic mask, suitable for fabricating a planar image sensor as described in any one of claims 13-25, characterized in that, The photomask is at least one of the first mask and the second mask; wherein, when there are consecutive masks up to the Nth mask, the photomask is at least one of the first mask to the Nth mask.

28. The photomask according to claim 27, characterized in that, The photomask includes a device pattern area and an alignment pattern area adjacent to the image area, wherein when at least one of a first alignment mark pattern, a second alignment mark pattern, a third alignment mark pattern and a fourth alignment mark pattern is present, each alignment mark pattern is located in the alignment pattern area.

Images