An RFLDMOS power radio frequency device structure and a preparation method thereof

Abstract

The application discloses a double-sided trench gate and field plate type RFLDMOS power radio frequency device structure and a preparation method thereof. A semiconductor substrate with high doping concentration is used as a semiconductor base of the whole device structure and as a source terminal of the whole device. A semiconductor epitaxial layer with tens of microns is obtained by epitaxial growth on a semiconductor substrate with hundreds of microns and with medium doping concentration. A top-bottom diffusion connection with high doping concentration is obtained by diffusion and is used for connecting a wafer surface and a substrate semiconductor substrate. The semiconductor substrate, the semiconductor epitaxial layer and the top-bottom diffusion connection are of a first semiconductor type. A drift region, a drain region doping and a source region doping are of a second semiconductor type. The drain region doping is electrically connected with a drain region metal to form a drain terminal of the device. The source region doping is electrically connected with a source region metal to form a source terminal of the device. A planar high-quality oxide is a high-quality oxide layer formed by thermal oxidation. A polysilicon gate adopts high doping concentration to minimize gate resistance and obtain a proper threshold voltage.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a dual-sided trench gate and field plate type RFLDMOS power radio frequency device structure and its fabrication method. Background Technology

[0002] Laterally double diffused metal oxide semiconductor (LDMOS) is a gate-controlled power device that can be divided into two main types based on its structure and application: switching LDMOS (SWLDMOS) and radio frequency LDMOS (RFLDMOS). SWLDMOS has low structural complexity and is well-compatible with planar silicon or silicon-on-insulator (SOI) processes, and is frequently used as a power switch in driver circuits and smart electronics. In contrast, RFLDMOS is generally an expensive discrete device, widely used as a radio frequency power amplifier and excitation source in aerospace, electronic communications, and advanced equipment fields. It is a core component of radar systems, wireless communication base stations, and high-end industrial / scientific / medical equipment.

[0003] Unlike SWLDMOS, RFLDMOS, developed for radio frequency applications, features a structure without a beak-like structure, a thick epitaxial layer, and a distinct multilayer field plate with a long drift region. Fabricated using a specially developed high-voltage process, it exhibits low on-resistance, excellent linearity, and low thermal resistance per watt, perfectly meeting the demands of long-pulse and high-duty-cycle radio frequency applications. It is the preferred choice for power amplifiers in P / L / S band radar and wireless base stations. Furthermore, its low inductance and excellent mismatch resistance make it ideal as an excitation source for CO2 lasers, plasma generators, and MRI scanners, finding applications in high-end industrial, scientific, and medical equipment. Summary of the Invention

[0004] To address the problems existing in the prior art, this invention provides a dual-trench gate and field-plate type RFLDMOS power RF device structure and its fabrication method, which provides stronger channel control, allows for the use of lower doping concentration channels, improves the hot carrier injection effect inside the channel, effectively mitigates the threshold drift problem of RFLDMOS, reduces the gate capacitance composed of gate-source capacitance and gate-drain capacitance, effectively reduces the surface electric field, allows for the use of higher doping concentration drift regions under the same voltage withstand requirements, greatly improves drift region resistance, significantly improves the overall RF performance of RFLDMOS, improves the hot carrier injection effect inside the drift region, effectively mitigates the on-current drift problem of RFLDMOS, and effectively extends the device lifespan.

[0005] The objective of this invention is achieved through the following technical solutions.

[0006] A dual-trench gate and field-plate type RFLDMOS power radio frequency device structure is disclosed. A highly doped semiconductor substrate serves as the semiconductor base for the entire device structure and also as the source terminal. A semiconductor epitaxial layer of tens of micrometers is epitaxially grown on a moderately doped semiconductor substrate of several hundred micrometers, with a doping concentration ranging from 5E16 cm⁻¹. -3 ~5E17 cm -3 High doping concentration refers to the concentration that causes a semiconductor to enter a degenerate state; for silicon-based devices, it refers to a doping concentration in the range of 1E19 cm⁻¹. -3 ~1E20 cm -3 High-doped top-bottom diffusion connections are obtained by diffusion and are used to connect the wafer surface to the substrate semiconductor substrate. The semiconductor substrate, semiconductor epitaxy, and top-bottom diffusion connections are of the first semiconductor type. The drift region is of the second semiconductor type, with a doping concentration ranging from 7.5E6 cm⁻¹. -3 ~5E17 cm -3 The entire RFLDMOS device achieves high voltage withstand properties by extending the electric field through the drift region; The drain region doping and source region doping are of the second semiconductor type, with high doping concentration. The drain region doping is electrically connected to the drain region metal to form the drain terminal of the device, and the source region doping is electrically connected to the source region metal to form the source terminal of the device. The planar high-quality oxide is a high-quality oxide layer formed by thermal oxidation. The polysilicon gate uses a high doping concentration to minimize the gate resistance and obtain an appropriate threshold voltage. The field plate is a single-layer polycrystalline silicon field plate. The field plate is electrically connected to the source end through interdigitated terminal design, which plays the role of modulating the surface electric field in the drift region. The high-quality oxide in the trench is a high-quality oxide layer obtained by thermal oxidation after trenching the side trenches. The high-quality oxide in the trench is in direct contact with the channel region and drift region under the polysilicon gate to form an oxide-silicon interface, ensuring the quality of the high-quality oxide in the trench and reducing the interface states of the oxide-silicon interface between the high-quality oxide in the trench and silicon. The high-quality oxide in the trench and the high-quality oxide in the planar are prepared separately to eliminate the steps at the junction of the high-quality oxide in the trench and the high-quality oxide in the planar areomer. The polysilicon filling in the trench is a polycrystalline filler with a high doping concentration to ensure the flatness of the surface and to electrically connect with the field plate.

[0007] The semiconductor substrate and the semiconductor epitaxial layer can be made of the same material, such as silicon-based, or they can be SiC substrate and compound epitaxy, or silicon-based substrate and SiC epitaxy.

[0008] Metal silicides are formed between the drain region doping and the drain region metal connection using metals such as Ti, Ni, and tungsten; metal silicides are also formed between the source region doping and the source region metal connection using metals such as Ti, Ni, and tungsten.

[0009] The top-bottom diffusion connection electrically connects the semiconductor substrate and the source metal connection. The semiconductor substrate and the source metal connection serve as the source terminal, which is connected to the reference potential during operation. The drain metal connection serves as the drain terminal, and the polysilicon gate serves as the gate terminal. During operation, a pulse signal or a continuous wave signal is applied. After amplification, the pulse signal or continuous wave signal is output from the drain terminal formed by the drain metal connection. During operation, a large current path is formed on the path from the drain metal connection to the source metal connection. At the same time, it needs to withstand the operating voltage of 28 / 50 / 65V without breakdown.

[0010] The high-quality trench oxide electrically completely separates the trench polysilicon filler from the polysilicon gate and the channel region under the polysilicon gate, as well as the trench polysilicon filler and drift region, forming a Si-SiO2 interface between the high-quality trench oxide and the channel region under the polysilicon gate, and between the trench polysilicon filler and drift region. By controlling the oxidation time conditions of thermal oxidation under the same nitrogen protection, the oxide layer thickness of the high-quality trench oxide is 4 to 7 times that of the gate oxide.

[0011] The side trench structure also includes trench polysilicon filling.

[0012] In addition to the vertical electric field pointing from the polysilicon gate to the semiconductor epitaxy, there is also a lateral electric field pointing from the polysilicon gate to the trench polysilicon filling.

[0013] According to Gauss's formula

[0014] Continuously distributed charge

[0015] Where ρ is the charge density, ε0 ​​is the vacuum permittivity, and dV is the differential of the volume element, which is a triple integral over the charge distribution region. Planar high-quality oxide and trench high-quality oxide are equivalent to capacitors with a constant dielectric. The polysilicon gate is an electric field vector source. When the device is operating, a gate voltage is applied to the polysilicon gate, which is equivalent to the voltage in the above formula. The term is an active electric field vector source. With the electric field vector source unchanged, the electric field vector density in the vertical direction from the polysilicon gate to the semiconductor epitaxy remains unchanged, and an additional lateral electric field is added from the polysilicon gate to the trench polysilicon filling.

[0016] The electric flux across the cross section can be obtained by surface integration:

[0017] in It is an electric field It is the surface A tiny area on the surface, whose direction is defined as the surface normal pointing outwards; When the device is working, a voltage is applied to the drain terminal, and the electric field points from the drain terminal to the source terminal in the drift region. If the voltage applied to the drain terminal remains unchanged at a certain moment, the current flux on the cross section remains unchanged. When the side structure formed by the trench polysilicon filling forms a lateral electric field, the absolute value of the electric field near the high-quality oxide of the trench will decrease due to the deflection of the electric field vector.

[0018] A method for fabricating a dual-sided trench gate and field plate type RFLDMOS power radio frequency device structure, comprising the following steps: 1) Grow semiconductor epitaxy on a semiconductor substrate or directly purchase an epitaxial wafer containing a semiconductor substrate and semiconductor epitaxy, and clean it to remove native oxides; 2) Active diffusion process is used to form top and bottom diffusion connections in semiconductor epitaxy. Then, oxide and polysilicon are deposited on the semiconductor epitaxy in sequence. Patterning etching is used to form patterns and define the implantation regions of the drift region. The top and bottom diffusion connections are not defined by the patterns of oxide and polysilicon. The top and bottom diffusion connections do not diffuse into the patterns of oxide and polysilicon, which meets the requirements. After selective drift region implantation, selective annealing is performed at 800°C for 30 minutes. 3) Remove oxides and polysilicon, and open side trenches. The final high-quality planar oxide or high-quality trench oxide is different. The difference is that the oxide is prepared by deposition, while the high-quality planar oxide or high-quality trench oxide is prepared by long-term thermal oxidation. The pattern and position definition of the side trenches are also formed by the method of depositing oxides and polysilicon and then patterning and etching. 4) Long-term thermal oxidation preparation under nitrogen protection, with controlled oxidation time and O2, NO, and N2O content to form planar high-quality oxides and grooved high-quality oxides; 5) Backfilling the trench with polysilicon filler fills the trench with polysilicon filler on top of the high-quality oxide in the trench. Then, dry etching is used to remove the polysilicon and expose the surface of the high-quality oxide in the planar area. Then, polysilicon gates are deposited and patterned on the high-quality oxide in the planar area to ensure that the polysilicon gates and the trench polysilicon filler are not electrically connected. 6) After depositing the intermediate oxide layer, polycrystalline or metallic tungsten nickel is deposited to form a field plate. The field plate and the trench polycrystalline silicon filler are electrically connected. In the case of multilayer field plates, each field plate is electrically connected to the trench polycrystalline silicon filler.

[0019] 7) After the processes of opening, selective silicide and tungsten filling, metal electrode and etching, the drain metal connection and source metal connection are formed as the drain and source of the device. The source metal connection, field plate, trench high-quality oxide are electrically connected at the end of the interdigitator.

[0020] Compared with the prior art, the advantages of the present invention are as follows: 1. The dual-sided trench gate and field plate type RFLDMOS power RF device disclosed in this patent has stronger control over the channel due to the presence of the side gate, and can use a channel with a lower doping concentration, which is beneficial to the improvement of the hot carrier injection effect inside the channel, and can effectively improve the threshold drift problem of RFLDMOS.

[0021] 2. The dual-sided trench gate and field plate type RFLDMOS power RF device disclosed in this patent has stronger control over the channel due to the presence of the side gate, and can use a channel with a lower doping concentration, which is beneficial to reduce the gate capacitance composed of gate-source capacitance and gate-drain capacitance, and significantly improves the overall RF performance of RFLDMOS.

[0022] 3. The dual-sided trench gate and field plate type RFLDMOS power RF device disclosed in this patent generates a corresponding lateral electric field in the drift region due to the presence of the side field plate. Without affecting the source-drain direction electric field strength in the field plate, the surface electric field is effectively reduced. Under the same voltage withstand requirement, a higher doping concentration drift region can be used, which greatly improves the drift region resistance and significantly improves the overall RF performance of RFLDMOS.

[0023] 4. The dual-sided trench gate and field plate type RFLDMOS power RF device disclosed in this patent generates a corresponding lateral electric field in the drift region due to the presence of the side field plate. Without affecting the source-drain direction electric field strength in the field plate, the surface electric field is effectively reduced, which is beneficial to improving the hot carrier injection effect in the drift region. It can effectively improve the RFLDMOS conduction current drift problem and effectively extend the device life. Attached Figure Description

[0024] Figure 1 This is a rear view (without side structure) three-dimensional structural diagram of the dual-groove gate and field plate type RFLDMOS power radio frequency device structure provided in the embodiments of the present invention.

[0025] Figure 2 This is a front view (with the side structure) of the three-dimensional structure of the dual-groove gate and field plate type RFLDMOS power radio frequency device structure provided in the embodiments of the present invention.

[0026] Figures 3a-5b This is a two-dimensional cross-sectional schematic diagram of the dual-groove gate and field plate type RFLDMOS power radio frequency device structure provided by the embodiments of the present invention.

[0027] in, Figure 3b For example Figure 3a A schematic diagram of the two-dimensional cut surface at the indicated location. Figure 4b For example Figure 4a A schematic diagram of the two-dimensional cut surface at the indicated location. Figure 5b For example Figure 5a A schematic diagram of the two-dimensional cut surface at the indicated location.

[0028] Figures 6a-7c The diagram shows the structure of a two-dimensional cross-section of the dual-groove gate and field plate type RFLDMOS power radio frequency device structure provided by the embodiments of the present invention, the electrical quantities on the cross-section, and the simulation results of the electrical quantities on the cross-section at that location.

[0029] in, Figure 6b For example Figure 6a A schematic diagram of the two-dimensional cut surface at the indicated location; the arrows indicate the electric field vector. Figure 6c The simulation results show the electric flux of the two-dimensional cross-section. Figure 7b For example Figure 7a A schematic diagram of the two-dimensional cut surface at the indicated location; the arrows indicate the electric field vector. Figure 7c The result is the simulation of the electric field vector of the two-dimensional cross-section.

[0030] Figure 8a -g is a reference fabrication method and process diagram of the dual-sided trench gate and field plate type RFLDMOS power radio frequency device structure provided in the embodiments of the present invention.

[0031] Figure 9 This is a three-dimensional schematic diagram illustrating a real-world embodiment of the double-sided trench gate and field plate type RFLDMOS power radio frequency device structure of the present invention, using repeated interdigitation.

[0032] In the diagram: Semiconductor substrate 001 Semiconductor epitaxy 002 Top and bottom diffusion connection 003 Drift region 004 Drain region doping 005 Source region doping 006 Drain region metal connection 007 Source region metal connection 008 Planar high-quality oxide 009 Polysilicon gate 010 Field plate 011 Trench high-quality oxide 012 Trench polysilicon filling 013 Oxide 021 Polysilicon 020. Detailed Implementation

[0033] The present invention will now be described in detail with reference to the accompanying drawings and specific embodiments.

[0034] Figure 1 This is a rear view (without side structure) three-dimensional structural diagram of the dual-groove gate and field plate type RFLDMOS power radio frequency device structure provided in the embodiments of the present invention. Figure 2 This is a front view (with the side structure) of the three-dimensional structure of the dual-groove gate and field plate type RFLDMOS power radio frequency device structure provided in the embodiments of the present invention.

[0035] The semiconductor substrate, semiconductor epitaxy, top and bottom diffusion connections, drift region, drain region doping, source region doping, drain region metal connection, source region metal connection, planar high-quality oxide, polysilicon gate, field plate, trench high-quality oxide, and trench polysilicon filling together constitute the RFLDMOS device structure with source, drain, and gate ports in this embodiment.

[0036] A highly doped semiconductor substrate serves as the semiconductor base for the entire device structure and also as the source terminal for the entire device. Epitaxial growth of tens of micrometers is achieved on a moderately doped semiconductor substrate of several hundred micrometers in diameter, with doping concentrations ranging from 5E16 cm⁻¹. -3 ~5E17 cm -3 In this invention document, high doping concentration refers to the concentration that causes a semiconductor to enter a degenerate state; for silicon-based devices, it refers to a doping concentration range of 1E19 cm⁻¹. -3 ~1E20 cm -3 .

[0037] Epitaxial wafers provided by silicon wafer manufacturers generally consist of a semiconductor substrate and a semiconductor epitaxial layer. The semiconductor substrate and semiconductor epitaxial layer are, but are not limited to, homogeneous materials such as silicon-based materials. They can also be SiC substrates and compound epitaxial layers, or silicon-based substrates and SiC epitaxial layers.

[0038] High-doped top-to-bottom diffusion connections are obtained through diffusion and serve to connect the wafer surface to the semiconductor substrate. The semiconductor substrate, semiconductor epitaxy, and top-to-bottom diffusion connections constitute the first semiconductor type.

[0039] The drift region is of the second semiconductor type, with a doping concentration ranging from 7.5E6 cm⁻¹. -3 ~5E17 cm -3 The entire RFLDMOS device achieves high breakdown voltage by extending the electric field through the drift region. The concentration of the drift region is negatively correlated with the on-resistance and breakdown voltage of the entire device. In practical applications, under certain breakdown voltage conditions, reducing the on-resistance is beneficial to improving the RF performance of the entire RFLDMOS.

[0040] Drain doping and source doping constitute a second semiconductor type, with high doping concentrations. The drain doping and drain metal connection form the drain terminal of the device. To achieve better connection performance, metals such as Ti, Ni, and tungsten are not limited to forming metal silicides between the drain doping and drain metal connection. Similarly, the source doping and source metal connection form the source terminal of the device. To achieve better connection performance, metals such as Ti, Ni, and tungsten are not limited to forming metal silicides between the source doping and source metal connection.

[0041] The planar high-quality oxide is a high-quality oxide layer formed by thermal oxidation. In this embodiment, a thermal oxidation method under nitrogen protection is used to prepare the planar high-quality oxide to ensure its quality. The quality of the planar high-quality oxide not only affects short-term oxide layer breakdown but also long-term hot carrier degradation of the device, directly impacting its lifespan.

[0042] Polysilicon gates, but not limited to those using more advanced metal gate processes, are employed. Polysilicon gates utilize high doping concentrations to minimize gate resistance and achieve an appropriate threshold voltage.

[0043] In this embodiment, the field plate is a single-layer polycrystalline silicon field plate, but the structure is not limited to a multilayer field plate with two or three layers, and the material is not limited to metal field plates such as tungsten or Ti. The field plate is electrically connected to the source end through an interpolation terminal design, which plays the role of modulating the surface electric field in the drift region.

[0044] The high-quality trench oxide is a high-quality oxide layer obtained by thermal oxidation after trenching the sidewalls. In this embodiment, a thermal oxidation method under nitrogen protection is used to ensure the quality of the high-quality trench oxide. The high-quality trench oxide is in direct contact with the channel region and drift region under the polysilicon gate, forming an oxide-silicon interface. Therefore, it is necessary to ensure the quality of the high-quality trench oxide to reduce the interface states at the oxide-silicon interface between the high-quality trench oxide and silicon. In this embodiment, the high-quality trench oxide and the planar high-quality oxide are prepared separately to eliminate the steps at the junction of the high-quality trench oxide and the planar high-quality oxide, but it is not limited to preparing the high-quality trench oxide and the planar high-quality oxide simultaneously while ensuring that there are no obvious steps at the junction of the high-quality trench oxide and the planar high-quality oxide.

[0045] The trench polycrystalline silicon filler is a highly doped polycrystalline filler, used to fill the side trenches. This ensures surface flatness and provides electrical connection to the field plate. This embodiment uses a highly doped polycrystalline filler based on the good filling properties and good contact with oxides, but it is not limited to using metals such as tungsten or nickel to achieve the same function of trench polycrystalline silicon filler while ensuring good filling.

[0046] Figures 3-5 are two-dimensional cross-sectional schematic diagrams of the dual-groove gate and field plate type RFLDMOS power radio frequency device structure provided by the embodiments of the present invention.

[0047] in, Figure 3b For example Figure 3a A schematic diagram of the two-dimensional cut surface at the indicated location. Figure 4b For example Figure 4a A schematic diagram of the two-dimensional cut surface at the indicated location. Figure 5b For example Figure 5a A schematic diagram of the two-dimensional cut surface at the indicated location.

[0048] Figure 3a The cut-off position of the cut surface shown is outside the side trench in this embodiment. The characteristic is that the cut surface passes through the top and bottom diffusion connection, source region doping, source region metal connection, polysilicon gate, field plate, planar high-quality oxide, drain region metal connection, drain region doping, drift region, semiconductor epitaxy, and semiconductor substrate, but does not intersect with the trench high-quality oxide or trench polysilicon filling.

[0049] Depend on Figure 3a The cut surface shown yields the following: Figure 3b The two-dimensional cross-sectional schematic diagram shown represents the main operating region of the RFLDMOS structure disclosed in this invention. Top and bottom diffusion connections electrically connect the semiconductor substrate and the source metal connection, with the semiconductor substrate and source metal connection serving as the source terminal, connected to the reference potential during operation. The drain metal connection serves as the drain terminal, and the polysilicon gate serves as the gate terminal. During operation, a pulse signal or continuous wave signal is applied, and after amplification, the pulse signal or continuous wave signal is output from the drain terminal formed by the drain metal connection. During operation, a large current path is formed on the path from the drain metal connection to the source metal connection, while simultaneously needing to withstand a large voltage (such as the typical operating voltage of 28 / 50 / 65V for communication or radar) without breakdown.

[0050] Figure 4a The cut-off position of the cut surface shown is at the side trench oxide layer position in this embodiment. The characteristic is that the cut surface passes through the top and bottom diffusion connection, source region doping, source region metal connection, field plate, trench high-quality oxide, drain region metal connection, drain region doping, drift region, semiconductor epitaxy, and semiconductor substrate, but does not intersect with the planar high-quality oxide and trench polysilicon filling.

[0051] Depend on Figure 4a The cut surface shown yields the following: Figure 4bThe two-dimensional cross-sectional schematic diagram shown represents the region between the main operating area and the side trench structure of the RFLDMOS structure disclosed in this invention. The high-quality trench oxide electrically completely separates the trench polysilicon filler from the polysilicon gate, the channel region beneath the polysilicon gate, and the trench polysilicon filler from the drift region. In this embodiment, a high-quality Si-SiO2 interface is formed between the high-quality trench oxide and the channel region beneath the polysilicon gate, and between the trench polysilicon filler and the drift region, but other oxide interfaces are not limited to ensuring the interface state density. By controlling conditions such as the oxidation time under nitrogen protection, the oxide layer thickness of the high-quality trench oxide is 4 to 7 times that of the gate oxide (varying depending on the breakdown voltage requirement). For example, in this embodiment, the gate oxide thickness is 230 angstroms, the maximum gate operating voltage is 25V, the implemented high-quality trench oxide oxide layer thickness is 1150 angstroms, and the drain operating breakdown voltage is 50V.

[0052] Figure 5a The cut-off position of the cut surface shown is at the side trench oxide layer position in this embodiment. The characteristic is that the cut surface passes through the top and bottom diffusion connection, source region doping, source region metal connection, field plate, trench high-quality oxide, trench polysilicon filling, drain region metal connection, drain region doping, drift region, semiconductor epitaxy, and semiconductor substrate, and does not intersect with the planar high-quality oxide.

[0053] Depend on Figure 5a The cut surface shown yields the following: Figure 5b The two-dimensional cross-sectional schematic diagram shown represents the side trench structure region of the RFLDMOS structure disclosed in this invention. In addition to the high-quality oxide trench as previously described, the side trench structure also includes trench polysilicon filling. In this embodiment, the heavily doped polysilicon trench filling serves two purposes: firstly, it fills the voids in the high-quality oxide trench, providing mechanical support; secondly, it acts as an electrode to fix the potential on one side of the high-quality oxide trench.

[0054] Figure 6b For example Figure 6a The schematic diagram of the two-dimensional cut surface shown is characterized by the fact that the cut surface passes through high-quality oxide trench, polysilicon trench filling, polysilicon gate, high-quality oxide planar surface, semiconductor epitaxy, and semiconductor substrate, reflecting the influence of the structure disclosed in this invention on the channel under the polysilicon gate.

[0055] Figure 6b The black arrows in the middle indicate the electric field vectors. In addition to the vertical electric field pointing from the polysilicon gate to the semiconductor epitaxy, there is also a lateral electric field pointing from the polysilicon gate to the trench polysilicon filling.

[0056] According to Gauss's formula

[0057] Continuously distributed charge

[0058] Where ρ is the charge density (the amount of charge per unit volume), ε0 is the vacuum permittivity, and dV is the differential of the volume element. This is a triple integral over the charge distribution region.

[0059] Planar high-quality oxide and trench high-quality oxide are equivalent to capacitors with a constant dielectric, while the polysilicon gate is a vector source of electric field. When the device operates, a gate voltage is applied to the polysilicon gate, which is equivalent to the voltage in the above equation. The term represents an active electric field vector source. With the electric field vector source unchanged, the vertical electric field vector density pointing from the polysilicon gate to the semiconductor epitaxial layer remains constant, while an additional lateral electric field is added pointing from the polysilicon gate to the polysilicon filling of the trench. This increased electric field vector density provides stronger control over the channel, allowing for the use of channels with lower doping concentrations. This has two advantages: firstly, it improves the hot carrier injection effect within the channel, effectively mitigating the threshold drift problem in RFLDMOS; secondly, it helps reduce the gate capacitance formed by the gate-source capacitance and gate-drain capacitance, significantly improving the overall RF performance of RFLDMOS. Figure 6c The simulation results show the electric field at the two-dimensional cross-section. The vertical axis represents the scalar value of the absolute value of the maximum electric field vector at the lateral position, and the horizontal axis represents the lateral position. As shown in the figure, due to the presence of the lateral structure, the RFLDMOS structure disclosed in this invention exhibits a significantly higher absolute value of the maximum electric field vector near the side compared to the traditional RFLDMOS structure, reflecting the enhanced channel control effect described above.

[0060] Figure 7b For example Figure 7a The schematic diagram of the two-dimensional cut surface shown is characterized by the fact that the cut surface passes through high-quality oxide trench, polysilicon trench filling, polysilicon gate, high-quality oxide planar surface, semiconductor epitaxy, and semiconductor substrate, reflecting the influence of the structure disclosed in this invention on the electric field distribution in the drift region.

[0061] Figure 7b The black plus sign in the middle indicates the electrical flux, which is the current flux from the outside to the inside in the direction perpendicular to the paper and from the leakage to the source.

[0062] The electric flux across the cross section can be obtained by surface integration:

[0063] in It is an electric field It is the surface A tiny area on the surface, whose direction is defined as the surface normal pointing outwards.

[0064] When the device is operating, a voltage is applied to the drain, and the electric field in the drift region points from the drain to the source. If the voltage applied to the drain remains constant at a given moment, the current flux across the cross-section remains constant. When the side structure formed by the polysilicon filling of the trench creates a lateral electric field, the absolute value of the electric field near the high-quality oxide in the trench decreases due to the shift in the electric field vector, effectively reducing the surface electric field. This has two effects: firstly, under the same voltage withstand requirements, a higher doping concentration in the drift region can be used, greatly improving the drift region resistance and significantly enhancing the overall RF performance of the RFLDMOS; secondly, it helps improve the hot carrier injection effect within the drift region, effectively mitigating the RFLDMOS conduction current drift problem and extending the device's lifespan.

[0065] Figure 7c The simulation results show the electric field vector of the two-dimensional cross-section. The vertical axis represents the scalar value of the absolute value of the maximum electric field vector at the lateral position, and the horizontal axis represents the lateral position. As shown in the figure, due to the presence of the lateral structure, the RFLDMOS structure disclosed in this invention exhibits a significant decrease in the absolute value of the maximum electric field vector near the side of the drift region compared to the traditional RFLDMOS structure, reflecting the previously mentioned effect of effectively reducing the surface electric field of the drift region.

[0066] Figure 8 illustrates a reference fabrication method and process flow for a dual-trench gate and field-plate type RFLDMOS power radio frequency device structure provided by an embodiment of the present invention. The RFLDMOS used in this illustrative process is, but is not limited to, a high-voltage device process. It highlights the key fabrication steps of the present invention. Variations based on the ideas of the present invention and actual design changes resulting from process evolution do not limit the scope of this patent.

[0067] Figure 8a The process involves growing semiconductor epitaxy on a semiconductor substrate or directly purchasing an epitaxial wafer containing a semiconductor substrate and semiconductor epitaxy, and then cleaning it to remove natural oxides.

[0068] Figure 8b Active diffusion technology is used to form top and bottom diffusion connections in semiconductor epitaxy. Then, oxide 021 and polysilicon 020 are deposited sequentially on the semiconductor epitaxial layer, and patterned etching is performed to form the pattern shown in the figure, defining the implantation region of the drift region. In this embodiment, the top and bottom diffusion connections are not defined by the pattern of oxide 021 and polysilicon 020; the requirement is met as long as the top and bottom diffusion connections do not diffuse beneath the pattern of oxide 021 and polysilicon 020. After selective drift region implantation, selective annealing at 800°C for 30 minutes is performed to repair implantation damage and ensure that the drift region reaches the designed depth.

[0069] Figure 8cThe process involves removing oxide 021 and polysilicon 020, and creating side trenches at the positions shown in the figure. In this embodiment, the final high-quality planar oxide or high-quality trench oxide of oxide 021 is not the same, the difference being that oxide 021 is prepared by deposition, while the planar high-quality oxide or trench high-quality oxide is prepared by long-term thermal oxidation. The pattern and position definition of the side trenches are also formed using the method of depositing oxide 021 and polysilicon 020 and then patterning and etching. In this embodiment, the trench depth is only 2-3 micrometers, thus avoiding the use of advanced deep trench processes such as ICP. The resulting advantages include: firstly, simpler and more reliable fabrication with a higher yield; secondly, a lower aspect ratio, reducing the likelihood of voids during backfilling and resulting in better filling quality; and thirdly, reducing the deeper defects that would occur if deep trench ion etching were used, protecting the integrity of the drift region.

[0070] Figure 8d The process involves prolonged thermal oxidation under nitrogen protection, controlling the oxidation time and the content of O2, NO, and N2O to form both planar high-quality oxides and trench high-quality oxides. In this embodiment, to avoid noticeable steps and maintain the surface flatness of the device, the planar high-quality oxides and trench high-quality oxides are formed in two stages.

[0071] Figure 8e The process involves backfilling the trench with polysilicon filler, which fills the trench with polysilicon over a high-quality oxide layer. Dry etching is then used to remove the polysilicon, exposing the planar high-quality oxide surface. Next, a polysilicon gate is deposited and patterned on the planar high-quality oxide layer and etched. In this process, it is ensured that the polysilicon gate and the trench polysilicon filler are electrically disconnected.

[0072] Figure 8f After depositing an intermediate oxide layer, polycrystalline silicon or tungsten-nickel metal is deposited to form a field plate. The field plate and the trench polycrystalline silicon filler are electrically connected. In this embodiment, only a single-layer field plate structure is used as a schematic diagram. In the case of multi-layer field plates, each field plate is electrically connected to the trench polycrystalline silicon filler.

[0073] Figure 8g After processes including aperture opening, selective silicide and tungsten filling, metal electrodes, and etching, drain and source metal connections are formed, serving as the drain and source of the device, respectively. The source metal connection, field plate, and high-quality oxide trench are electrically connected at the ends of the interdigitators.

[0074] Figure 9 This is a three-dimensional schematic diagram illustrating a real-world embodiment of the double-sided trench gate and field plate type RFLDMOS power radio frequency device structure of the present invention, using repeated interdigitation.

[0075] like Figure 9As shown, the interpolation direction from the inside out on the paper is the interpolation direction. The side structure formed by the trench high-quality oxide and trench polysilicon filling repeatedly intersects with the main region of the RFLDMOS formed by the semiconductor substrate, semiconductor epitaxy, top and bottom diffusion connections, drift region, drain region doping, source region doping, drain region metal connection, source region metal connection, planar high-quality oxide, polysilicon gate, and field plate on the interpolation. In this embodiment, the width ratio between the two is between 1:3 and 1:4. Too small a width ratio weakens the effect of the side structure, while too large a width ratio reduces the power density of the entire device.

[0076] This invention discloses a dual-sided trench gate and field-plate type RFLDMOS power radio frequency device. The dual-sided trench backfill process disclosed in this invention forms additional side gates on both sides of the RFLDMOS gate region. The side gates are composed of polysilicon and high-quality oxides formed by thermal oxidation.

[0077] The side field plate is also composed of high-quality oxide formed by polycrystalline silicon and thermal oxidation.

[0078] The side gate and side field plate are structurally realized by the side oxide-polysilicon structure. The polysilicon in the oxide-polysilicon structure and the original planar polysilicon gate have the same polysilicon doping concentration. The high-quality oxide formed by thermal oxidation can selectively be consistent with the original planar field plate. The side field plate and the original planar field plate are electrically connected.

[0079] The side-side gate and the side-side polysilicon field plate are arranged in a cross-intercalation form, which affects each RFLDMOS intercalation finger and thus has a beneficial effect on the overall device.

[0080] The core technology utilizes the effect of double-sided trenches to generate lateral electric field components in the channel and drift region. The double-sided trenches used have a relatively shallow trench depth and low aspect ratio. The process and structure are different from the methods of using deep trenches for buried gate or source / drain etching in terms of purpose and effect. Moreover, the fabrication is simpler, more reliable, and has a higher yield. General etching processes can meet the requirements.

Claims

1. An RFLDMOS power radio frequency device structure, characterized in that: A highly doped semiconductor substrate serves as the semiconductor base for the entire device structure and also acts as the source terminal for the entire device. A moderately doped semiconductor epitaxial layer of tens of micrometers is epitaxially grown on the hundreds-micrometer-thick semiconductor substrate, with a doping concentration ranging from 5E16 cm⁻¹. -3 ~5E17 cm -3 High doping concentration refers to the concentration that allows a semiconductor to enter a degenerate state; for silicon-based devices, it refers to a doping concentration range of 1E19cm⁻¹. -3 ~1E20 cm -3 The top and bottom diffusion connections with high doping concentrations are obtained by diffusion and are used to connect the source region doping to the semiconductor substrate. The semiconductor substrate, semiconductor epitaxial layer, and top and bottom diffusion connections are of the first conductivity type. The drift region is located in the semiconductor epitaxial layer. It exhibits a second conductivity type and has a doping concentration ranging from 7.5E6 cm⁻¹. -3 ~5E17 cm -3 The entire RFLDMOS device achieves high voltage withstand properties by extending the electric field through the drift region; Drain doping is located in the drift region, and source doping is located above the top and bottom diffusion connections. Both drain and source doping are of the second conductivity type, with high doping concentrations. Drain doping is electrically connected to the drain metal connection to form the drain terminal of the device, and source doping is electrically connected to the source metal connection to form the source terminal of the device. A planar high-quality oxide is located between the source and drain metal connections. It is a high-quality oxide layer formed by thermal oxidation and serves as the gate oxide. The polysilicon gate is located above the planar high-quality oxide and uses a high doping concentration to minimize the gate resistance and obtain an appropriate threshold voltage. In the direction perpendicular to the source to the drain, a high-quality trench oxide is formed in the semiconductor epitaxial layer on the side of the polysilicon gate. The high-quality trench oxide is a high-quality oxide layer obtained by thermal oxidation after trenching on the side. The high-quality trench oxide is in direct contact with the channel region and drift region under the polysilicon gate to form an oxide-silicon interface, ensuring the quality of the high-quality trench oxide and reducing the interface states of the oxide-silicon interface between the high-quality trench oxide and silicon. High-quality trench oxides and high-quality planar oxides were prepared separately to eliminate the steps at the junction of the high-quality trench oxides and the high-quality planar oxides. The trench polycrystalline silicon filler is a highly doped polycrystalline filler that fills the top of the high-quality oxide in the trench to ensure a smooth surface. The field plate is located above the planar high-quality oxide, the trench high-quality oxide, the trench polysilicon filler, and the polysilicon gate. The field plate is a single-layer polysilicon field plate. The field plate is electrically connected to the source end through the interpolation terminal design, which plays the role of modulating the surface electric field in the drift region. The trench polysilicon filler is directly electrically connected to the field plate, while the polysilicon gate is not electrically connected to the trench polysilicon filler.

2. The RFLDMOS power radio frequency device structure according to claim 1, characterized in that: The semiconductor substrate and semiconductor epitaxial layer are homogeneous silicon materials, SiC substrate and compound epitaxial layer, or silicon-based substrate and SiC epitaxial layer.

3. The RFLDMOS power radio frequency device structure according to claim 1, characterized in that: Metal silicides are formed between the drain region doping and the drain region metal connection using Ti, Ni, or tungsten metal; metal silicides are also formed between the source region doping and the source region metal connection using Ti, Ni, or tungsten metal.

4. The RFLDMOS power radio frequency device structure according to claim 1, characterized in that: The top-bottom diffusion connection electrically connects the semiconductor substrate and the source metal connection. The semiconductor substrate and the source metal connection serve as the source terminal, which is connected to the reference potential during operation. The drain metal connection serves as the drain terminal, and the polysilicon gate serves as the gate terminal. During operation, a pulse signal or a continuous wave signal is applied. After amplification, the pulse signal or continuous wave signal is output from the drain terminal formed by the drain metal connection. During operation, a large current path is formed on the path from the drain metal connection to the source metal connection. At the same time, it needs to withstand an operating voltage of 65V without breakdown.

5. The RFLDMOS power radio frequency device structure according to claim 1, characterized in that: The high-quality trench oxide electrically completely separates the trench polysilicon filler from the polysilicon gate, the channel region under the polysilicon gate, and the drift region. A Si-SiO2 interface is formed between the high-quality trench oxide and the channel region under the polysilicon gate, the trench polysilicon filler, and the drift region. By controlling the oxidation time conditions under the same nitrogen protection, the oxide layer thickness of the high-quality trench oxide is 4 to 7 times that of the gate oxide.

6. The RFLDMOS power radio frequency device structure according to claim 1, characterized in that: In addition to the vertical electric field pointing from the polysilicon gate to the semiconductor epitaxial layer, there is also a lateral electric field pointing from the polysilicon gate to the trench polysilicon filling. According to Gauss's formula Continuously distributed charge Where ρ is the charge density, ε0 ​​is the vacuum permittivity, and dV is the differential of the volume element, which is a triple integral over the charge distribution region. Planar high-quality oxide and trench high-quality oxide are equivalent to capacitors with a constant dielectric. The polysilicon gate is an electric field vector source. When the device is operating, a gate voltage is applied to the polysilicon gate, which is equivalent to the voltage in the above formula. The term is an active electric field vector source. With the electric field vector source unchanged, the electric field vector density in the vertical direction from the polysilicon gate to the semiconductor epitaxial layer remains unchanged, and an additional lateral electric field is added from the polysilicon gate to the trench polysilicon filling.

7. The RFLDMOS power radio frequency device structure according to claim 1, characterized in that: The electric flux across the cross section can be obtained by surface integration: in It is an electric field. It is the surface A tiny area on the surface, whose direction is defined as the surface normal pointing outwards; When the device is working, a voltage is applied to the drain terminal, and the electric field in the drift region points from the drain terminal to the source terminal. If the voltage applied to the drain terminal remains unchanged at a certain moment, the current flux on the cross section remains unchanged. When the side structure formed by the trench polysilicon filling forms a lateral electric field, the absolute value of the electric field near the high-quality oxide of the trench will decrease due to the deflection of the electric field vector.

8. A method for fabricating the RFLDMOS power radio frequency device structure according to claim 1, characterized in that... Includes the following steps: 1) Grow a semiconductor epitaxial layer on a semiconductor substrate or directly purchase an epitaxial wafer containing a semiconductor substrate and a semiconductor epitaxial layer and clean it to remove native oxides; 2) Active diffusion process is used to form top and bottom diffusion connections in the semiconductor epitaxial layer. Then, oxide and polysilicon are deposited sequentially on the semiconductor epitaxial layer. Patterning etching is used to form patterns and define the implantation regions of the drift regions. The top and bottom diffusion connections are not defined by the patterns of oxide and polysilicon. The requirement is met if the top and bottom diffusion connections do not diffuse into the patterns of oxide and polysilicon. After selective drift region implantation, annealing is performed at 800°C for 30 minutes. 3) Remove oxides and polysilicon, and open side trenches. The oxides are different from planar high-quality oxides or trench high-quality oxides. The difference is that the oxides are prepared by deposition, while the planar high-quality oxides or trench high-quality oxides are prepared by long-term thermal oxidation. The pattern and position definition of the side trenches are also formed by the method of depositing oxides and polysilicon and then patterning and etching. 4) Prepared by long-term thermal oxidation under nitrogen protection, and by controlling the oxidation time and the content of O2, NO and N2O, high-quality planar oxides and high-quality grooved oxides are formed. 5) Backfilling the trench with polysilicon filler fills the trench with polysilicon filler on top of the high-quality oxide. Then, dry etching is used to remove the polysilicon to expose the surface of the planar high-quality oxide. Then, polysilicon gates are deposited and patterned on the planar high-quality oxide to ensure that the polysilicon gates and the trench polysilicon filler are not electrically connected. 6) After depositing the intermediate oxide layer, polysilicon or tungsten nickel is deposited to form a field plate. The field plate and the trench polysilicon filler are electrically connected. In the case of multi-layer field plates, each field plate is electrically connected to the trench polysilicon filler. 7) After the processes of opening holes, selective silicide and tungsten filling, metal electrodes and etching, the drain metal connection and source metal connection are formed as the drain terminal and source terminal of the device, respectively. The source metal connection and the field plate are electrically connected at the end of the interdigitated finger.

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