A load-independent Class E ZVS constant voltage and constant current dual-output inverter

Abstract

This invention discloses a load-independent Class E ZVS constant voltage and constant current dual-output inverter, comprising a DC voltage source, a compensation inductor, a parallel resonant output port, a switching transistor, a compensation capacitor, and a series resonant output port. The DC voltage source, compensation inductor, parallel resonant output port, and series resonant output port are connected sequentially. The switching transistor and compensation capacitor are connected in parallel across the series resonant output port. The current flowing through the first load resistor is a constant output sinusoidal current with an amplitude of I1, and the voltage across the second load resistor is a constant output sinusoidal voltage with an amplitude of V2. Simultaneously, for any given voltage V1 across the first load resistor and current I2 flowing through the second load resistor, the voltage across the switching transistor is 0 at the instant of switching on. This invention can simultaneously supply power to two loads, achieving ZVS, constant voltage output, and constant current output over a wide load range.

Description

Technical Field

[0001] This invention belongs to the field of high-frequency inverter technology, specifically relating to a load-independent Class E ZVS constant voltage and constant current dual-output inverter. Background Technology

[0002] With the continuous development of power electronics technology, ultra-high frequency inverter technology has gradually become a research hotspot. High-frequency inverters typically operate at frequencies ranging from a few to several hundred MHz. For power electronic converters, increasing the operating frequency helps reduce the number and size of passive components, thereby reducing the overall system size and increasing the power density. Therefore, we pursue increasingly higher operating frequencies. However, increasing the operating frequency presents several challenges: higher operating frequencies mean more switching cycles, resulting in greater switching losses and potentially overheating of switching devices, reducing system efficiency; fewer passive components mean that parasitic parameters of circuit elements have a greater impact on the circuit's operating state; and there are also issues such as electromagnetic interference.

[0003] Traditional inverters suffer from various problems and suboptimal performance at high frequencies. Currently, Class E inverters and their derivatives and improvements are widely used in high-frequency applications. These topologies employ only a single switch, and through the design of the switch's duty cycle and impedance network, the switch operates in a soft-switching state, ideally with near-zero losses. This type of topology offers advantages such as high frequency, high efficiency, and simple structure. The classic Class E inverter uses a single switch that can operate in both zero-voltage conduction and zero-derivative conduction states, resulting in a simple structure, high transmission efficiency, and applicability to very high-frequency applications. However, the classic Class E inverter has only one optimal operating point. To achieve constant output, many researchers have analyzed the topologies in recent years, leading to load-independent output inverters. Currently, most Class E inverters are single-output structures, and a single constant output cannot meet the complex requirements of simultaneously powering multiple loads. Summary of the Invention

[0004] Technical Problem Solved: This invention proposes a load-independent Class E ZVS constant voltage and constant current dual-output inverter. Compared to a single-output structure, this inverter structure can generate two outputs, simultaneously powering two loads, thus reducing the number of inverters required and simplifying system control. This invention achieves this by designing the choke inductor in the original Class E inverter to a finite value, participating in series resonance to provide a constant voltage sinusoidal output to the load; and by designing a parallel resonant network to filter out the constant sinusoidal component in the input current, thereby providing a constant current sinusoidal output to the load. Through circuit parameter design, ZVS, constant voltage output, and constant current output are achieved over a wide load range. This invention is significant for a deeper understanding of Class E topologies, achieving multiple constant outputs (constant voltage and constant current dual outputs), and obtaining independent load operation.

[0005] Technical solution:

[0006] A load-independent Class E ZVS constant voltage and constant current dual-output inverter, comprising a DC voltage source, a compensation inductor, a parallel resonant output port, a switching transistor, a compensation capacitor, and a series resonant output port;

[0007] The DC voltage source, the compensation inductor, the parallel resonant output port, and the series resonant output port are connected in sequence, and the switching transistor and the compensation capacitor are connected in parallel across the two ends of the series resonant output port. The parallel resonant output port includes a first load resistor, a first inductor, and a first capacitor connected in parallel. The series resonant output port includes a second inductor, a second capacitor, and a second load resistor connected in series.

[0008] Among them, the current flowing through the first load resistor is a sinusoidal current with constant output and amplitude I1, and the voltage across the second load resistor is a sinusoidal voltage with constant output and amplitude V2; at the same time, for any given voltage V1 across the first load resistor and current I2 flowing through the second load resistor, the voltage of the switching transistor is 0 at the moment of switching on.

[0009] Furthermore, the parameter values ​​of the compensation capacitor and the compensation inductor are:

[0010]

[0011]

[0012] In the formula, C s This is the capacitance value of the compensation capacitor, L. in It is the inductance value of the compensating inductor, V in ω is the voltage value of the DC voltage source; ω is the resonant angular frequency, ω=2πf, f is the switching frequency; the parameter q represents the ratio of the resonant frequency of the finite choke L1 and the parallel capacitor C1 to the switching frequency. m is a function of D and q, and its function expression is:

[0013]

[0014] In the formula, D is the duty cycle.

[0015] Furthermore, the maximum value R of the first load resistance 1max for:

[0016]

[0017] The minimum value R of the second load resistance 2min for:

[0018]

[0019] In the formula, h is a function of D and q, and its function expression is:

[0020]

[0021] Furthermore, the operating range of the load-independent Class E ZVS constant voltage and constant current dual-output inverter is as follows:

[0022]

[0023] In the formula, R 1n and R 2n R 1max and R 2min The per-unit value is obtained by normalizing the resistance value R1 of the first load resistor and the resistance value R2 of the second load resistor, respectively, using the reference value as the standard value.

[0024] Furthermore, the parameters of the compensation capacitor and compensation inductor in the equivalent circuit topology of the load-independent Class E ZVS constant voltage constant current dual output inverter are as follows:

[0025]

[0026] L 2x =nL in (k Rn +1) (19)

[0027] In the formula, C 1x It is the capacitance value of the compensation capacitor in the equivalent circuit topology, L. 2x It is the inductance value of the compensation inductor in the equivalent circuit topology; parameter k R Let R1 be the product of the resistance of the first load resistor and R2 be the resistance of the second load resistor, and let n be a function of D and q, with the function expression being:

[0028]

[0029] Furthermore, the k Rn The value is 1.

[0030] Beneficial effects:

[0031] The load-independent Class E ZVS constant voltage and constant current dual-output inverter of this invention, compared with the prior art, requires only one switching transistor to achieve DC-AC conversion, resulting in a simpler structure and reduced cost; it can achieve zero-voltage switching of the switching transistor, thereby reducing switching losses; its low-loss and easy-to-control characteristics make it well-suited for high-frequency conversion applications; it can achieve constant output of a Class E inverter and has two output ports, constant voltage and constant current, which can simultaneously power two loads, reducing the number of inverters required and simplifying the control system structure. Details are as follows:

[0032] First, the load-independent Class E ZVS constant voltage and constant current dual-output inverter of this invention, through appropriate resonant parameter design, can generate quasi-CC power and quasi-CV power respectively for parallel resonant output and series resonant output. Detailed analysis shows that the output current or voltage variation is very small within the operating range.

[0033] Secondly, the load-independent Class E ZVS constant voltage and constant current dual-output inverter of the present invention can achieve ZVS condition for the MOSFET when outputting CC and CV, which greatly reduces switching losses and allows for higher operating frequencies.

[0034] Third, the load-independent Class E ZVS constant voltage and constant current dual-output inverter of this invention, considering constant output and ZVS characteristics, provides a detailed analysis of the proposed load-independent dual-output Class E inverter's operating range. This depends on the resonant design, for example, using k... Rn =1 design to ensure that both CC and CV outputs have sufficient operating range.

[0035] Fourth, the load-independent Class E ZVS constant voltage and constant current dual-output inverter of this invention establishes a 1MHz Class E inverter hardware with dual outputs, and provides experimental results to verify the effectiveness of the recommendations in this paper. The system achieves a maximum efficiency of 92.6%. Attached Figure Description

[0036] Figure 1 This is a schematic diagram of the load-independent Class E ZVS constant voltage and constant current dual-output inverter of the present invention;

[0037] Figure 2 This is a schematic diagram of the equivalent topology of the load-independent Class E ZVS constant voltage and constant current dual-output inverter of the present invention;

[0038] Figure 3The diagram shows the equivalent topology of the load-independent Class E ZVS constant voltage and constant current dual-output inverter of the present invention under different switching states, wherein (a) is the equivalent topology when the switch is closed, and (b) is the equivalent topology when the switch is open.

[0039] Figure 4 A schematic diagram illustrating the load variation range required to strictly meet constant output voltage and current;

[0040] Figure 5 A schematic diagram illustrating the impact of different loads (critical duty cycles) on ZVS;

[0041] Figure 6 The following are schematic diagrams of the output waveforms of the circuit under different loads: (a) R1 = 15Ω, R2 = 80Ω, (b) R1 = 10Ω, R2 = 40Ω, (c) R1 = 5Ω, R2 = 30Ω. Detailed Implementation

[0042] The following embodiments are provided to enable those skilled in the art to more fully understand the present invention, but do not limit the invention in any way.

[0043] Example 1

[0044] This invention discloses a load-independent Class E ZVS constant voltage and constant current dual-output inverter, which includes a DC voltage source, a compensation inductor, a parallel resonant output port, a switching transistor, a compensation capacitor, and a series resonant output port.

[0045] The DC voltage source, the compensation inductor, the parallel resonant output port, and the series resonant output port are connected in sequence, and the switching transistor and the compensation capacitor are connected in parallel across the two ends of the series resonant output port. The parallel resonant output port includes a first load resistor, a first inductor, and a first capacitor connected in parallel. The series resonant output port includes a second inductor, a second capacitor, and a second load resistor connected in series.

[0046] Among them, the current flowing through the first load resistor is a sinusoidal current with constant output and amplitude I1, and the voltage across the second load resistor is a sinusoidal voltage with constant output and amplitude V2; at the same time, for any given voltage V1 across the first load resistor and current I2 flowing through the second load resistor, the voltage of the switching transistor is 0 at the moment of switching on.

[0047] See Figure 1 The present invention proposes a load-independent Class E ZVS constant voltage and constant current dual-output inverter, comprising a DC voltage source, three inductors, three capacitors, two load resistors, and a switching transistor. The circuit has two output ports: a parallel resonant output port and a series resonant output port, each connected to a load resistor.

[0048] First, by analyzing the circuit topology, the conditions that the load-independent constant voltage and constant current output and ZVS need to be satisfied are derived. The specific process is as follows.

[0049] Before performing load-independent analysis and setting network parameters, it is necessary to derive and analyze the basic topology. The equivalent circuit can be obtained when the topology satisfies the following assumptions (see figure). Figure 2 :

[0050] Assume 1) The switch is an ideal switch that can be turned on and off instantly.

[0051] Assume 2) L1 and C1 resonate at the switching frequency f, and the quality factor is defined as:

[0052]

[0053] Q1 is large enough that the output voltage and output current are sinusoidal, as expressed by:

[0054] v1(ωt)=V1sin(ωt+α) (22);

[0055] i1(ωt)=I1sin(ωt+α) (23);

[0056] Assume 3) L2 and C2 resonate at the switching frequency f, and the quality factor is defined as:

[0057]

[0058] Q2 is large enough that the output current and output voltage are sinusoidal, as expressed by:

[0059] i2(ωt)=I2sin(ωt+β) (25);

[0060] v2(ωt)=V2sin(ωt+β) (26);

[0061] Assumption 4) All passive components in the circuit are ideal components. 1x For capacitive flow, through C 1x current i 1x Lagging behind v190°, the expression is:

[0062] i 1x =I 1x cos(ωt+α) (27);

[0063] L 2x For the sake of emotion, L 2x The voltage across the terminals leads the current i290°, expressed as:

[0064] v2x (ωt)=V 2x cos(ωt+β) (28);

[0065] In the equivalent circuit topology, C 1x It is a compensation capacitor, L 2x It's a compensating inductor. The reference directions for voltage and current are... Figure 2 It is displayed in the middle.

[0066] Furthermore, from assumptions 2) and 3), we know that a parallel resonant network can be equivalent to a sinusoidal voltage source, and a series resonant network can be equivalent to a sinusoidal current source, thus obtaining a simplified equivalent circuit structure, such as... Figure 3 As shown.

[0067] Analyze the topology and derive the theoretical equations. By combining the KCL equations and the equations for inductance and capacitance when the switch is closed and open, the differential equations for the Class E inverter circuit model are obtained:

[0068]

[0069] Solving the differential equation yields:

[0070]

[0071]

[0072] Where K1 and K2 are constants, and q is defined as:

[0073]

[0074] Conditions met:

[0075]

[0076] After obtaining the general solution of the circuit differential equation, load-independent analysis is performed. The fundamental input current i and the fundamental switching voltage v are analyzed. DS Perform Fourier analysis to decompose the current i into sine and cosine components with a phase angle of α, and decompose the voltage v DS It is decomposed into sine and cosine components with a phase angle of β.

[0077] The basic sinusoidal component of i is:

[0078]

[0079] The basic cosine components of i are:

[0080]

[0081] v DS The basic sine components are:

[0082]

[0083] v DS The basic cosine components are:

[0084]

[0085] The conditions that must be met for load independence are: load-independent zero-voltage switching (ZVS), constant current output, and constant voltage output. These will be analyzed and calculated one by one.

[0086] 1) Load-independent ZVS

[0087] The condition for ZVS is that for any given V1 and I2, the switching voltage is 0 at the instant of switching on. That is, for any V1 and I2, equation (38) always holds:

[0088] v DS (2π)=Z(V1, I2)=0 (38);

[0089] Equation (37) always holds true and can be equivalent to conditional equations (39)-(40):

[0090]

[0091]

[0092] 2) Constant current output

[0093] For any given V1 and I2, the value of I1 remains unchanged and should satisfy the following equation:

[0094]

[0095]

[0096] 3) Constant voltage output

[0097] For any given V1 and I2, the value of V2 remains unchanged and should satisfy the following equation:

[0098]

[0099]

[0100] Different given duty cycles D const Based on the above load-independent conditional equations, the parameters q, α, and β in equations (30) and (31) can be solved to obtain particular solutions. The obtained solutions can ensure that the values ​​of I1 and V2 remain unchanged when V1 and I2 change, and ZVS is also guaranteed.

[0101] The fundamental frequency output can be obtained by using a filter network in the circuit. Then, by designing an appropriate L... 2x C 1x The value of I 1b and V 2b It can be canceled, thus obtaining load-independent ZVS, constant current and voltage output.

[0102] I 1b and V 2b It can be decomposed into two terms, each of which is related to V1 and I2.

[0103] C can be derived from the solution of the differential equation. 1x L 2x expression:

[0104]

[0105]

[0106] In equations (45)-(46), m and n are functions of D, α, β, and q, and their function expressions are shown in equations (3) and (10). R The product of R1 and R2 is such that only the product of R1 and R2 equals the given k. R Only when the load resistance deviates from this optimal value can a strictly constant output independent of the load be observed. If the load resistance deviates from this optimal value, the output current and voltage will also change. Different k... R The impact of different values ​​on the system output value.

[0107] The operating range of the circuit load can be determined from the expression of the solution to the differential equation, the characteristics of the MOSFET switch, etc.

[0108]

[0109] According to the inequality, R1 has a maximum value and R2 has a minimum value, which can be expressed as:

[0110]

[0111]

[0112] With R 1max and R 2min Using R1 and R2 as the baseline, we standardize them to per unit, and the per-unit value is denoted as R. 1n R 2n .

[0113] From equations (45) and (46), we get:

[0114]

[0115] L 2x=nL in (k Rn +1) (51); where:

[0116]

[0117] Load independence requires the following two conditions to be met:

[0118]

[0119] R 1n R 2n =k Rn (54).

[0120] The operating range of the frequency converter can be plotted from equations (53)-(54) as follows: Figure 4 As shown. The triangular region represents the maximum working range. Each k Rn The value corresponds to a line segment originating from the origin. For C 1x L 2x Given a value, when R 1n R 2n When the load varies along the corresponding line segment, the circuit satisfies the load independence condition. The load area is very small when operating with strictly constant output. However, as described below, the circuit can achieve ZVS and quasi-constant output when the load moves within a certain range.

[0121] The previous section established the conditions required for the inverter to strictly meet constant voltage, constant current output, and ZVS. The following section will discuss the circuit characteristics when the load deviates from the constant load region, and the duty cycle D... const The actual working range when it remains unchanged.

[0122] When the load resistance changes, the MOSFET may no longer meet the ZVS (Zero Voltage Spectrum) requirement, such as... Figure 5 As shown in the figure, four possible scenarios are illustrated. When v DS When the duty cycle drops to zero, the critical duty cycle is denoted as D. crit Theoretically, when 0 ≤ ωt ≤ 2πD crit When the switch is turned on, 2πD crit The switch is turned off when ωt ≤ 2πt. It should be noted that D... crit It is precisely the duty cycle that ZVS can achieve under different load resistances, and D const This refers to the actual duty cycle generated by the controller to obtain a constant output from the MOSFET. Therefore, the actual on-time of the switch is ωt = 2π(D crit -D const If D crit >D const Before the switch drive signal arrives, v DSWhen the voltage drops to 0, the body diode of the MOSFET turns on. In this case, the circuit can be considered to roughly satisfy the ZVS condition. If D crit =D const Then the circuit can accurately implement ZVS. If D crit <D const When the switch is turned on, v Ds The inability to reduce the value to 0 prevents ZVS from being achieved. Therefore, D crit It should be equal to or greater than D const This is to ensure ZVS. Otherwise, when the MOSFET is turned on, v DS When D is non-zero, switching losses will occur. Specifically, when D... crit >D const At that time, v DS After the voltage drops to zero, the body diode of S1 begins to conduct. However, before S1 is turned on, capacitor C... s It may recharge, causing v DS An increase. To avoid this, the following conditions should be met:

[0123] i D (2π(D crit -D const ))≤0 (55);

[0124] Based on (34)-(38) and (55), the output current I1, output voltage V2, and critical duty cycle D for achieving ZVS can be solved. crit Choose I from (34) and (36) 1_const and V 2_const This serves as a reference value for current and voltage. Then, the normalized load voltage and current under different load resistances can be calculated as follows:

[0125]

[0126]

[0127] Assume D const =0.5 to achieve maximum power capacity, then the values ​​of q, m, and n can be obtained from the appendix. Then, I 1n V 2n and D crit The solution is only related to R 1n R 2n and k Rn Related. When R 1n R 2n The value is equal to k Rn At that time, D crit =D const =0.5, I 1n =1, V 2n=1, which is consistent with what was mentioned earlier. When k Rn When R increases, 1n The larger the range of k, the greater the range; when k Rn When R decreases, 2n The larger the range, the better. This paper chooses k. Rn =1 to obtain a balanced load range for the two outputs.

[0128] Therefore, in this invention, see as follows Figure 2 To obtain the equivalent circuit structure diagram, the DC voltage V needs to be determined first. in Given the switching frequency f, angular frequency ω = 2πf, constant current tank current amplitude I1, quality factor Q1, quality factor Q2, and switching duty cycle D, q, α, β, m, n, and h can be determined after selecting D. The formulas for calculating α and β are:

[0129] α=(2-D const )π (58);

[0130] β=(1.5-D const )π (59);

[0131] The values ​​of m, n, and h are obtained by calculation using equations (3), (6), and (10).

[0132] After determining the values ​​of q, α, β, m, n, and h, the circuit parameters can be calculated. The values ​​of parameters C and L can be calculated using the following formula:

[0133]

[0134]

[0135] The maximum or minimum load resistance can be calculated using the following formula:

[0136]

[0137]

[0138] The circuit parameters C1 and L2 can be calculated using the following formula:

[0139]

[0140]

[0141] Circuit parameter C 1x L 2x It can be calculated by the following formula, where k Rn As mentioned above, take 1:

[0142]

[0143] L2x =nL in (k Rn +1) (67);

[0144] The operating range of the circuit is:

[0145]

[0146] Example 2

[0147] Selected parameter DC voltage V in The switching frequency f, the angular frequency ω=2πf, the constant current tank current amplitude I1, the quality factor Q1, the quality factor Q2, and the switching duty cycle D.

[0148] Furthermore, by determining the values ​​of parameters q, α, β, m, n, and h, and substituting them into the general solution of the differential equation, the constant voltage amplitude V2, the maximum power P, the maximum load resistance, and the maximum values ​​of V1 and I2 can be calculated.

[0149] From the calculation formulas (64)-(67), we can obtain C1, L2, and C. 1x L 2x The specific parameter values ​​are shown in Table 1.

[0150] Table 1

[0151]

[0152] Output port waveform as follows Figure 6 It can be seen that under different loads, when S1 is turned on, the switching voltage v DS The voltage is always zero, thus achieving ZVS. I1 and V2 are slightly different; I1 is close to 2A, and V2 is close to 38.2V, which is consistent with the circuit parameter design in the table. When R1 = 10Ω and R2 = 40Ω, the maximum output power of the circuit within the designed load range is 32.6W. Both v1 and v2 are approximately sinusoidal.

[0153] As can be seen from the above embodiments, the load-independent Class E ZVS constant voltage and constant current dual-output inverter proposed in this invention can achieve quasi-constant voltage and constant current dual output, and can supply power to two loads at the same time; the switch operates in ZVS state, which can effectively reduce losses.

[0154] The above are merely preferred embodiments of the present invention. The scope of protection of the present invention is not limited to the above embodiments. All technical solutions falling within the scope of the present invention's concept are within the scope of protection of the present invention. It should be noted that for those skilled in the art, any improvements and modifications made without departing from the principles of the present invention should be considered within the scope of protection of the present invention.

Claims

1. A load-independent Class E ZVS constant voltage and constant current dual-output inverter, characterized in that, The load-independent Class E ZVS constant voltage and constant current dual-output inverter includes a DC voltage source, a compensation inductor, a parallel resonant output port, a switching transistor, a compensation capacitor, and a series resonant output port. The DC voltage source, the compensation inductor, the parallel resonant output port, and the series resonant output port are connected in sequence, and the switching transistor and the compensation capacitor are connected in parallel across the two ends of the series resonant output port. The parallel resonant output port includes a first load resistor, a first inductor, and a first capacitor connected in parallel. The series resonant output port includes a second inductor, a second capacitor, and a second load resistor connected in series. Among them, the current flowing through the first load resistor is a sinusoidal current with constant output and amplitude I1, and the voltage across the second load resistor is a sinusoidal voltage with constant output and amplitude V2; at the same time, for any given voltage V1 across the first load resistor and current I2 flowing through the second load resistor, the voltage of the switching transistor is 0 at the moment of switching on. The parameter values ​​of the compensation capacitor and compensation inductor are: ； ； In the formula, This is the capacitance value of the compensation capacitor. It is the inductance value of the compensating inductor. It is the voltage value of the DC voltage source; It is the resonant angular frequency, ω=2πf, where f is the switching frequency; the parameter q represents the ratio of the resonant frequency of the finite choke L1 and the parallel capacitor C1 to the switching frequency. ; It is a function of D and q, and its function expression is: ； In the formula, D is the duty cycle; The parameters of the compensation capacitor and compensation inductor in the equivalent circuit topology of the load-independent Class E ZVS constant voltage constant current dual output inverter are as follows: ； ； In the formula, It is the capacitance value of the compensation capacitor in the equivalent circuit topology. It is the inductance value of the compensation inductor in the equivalent circuit topology; parameter k R It is the product of the resistance value R1 of the first load resistor and the resistance value R2 of the second load resistor. It is a function of D and q, and its function expression is: 。 2. The load-independent Class E ZVS constant voltage and constant current dual-output inverter according to claim 1, characterized in that, The maximum value of the first load resistance for: ； Minimum value of the second load resistance for: ； In the formula, It is a function of D and q, and its function expression is: 。 3. The load-independent Class E ZVS constant voltage and constant current dual-output inverter according to claim 2, characterized in that, The operating range of the load-independent Class E ZVS constant voltage and constant current dual-output inverter is: ； In the formula, and Therefore and The per-unit value is obtained by normalizing the resistance value R1 of the first load resistor and the resistance value R2 of the second load resistor, respectively, using the reference value as the standard value.

4. The load-independent Class E ZVS constant voltage and constant current dual-output inverter according to claim 1, characterized in that, The parameters of the compensation capacitor and compensation inductor in the equivalent circuit topology of the load-independent Class E ZVS constant voltage constant current dual output inverter are as follows: ； ； In the formula, It is the capacitance value of the compensation capacitor in the equivalent circuit topology. It is the inductance value of the compensation inductor in the equivalent circuit topology; parameter k R It is the product of the resistance value R1 of the first load resistor and the resistance value R2 of the second load resistor. It is a function of D and q, and its function expression is: 。 5. The load-independent Class E ZVS constant voltage and constant current dual-output inverter according to claim 1, characterized in that, The The value of is 1.

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